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Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_42 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_84
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_42
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = and(io.in.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
invalidate route_buffer.io.enq.bits.flow.egress_node_id
invalidate route_buffer.io.enq.bits.flow.egress_node
invalidate route_buffer.io.enq.bits.flow.ingress_node_id
invalidate route_buffer.io.enq.bits.flow.ingress_node
invalidate route_buffer.io.enq.bits.flow.vnet_id
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h2))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0]
node _T_6 = and(io.in.ready, io.in.valid)
node _T_7 = and(_T_6, io.in.bits.head)
node _T_8 = and(_T_7, at_dest)
when _T_8 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<3>(0h5), io.in.bits.egress_id)
when _T_9 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_10 = eq(UInt<3>(0h6), io.in.bits.egress_id)
when _T_10 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_11 = eq(UInt<3>(0h7), io.in.bits.egress_id)
when _T_11 :
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1)
node _T_12 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_13 = and(route_q.io.enq.valid, _T_12)
node _T_14 = eq(_T_13, UInt<1>(0h0))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_14, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_85
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_42
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0]
node _T_18 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_19 = and(vcalloc_q.io.enq.valid, _T_18)
node _T_20 = eq(_T_19, UInt<1>(0h0))
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_20, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node c_hi = cat(c_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _c_T = cat(c_hi, c_lo)
node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0])
node _c_T_1 = cat(c_hi_1, c_lo_1)
node c_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node c_hi_2 = cat(c_hi_hi_1, io.out_credit_available.`0`[2])
node _c_T_2 = cat(c_hi_2, c_lo_2)
node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _c_T_3 = cat(c_hi_3, c_lo_3)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_channel_oh_0 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[4], vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 4, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1
connect io.in.ready, UInt<1>(0h0)
connect io.router_req.valid, UInt<1>(0h0)
invalidate io.router_req.bits.flow.egress_node_id
invalidate io.router_req.bits.flow.egress_node
invalidate io.router_req.bits.flow.ingress_node_id
invalidate io.router_req.bits.flow.ingress_node
invalidate io.router_req.bits.flow.vnet_id
invalidate io.router_req.bits.src_virt_id
connect io.vcalloc_req.valid, UInt<1>(0h0)
invalidate io.vcalloc_req.bits.vc_sel.`0`[0]
invalidate io.vcalloc_req.bits.vc_sel.`0`[1]
invalidate io.vcalloc_req.bits.vc_sel.`0`[2]
invalidate io.vcalloc_req.bits.vc_sel.`0`[3]
invalidate io.vcalloc_req.bits.vc_sel.`0`[4]
invalidate io.vcalloc_req.bits.vc_sel.`1`[0]
invalidate io.vcalloc_req.bits.vc_sel.`2`[0]
invalidate io.vcalloc_req.bits.vc_sel.`3`[0]
invalidate io.vcalloc_req.bits.in_vc
invalidate io.vcalloc_req.bits.flow.egress_node_id
invalidate io.vcalloc_req.bits.flow.egress_node
invalidate io.vcalloc_req.bits.flow.ingress_node_id
invalidate io.vcalloc_req.bits.flow.ingress_node
invalidate io.vcalloc_req.bits.flow.vnet_id
connect io.salloc_req[0].valid, UInt<1>(0h0)
invalidate io.salloc_req[0].bits.tail
invalidate io.salloc_req[0].bits.vc_sel.`0`[0]
invalidate io.salloc_req[0].bits.vc_sel.`0`[1]
invalidate io.salloc_req[0].bits.vc_sel.`0`[2]
invalidate io.salloc_req[0].bits.vc_sel.`0`[3]
invalidate io.salloc_req[0].bits.vc_sel.`0`[4]
invalidate io.salloc_req[0].bits.vc_sel.`1`[0]
invalidate io.salloc_req[0].bits.vc_sel.`2`[0]
invalidate io.salloc_req[0].bits.vc_sel.`3`[0]
connect io.out[0].valid, UInt<1>(0h0)
invalidate io.out[0].bits.out_virt_channel
invalidate io.out[0].bits.flit.virt_channel_id
invalidate io.out[0].bits.flit.flow.egress_node_id
invalidate io.out[0].bits.flit.flow.egress_node
invalidate io.out[0].bits.flit.flow.ingress_node_id
invalidate io.out[0].bits.flit.flow.ingress_node
invalidate io.out[0].bits.flit.flow.vnet_id
invalidate io.out[0].bits.flit.payload
invalidate io.out[0].bits.flit.tail
invalidate io.out[0].bits.flit.head | module IngressUnit_42( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset // @[IngressUnit.scala:11:7]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_65 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_19 = and(_T_17, _T_18)
node _T_20 = or(_T_12, _T_19)
node _T_21 = or(_T_5, _T_20)
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_21, UInt<1>(0h1), "") : assert_1
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_32 = and(_T_30, _T_31)
node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_39 = and(_T_37, _T_38)
node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_42 = and(_T_40, _T_41)
node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_46 = and(_T_44, _T_45)
node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_49 = and(_T_47, _T_48)
node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_60 = and(_T_58, _T_59)
node _T_61 = or(_T_32, _T_39)
node _T_62 = or(_T_61, _T_46)
node _T_63 = or(_T_62, _T_53)
node _T_64 = or(_T_63, _T_60)
node _T_65 = or(_T_25, _T_64)
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_65, UInt<1>(0h1), "") : assert_2
node _T_69 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_70 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_71 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_78 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_85 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_86 = and(_T_84, _T_85)
node _T_87 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_92 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_97 = and(_T_95, _T_96)
node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_99 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_104 = and(_T_102, _T_103)
node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_106 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_107 = and(_T_105, _T_106)
node _T_108 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_109 = and(_T_107, _T_108)
node _T_110 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_111 = and(_T_109, _T_110)
node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_113 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_114 = and(_T_112, _T_113)
node _T_115 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_118 = and(_T_116, _T_117)
node _T_119 = or(_T_76, _T_83)
node _T_120 = or(_T_119, _T_90)
node _T_121 = or(_T_120, _T_97)
node _T_122 = or(_T_121, _T_104)
node _T_123 = or(_T_122, _T_111)
node _T_124 = or(_T_123, _T_118)
node _T_125 = or(_T_69, _T_124)
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_125, UInt<1>(0h1), "") : assert_3
node _T_129 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_139 = and(_T_137, _T_138)
node _T_140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_153 = and(_T_151, _T_152)
node _T_154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_159 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_160 = and(_T_158, _T_159)
node _T_161 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_166 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_167 = and(_T_165, _T_166)
node _T_168 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_173 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_174 = and(_T_172, _T_173)
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_185 = and(_T_183, _T_184)
node _T_186 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_192 = and(_T_190, _T_191)
node _T_193 = or(_T_136, _T_143)
node _T_194 = or(_T_193, _T_150)
node _T_195 = or(_T_194, _T_157)
node _T_196 = or(_T_195, _T_164)
node _T_197 = or(_T_196, _T_171)
node _T_198 = or(_T_197, _T_178)
node _T_199 = or(_T_198, _T_185)
node _T_200 = or(_T_199, _T_192)
node _T_201 = or(_T_129, _T_200)
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_201, UInt<1>(0h1), "") : assert_4
node _T_205 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_207 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_208 = and(_T_206, _T_207)
node _T_209 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_214 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_215 = and(_T_213, _T_214)
node _T_216 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_221 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_228 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_229 = and(_T_227, _T_228)
node _T_230 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_235 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_236 = and(_T_234, _T_235)
node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_242 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_249 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_254 = and(_T_252, _T_253)
node _T_255 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_261 = and(_T_259, _T_260)
node _T_262 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_268 = and(_T_266, _T_267)
node _T_269 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_282 = and(_T_280, _T_281)
node _T_283 = or(_T_212, _T_219)
node _T_284 = or(_T_283, _T_226)
node _T_285 = or(_T_284, _T_233)
node _T_286 = or(_T_285, _T_240)
node _T_287 = or(_T_286, _T_247)
node _T_288 = or(_T_287, _T_254)
node _T_289 = or(_T_288, _T_261)
node _T_290 = or(_T_289, _T_268)
node _T_291 = or(_T_290, _T_275)
node _T_292 = or(_T_291, _T_282)
node _T_293 = or(_T_205, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_293, UInt<1>(0h1), "") : assert_5
node _T_297 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_299 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_306 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_313 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_316 = and(_T_314, _T_315)
node _T_317 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_320 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_327 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_328 = and(_T_326, _T_327)
node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_330 = and(_T_328, _T_329)
node _T_331 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_332 = and(_T_330, _T_331)
node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_334 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_335 = and(_T_333, _T_334)
node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_339 = and(_T_337, _T_338)
node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_341 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_346 = and(_T_344, _T_345)
node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_348 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_349 = and(_T_347, _T_348)
node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_353 = and(_T_351, _T_352)
node _T_354 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_355 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_360 = and(_T_358, _T_359)
node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_362 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_369 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_370 = and(_T_368, _T_369)
node _T_371 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_374 = and(_T_372, _T_373)
node _T_375 = or(_T_304, _T_311)
node _T_376 = or(_T_375, _T_318)
node _T_377 = or(_T_376, _T_325)
node _T_378 = or(_T_377, _T_332)
node _T_379 = or(_T_378, _T_339)
node _T_380 = or(_T_379, _T_346)
node _T_381 = or(_T_380, _T_353)
node _T_382 = or(_T_381, _T_360)
node _T_383 = or(_T_382, _T_367)
node _T_384 = or(_T_383, _T_374)
node _T_385 = or(_T_297, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_385, UInt<1>(0h1), "") : assert_6
node _T_389 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_391 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_398 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_399 = and(_T_397, _T_398)
node _T_400 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_401 = and(_T_399, _T_400)
node _T_402 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_405 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_406 = and(_T_404, _T_405)
node _T_407 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_408 = and(_T_406, _T_407)
node _T_409 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_412 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_415 = and(_T_413, _T_414)
node _T_416 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_419 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_420 = and(_T_418, _T_419)
node _T_421 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_426 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_427 = and(_T_425, _T_426)
node _T_428 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_433 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_440 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_447 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_448 = and(_T_446, _T_447)
node _T_449 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_454 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_455 = and(_T_453, _T_454)
node _T_456 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_461 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_462 = and(_T_460, _T_461)
node _T_463 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_464 = and(_T_462, _T_463)
node _T_465 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_466 = and(_T_464, _T_465)
node _T_467 = or(_T_396, _T_403)
node _T_468 = or(_T_467, _T_410)
node _T_469 = or(_T_468, _T_417)
node _T_470 = or(_T_469, _T_424)
node _T_471 = or(_T_470, _T_431)
node _T_472 = or(_T_471, _T_438)
node _T_473 = or(_T_472, _T_445)
node _T_474 = or(_T_473, _T_452)
node _T_475 = or(_T_474, _T_459)
node _T_476 = or(_T_475, _T_466)
node _T_477 = or(_T_389, _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_477, UInt<1>(0h1), "") : assert_7
node _T_481 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_482 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_483 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_484 = and(_T_482, _T_483)
node _T_485 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_488 = and(_T_486, _T_487)
node _T_489 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_490 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_491 = and(_T_489, _T_490)
node _T_492 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_497 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_498 = and(_T_496, _T_497)
node _T_499 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_500 = and(_T_498, _T_499)
node _T_501 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_504 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_505 = and(_T_503, _T_504)
node _T_506 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_509 = and(_T_507, _T_508)
node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_511 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_512 = and(_T_510, _T_511)
node _T_513 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_514 = and(_T_512, _T_513)
node _T_515 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_516 = and(_T_514, _T_515)
node _T_517 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_518 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_523 = and(_T_521, _T_522)
node _T_524 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_525 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_526 = and(_T_524, _T_525)
node _T_527 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_528 = and(_T_526, _T_527)
node _T_529 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_530 = and(_T_528, _T_529)
node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_532 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_535 = and(_T_533, _T_534)
node _T_536 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_537 = and(_T_535, _T_536)
node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_539 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_540 = and(_T_538, _T_539)
node _T_541 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_542 = and(_T_540, _T_541)
node _T_543 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_546 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_547 = and(_T_545, _T_546)
node _T_548 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_549 = and(_T_547, _T_548)
node _T_550 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_553 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(_T_488, _T_495)
node _T_560 = or(_T_559, _T_502)
node _T_561 = or(_T_560, _T_509)
node _T_562 = or(_T_561, _T_516)
node _T_563 = or(_T_562, _T_523)
node _T_564 = or(_T_563, _T_530)
node _T_565 = or(_T_564, _T_537)
node _T_566 = or(_T_565, _T_544)
node _T_567 = or(_T_566, _T_551)
node _T_568 = or(_T_567, _T_558)
node _T_569 = or(_T_481, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_569, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_65( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_NoOutput_14 :
output auto : { }
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset | module BundleBridgeNexus_NoOutput_14(); // @[BundleBridgeNexus.scala:20:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_161 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_161( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[30]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
connect _source_ok_WIRE[20], _source_ok_T_40
connect _source_ok_WIRE[21], _source_ok_T_41
connect _source_ok_WIRE[22], _source_ok_T_42
connect _source_ok_WIRE[23], _source_ok_T_43
connect _source_ok_WIRE[24], _source_ok_T_44
connect _source_ok_WIRE[25], _source_ok_T_45
connect _source_ok_WIRE[26], _source_ok_T_46
connect _source_ok_WIRE[27], _source_ok_T_47
connect _source_ok_WIRE[28], _source_ok_T_48
connect _source_ok_WIRE[29], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14])
node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15])
node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22])
node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23])
node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24])
node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28])
node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_201 = eq(_T_200, UInt<1>(0h0))
node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = or(_T_201, _T_206)
node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_209 = eq(_T_208, UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = or(_T_209, _T_214)
node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_217 = eq(_T_216, UInt<1>(0h0))
node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = or(_T_217, _T_222)
node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_225, _T_230)
node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<1>(0h0)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = or(_T_233, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_243 = cvt(_T_242)
node _T_244 = and(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = asSInt(_T_244)
node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0)))
node _T_247 = or(_T_241, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_249 = eq(_T_248, UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<1>(0h0)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = or(_T_249, _T_254)
node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_257 = eq(_T_256, UInt<1>(0h0))
node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = or(_T_257, _T_262)
node _T_264 = and(_T_11, _T_24)
node _T_265 = and(_T_264, _T_37)
node _T_266 = and(_T_265, _T_50)
node _T_267 = and(_T_266, _T_63)
node _T_268 = and(_T_267, _T_71)
node _T_269 = and(_T_268, _T_79)
node _T_270 = and(_T_269, _T_87)
node _T_271 = and(_T_270, _T_95)
node _T_272 = and(_T_271, _T_103)
node _T_273 = and(_T_272, _T_111)
node _T_274 = and(_T_273, _T_119)
node _T_275 = and(_T_274, _T_127)
node _T_276 = and(_T_275, _T_135)
node _T_277 = and(_T_276, _T_143)
node _T_278 = and(_T_277, _T_151)
node _T_279 = and(_T_278, _T_159)
node _T_280 = and(_T_279, _T_167)
node _T_281 = and(_T_280, _T_175)
node _T_282 = and(_T_281, _T_183)
node _T_283 = and(_T_282, _T_191)
node _T_284 = and(_T_283, _T_199)
node _T_285 = and(_T_284, _T_207)
node _T_286 = and(_T_285, _T_215)
node _T_287 = and(_T_286, _T_223)
node _T_288 = and(_T_287, _T_231)
node _T_289 = and(_T_288, _T_239)
node _T_290 = and(_T_289, _T_247)
node _T_291 = and(_T_290, _T_255)
node _T_292 = and(_T_291, _T_263)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_292, UInt<1>(0h1), "") : assert_1
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_296 :
node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<1>(0h0))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<1>(0h1))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<2>(0h2))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_319 = shr(io.in.a.bits.source, 2)
node _T_320 = eq(_T_319, UInt<2>(0h3))
node _T_321 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_322 = and(_T_320, _T_321)
node _T_323 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_350 = or(_T_300, _T_306)
node _T_351 = or(_T_350, _T_312)
node _T_352 = or(_T_351, _T_318)
node _T_353 = or(_T_352, _T_324)
node _T_354 = or(_T_353, _T_325)
node _T_355 = or(_T_354, _T_326)
node _T_356 = or(_T_355, _T_327)
node _T_357 = or(_T_356, _T_328)
node _T_358 = or(_T_357, _T_329)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_331)
node _T_361 = or(_T_360, _T_332)
node _T_362 = or(_T_361, _T_333)
node _T_363 = or(_T_362, _T_334)
node _T_364 = or(_T_363, _T_335)
node _T_365 = or(_T_364, _T_336)
node _T_366 = or(_T_365, _T_337)
node _T_367 = or(_T_366, _T_338)
node _T_368 = or(_T_367, _T_339)
node _T_369 = or(_T_368, _T_340)
node _T_370 = or(_T_369, _T_341)
node _T_371 = or(_T_370, _T_342)
node _T_372 = or(_T_371, _T_343)
node _T_373 = or(_T_372, _T_344)
node _T_374 = or(_T_373, _T_345)
node _T_375 = or(_T_374, _T_346)
node _T_376 = or(_T_375, _T_347)
node _T_377 = or(_T_376, _T_348)
node _T_378 = or(_T_377, _T_349)
node _T_379 = and(_T_299, _T_378)
node _T_380 = or(UInt<1>(0h0), _T_379)
node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_382 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<14>(0h2000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_388 = cvt(_T_387)
node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000)))
node _T_390 = asSInt(_T_389)
node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0)))
node _T_392 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_393 = cvt(_T_392)
node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000)))
node _T_395 = asSInt(_T_394)
node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0)))
node _T_397 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_398 = cvt(_T_397)
node _T_399 = and(_T_398, asSInt(UInt<18>(0h2f000)))
node _T_400 = asSInt(_T_399)
node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0)))
node _T_402 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<17>(0h10000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<13>(0h1000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_413 = cvt(_T_412)
node _T_414 = and(_T_413, asSInt(UInt<27>(0h4000000)))
node _T_415 = asSInt(_T_414)
node _T_416 = eq(_T_415, asSInt(UInt<1>(0h0)))
node _T_417 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = or(_T_386, _T_391)
node _T_423 = or(_T_422, _T_396)
node _T_424 = or(_T_423, _T_401)
node _T_425 = or(_T_424, _T_406)
node _T_426 = or(_T_425, _T_411)
node _T_427 = or(_T_426, _T_416)
node _T_428 = or(_T_427, _T_421)
node _T_429 = and(_T_381, _T_428)
node _T_430 = or(UInt<1>(0h0), _T_429)
node _T_431 = and(_T_380, _T_430)
node _T_432 = asUInt(reset)
node _T_433 = eq(_T_432, UInt<1>(0h0))
when _T_433 :
node _T_434 = eq(_T_431, UInt<1>(0h0))
when _T_434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_431, UInt<1>(0h1), "") : assert_2
node _T_435 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_436 = shr(io.in.a.bits.source, 2)
node _T_437 = eq(_T_436, UInt<1>(0h0))
node _T_438 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_439 = and(_T_437, _T_438)
node _T_440 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_441 = and(_T_439, _T_440)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_442 = shr(io.in.a.bits.source, 2)
node _T_443 = eq(_T_442, UInt<1>(0h1))
node _T_444 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_445 = and(_T_443, _T_444)
node _T_446 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_447 = and(_T_445, _T_446)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_448 = shr(io.in.a.bits.source, 2)
node _T_449 = eq(_T_448, UInt<2>(0h2))
node _T_450 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_451 = and(_T_449, _T_450)
node _T_452 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_453 = and(_T_451, _T_452)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_454 = shr(io.in.a.bits.source, 2)
node _T_455 = eq(_T_454, UInt<2>(0h3))
node _T_456 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_457 = and(_T_455, _T_456)
node _T_458 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_461 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_462 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_463 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_465 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_466 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_467 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_469 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_473 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_474 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_475 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_476 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_477 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_478 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_479 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_480 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_481 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_482 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_484 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[30]
connect _WIRE[0], _T_435
connect _WIRE[1], _T_441
connect _WIRE[2], _T_447
connect _WIRE[3], _T_453
connect _WIRE[4], _T_459
connect _WIRE[5], _T_460
connect _WIRE[6], _T_461
connect _WIRE[7], _T_462
connect _WIRE[8], _T_463
connect _WIRE[9], _T_464
connect _WIRE[10], _T_465
connect _WIRE[11], _T_466
connect _WIRE[12], _T_467
connect _WIRE[13], _T_468
connect _WIRE[14], _T_469
connect _WIRE[15], _T_470
connect _WIRE[16], _T_471
connect _WIRE[17], _T_472
connect _WIRE[18], _T_473
connect _WIRE[19], _T_474
connect _WIRE[20], _T_475
connect _WIRE[21], _T_476
connect _WIRE[22], _T_477
connect _WIRE[23], _T_478
connect _WIRE[24], _T_479
connect _WIRE[25], _T_480
connect _WIRE[26], _T_481
connect _WIRE[27], _T_482
connect _WIRE[28], _T_483
connect _WIRE[29], _T_484
node _T_485 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_486 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_487 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_488 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_489 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_490 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_491 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_492 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_493 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_494 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_495 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_496 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_497 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_498 = mux(_WIRE[5], _T_485, UInt<1>(0h0))
node _T_499 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_500 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_501 = mux(_WIRE[8], _T_486, UInt<1>(0h0))
node _T_502 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_503 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_504 = mux(_WIRE[11], _T_487, UInt<1>(0h0))
node _T_505 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_506 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_507 = mux(_WIRE[14], _T_488, UInt<1>(0h0))
node _T_508 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_509 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_510 = mux(_WIRE[17], _T_489, UInt<1>(0h0))
node _T_511 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_512 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_513 = mux(_WIRE[20], _T_490, UInt<1>(0h0))
node _T_514 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_515 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_516 = mux(_WIRE[23], _T_491, UInt<1>(0h0))
node _T_517 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_518 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_519 = mux(_WIRE[26], _T_492, UInt<1>(0h0))
node _T_520 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_521 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_522 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_523 = or(_T_493, _T_494)
node _T_524 = or(_T_523, _T_495)
node _T_525 = or(_T_524, _T_496)
node _T_526 = or(_T_525, _T_497)
node _T_527 = or(_T_526, _T_498)
node _T_528 = or(_T_527, _T_499)
node _T_529 = or(_T_528, _T_500)
node _T_530 = or(_T_529, _T_501)
node _T_531 = or(_T_530, _T_502)
node _T_532 = or(_T_531, _T_503)
node _T_533 = or(_T_532, _T_504)
node _T_534 = or(_T_533, _T_505)
node _T_535 = or(_T_534, _T_506)
node _T_536 = or(_T_535, _T_507)
node _T_537 = or(_T_536, _T_508)
node _T_538 = or(_T_537, _T_509)
node _T_539 = or(_T_538, _T_510)
node _T_540 = or(_T_539, _T_511)
node _T_541 = or(_T_540, _T_512)
node _T_542 = or(_T_541, _T_513)
node _T_543 = or(_T_542, _T_514)
node _T_544 = or(_T_543, _T_515)
node _T_545 = or(_T_544, _T_516)
node _T_546 = or(_T_545, _T_517)
node _T_547 = or(_T_546, _T_518)
node _T_548 = or(_T_547, _T_519)
node _T_549 = or(_T_548, _T_520)
node _T_550 = or(_T_549, _T_521)
node _T_551 = or(_T_550, _T_522)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_551
node _T_552 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_553 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_554 = and(_T_552, _T_553)
node _T_555 = or(UInt<1>(0h0), _T_554)
node _T_556 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_557 = cvt(_T_556)
node _T_558 = and(_T_557, asSInt(UInt<14>(0h2000)))
node _T_559 = asSInt(_T_558)
node _T_560 = eq(_T_559, asSInt(UInt<1>(0h0)))
node _T_561 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_562 = cvt(_T_561)
node _T_563 = and(_T_562, asSInt(UInt<13>(0h1000)))
node _T_564 = asSInt(_T_563)
node _T_565 = eq(_T_564, asSInt(UInt<1>(0h0)))
node _T_566 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_567 = cvt(_T_566)
node _T_568 = and(_T_567, asSInt(UInt<17>(0h10000)))
node _T_569 = asSInt(_T_568)
node _T_570 = eq(_T_569, asSInt(UInt<1>(0h0)))
node _T_571 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<18>(0h2f000)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<17>(0h10000)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<13>(0h1000)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<27>(0h4000000)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<13>(0h1000)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = or(_T_560, _T_565)
node _T_597 = or(_T_596, _T_570)
node _T_598 = or(_T_597, _T_575)
node _T_599 = or(_T_598, _T_580)
node _T_600 = or(_T_599, _T_585)
node _T_601 = or(_T_600, _T_590)
node _T_602 = or(_T_601, _T_595)
node _T_603 = and(_T_555, _T_602)
node _T_604 = or(UInt<1>(0h0), _T_603)
node _T_605 = and(_WIRE_1, _T_604)
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_605, UInt<1>(0h1), "") : assert_3
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(source_ok, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_612 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_612, UInt<1>(0h1), "") : assert_5
node _T_616 = asUInt(reset)
node _T_617 = eq(_T_616, UInt<1>(0h0))
when _T_617 :
node _T_618 = eq(is_aligned, UInt<1>(0h0))
when _T_618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_619 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(_T_619, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_619, UInt<1>(0h1), "") : assert_7
node _T_623 = not(io.in.a.bits.mask)
node _T_624 = eq(_T_623, UInt<1>(0h0))
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(_T_624, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_624, UInt<1>(0h1), "") : assert_8
node _T_628 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_628, UInt<1>(0h1), "") : assert_9
node _T_632 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_632 :
node _T_633 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_634 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_635 = and(_T_633, _T_634)
node _T_636 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_637 = shr(io.in.a.bits.source, 2)
node _T_638 = eq(_T_637, UInt<1>(0h0))
node _T_639 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_640 = and(_T_638, _T_639)
node _T_641 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_642 = and(_T_640, _T_641)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_643 = shr(io.in.a.bits.source, 2)
node _T_644 = eq(_T_643, UInt<1>(0h1))
node _T_645 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_646 = and(_T_644, _T_645)
node _T_647 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_648 = and(_T_646, _T_647)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_649 = shr(io.in.a.bits.source, 2)
node _T_650 = eq(_T_649, UInt<2>(0h2))
node _T_651 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_652 = and(_T_650, _T_651)
node _T_653 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_654 = and(_T_652, _T_653)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_655 = shr(io.in.a.bits.source, 2)
node _T_656 = eq(_T_655, UInt<2>(0h3))
node _T_657 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_658 = and(_T_656, _T_657)
node _T_659 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_662 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_663 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_664 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_665 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_666 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_667 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_668 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_669 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_673 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_674 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_675 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_679 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_680 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_681 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_682 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_683 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_684 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_685 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_686 = or(_T_636, _T_642)
node _T_687 = or(_T_686, _T_648)
node _T_688 = or(_T_687, _T_654)
node _T_689 = or(_T_688, _T_660)
node _T_690 = or(_T_689, _T_661)
node _T_691 = or(_T_690, _T_662)
node _T_692 = or(_T_691, _T_663)
node _T_693 = or(_T_692, _T_664)
node _T_694 = or(_T_693, _T_665)
node _T_695 = or(_T_694, _T_666)
node _T_696 = or(_T_695, _T_667)
node _T_697 = or(_T_696, _T_668)
node _T_698 = or(_T_697, _T_669)
node _T_699 = or(_T_698, _T_670)
node _T_700 = or(_T_699, _T_671)
node _T_701 = or(_T_700, _T_672)
node _T_702 = or(_T_701, _T_673)
node _T_703 = or(_T_702, _T_674)
node _T_704 = or(_T_703, _T_675)
node _T_705 = or(_T_704, _T_676)
node _T_706 = or(_T_705, _T_677)
node _T_707 = or(_T_706, _T_678)
node _T_708 = or(_T_707, _T_679)
node _T_709 = or(_T_708, _T_680)
node _T_710 = or(_T_709, _T_681)
node _T_711 = or(_T_710, _T_682)
node _T_712 = or(_T_711, _T_683)
node _T_713 = or(_T_712, _T_684)
node _T_714 = or(_T_713, _T_685)
node _T_715 = and(_T_635, _T_714)
node _T_716 = or(UInt<1>(0h0), _T_715)
node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<14>(0h2000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<13>(0h1000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<17>(0h10000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<18>(0h2f000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<17>(0h10000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_744 = cvt(_T_743)
node _T_745 = and(_T_744, asSInt(UInt<13>(0h1000)))
node _T_746 = asSInt(_T_745)
node _T_747 = eq(_T_746, asSInt(UInt<1>(0h0)))
node _T_748 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_749 = cvt(_T_748)
node _T_750 = and(_T_749, asSInt(UInt<27>(0h4000000)))
node _T_751 = asSInt(_T_750)
node _T_752 = eq(_T_751, asSInt(UInt<1>(0h0)))
node _T_753 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<13>(0h1000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = or(_T_722, _T_727)
node _T_759 = or(_T_758, _T_732)
node _T_760 = or(_T_759, _T_737)
node _T_761 = or(_T_760, _T_742)
node _T_762 = or(_T_761, _T_747)
node _T_763 = or(_T_762, _T_752)
node _T_764 = or(_T_763, _T_757)
node _T_765 = and(_T_717, _T_764)
node _T_766 = or(UInt<1>(0h0), _T_765)
node _T_767 = and(_T_716, _T_766)
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_767, UInt<1>(0h1), "") : assert_10
node _T_771 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_772 = shr(io.in.a.bits.source, 2)
node _T_773 = eq(_T_772, UInt<1>(0h0))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_777 = and(_T_775, _T_776)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_778 = shr(io.in.a.bits.source, 2)
node _T_779 = eq(_T_778, UInt<1>(0h1))
node _T_780 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_781 = and(_T_779, _T_780)
node _T_782 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_783 = and(_T_781, _T_782)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_784 = shr(io.in.a.bits.source, 2)
node _T_785 = eq(_T_784, UInt<2>(0h2))
node _T_786 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_787 = and(_T_785, _T_786)
node _T_788 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_789 = and(_T_787, _T_788)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<2>(0h3))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _T_796 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_797 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_798 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_799 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_800 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_801 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_802 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_803 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_804 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_805 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_806 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_807 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_808 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_809 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_810 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_811 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_817 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_818 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_819 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_820 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[30]
connect _WIRE_2[0], _T_771
connect _WIRE_2[1], _T_777
connect _WIRE_2[2], _T_783
connect _WIRE_2[3], _T_789
connect _WIRE_2[4], _T_795
connect _WIRE_2[5], _T_796
connect _WIRE_2[6], _T_797
connect _WIRE_2[7], _T_798
connect _WIRE_2[8], _T_799
connect _WIRE_2[9], _T_800
connect _WIRE_2[10], _T_801
connect _WIRE_2[11], _T_802
connect _WIRE_2[12], _T_803
connect _WIRE_2[13], _T_804
connect _WIRE_2[14], _T_805
connect _WIRE_2[15], _T_806
connect _WIRE_2[16], _T_807
connect _WIRE_2[17], _T_808
connect _WIRE_2[18], _T_809
connect _WIRE_2[19], _T_810
connect _WIRE_2[20], _T_811
connect _WIRE_2[21], _T_812
connect _WIRE_2[22], _T_813
connect _WIRE_2[23], _T_814
connect _WIRE_2[24], _T_815
connect _WIRE_2[25], _T_816
connect _WIRE_2[26], _T_817
connect _WIRE_2[27], _T_818
connect _WIRE_2[28], _T_819
connect _WIRE_2[29], _T_820
node _T_821 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_822 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_823 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_824 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_825 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_826 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_827 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_828 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_829 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_830 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_831 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_832 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_833 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_834 = mux(_WIRE_2[5], _T_821, UInt<1>(0h0))
node _T_835 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_836 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_837 = mux(_WIRE_2[8], _T_822, UInt<1>(0h0))
node _T_838 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_839 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_840 = mux(_WIRE_2[11], _T_823, UInt<1>(0h0))
node _T_841 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_842 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_843 = mux(_WIRE_2[14], _T_824, UInt<1>(0h0))
node _T_844 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_845 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_846 = mux(_WIRE_2[17], _T_825, UInt<1>(0h0))
node _T_847 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_848 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_849 = mux(_WIRE_2[20], _T_826, UInt<1>(0h0))
node _T_850 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0))
node _T_851 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = mux(_WIRE_2[23], _T_827, UInt<1>(0h0))
node _T_853 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0))
node _T_854 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0))
node _T_855 = mux(_WIRE_2[26], _T_828, UInt<1>(0h0))
node _T_856 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0))
node _T_857 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0))
node _T_858 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0))
node _T_859 = or(_T_829, _T_830)
node _T_860 = or(_T_859, _T_831)
node _T_861 = or(_T_860, _T_832)
node _T_862 = or(_T_861, _T_833)
node _T_863 = or(_T_862, _T_834)
node _T_864 = or(_T_863, _T_835)
node _T_865 = or(_T_864, _T_836)
node _T_866 = or(_T_865, _T_837)
node _T_867 = or(_T_866, _T_838)
node _T_868 = or(_T_867, _T_839)
node _T_869 = or(_T_868, _T_840)
node _T_870 = or(_T_869, _T_841)
node _T_871 = or(_T_870, _T_842)
node _T_872 = or(_T_871, _T_843)
node _T_873 = or(_T_872, _T_844)
node _T_874 = or(_T_873, _T_845)
node _T_875 = or(_T_874, _T_846)
node _T_876 = or(_T_875, _T_847)
node _T_877 = or(_T_876, _T_848)
node _T_878 = or(_T_877, _T_849)
node _T_879 = or(_T_878, _T_850)
node _T_880 = or(_T_879, _T_851)
node _T_881 = or(_T_880, _T_852)
node _T_882 = or(_T_881, _T_853)
node _T_883 = or(_T_882, _T_854)
node _T_884 = or(_T_883, _T_855)
node _T_885 = or(_T_884, _T_856)
node _T_886 = or(_T_885, _T_857)
node _T_887 = or(_T_886, _T_858)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_887
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<14>(0h2000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_898 = cvt(_T_897)
node _T_899 = and(_T_898, asSInt(UInt<13>(0h1000)))
node _T_900 = asSInt(_T_899)
node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0)))
node _T_902 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_903 = cvt(_T_902)
node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000)))
node _T_905 = asSInt(_T_904)
node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0)))
node _T_907 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_908 = cvt(_T_907)
node _T_909 = and(_T_908, asSInt(UInt<18>(0h2f000)))
node _T_910 = asSInt(_T_909)
node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0)))
node _T_912 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_913 = cvt(_T_912)
node _T_914 = and(_T_913, asSInt(UInt<17>(0h10000)))
node _T_915 = asSInt(_T_914)
node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0)))
node _T_917 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_918 = cvt(_T_917)
node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000)))
node _T_920 = asSInt(_T_919)
node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0)))
node _T_922 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_923 = cvt(_T_922)
node _T_924 = and(_T_923, asSInt(UInt<27>(0h4000000)))
node _T_925 = asSInt(_T_924)
node _T_926 = eq(_T_925, asSInt(UInt<1>(0h0)))
node _T_927 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_928 = cvt(_T_927)
node _T_929 = and(_T_928, asSInt(UInt<13>(0h1000)))
node _T_930 = asSInt(_T_929)
node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0)))
node _T_932 = or(_T_896, _T_901)
node _T_933 = or(_T_932, _T_906)
node _T_934 = or(_T_933, _T_911)
node _T_935 = or(_T_934, _T_916)
node _T_936 = or(_T_935, _T_921)
node _T_937 = or(_T_936, _T_926)
node _T_938 = or(_T_937, _T_931)
node _T_939 = and(_T_891, _T_938)
node _T_940 = or(UInt<1>(0h0), _T_939)
node _T_941 = and(_WIRE_3, _T_940)
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_941, UInt<1>(0h1), "") : assert_11
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(source_ok, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_948 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_948, UInt<1>(0h1), "") : assert_13
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(is_aligned, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_955 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_955, UInt<1>(0h1), "") : assert_15
node _T_959 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_959, UInt<1>(0h1), "") : assert_16
node _T_963 = not(io.in.a.bits.mask)
node _T_964 = eq(_T_963, UInt<1>(0h0))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_964, UInt<1>(0h1), "") : assert_17
node _T_968 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_968, UInt<1>(0h1), "") : assert_18
node _T_972 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_972 :
node _T_973 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_974 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_975 = and(_T_973, _T_974)
node _T_976 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_977 = shr(io.in.a.bits.source, 2)
node _T_978 = eq(_T_977, UInt<1>(0h0))
node _T_979 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_980 = and(_T_978, _T_979)
node _T_981 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_982 = and(_T_980, _T_981)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_983 = shr(io.in.a.bits.source, 2)
node _T_984 = eq(_T_983, UInt<1>(0h1))
node _T_985 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_986 = and(_T_984, _T_985)
node _T_987 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_988 = and(_T_986, _T_987)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_989 = shr(io.in.a.bits.source, 2)
node _T_990 = eq(_T_989, UInt<2>(0h2))
node _T_991 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_992 = and(_T_990, _T_991)
node _T_993 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_994 = and(_T_992, _T_993)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_995 = shr(io.in.a.bits.source, 2)
node _T_996 = eq(_T_995, UInt<2>(0h3))
node _T_997 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_998 = and(_T_996, _T_997)
node _T_999 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_1000 = and(_T_998, _T_999)
node _T_1001 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1007 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1008 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1009 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1010 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1011 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1012 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1013 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1014 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1015 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1016 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1017 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1018 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1019 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1025 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1026 = or(_T_976, _T_982)
node _T_1027 = or(_T_1026, _T_988)
node _T_1028 = or(_T_1027, _T_994)
node _T_1029 = or(_T_1028, _T_1000)
node _T_1030 = or(_T_1029, _T_1001)
node _T_1031 = or(_T_1030, _T_1002)
node _T_1032 = or(_T_1031, _T_1003)
node _T_1033 = or(_T_1032, _T_1004)
node _T_1034 = or(_T_1033, _T_1005)
node _T_1035 = or(_T_1034, _T_1006)
node _T_1036 = or(_T_1035, _T_1007)
node _T_1037 = or(_T_1036, _T_1008)
node _T_1038 = or(_T_1037, _T_1009)
node _T_1039 = or(_T_1038, _T_1010)
node _T_1040 = or(_T_1039, _T_1011)
node _T_1041 = or(_T_1040, _T_1012)
node _T_1042 = or(_T_1041, _T_1013)
node _T_1043 = or(_T_1042, _T_1014)
node _T_1044 = or(_T_1043, _T_1015)
node _T_1045 = or(_T_1044, _T_1016)
node _T_1046 = or(_T_1045, _T_1017)
node _T_1047 = or(_T_1046, _T_1018)
node _T_1048 = or(_T_1047, _T_1019)
node _T_1049 = or(_T_1048, _T_1020)
node _T_1050 = or(_T_1049, _T_1021)
node _T_1051 = or(_T_1050, _T_1022)
node _T_1052 = or(_T_1051, _T_1023)
node _T_1053 = or(_T_1052, _T_1024)
node _T_1054 = or(_T_1053, _T_1025)
node _T_1055 = and(_T_975, _T_1054)
node _T_1056 = or(UInt<1>(0h0), _T_1055)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_19
node _T_1060 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1061 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1062 = and(_T_1060, _T_1061)
node _T_1063 = or(UInt<1>(0h0), _T_1062)
node _T_1064 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1065 = cvt(_T_1064)
node _T_1066 = and(_T_1065, asSInt(UInt<13>(0h1000)))
node _T_1067 = asSInt(_T_1066)
node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0)))
node _T_1069 = and(_T_1063, _T_1068)
node _T_1070 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1071 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = or(UInt<1>(0h0), _T_1072)
node _T_1074 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1075 = cvt(_T_1074)
node _T_1076 = and(_T_1075, asSInt(UInt<14>(0h2000)))
node _T_1077 = asSInt(_T_1076)
node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0)))
node _T_1079 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1080 = cvt(_T_1079)
node _T_1081 = and(_T_1080, asSInt(UInt<17>(0h10000)))
node _T_1082 = asSInt(_T_1081)
node _T_1083 = eq(_T_1082, asSInt(UInt<1>(0h0)))
node _T_1084 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1085 = cvt(_T_1084)
node _T_1086 = and(_T_1085, asSInt(UInt<18>(0h2f000)))
node _T_1087 = asSInt(_T_1086)
node _T_1088 = eq(_T_1087, asSInt(UInt<1>(0h0)))
node _T_1089 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1090 = cvt(_T_1089)
node _T_1091 = and(_T_1090, asSInt(UInt<17>(0h10000)))
node _T_1092 = asSInt(_T_1091)
node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0)))
node _T_1094 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1095 = cvt(_T_1094)
node _T_1096 = and(_T_1095, asSInt(UInt<13>(0h1000)))
node _T_1097 = asSInt(_T_1096)
node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0)))
node _T_1099 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1100 = cvt(_T_1099)
node _T_1101 = and(_T_1100, asSInt(UInt<27>(0h4000000)))
node _T_1102 = asSInt(_T_1101)
node _T_1103 = eq(_T_1102, asSInt(UInt<1>(0h0)))
node _T_1104 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1105 = cvt(_T_1104)
node _T_1106 = and(_T_1105, asSInt(UInt<13>(0h1000)))
node _T_1107 = asSInt(_T_1106)
node _T_1108 = eq(_T_1107, asSInt(UInt<1>(0h0)))
node _T_1109 = or(_T_1078, _T_1083)
node _T_1110 = or(_T_1109, _T_1088)
node _T_1111 = or(_T_1110, _T_1093)
node _T_1112 = or(_T_1111, _T_1098)
node _T_1113 = or(_T_1112, _T_1103)
node _T_1114 = or(_T_1113, _T_1108)
node _T_1115 = and(_T_1073, _T_1114)
node _T_1116 = or(UInt<1>(0h0), _T_1069)
node _T_1117 = or(_T_1116, _T_1115)
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_20
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(source_ok, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(is_aligned, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_1127 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_23
node _T_1131 = eq(io.in.a.bits.mask, mask)
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_24
node _T_1135 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_25
node _T_1139 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1141 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1142 = and(_T_1140, _T_1141)
node _T_1143 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_1144 = shr(io.in.a.bits.source, 2)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
node _T_1146 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_1147 = and(_T_1145, _T_1146)
node _T_1148 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_1149 = and(_T_1147, _T_1148)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_1150 = shr(io.in.a.bits.source, 2)
node _T_1151 = eq(_T_1150, UInt<1>(0h1))
node _T_1152 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_1155 = and(_T_1153, _T_1154)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_1156 = shr(io.in.a.bits.source, 2)
node _T_1157 = eq(_T_1156, UInt<2>(0h2))
node _T_1158 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_1159 = and(_T_1157, _T_1158)
node _T_1160 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_1161 = and(_T_1159, _T_1160)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_1162 = shr(io.in.a.bits.source, 2)
node _T_1163 = eq(_T_1162, UInt<2>(0h3))
node _T_1164 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_1165 = and(_T_1163, _T_1164)
node _T_1166 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_1167 = and(_T_1165, _T_1166)
node _T_1168 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1169 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1170 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1171 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1172 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1173 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1174 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1175 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1176 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1177 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1178 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1179 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1180 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1181 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1182 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1183 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1184 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1185 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1186 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1187 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1188 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1189 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1190 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1191 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1193 = or(_T_1143, _T_1149)
node _T_1194 = or(_T_1193, _T_1155)
node _T_1195 = or(_T_1194, _T_1161)
node _T_1196 = or(_T_1195, _T_1167)
node _T_1197 = or(_T_1196, _T_1168)
node _T_1198 = or(_T_1197, _T_1169)
node _T_1199 = or(_T_1198, _T_1170)
node _T_1200 = or(_T_1199, _T_1171)
node _T_1201 = or(_T_1200, _T_1172)
node _T_1202 = or(_T_1201, _T_1173)
node _T_1203 = or(_T_1202, _T_1174)
node _T_1204 = or(_T_1203, _T_1175)
node _T_1205 = or(_T_1204, _T_1176)
node _T_1206 = or(_T_1205, _T_1177)
node _T_1207 = or(_T_1206, _T_1178)
node _T_1208 = or(_T_1207, _T_1179)
node _T_1209 = or(_T_1208, _T_1180)
node _T_1210 = or(_T_1209, _T_1181)
node _T_1211 = or(_T_1210, _T_1182)
node _T_1212 = or(_T_1211, _T_1183)
node _T_1213 = or(_T_1212, _T_1184)
node _T_1214 = or(_T_1213, _T_1185)
node _T_1215 = or(_T_1214, _T_1186)
node _T_1216 = or(_T_1215, _T_1187)
node _T_1217 = or(_T_1216, _T_1188)
node _T_1218 = or(_T_1217, _T_1189)
node _T_1219 = or(_T_1218, _T_1190)
node _T_1220 = or(_T_1219, _T_1191)
node _T_1221 = or(_T_1220, _T_1192)
node _T_1222 = and(_T_1142, _T_1221)
node _T_1223 = or(UInt<1>(0h0), _T_1222)
node _T_1224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1226 = and(_T_1224, _T_1225)
node _T_1227 = or(UInt<1>(0h0), _T_1226)
node _T_1228 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1229 = cvt(_T_1228)
node _T_1230 = and(_T_1229, asSInt(UInt<13>(0h1000)))
node _T_1231 = asSInt(_T_1230)
node _T_1232 = eq(_T_1231, asSInt(UInt<1>(0h0)))
node _T_1233 = and(_T_1227, _T_1232)
node _T_1234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1235 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1236 = and(_T_1234, _T_1235)
node _T_1237 = or(UInt<1>(0h0), _T_1236)
node _T_1238 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1239 = cvt(_T_1238)
node _T_1240 = and(_T_1239, asSInt(UInt<14>(0h2000)))
node _T_1241 = asSInt(_T_1240)
node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1244 = cvt(_T_1243)
node _T_1245 = and(_T_1244, asSInt(UInt<18>(0h2f000)))
node _T_1246 = asSInt(_T_1245)
node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0)))
node _T_1248 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1249 = cvt(_T_1248)
node _T_1250 = and(_T_1249, asSInt(UInt<17>(0h10000)))
node _T_1251 = asSInt(_T_1250)
node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0)))
node _T_1253 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1254 = cvt(_T_1253)
node _T_1255 = and(_T_1254, asSInt(UInt<13>(0h1000)))
node _T_1256 = asSInt(_T_1255)
node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0)))
node _T_1258 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1259 = cvt(_T_1258)
node _T_1260 = and(_T_1259, asSInt(UInt<27>(0h4000000)))
node _T_1261 = asSInt(_T_1260)
node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0)))
node _T_1263 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1264 = cvt(_T_1263)
node _T_1265 = and(_T_1264, asSInt(UInt<13>(0h1000)))
node _T_1266 = asSInt(_T_1265)
node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0)))
node _T_1268 = or(_T_1242, _T_1247)
node _T_1269 = or(_T_1268, _T_1252)
node _T_1270 = or(_T_1269, _T_1257)
node _T_1271 = or(_T_1270, _T_1262)
node _T_1272 = or(_T_1271, _T_1267)
node _T_1273 = and(_T_1237, _T_1272)
node _T_1274 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1275 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1276 = cvt(_T_1275)
node _T_1277 = and(_T_1276, asSInt(UInt<17>(0h10000)))
node _T_1278 = asSInt(_T_1277)
node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0)))
node _T_1280 = and(_T_1274, _T_1279)
node _T_1281 = or(UInt<1>(0h0), _T_1233)
node _T_1282 = or(_T_1281, _T_1273)
node _T_1283 = or(_T_1282, _T_1280)
node _T_1284 = and(_T_1223, _T_1283)
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_26
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(source_ok, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(is_aligned, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_1294 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_29
node _T_1298 = eq(io.in.a.bits.mask, mask)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_30
node _T_1302 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1302 :
node _T_1303 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1304 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1307 = shr(io.in.a.bits.source, 2)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
node _T_1309 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1310 = and(_T_1308, _T_1309)
node _T_1311 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1312 = and(_T_1310, _T_1311)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1313 = shr(io.in.a.bits.source, 2)
node _T_1314 = eq(_T_1313, UInt<1>(0h1))
node _T_1315 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1316 = and(_T_1314, _T_1315)
node _T_1317 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1318 = and(_T_1316, _T_1317)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1319 = shr(io.in.a.bits.source, 2)
node _T_1320 = eq(_T_1319, UInt<2>(0h2))
node _T_1321 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1324 = and(_T_1322, _T_1323)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1325 = shr(io.in.a.bits.source, 2)
node _T_1326 = eq(_T_1325, UInt<2>(0h3))
node _T_1327 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1328 = and(_T_1326, _T_1327)
node _T_1329 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1330 = and(_T_1328, _T_1329)
node _T_1331 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1332 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1333 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1334 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1335 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1336 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1337 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1338 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1339 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1340 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1341 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1342 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1343 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1344 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1352 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1353 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1354 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1355 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1356 = or(_T_1306, _T_1312)
node _T_1357 = or(_T_1356, _T_1318)
node _T_1358 = or(_T_1357, _T_1324)
node _T_1359 = or(_T_1358, _T_1330)
node _T_1360 = or(_T_1359, _T_1331)
node _T_1361 = or(_T_1360, _T_1332)
node _T_1362 = or(_T_1361, _T_1333)
node _T_1363 = or(_T_1362, _T_1334)
node _T_1364 = or(_T_1363, _T_1335)
node _T_1365 = or(_T_1364, _T_1336)
node _T_1366 = or(_T_1365, _T_1337)
node _T_1367 = or(_T_1366, _T_1338)
node _T_1368 = or(_T_1367, _T_1339)
node _T_1369 = or(_T_1368, _T_1340)
node _T_1370 = or(_T_1369, _T_1341)
node _T_1371 = or(_T_1370, _T_1342)
node _T_1372 = or(_T_1371, _T_1343)
node _T_1373 = or(_T_1372, _T_1344)
node _T_1374 = or(_T_1373, _T_1345)
node _T_1375 = or(_T_1374, _T_1346)
node _T_1376 = or(_T_1375, _T_1347)
node _T_1377 = or(_T_1376, _T_1348)
node _T_1378 = or(_T_1377, _T_1349)
node _T_1379 = or(_T_1378, _T_1350)
node _T_1380 = or(_T_1379, _T_1351)
node _T_1381 = or(_T_1380, _T_1352)
node _T_1382 = or(_T_1381, _T_1353)
node _T_1383 = or(_T_1382, _T_1354)
node _T_1384 = or(_T_1383, _T_1355)
node _T_1385 = and(_T_1305, _T_1384)
node _T_1386 = or(UInt<1>(0h0), _T_1385)
node _T_1387 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1388 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1389 = and(_T_1387, _T_1388)
node _T_1390 = or(UInt<1>(0h0), _T_1389)
node _T_1391 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1392 = cvt(_T_1391)
node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000)))
node _T_1394 = asSInt(_T_1393)
node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0)))
node _T_1396 = and(_T_1390, _T_1395)
node _T_1397 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1398 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1399 = and(_T_1397, _T_1398)
node _T_1400 = or(UInt<1>(0h0), _T_1399)
node _T_1401 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1402 = cvt(_T_1401)
node _T_1403 = and(_T_1402, asSInt(UInt<14>(0h2000)))
node _T_1404 = asSInt(_T_1403)
node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0)))
node _T_1406 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1407 = cvt(_T_1406)
node _T_1408 = and(_T_1407, asSInt(UInt<18>(0h2f000)))
node _T_1409 = asSInt(_T_1408)
node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0)))
node _T_1411 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<17>(0h10000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<27>(0h4000000)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1427 = cvt(_T_1426)
node _T_1428 = and(_T_1427, asSInt(UInt<13>(0h1000)))
node _T_1429 = asSInt(_T_1428)
node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0)))
node _T_1431 = or(_T_1405, _T_1410)
node _T_1432 = or(_T_1431, _T_1415)
node _T_1433 = or(_T_1432, _T_1420)
node _T_1434 = or(_T_1433, _T_1425)
node _T_1435 = or(_T_1434, _T_1430)
node _T_1436 = and(_T_1400, _T_1435)
node _T_1437 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1438 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1439 = cvt(_T_1438)
node _T_1440 = and(_T_1439, asSInt(UInt<17>(0h10000)))
node _T_1441 = asSInt(_T_1440)
node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0)))
node _T_1443 = and(_T_1437, _T_1442)
node _T_1444 = or(UInt<1>(0h0), _T_1396)
node _T_1445 = or(_T_1444, _T_1436)
node _T_1446 = or(_T_1445, _T_1443)
node _T_1447 = and(_T_1386, _T_1446)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_31
node _T_1451 = asUInt(reset)
node _T_1452 = eq(_T_1451, UInt<1>(0h0))
when _T_1452 :
node _T_1453 = eq(source_ok, UInt<1>(0h0))
when _T_1453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1454 = asUInt(reset)
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(is_aligned, UInt<1>(0h0))
when _T_1456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1457 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_34
node _T_1461 = not(mask)
node _T_1462 = and(io.in.a.bits.mask, _T_1461)
node _T_1463 = eq(_T_1462, UInt<1>(0h0))
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(_T_1463, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1463, UInt<1>(0h1), "") : assert_35
node _T_1467 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1467 :
node _T_1468 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1469 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1470 = and(_T_1468, _T_1469)
node _T_1471 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1472 = shr(io.in.a.bits.source, 2)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
node _T_1474 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1475 = and(_T_1473, _T_1474)
node _T_1476 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1477 = and(_T_1475, _T_1476)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1478 = shr(io.in.a.bits.source, 2)
node _T_1479 = eq(_T_1478, UInt<1>(0h1))
node _T_1480 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1481 = and(_T_1479, _T_1480)
node _T_1482 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1483 = and(_T_1481, _T_1482)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1484 = shr(io.in.a.bits.source, 2)
node _T_1485 = eq(_T_1484, UInt<2>(0h2))
node _T_1486 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1487 = and(_T_1485, _T_1486)
node _T_1488 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1489 = and(_T_1487, _T_1488)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1490 = shr(io.in.a.bits.source, 2)
node _T_1491 = eq(_T_1490, UInt<2>(0h3))
node _T_1492 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1493 = and(_T_1491, _T_1492)
node _T_1494 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1495 = and(_T_1493, _T_1494)
node _T_1496 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1497 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1498 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1499 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1500 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1501 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1502 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1503 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1504 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1505 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1506 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1507 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1508 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1509 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1510 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1511 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1512 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1513 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1514 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1515 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1516 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1517 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1518 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1519 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1520 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1521 = or(_T_1471, _T_1477)
node _T_1522 = or(_T_1521, _T_1483)
node _T_1523 = or(_T_1522, _T_1489)
node _T_1524 = or(_T_1523, _T_1495)
node _T_1525 = or(_T_1524, _T_1496)
node _T_1526 = or(_T_1525, _T_1497)
node _T_1527 = or(_T_1526, _T_1498)
node _T_1528 = or(_T_1527, _T_1499)
node _T_1529 = or(_T_1528, _T_1500)
node _T_1530 = or(_T_1529, _T_1501)
node _T_1531 = or(_T_1530, _T_1502)
node _T_1532 = or(_T_1531, _T_1503)
node _T_1533 = or(_T_1532, _T_1504)
node _T_1534 = or(_T_1533, _T_1505)
node _T_1535 = or(_T_1534, _T_1506)
node _T_1536 = or(_T_1535, _T_1507)
node _T_1537 = or(_T_1536, _T_1508)
node _T_1538 = or(_T_1537, _T_1509)
node _T_1539 = or(_T_1538, _T_1510)
node _T_1540 = or(_T_1539, _T_1511)
node _T_1541 = or(_T_1540, _T_1512)
node _T_1542 = or(_T_1541, _T_1513)
node _T_1543 = or(_T_1542, _T_1514)
node _T_1544 = or(_T_1543, _T_1515)
node _T_1545 = or(_T_1544, _T_1516)
node _T_1546 = or(_T_1545, _T_1517)
node _T_1547 = or(_T_1546, _T_1518)
node _T_1548 = or(_T_1547, _T_1519)
node _T_1549 = or(_T_1548, _T_1520)
node _T_1550 = and(_T_1470, _T_1549)
node _T_1551 = or(UInt<1>(0h0), _T_1550)
node _T_1552 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1553 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1554 = and(_T_1552, _T_1553)
node _T_1555 = or(UInt<1>(0h0), _T_1554)
node _T_1556 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1557 = cvt(_T_1556)
node _T_1558 = and(_T_1557, asSInt(UInt<14>(0h2000)))
node _T_1559 = asSInt(_T_1558)
node _T_1560 = eq(_T_1559, asSInt(UInt<1>(0h0)))
node _T_1561 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1562 = cvt(_T_1561)
node _T_1563 = and(_T_1562, asSInt(UInt<13>(0h1000)))
node _T_1564 = asSInt(_T_1563)
node _T_1565 = eq(_T_1564, asSInt(UInt<1>(0h0)))
node _T_1566 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1567 = cvt(_T_1566)
node _T_1568 = and(_T_1567, asSInt(UInt<18>(0h2f000)))
node _T_1569 = asSInt(_T_1568)
node _T_1570 = eq(_T_1569, asSInt(UInt<1>(0h0)))
node _T_1571 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1572 = cvt(_T_1571)
node _T_1573 = and(_T_1572, asSInt(UInt<17>(0h10000)))
node _T_1574 = asSInt(_T_1573)
node _T_1575 = eq(_T_1574, asSInt(UInt<1>(0h0)))
node _T_1576 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1577 = cvt(_T_1576)
node _T_1578 = and(_T_1577, asSInt(UInt<13>(0h1000)))
node _T_1579 = asSInt(_T_1578)
node _T_1580 = eq(_T_1579, asSInt(UInt<1>(0h0)))
node _T_1581 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1582 = cvt(_T_1581)
node _T_1583 = and(_T_1582, asSInt(UInt<27>(0h4000000)))
node _T_1584 = asSInt(_T_1583)
node _T_1585 = eq(_T_1584, asSInt(UInt<1>(0h0)))
node _T_1586 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1587 = cvt(_T_1586)
node _T_1588 = and(_T_1587, asSInt(UInt<13>(0h1000)))
node _T_1589 = asSInt(_T_1588)
node _T_1590 = eq(_T_1589, asSInt(UInt<1>(0h0)))
node _T_1591 = or(_T_1560, _T_1565)
node _T_1592 = or(_T_1591, _T_1570)
node _T_1593 = or(_T_1592, _T_1575)
node _T_1594 = or(_T_1593, _T_1580)
node _T_1595 = or(_T_1594, _T_1585)
node _T_1596 = or(_T_1595, _T_1590)
node _T_1597 = and(_T_1555, _T_1596)
node _T_1598 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1599 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1600 = cvt(_T_1599)
node _T_1601 = and(_T_1600, asSInt(UInt<17>(0h10000)))
node _T_1602 = asSInt(_T_1601)
node _T_1603 = eq(_T_1602, asSInt(UInt<1>(0h0)))
node _T_1604 = and(_T_1598, _T_1603)
node _T_1605 = or(UInt<1>(0h0), _T_1597)
node _T_1606 = or(_T_1605, _T_1604)
node _T_1607 = and(_T_1551, _T_1606)
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(_T_1607, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1607, UInt<1>(0h1), "") : assert_36
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(source_ok, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1614 = asUInt(reset)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
when _T_1615 :
node _T_1616 = eq(is_aligned, UInt<1>(0h0))
when _T_1616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1617 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1618 = asUInt(reset)
node _T_1619 = eq(_T_1618, UInt<1>(0h0))
when _T_1619 :
node _T_1620 = eq(_T_1617, UInt<1>(0h0))
when _T_1620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1617, UInt<1>(0h1), "") : assert_39
node _T_1621 = eq(io.in.a.bits.mask, mask)
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_40
node _T_1625 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1625 :
node _T_1626 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1627 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1628 = and(_T_1626, _T_1627)
node _T_1629 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1630 = shr(io.in.a.bits.source, 2)
node _T_1631 = eq(_T_1630, UInt<1>(0h0))
node _T_1632 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1633 = and(_T_1631, _T_1632)
node _T_1634 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1635 = and(_T_1633, _T_1634)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1636 = shr(io.in.a.bits.source, 2)
node _T_1637 = eq(_T_1636, UInt<1>(0h1))
node _T_1638 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1639 = and(_T_1637, _T_1638)
node _T_1640 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1641 = and(_T_1639, _T_1640)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1642 = shr(io.in.a.bits.source, 2)
node _T_1643 = eq(_T_1642, UInt<2>(0h2))
node _T_1644 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1645 = and(_T_1643, _T_1644)
node _T_1646 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1647 = and(_T_1645, _T_1646)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1648 = shr(io.in.a.bits.source, 2)
node _T_1649 = eq(_T_1648, UInt<2>(0h3))
node _T_1650 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1651 = and(_T_1649, _T_1650)
node _T_1652 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1653 = and(_T_1651, _T_1652)
node _T_1654 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1655 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1656 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1657 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1658 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1659 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1660 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1661 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1662 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1663 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1664 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1665 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1666 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1667 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1668 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1669 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1670 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1671 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1672 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1673 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1674 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1675 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1676 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1677 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1678 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1679 = or(_T_1629, _T_1635)
node _T_1680 = or(_T_1679, _T_1641)
node _T_1681 = or(_T_1680, _T_1647)
node _T_1682 = or(_T_1681, _T_1653)
node _T_1683 = or(_T_1682, _T_1654)
node _T_1684 = or(_T_1683, _T_1655)
node _T_1685 = or(_T_1684, _T_1656)
node _T_1686 = or(_T_1685, _T_1657)
node _T_1687 = or(_T_1686, _T_1658)
node _T_1688 = or(_T_1687, _T_1659)
node _T_1689 = or(_T_1688, _T_1660)
node _T_1690 = or(_T_1689, _T_1661)
node _T_1691 = or(_T_1690, _T_1662)
node _T_1692 = or(_T_1691, _T_1663)
node _T_1693 = or(_T_1692, _T_1664)
node _T_1694 = or(_T_1693, _T_1665)
node _T_1695 = or(_T_1694, _T_1666)
node _T_1696 = or(_T_1695, _T_1667)
node _T_1697 = or(_T_1696, _T_1668)
node _T_1698 = or(_T_1697, _T_1669)
node _T_1699 = or(_T_1698, _T_1670)
node _T_1700 = or(_T_1699, _T_1671)
node _T_1701 = or(_T_1700, _T_1672)
node _T_1702 = or(_T_1701, _T_1673)
node _T_1703 = or(_T_1702, _T_1674)
node _T_1704 = or(_T_1703, _T_1675)
node _T_1705 = or(_T_1704, _T_1676)
node _T_1706 = or(_T_1705, _T_1677)
node _T_1707 = or(_T_1706, _T_1678)
node _T_1708 = and(_T_1628, _T_1707)
node _T_1709 = or(UInt<1>(0h0), _T_1708)
node _T_1710 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1711 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1712 = and(_T_1710, _T_1711)
node _T_1713 = or(UInt<1>(0h0), _T_1712)
node _T_1714 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1715 = cvt(_T_1714)
node _T_1716 = and(_T_1715, asSInt(UInt<14>(0h2000)))
node _T_1717 = asSInt(_T_1716)
node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0)))
node _T_1719 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1720 = cvt(_T_1719)
node _T_1721 = and(_T_1720, asSInt(UInt<13>(0h1000)))
node _T_1722 = asSInt(_T_1721)
node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0)))
node _T_1724 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1725 = cvt(_T_1724)
node _T_1726 = and(_T_1725, asSInt(UInt<18>(0h2f000)))
node _T_1727 = asSInt(_T_1726)
node _T_1728 = eq(_T_1727, asSInt(UInt<1>(0h0)))
node _T_1729 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1730 = cvt(_T_1729)
node _T_1731 = and(_T_1730, asSInt(UInt<17>(0h10000)))
node _T_1732 = asSInt(_T_1731)
node _T_1733 = eq(_T_1732, asSInt(UInt<1>(0h0)))
node _T_1734 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1735 = cvt(_T_1734)
node _T_1736 = and(_T_1735, asSInt(UInt<13>(0h1000)))
node _T_1737 = asSInt(_T_1736)
node _T_1738 = eq(_T_1737, asSInt(UInt<1>(0h0)))
node _T_1739 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1740 = cvt(_T_1739)
node _T_1741 = and(_T_1740, asSInt(UInt<27>(0h4000000)))
node _T_1742 = asSInt(_T_1741)
node _T_1743 = eq(_T_1742, asSInt(UInt<1>(0h0)))
node _T_1744 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1745 = cvt(_T_1744)
node _T_1746 = and(_T_1745, asSInt(UInt<13>(0h1000)))
node _T_1747 = asSInt(_T_1746)
node _T_1748 = eq(_T_1747, asSInt(UInt<1>(0h0)))
node _T_1749 = or(_T_1718, _T_1723)
node _T_1750 = or(_T_1749, _T_1728)
node _T_1751 = or(_T_1750, _T_1733)
node _T_1752 = or(_T_1751, _T_1738)
node _T_1753 = or(_T_1752, _T_1743)
node _T_1754 = or(_T_1753, _T_1748)
node _T_1755 = and(_T_1713, _T_1754)
node _T_1756 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1757 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1758 = cvt(_T_1757)
node _T_1759 = and(_T_1758, asSInt(UInt<17>(0h10000)))
node _T_1760 = asSInt(_T_1759)
node _T_1761 = eq(_T_1760, asSInt(UInt<1>(0h0)))
node _T_1762 = and(_T_1756, _T_1761)
node _T_1763 = or(UInt<1>(0h0), _T_1755)
node _T_1764 = or(_T_1763, _T_1762)
node _T_1765 = and(_T_1709, _T_1764)
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(_T_1765, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1765, UInt<1>(0h1), "") : assert_41
node _T_1769 = asUInt(reset)
node _T_1770 = eq(_T_1769, UInt<1>(0h0))
when _T_1770 :
node _T_1771 = eq(source_ok, UInt<1>(0h0))
when _T_1771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1772 = asUInt(reset)
node _T_1773 = eq(_T_1772, UInt<1>(0h0))
when _T_1773 :
node _T_1774 = eq(is_aligned, UInt<1>(0h0))
when _T_1774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1775 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1776 = asUInt(reset)
node _T_1777 = eq(_T_1776, UInt<1>(0h0))
when _T_1777 :
node _T_1778 = eq(_T_1775, UInt<1>(0h0))
when _T_1778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1775, UInt<1>(0h1), "") : assert_44
node _T_1779 = eq(io.in.a.bits.mask, mask)
node _T_1780 = asUInt(reset)
node _T_1781 = eq(_T_1780, UInt<1>(0h0))
when _T_1781 :
node _T_1782 = eq(_T_1779, UInt<1>(0h0))
when _T_1782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1779, UInt<1>(0h1), "") : assert_45
node _T_1783 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1783 :
node _T_1784 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1785 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1786 = and(_T_1784, _T_1785)
node _T_1787 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1788 = shr(io.in.a.bits.source, 2)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
node _T_1790 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1791 = and(_T_1789, _T_1790)
node _T_1792 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1793 = and(_T_1791, _T_1792)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1794 = shr(io.in.a.bits.source, 2)
node _T_1795 = eq(_T_1794, UInt<1>(0h1))
node _T_1796 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1797 = and(_T_1795, _T_1796)
node _T_1798 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1799 = and(_T_1797, _T_1798)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1800 = shr(io.in.a.bits.source, 2)
node _T_1801 = eq(_T_1800, UInt<2>(0h2))
node _T_1802 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1803 = and(_T_1801, _T_1802)
node _T_1804 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1805 = and(_T_1803, _T_1804)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1806 = shr(io.in.a.bits.source, 2)
node _T_1807 = eq(_T_1806, UInt<2>(0h3))
node _T_1808 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1809 = and(_T_1807, _T_1808)
node _T_1810 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1811 = and(_T_1809, _T_1810)
node _T_1812 = eq(io.in.a.bits.source, UInt<6>(0h3c))
node _T_1813 = eq(io.in.a.bits.source, UInt<6>(0h3d))
node _T_1814 = eq(io.in.a.bits.source, UInt<6>(0h3e))
node _T_1815 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_1816 = eq(io.in.a.bits.source, UInt<6>(0h39))
node _T_1817 = eq(io.in.a.bits.source, UInt<6>(0h3a))
node _T_1818 = eq(io.in.a.bits.source, UInt<6>(0h34))
node _T_1819 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1820 = eq(io.in.a.bits.source, UInt<6>(0h36))
node _T_1821 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_1822 = eq(io.in.a.bits.source, UInt<6>(0h31))
node _T_1823 = eq(io.in.a.bits.source, UInt<6>(0h32))
node _T_1824 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1825 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1826 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1827 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1828 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1829 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1830 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1831 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1832 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1833 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1834 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1835 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1836 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1837 = or(_T_1787, _T_1793)
node _T_1838 = or(_T_1837, _T_1799)
node _T_1839 = or(_T_1838, _T_1805)
node _T_1840 = or(_T_1839, _T_1811)
node _T_1841 = or(_T_1840, _T_1812)
node _T_1842 = or(_T_1841, _T_1813)
node _T_1843 = or(_T_1842, _T_1814)
node _T_1844 = or(_T_1843, _T_1815)
node _T_1845 = or(_T_1844, _T_1816)
node _T_1846 = or(_T_1845, _T_1817)
node _T_1847 = or(_T_1846, _T_1818)
node _T_1848 = or(_T_1847, _T_1819)
node _T_1849 = or(_T_1848, _T_1820)
node _T_1850 = or(_T_1849, _T_1821)
node _T_1851 = or(_T_1850, _T_1822)
node _T_1852 = or(_T_1851, _T_1823)
node _T_1853 = or(_T_1852, _T_1824)
node _T_1854 = or(_T_1853, _T_1825)
node _T_1855 = or(_T_1854, _T_1826)
node _T_1856 = or(_T_1855, _T_1827)
node _T_1857 = or(_T_1856, _T_1828)
node _T_1858 = or(_T_1857, _T_1829)
node _T_1859 = or(_T_1858, _T_1830)
node _T_1860 = or(_T_1859, _T_1831)
node _T_1861 = or(_T_1860, _T_1832)
node _T_1862 = or(_T_1861, _T_1833)
node _T_1863 = or(_T_1862, _T_1834)
node _T_1864 = or(_T_1863, _T_1835)
node _T_1865 = or(_T_1864, _T_1836)
node _T_1866 = and(_T_1786, _T_1865)
node _T_1867 = or(UInt<1>(0h0), _T_1866)
node _T_1868 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1869 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1870 = and(_T_1868, _T_1869)
node _T_1871 = or(UInt<1>(0h0), _T_1870)
node _T_1872 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1873 = cvt(_T_1872)
node _T_1874 = and(_T_1873, asSInt(UInt<13>(0h1000)))
node _T_1875 = asSInt(_T_1874)
node _T_1876 = eq(_T_1875, asSInt(UInt<1>(0h0)))
node _T_1877 = and(_T_1871, _T_1876)
node _T_1878 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1879 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1880 = cvt(_T_1879)
node _T_1881 = and(_T_1880, asSInt(UInt<14>(0h2000)))
node _T_1882 = asSInt(_T_1881)
node _T_1883 = eq(_T_1882, asSInt(UInt<1>(0h0)))
node _T_1884 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1885 = cvt(_T_1884)
node _T_1886 = and(_T_1885, asSInt(UInt<17>(0h10000)))
node _T_1887 = asSInt(_T_1886)
node _T_1888 = eq(_T_1887, asSInt(UInt<1>(0h0)))
node _T_1889 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1890 = cvt(_T_1889)
node _T_1891 = and(_T_1890, asSInt(UInt<18>(0h2f000)))
node _T_1892 = asSInt(_T_1891)
node _T_1893 = eq(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1895 = cvt(_T_1894)
node _T_1896 = and(_T_1895, asSInt(UInt<17>(0h10000)))
node _T_1897 = asSInt(_T_1896)
node _T_1898 = eq(_T_1897, asSInt(UInt<1>(0h0)))
node _T_1899 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1900 = cvt(_T_1899)
node _T_1901 = and(_T_1900, asSInt(UInt<13>(0h1000)))
node _T_1902 = asSInt(_T_1901)
node _T_1903 = eq(_T_1902, asSInt(UInt<1>(0h0)))
node _T_1904 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1905 = cvt(_T_1904)
node _T_1906 = and(_T_1905, asSInt(UInt<27>(0h4000000)))
node _T_1907 = asSInt(_T_1906)
node _T_1908 = eq(_T_1907, asSInt(UInt<1>(0h0)))
node _T_1909 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1910 = cvt(_T_1909)
node _T_1911 = and(_T_1910, asSInt(UInt<13>(0h1000)))
node _T_1912 = asSInt(_T_1911)
node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0)))
node _T_1914 = or(_T_1883, _T_1888)
node _T_1915 = or(_T_1914, _T_1893)
node _T_1916 = or(_T_1915, _T_1898)
node _T_1917 = or(_T_1916, _T_1903)
node _T_1918 = or(_T_1917, _T_1908)
node _T_1919 = or(_T_1918, _T_1913)
node _T_1920 = and(_T_1878, _T_1919)
node _T_1921 = or(UInt<1>(0h0), _T_1877)
node _T_1922 = or(_T_1921, _T_1920)
node _T_1923 = and(_T_1867, _T_1922)
node _T_1924 = asUInt(reset)
node _T_1925 = eq(_T_1924, UInt<1>(0h0))
when _T_1925 :
node _T_1926 = eq(_T_1923, UInt<1>(0h0))
when _T_1926 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1923, UInt<1>(0h1), "") : assert_46
node _T_1927 = asUInt(reset)
node _T_1928 = eq(_T_1927, UInt<1>(0h0))
when _T_1928 :
node _T_1929 = eq(source_ok, UInt<1>(0h0))
when _T_1929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1930 = asUInt(reset)
node _T_1931 = eq(_T_1930, UInt<1>(0h0))
when _T_1931 :
node _T_1932 = eq(is_aligned, UInt<1>(0h0))
when _T_1932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1933 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1934 = asUInt(reset)
node _T_1935 = eq(_T_1934, UInt<1>(0h0))
when _T_1935 :
node _T_1936 = eq(_T_1933, UInt<1>(0h0))
when _T_1936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1933, UInt<1>(0h1), "") : assert_49
node _T_1937 = eq(io.in.a.bits.mask, mask)
node _T_1938 = asUInt(reset)
node _T_1939 = eq(_T_1938, UInt<1>(0h0))
when _T_1939 :
node _T_1940 = eq(_T_1937, UInt<1>(0h0))
when _T_1940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1937, UInt<1>(0h1), "") : assert_50
node _T_1941 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1942 = asUInt(reset)
node _T_1943 = eq(_T_1942, UInt<1>(0h0))
when _T_1943 :
node _T_1944 = eq(_T_1941, UInt<1>(0h0))
when _T_1944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1941, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1945 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1946 = asUInt(reset)
node _T_1947 = eq(_T_1946, UInt<1>(0h0))
when _T_1947 :
node _T_1948 = eq(_T_1945, UInt<1>(0h0))
when _T_1948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1945, UInt<1>(0h1), "") : assert_52
node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_85 = shr(io.in.d.bits.source, 2)
node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1))
node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_91 = shr(io.in.d.bits.source, 2)
node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2))
node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93)
node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_97 = shr(io.in.d.bits.source, 2)
node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3))
node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c))
node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d))
node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e))
node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39))
node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a))
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36))
node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31))
node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32))
node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[30]
connect _source_ok_WIRE_1[0], _source_ok_T_78
connect _source_ok_WIRE_1[1], _source_ok_T_84
connect _source_ok_WIRE_1[2], _source_ok_T_90
connect _source_ok_WIRE_1[3], _source_ok_T_96
connect _source_ok_WIRE_1[4], _source_ok_T_102
connect _source_ok_WIRE_1[5], _source_ok_T_103
connect _source_ok_WIRE_1[6], _source_ok_T_104
connect _source_ok_WIRE_1[7], _source_ok_T_105
connect _source_ok_WIRE_1[8], _source_ok_T_106
connect _source_ok_WIRE_1[9], _source_ok_T_107
connect _source_ok_WIRE_1[10], _source_ok_T_108
connect _source_ok_WIRE_1[11], _source_ok_T_109
connect _source_ok_WIRE_1[12], _source_ok_T_110
connect _source_ok_WIRE_1[13], _source_ok_T_111
connect _source_ok_WIRE_1[14], _source_ok_T_112
connect _source_ok_WIRE_1[15], _source_ok_T_113
connect _source_ok_WIRE_1[16], _source_ok_T_114
connect _source_ok_WIRE_1[17], _source_ok_T_115
connect _source_ok_WIRE_1[18], _source_ok_T_116
connect _source_ok_WIRE_1[19], _source_ok_T_117
connect _source_ok_WIRE_1[20], _source_ok_T_118
connect _source_ok_WIRE_1[21], _source_ok_T_119
connect _source_ok_WIRE_1[22], _source_ok_T_120
connect _source_ok_WIRE_1[23], _source_ok_T_121
connect _source_ok_WIRE_1[24], _source_ok_T_122
connect _source_ok_WIRE_1[25], _source_ok_T_123
connect _source_ok_WIRE_1[26], _source_ok_T_124
connect _source_ok_WIRE_1[27], _source_ok_T_125
connect _source_ok_WIRE_1[28], _source_ok_T_126
connect _source_ok_WIRE_1[29], _source_ok_T_127
node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2])
node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3])
node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10])
node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11])
node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12])
node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13])
node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14])
node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15])
node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16])
node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17])
node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18])
node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19])
node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20])
node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21])
node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22])
node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23])
node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24])
node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25])
node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26])
node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27])
node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28])
node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1949 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1949 :
node _T_1950 = asUInt(reset)
node _T_1951 = eq(_T_1950, UInt<1>(0h0))
when _T_1951 :
node _T_1952 = eq(source_ok_1, UInt<1>(0h0))
when _T_1952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1953 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1954 = asUInt(reset)
node _T_1955 = eq(_T_1954, UInt<1>(0h0))
when _T_1955 :
node _T_1956 = eq(_T_1953, UInt<1>(0h0))
when _T_1956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1953, UInt<1>(0h1), "") : assert_54
node _T_1957 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1958 = asUInt(reset)
node _T_1959 = eq(_T_1958, UInt<1>(0h0))
when _T_1959 :
node _T_1960 = eq(_T_1957, UInt<1>(0h0))
when _T_1960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1957, UInt<1>(0h1), "") : assert_55
node _T_1961 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1962 = asUInt(reset)
node _T_1963 = eq(_T_1962, UInt<1>(0h0))
when _T_1963 :
node _T_1964 = eq(_T_1961, UInt<1>(0h0))
when _T_1964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1961, UInt<1>(0h1), "") : assert_56
node _T_1965 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1966 = asUInt(reset)
node _T_1967 = eq(_T_1966, UInt<1>(0h0))
when _T_1967 :
node _T_1968 = eq(_T_1965, UInt<1>(0h0))
when _T_1968 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1965, UInt<1>(0h1), "") : assert_57
node _T_1969 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1969 :
node _T_1970 = asUInt(reset)
node _T_1971 = eq(_T_1970, UInt<1>(0h0))
when _T_1971 :
node _T_1972 = eq(source_ok_1, UInt<1>(0h0))
when _T_1972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(sink_ok, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1976 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_60
node _T_1980 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1981 = asUInt(reset)
node _T_1982 = eq(_T_1981, UInt<1>(0h0))
when _T_1982 :
node _T_1983 = eq(_T_1980, UInt<1>(0h0))
when _T_1983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1980, UInt<1>(0h1), "") : assert_61
node _T_1984 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1985 = asUInt(reset)
node _T_1986 = eq(_T_1985, UInt<1>(0h0))
when _T_1986 :
node _T_1987 = eq(_T_1984, UInt<1>(0h0))
when _T_1987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1984, UInt<1>(0h1), "") : assert_62
node _T_1988 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1989 = asUInt(reset)
node _T_1990 = eq(_T_1989, UInt<1>(0h0))
when _T_1990 :
node _T_1991 = eq(_T_1988, UInt<1>(0h0))
when _T_1991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1988, UInt<1>(0h1), "") : assert_63
node _T_1992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1993 = or(UInt<1>(0h1), _T_1992)
node _T_1994 = asUInt(reset)
node _T_1995 = eq(_T_1994, UInt<1>(0h0))
when _T_1995 :
node _T_1996 = eq(_T_1993, UInt<1>(0h0))
when _T_1996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1993, UInt<1>(0h1), "") : assert_64
node _T_1997 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1997 :
node _T_1998 = asUInt(reset)
node _T_1999 = eq(_T_1998, UInt<1>(0h0))
when _T_1999 :
node _T_2000 = eq(source_ok_1, UInt<1>(0h0))
when _T_2000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_2001 = asUInt(reset)
node _T_2002 = eq(_T_2001, UInt<1>(0h0))
when _T_2002 :
node _T_2003 = eq(sink_ok, UInt<1>(0h0))
when _T_2003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_2004 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_2005 = asUInt(reset)
node _T_2006 = eq(_T_2005, UInt<1>(0h0))
when _T_2006 :
node _T_2007 = eq(_T_2004, UInt<1>(0h0))
when _T_2007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_2004, UInt<1>(0h1), "") : assert_67
node _T_2008 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2009 = asUInt(reset)
node _T_2010 = eq(_T_2009, UInt<1>(0h0))
when _T_2010 :
node _T_2011 = eq(_T_2008, UInt<1>(0h0))
when _T_2011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_2008, UInt<1>(0h1), "") : assert_68
node _T_2012 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_2013 = asUInt(reset)
node _T_2014 = eq(_T_2013, UInt<1>(0h0))
when _T_2014 :
node _T_2015 = eq(_T_2012, UInt<1>(0h0))
when _T_2015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_2012, UInt<1>(0h1), "") : assert_69
node _T_2016 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2017 = or(_T_2016, io.in.d.bits.corrupt)
node _T_2018 = asUInt(reset)
node _T_2019 = eq(_T_2018, UInt<1>(0h0))
when _T_2019 :
node _T_2020 = eq(_T_2017, UInt<1>(0h0))
when _T_2020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_2017, UInt<1>(0h1), "") : assert_70
node _T_2021 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2022 = or(UInt<1>(0h1), _T_2021)
node _T_2023 = asUInt(reset)
node _T_2024 = eq(_T_2023, UInt<1>(0h0))
when _T_2024 :
node _T_2025 = eq(_T_2022, UInt<1>(0h0))
when _T_2025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_2022, UInt<1>(0h1), "") : assert_71
node _T_2026 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_2026 :
node _T_2027 = asUInt(reset)
node _T_2028 = eq(_T_2027, UInt<1>(0h0))
when _T_2028 :
node _T_2029 = eq(source_ok_1, UInt<1>(0h0))
when _T_2029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_2030 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2031 = asUInt(reset)
node _T_2032 = eq(_T_2031, UInt<1>(0h0))
when _T_2032 :
node _T_2033 = eq(_T_2030, UInt<1>(0h0))
when _T_2033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_2030, UInt<1>(0h1), "") : assert_73
node _T_2034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2035 = asUInt(reset)
node _T_2036 = eq(_T_2035, UInt<1>(0h0))
when _T_2036 :
node _T_2037 = eq(_T_2034, UInt<1>(0h0))
when _T_2037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_2034, UInt<1>(0h1), "") : assert_74
node _T_2038 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2039 = or(UInt<1>(0h1), _T_2038)
node _T_2040 = asUInt(reset)
node _T_2041 = eq(_T_2040, UInt<1>(0h0))
when _T_2041 :
node _T_2042 = eq(_T_2039, UInt<1>(0h0))
when _T_2042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_2039, UInt<1>(0h1), "") : assert_75
node _T_2043 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_2043 :
node _T_2044 = asUInt(reset)
node _T_2045 = eq(_T_2044, UInt<1>(0h0))
when _T_2045 :
node _T_2046 = eq(source_ok_1, UInt<1>(0h0))
when _T_2046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_2047 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2048 = asUInt(reset)
node _T_2049 = eq(_T_2048, UInt<1>(0h0))
when _T_2049 :
node _T_2050 = eq(_T_2047, UInt<1>(0h0))
when _T_2050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_2047, UInt<1>(0h1), "") : assert_77
node _T_2051 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2052 = or(_T_2051, io.in.d.bits.corrupt)
node _T_2053 = asUInt(reset)
node _T_2054 = eq(_T_2053, UInt<1>(0h0))
when _T_2054 :
node _T_2055 = eq(_T_2052, UInt<1>(0h0))
when _T_2055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_2052, UInt<1>(0h1), "") : assert_78
node _T_2056 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2057 = or(UInt<1>(0h1), _T_2056)
node _T_2058 = asUInt(reset)
node _T_2059 = eq(_T_2058, UInt<1>(0h0))
when _T_2059 :
node _T_2060 = eq(_T_2057, UInt<1>(0h0))
when _T_2060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_2057, UInt<1>(0h1), "") : assert_79
node _T_2061 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_2061 :
node _T_2062 = asUInt(reset)
node _T_2063 = eq(_T_2062, UInt<1>(0h0))
when _T_2063 :
node _T_2064 = eq(source_ok_1, UInt<1>(0h0))
when _T_2064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_2065 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_81
node _T_2069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_2070 = asUInt(reset)
node _T_2071 = eq(_T_2070, UInt<1>(0h0))
when _T_2071 :
node _T_2072 = eq(_T_2069, UInt<1>(0h0))
when _T_2072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_2069, UInt<1>(0h1), "") : assert_82
node _T_2073 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_2074 = or(UInt<1>(0h1), _T_2073)
node _T_2075 = asUInt(reset)
node _T_2076 = eq(_T_2075, UInt<1>(0h0))
when _T_2076 :
node _T_2077 = eq(_T_2074, UInt<1>(0h0))
when _T_2077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_2074, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_2078 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_2079 = asUInt(reset)
node _T_2080 = eq(_T_2079, UInt<1>(0h0))
when _T_2080 :
node _T_2081 = eq(_T_2078, UInt<1>(0h0))
when _T_2081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_2078, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_2082 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_2083 = asUInt(reset)
node _T_2084 = eq(_T_2083, UInt<1>(0h0))
when _T_2084 :
node _T_2085 = eq(_T_2082, UInt<1>(0h0))
when _T_2085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_2082, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_2086 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_2087 = asUInt(reset)
node _T_2088 = eq(_T_2087, UInt<1>(0h0))
when _T_2088 :
node _T_2089 = eq(_T_2086, UInt<1>(0h0))
when _T_2089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_2086, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2090 = eq(a_first, UInt<1>(0h0))
node _T_2091 = and(io.in.a.valid, _T_2090)
when _T_2091 :
node _T_2092 = eq(io.in.a.bits.opcode, opcode)
node _T_2093 = asUInt(reset)
node _T_2094 = eq(_T_2093, UInt<1>(0h0))
when _T_2094 :
node _T_2095 = eq(_T_2092, UInt<1>(0h0))
when _T_2095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_2092, UInt<1>(0h1), "") : assert_87
node _T_2096 = eq(io.in.a.bits.param, param)
node _T_2097 = asUInt(reset)
node _T_2098 = eq(_T_2097, UInt<1>(0h0))
when _T_2098 :
node _T_2099 = eq(_T_2096, UInt<1>(0h0))
when _T_2099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_2096, UInt<1>(0h1), "") : assert_88
node _T_2100 = eq(io.in.a.bits.size, size)
node _T_2101 = asUInt(reset)
node _T_2102 = eq(_T_2101, UInt<1>(0h0))
when _T_2102 :
node _T_2103 = eq(_T_2100, UInt<1>(0h0))
when _T_2103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_2100, UInt<1>(0h1), "") : assert_89
node _T_2104 = eq(io.in.a.bits.source, source)
node _T_2105 = asUInt(reset)
node _T_2106 = eq(_T_2105, UInt<1>(0h0))
when _T_2106 :
node _T_2107 = eq(_T_2104, UInt<1>(0h0))
when _T_2107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_2104, UInt<1>(0h1), "") : assert_90
node _T_2108 = eq(io.in.a.bits.address, address)
node _T_2109 = asUInt(reset)
node _T_2110 = eq(_T_2109, UInt<1>(0h0))
when _T_2110 :
node _T_2111 = eq(_T_2108, UInt<1>(0h0))
when _T_2111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_2108, UInt<1>(0h1), "") : assert_91
node _T_2112 = and(io.in.a.ready, io.in.a.valid)
node _T_2113 = and(_T_2112, a_first)
when _T_2113 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2114 = eq(d_first, UInt<1>(0h0))
node _T_2115 = and(io.in.d.valid, _T_2114)
when _T_2115 :
node _T_2116 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2117 = asUInt(reset)
node _T_2118 = eq(_T_2117, UInt<1>(0h0))
when _T_2118 :
node _T_2119 = eq(_T_2116, UInt<1>(0h0))
when _T_2119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_2116, UInt<1>(0h1), "") : assert_92
node _T_2120 = eq(io.in.d.bits.param, param_1)
node _T_2121 = asUInt(reset)
node _T_2122 = eq(_T_2121, UInt<1>(0h0))
when _T_2122 :
node _T_2123 = eq(_T_2120, UInt<1>(0h0))
when _T_2123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_2120, UInt<1>(0h1), "") : assert_93
node _T_2124 = eq(io.in.d.bits.size, size_1)
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_94
node _T_2128 = eq(io.in.d.bits.source, source_1)
node _T_2129 = asUInt(reset)
node _T_2130 = eq(_T_2129, UInt<1>(0h0))
when _T_2130 :
node _T_2131 = eq(_T_2128, UInt<1>(0h0))
when _T_2131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_2128, UInt<1>(0h1), "") : assert_95
node _T_2132 = eq(io.in.d.bits.sink, sink)
node _T_2133 = asUInt(reset)
node _T_2134 = eq(_T_2133, UInt<1>(0h0))
when _T_2134 :
node _T_2135 = eq(_T_2132, UInt<1>(0h0))
when _T_2135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_2132, UInt<1>(0h1), "") : assert_96
node _T_2136 = eq(io.in.d.bits.denied, denied)
node _T_2137 = asUInt(reset)
node _T_2138 = eq(_T_2137, UInt<1>(0h0))
when _T_2138 :
node _T_2139 = eq(_T_2136, UInt<1>(0h0))
when _T_2139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_2136, UInt<1>(0h1), "") : assert_97
node _T_2140 = and(io.in.d.ready, io.in.d.valid)
node _T_2141 = and(_T_2140, d_first)
when _T_2141 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2142 = and(io.in.a.valid, a_first_1)
node _T_2143 = and(_T_2142, UInt<1>(0h1))
when _T_2143 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2144 = and(io.in.a.ready, io.in.a.valid)
node _T_2145 = and(_T_2144, a_first_1)
node _T_2146 = and(_T_2145, UInt<1>(0h1))
when _T_2146 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2147 = dshr(inflight, io.in.a.bits.source)
node _T_2148 = bits(_T_2147, 0, 0)
node _T_2149 = eq(_T_2148, UInt<1>(0h0))
node _T_2150 = asUInt(reset)
node _T_2151 = eq(_T_2150, UInt<1>(0h0))
when _T_2151 :
node _T_2152 = eq(_T_2149, UInt<1>(0h0))
when _T_2152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_2149, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2153 = and(io.in.d.valid, d_first_1)
node _T_2154 = and(_T_2153, UInt<1>(0h1))
node _T_2155 = eq(d_release_ack, UInt<1>(0h0))
node _T_2156 = and(_T_2154, _T_2155)
when _T_2156 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2157 = and(io.in.d.ready, io.in.d.valid)
node _T_2158 = and(_T_2157, d_first_1)
node _T_2159 = and(_T_2158, UInt<1>(0h1))
node _T_2160 = eq(d_release_ack, UInt<1>(0h0))
node _T_2161 = and(_T_2159, _T_2160)
when _T_2161 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2162 = and(io.in.d.valid, d_first_1)
node _T_2163 = and(_T_2162, UInt<1>(0h1))
node _T_2164 = eq(d_release_ack, UInt<1>(0h0))
node _T_2165 = and(_T_2163, _T_2164)
when _T_2165 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2166 = dshr(inflight, io.in.d.bits.source)
node _T_2167 = bits(_T_2166, 0, 0)
node _T_2168 = or(_T_2167, same_cycle_resp)
node _T_2169 = asUInt(reset)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
when _T_2170 :
node _T_2171 = eq(_T_2168, UInt<1>(0h0))
when _T_2171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_2168, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_2172 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2173 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2174 = or(_T_2172, _T_2173)
node _T_2175 = asUInt(reset)
node _T_2176 = eq(_T_2175, UInt<1>(0h0))
when _T_2176 :
node _T_2177 = eq(_T_2174, UInt<1>(0h0))
when _T_2177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_2174, UInt<1>(0h1), "") : assert_100
node _T_2178 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2179 = asUInt(reset)
node _T_2180 = eq(_T_2179, UInt<1>(0h0))
when _T_2180 :
node _T_2181 = eq(_T_2178, UInt<1>(0h0))
when _T_2181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_2178, UInt<1>(0h1), "") : assert_101
else :
node _T_2182 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2183 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2184 = or(_T_2182, _T_2183)
node _T_2185 = asUInt(reset)
node _T_2186 = eq(_T_2185, UInt<1>(0h0))
when _T_2186 :
node _T_2187 = eq(_T_2184, UInt<1>(0h0))
when _T_2187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_2184, UInt<1>(0h1), "") : assert_102
node _T_2188 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2189 = asUInt(reset)
node _T_2190 = eq(_T_2189, UInt<1>(0h0))
when _T_2190 :
node _T_2191 = eq(_T_2188, UInt<1>(0h0))
when _T_2191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_2188, UInt<1>(0h1), "") : assert_103
node _T_2192 = and(io.in.d.valid, d_first_1)
node _T_2193 = and(_T_2192, a_first_1)
node _T_2194 = and(_T_2193, io.in.a.valid)
node _T_2195 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2196 = and(_T_2194, _T_2195)
node _T_2197 = eq(d_release_ack, UInt<1>(0h0))
node _T_2198 = and(_T_2196, _T_2197)
when _T_2198 :
node _T_2199 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2200 = or(_T_2199, io.in.a.ready)
node _T_2201 = asUInt(reset)
node _T_2202 = eq(_T_2201, UInt<1>(0h0))
when _T_2202 :
node _T_2203 = eq(_T_2200, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_2200, UInt<1>(0h1), "") : assert_104
node _T_2204 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2205 = orr(a_set_wo_ready)
node _T_2206 = eq(_T_2205, UInt<1>(0h0))
node _T_2207 = or(_T_2204, _T_2206)
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
node _T_2210 = eq(_T_2207, UInt<1>(0h0))
when _T_2210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_2207, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_38
node _T_2211 = orr(inflight)
node _T_2212 = eq(_T_2211, UInt<1>(0h0))
node _T_2213 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2214 = or(_T_2212, _T_2213)
node _T_2215 = lt(watchdog, plusarg_reader.out)
node _T_2216 = or(_T_2214, _T_2215)
node _T_2217 = asUInt(reset)
node _T_2218 = eq(_T_2217, UInt<1>(0h0))
when _T_2218 :
node _T_2219 = eq(_T_2216, UInt<1>(0h0))
when _T_2219 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_2216, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2220 = and(io.in.a.ready, io.in.a.valid)
node _T_2221 = and(io.in.d.ready, io.in.d.valid)
node _T_2222 = or(_T_2220, _T_2221)
when _T_2222 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_2223 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_2224 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_2225 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_2226 = and(_T_2224, _T_2225)
node _T_2227 = and(_T_2223, _T_2226)
when _T_2227 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_2228 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_2229 = and(_T_2228, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_2230 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_2231 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_2232 = and(_T_2230, _T_2231)
node _T_2233 = and(_T_2229, _T_2232)
when _T_2233 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_2234 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_2235 = bits(_T_2234, 0, 0)
node _T_2236 = eq(_T_2235, UInt<1>(0h0))
node _T_2237 = asUInt(reset)
node _T_2238 = eq(_T_2237, UInt<1>(0h0))
when _T_2238 :
node _T_2239 = eq(_T_2236, UInt<1>(0h0))
when _T_2239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_2236, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2240 = and(io.in.d.valid, d_first_2)
node _T_2241 = and(_T_2240, UInt<1>(0h1))
node _T_2242 = and(_T_2241, d_release_ack_1)
when _T_2242 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2243 = and(io.in.d.ready, io.in.d.valid)
node _T_2244 = and(_T_2243, d_first_2)
node _T_2245 = and(_T_2244, UInt<1>(0h1))
node _T_2246 = and(_T_2245, d_release_ack_1)
when _T_2246 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2247 = and(io.in.d.valid, d_first_2)
node _T_2248 = and(_T_2247, UInt<1>(0h1))
node _T_2249 = and(_T_2248, d_release_ack_1)
when _T_2249 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2250 = dshr(inflight_1, io.in.d.bits.source)
node _T_2251 = bits(_T_2250, 0, 0)
node _T_2252 = or(_T_2251, same_cycle_resp_1)
node _T_2253 = asUInt(reset)
node _T_2254 = eq(_T_2253, UInt<1>(0h0))
when _T_2254 :
node _T_2255 = eq(_T_2252, UInt<1>(0h0))
when _T_2255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_2252, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_2256 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_2257 = asUInt(reset)
node _T_2258 = eq(_T_2257, UInt<1>(0h0))
when _T_2258 :
node _T_2259 = eq(_T_2256, UInt<1>(0h0))
when _T_2259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_2256, UInt<1>(0h1), "") : assert_109
else :
node _T_2260 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2261 = asUInt(reset)
node _T_2262 = eq(_T_2261, UInt<1>(0h0))
when _T_2262 :
node _T_2263 = eq(_T_2260, UInt<1>(0h0))
when _T_2263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_2260, UInt<1>(0h1), "") : assert_110
node _T_2264 = and(io.in.d.valid, d_first_2)
node _T_2265 = and(_T_2264, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_2266 = and(_T_2265, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_2267 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_2268 = and(_T_2266, _T_2267)
node _T_2269 = and(_T_2268, d_release_ack_1)
node _T_2270 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2271 = and(_T_2269, _T_2270)
when _T_2271 :
node _T_2272 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_2273 = or(_T_2272, _WIRE_27.ready)
node _T_2274 = asUInt(reset)
node _T_2275 = eq(_T_2274, UInt<1>(0h0))
when _T_2275 :
node _T_2276 = eq(_T_2273, UInt<1>(0h0))
when _T_2276 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_2273, UInt<1>(0h1), "") : assert_111
node _T_2277 = orr(c_set_wo_ready)
when _T_2277 :
node _T_2278 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2279 = asUInt(reset)
node _T_2280 = eq(_T_2279, UInt<1>(0h0))
when _T_2280 :
node _T_2281 = eq(_T_2278, UInt<1>(0h0))
when _T_2281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_2278, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_39
node _T_2282 = orr(inflight_1)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
node _T_2284 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2285 = or(_T_2283, _T_2284)
node _T_2286 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2287 = or(_T_2285, _T_2286)
node _T_2288 = asUInt(reset)
node _T_2289 = eq(_T_2288, UInt<1>(0h0))
when _T_2289 :
node _T_2290 = eq(_T_2287, UInt<1>(0h0))
when _T_2290 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_2287, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_2291 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_2292 = and(io.in.d.ready, io.in.d.valid)
node _T_2293 = or(_T_2291, _T_2292)
when _T_2293 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31]
wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31]
wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31]
wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31]
wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31]
wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31]
wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31]
wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31]
wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31]
wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31]
wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31]
wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31]
wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31]
wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31]
wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31]
wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31]
wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31]
wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31]
wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31]
wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31]
wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31]
wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46]
wire _T_2220 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2220; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2220; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_2293 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2293; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2293; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2293; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2146 = _T_2220 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2146 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2146 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2146 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2146 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2146 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_2192 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2192 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2161 = _T_2293 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2161 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2161 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2161 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2264 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2264 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_2246 = _T_2293 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2246 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2246 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2246 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_43 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_51
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_43( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_51 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_cbus_out_i1_o8_a29d64s7k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.user.amba_prot.fetch
invalidate anonIn.a.bits.user.amba_prot.secure
invalidate anonIn.a.bits.user.amba_prot.privileged
invalidate anonIn.a.bits.user.amba_prot.writealloc
invalidate anonIn.a.bits.user.amba_prot.readalloc
invalidate anonIn.a.bits.user.amba_prot.modifiable
invalidate anonIn.a.bits.user.amba_prot.bufferable
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_18
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
wire x1_anonOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_1.d.bits.corrupt
invalidate x1_anonOut_1.d.bits.data
invalidate x1_anonOut_1.d.bits.denied
invalidate x1_anonOut_1.d.bits.sink
invalidate x1_anonOut_1.d.bits.source
invalidate x1_anonOut_1.d.bits.size
invalidate x1_anonOut_1.d.bits.param
invalidate x1_anonOut_1.d.bits.opcode
invalidate x1_anonOut_1.d.valid
invalidate x1_anonOut_1.d.ready
invalidate x1_anonOut_1.a.bits.corrupt
invalidate x1_anonOut_1.a.bits.data
invalidate x1_anonOut_1.a.bits.mask
invalidate x1_anonOut_1.a.bits.user.amba_prot.fetch
invalidate x1_anonOut_1.a.bits.user.amba_prot.secure
invalidate x1_anonOut_1.a.bits.user.amba_prot.privileged
invalidate x1_anonOut_1.a.bits.user.amba_prot.writealloc
invalidate x1_anonOut_1.a.bits.user.amba_prot.readalloc
invalidate x1_anonOut_1.a.bits.user.amba_prot.modifiable
invalidate x1_anonOut_1.a.bits.user.amba_prot.bufferable
invalidate x1_anonOut_1.a.bits.address
invalidate x1_anonOut_1.a.bits.source
invalidate x1_anonOut_1.a.bits.size
invalidate x1_anonOut_1.a.bits.param
invalidate x1_anonOut_1.a.bits.opcode
invalidate x1_anonOut_1.a.valid
invalidate x1_anonOut_1.a.ready
wire x1_anonOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_2.d.bits.corrupt
invalidate x1_anonOut_2.d.bits.data
invalidate x1_anonOut_2.d.bits.denied
invalidate x1_anonOut_2.d.bits.sink
invalidate x1_anonOut_2.d.bits.source
invalidate x1_anonOut_2.d.bits.size
invalidate x1_anonOut_2.d.bits.param
invalidate x1_anonOut_2.d.bits.opcode
invalidate x1_anonOut_2.d.valid
invalidate x1_anonOut_2.d.ready
invalidate x1_anonOut_2.a.bits.corrupt
invalidate x1_anonOut_2.a.bits.data
invalidate x1_anonOut_2.a.bits.mask
invalidate x1_anonOut_2.a.bits.address
invalidate x1_anonOut_2.a.bits.source
invalidate x1_anonOut_2.a.bits.size
invalidate x1_anonOut_2.a.bits.param
invalidate x1_anonOut_2.a.bits.opcode
invalidate x1_anonOut_2.a.valid
invalidate x1_anonOut_2.a.ready
wire x1_anonOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_3.d.bits.corrupt
invalidate x1_anonOut_3.d.bits.data
invalidate x1_anonOut_3.d.bits.denied
invalidate x1_anonOut_3.d.bits.sink
invalidate x1_anonOut_3.d.bits.source
invalidate x1_anonOut_3.d.bits.size
invalidate x1_anonOut_3.d.bits.param
invalidate x1_anonOut_3.d.bits.opcode
invalidate x1_anonOut_3.d.valid
invalidate x1_anonOut_3.d.ready
invalidate x1_anonOut_3.a.bits.corrupt
invalidate x1_anonOut_3.a.bits.data
invalidate x1_anonOut_3.a.bits.mask
invalidate x1_anonOut_3.a.bits.address
invalidate x1_anonOut_3.a.bits.source
invalidate x1_anonOut_3.a.bits.size
invalidate x1_anonOut_3.a.bits.param
invalidate x1_anonOut_3.a.bits.opcode
invalidate x1_anonOut_3.a.valid
invalidate x1_anonOut_3.a.ready
wire x1_anonOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_4.d.bits.corrupt
invalidate x1_anonOut_4.d.bits.data
invalidate x1_anonOut_4.d.bits.denied
invalidate x1_anonOut_4.d.bits.sink
invalidate x1_anonOut_4.d.bits.source
invalidate x1_anonOut_4.d.bits.size
invalidate x1_anonOut_4.d.bits.param
invalidate x1_anonOut_4.d.bits.opcode
invalidate x1_anonOut_4.d.valid
invalidate x1_anonOut_4.d.ready
invalidate x1_anonOut_4.a.bits.corrupt
invalidate x1_anonOut_4.a.bits.data
invalidate x1_anonOut_4.a.bits.mask
invalidate x1_anonOut_4.a.bits.address
invalidate x1_anonOut_4.a.bits.source
invalidate x1_anonOut_4.a.bits.size
invalidate x1_anonOut_4.a.bits.param
invalidate x1_anonOut_4.a.bits.opcode
invalidate x1_anonOut_4.a.valid
invalidate x1_anonOut_4.a.ready
wire x1_anonOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_5.d.bits.corrupt
invalidate x1_anonOut_5.d.bits.data
invalidate x1_anonOut_5.d.bits.denied
invalidate x1_anonOut_5.d.bits.sink
invalidate x1_anonOut_5.d.bits.source
invalidate x1_anonOut_5.d.bits.size
invalidate x1_anonOut_5.d.bits.param
invalidate x1_anonOut_5.d.bits.opcode
invalidate x1_anonOut_5.d.valid
invalidate x1_anonOut_5.d.ready
invalidate x1_anonOut_5.a.bits.corrupt
invalidate x1_anonOut_5.a.bits.data
invalidate x1_anonOut_5.a.bits.mask
invalidate x1_anonOut_5.a.bits.address
invalidate x1_anonOut_5.a.bits.source
invalidate x1_anonOut_5.a.bits.size
invalidate x1_anonOut_5.a.bits.param
invalidate x1_anonOut_5.a.bits.opcode
invalidate x1_anonOut_5.a.valid
invalidate x1_anonOut_5.a.ready
wire x1_anonOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut_6.d.bits.corrupt
invalidate x1_anonOut_6.d.bits.data
invalidate x1_anonOut_6.d.bits.denied
invalidate x1_anonOut_6.d.bits.sink
invalidate x1_anonOut_6.d.bits.source
invalidate x1_anonOut_6.d.bits.size
invalidate x1_anonOut_6.d.bits.param
invalidate x1_anonOut_6.d.bits.opcode
invalidate x1_anonOut_6.d.valid
invalidate x1_anonOut_6.d.ready
invalidate x1_anonOut_6.a.bits.corrupt
invalidate x1_anonOut_6.a.bits.data
invalidate x1_anonOut_6.a.bits.mask
invalidate x1_anonOut_6.a.bits.address
invalidate x1_anonOut_6.a.bits.source
invalidate x1_anonOut_6.a.bits.size
invalidate x1_anonOut_6.a.bits.param
invalidate x1_anonOut_6.a.bits.opcode
invalidate x1_anonOut_6.a.valid
invalidate x1_anonOut_6.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect auto.anon_out_2, x1_anonOut_1
connect auto.anon_out_3, x1_anonOut_2
connect auto.anon_out_4, x1_anonOut_3
connect auto.anon_out_5, x1_anonOut_4
connect auto.anon_out_6, x1_anonOut_5
connect auto.anon_out_7, x1_anonOut_6
connect anonIn, auto.anon_in
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
invalidate in[0].a.bits.user.amba_prot.fetch
invalidate in[0].a.bits.user.amba_prot.secure
invalidate in[0].a.bits.user.amba_prot.privileged
invalidate in[0].a.bits.user.amba_prot.writealloc
invalidate in[0].a.bits.user.amba_prot.readalloc
invalidate in[0].a.bits.user.amba_prot.modifiable
invalidate in[0].a.bits.user.amba_prot.bufferable
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.user.amba_prot.fetch
invalidate _WIRE_9.bits.user.amba_prot.secure
invalidate _WIRE_9.bits.user.amba_prot.privileged
invalidate _WIRE_9.bits.user.amba_prot.writealloc
invalidate _WIRE_9.bits.user.amba_prot.readalloc
invalidate _WIRE_9.bits.user.amba_prot.modifiable
invalidate _WIRE_9.bits.user.amba_prot.bufferable
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.user.amba_prot.fetch
invalidate _WIRE_11.bits.user.amba_prot.secure
invalidate _WIRE_11.bits.user.amba_prot.privileged
invalidate _WIRE_11.bits.user.amba_prot.writealloc
invalidate _WIRE_11.bits.user.amba_prot.readalloc
invalidate _WIRE_11.bits.user.amba_prot.modifiable
invalidate _WIRE_11.bits.user.amba_prot.bufferable
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 6, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[8]
invalidate out[0].a.bits.user.amba_prot.fetch
invalidate out[0].a.bits.user.amba_prot.secure
invalidate out[0].a.bits.user.amba_prot.privileged
invalidate out[0].a.bits.user.amba_prot.writealloc
invalidate out[0].a.bits.user.amba_prot.readalloc
invalidate out[0].a.bits.user.amba_prot.modifiable
invalidate out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<14>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.valid, UInt<1>(0h0)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<14>(0h0)
connect _WIRE_30.bits.source, UInt<7>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.ready, UInt<1>(0h1)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_32.bits.address, UInt<29>(0h0)
connect _WIRE_32.bits.source, UInt<7>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.user.amba_prot.fetch
invalidate _WIRE_33.bits.user.amba_prot.secure
invalidate _WIRE_33.bits.user.amba_prot.privileged
invalidate _WIRE_33.bits.user.amba_prot.writealloc
invalidate _WIRE_33.bits.user.amba_prot.readalloc
invalidate _WIRE_33.bits.user.amba_prot.modifiable
invalidate _WIRE_33.bits.user.amba_prot.bufferable
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<14>(0h0)
connect _WIRE_34.bits.source, UInt<7>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_36.bits.address, UInt<29>(0h0)
connect _WIRE_36.bits.source, UInt<7>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.ready, UInt<1>(0h1)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<14>(0h0)
connect _WIRE_38.bits.source, UInt<7>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.ready, UInt<1>(0h1)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.valid, UInt<1>(0h0)
invalidate out[1].a.bits.user.amba_prot.fetch
invalidate out[1].a.bits.user.amba_prot.secure
invalidate out[1].a.bits.user.amba_prot.privileged
invalidate out[1].a.bits.user.amba_prot.writealloc
invalidate out[1].a.bits.user.amba_prot.readalloc
invalidate out[1].a.bits.user.amba_prot.modifiable
invalidate out[1].a.bits.user.amba_prot.bufferable
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<29>(0h0)
connect _WIRE_48.bits.source, UInt<7>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<26>(0h0)
connect _WIRE_50.bits.source, UInt<7>(0h0)
connect _WIRE_50.bits.size, UInt<3>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<29>(0h0)
connect _WIRE_52.bits.source, UInt<7>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<26>(0h0)
connect _WIRE_54.bits.source, UInt<7>(0h0)
connect _WIRE_54.bits.size, UInt<3>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_56.bits.address, UInt<29>(0h0)
connect _WIRE_56.bits.source, UInt<7>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.user.amba_prot.fetch
invalidate _WIRE_57.bits.user.amba_prot.secure
invalidate _WIRE_57.bits.user.amba_prot.privileged
invalidate _WIRE_57.bits.user.amba_prot.writealloc
invalidate _WIRE_57.bits.user.amba_prot.readalloc
invalidate _WIRE_57.bits.user.amba_prot.modifiable
invalidate _WIRE_57.bits.user.amba_prot.bufferable
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<26>(0h0)
connect _WIRE_58.bits.source, UInt<7>(0h0)
connect _WIRE_58.bits.size, UInt<3>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_60.bits.address, UInt<29>(0h0)
connect _WIRE_60.bits.source, UInt<7>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<26>(0h0)
connect _WIRE_62.bits.source, UInt<7>(0h0)
connect _WIRE_62.bits.size, UInt<3>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
invalidate out[2].a.bits.user.amba_prot.fetch
invalidate out[2].a.bits.user.amba_prot.secure
invalidate out[2].a.bits.user.amba_prot.privileged
invalidate out[2].a.bits.user.amba_prot.writealloc
invalidate out[2].a.bits.user.amba_prot.readalloc
invalidate out[2].a.bits.user.amba_prot.modifiable
invalidate out[2].a.bits.user.amba_prot.bufferable
connect x1_anonOut_1.a.bits.corrupt, out[2].a.bits.corrupt
connect x1_anonOut_1.a.bits.data, out[2].a.bits.data
connect x1_anonOut_1.a.bits.mask, out[2].a.bits.mask
connect x1_anonOut_1.a.bits.user.amba_prot.fetch, out[2].a.bits.user.amba_prot.fetch
connect x1_anonOut_1.a.bits.user.amba_prot.secure, out[2].a.bits.user.amba_prot.secure
connect x1_anonOut_1.a.bits.user.amba_prot.privileged, out[2].a.bits.user.amba_prot.privileged
connect x1_anonOut_1.a.bits.user.amba_prot.writealloc, out[2].a.bits.user.amba_prot.writealloc
connect x1_anonOut_1.a.bits.user.amba_prot.readalloc, out[2].a.bits.user.amba_prot.readalloc
connect x1_anonOut_1.a.bits.user.amba_prot.modifiable, out[2].a.bits.user.amba_prot.modifiable
connect x1_anonOut_1.a.bits.user.amba_prot.bufferable, out[2].a.bits.user.amba_prot.bufferable
connect x1_anonOut_1.a.bits.address, out[2].a.bits.address
connect x1_anonOut_1.a.bits.source, out[2].a.bits.source
connect x1_anonOut_1.a.bits.size, out[2].a.bits.size
connect x1_anonOut_1.a.bits.param, out[2].a.bits.param
connect x1_anonOut_1.a.bits.opcode, out[2].a.bits.opcode
connect x1_anonOut_1.a.valid, out[2].a.valid
connect out[2].a.ready, x1_anonOut_1.a.ready
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.mask, UInt<8>(0h0)
connect _WIRE_72.bits.address, UInt<29>(0h0)
connect _WIRE_72.bits.source, UInt<7>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<2>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.mask
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
invalidate _WIRE_73.valid
invalidate _WIRE_73.ready
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_74.bits.corrupt, UInt<1>(0h0)
connect _WIRE_74.bits.data, UInt<64>(0h0)
connect _WIRE_74.bits.mask, UInt<8>(0h0)
connect _WIRE_74.bits.address, UInt<29>(0h0)
connect _WIRE_74.bits.source, UInt<7>(0h0)
connect _WIRE_74.bits.size, UInt<3>(0h0)
connect _WIRE_74.bits.param, UInt<2>(0h0)
connect _WIRE_74.bits.opcode, UInt<3>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.corrupt
invalidate _WIRE_75.bits.data
invalidate _WIRE_75.bits.mask
invalidate _WIRE_75.bits.address
invalidate _WIRE_75.bits.source
invalidate _WIRE_75.bits.size
invalidate _WIRE_75.bits.param
invalidate _WIRE_75.bits.opcode
invalidate _WIRE_75.valid
invalidate _WIRE_75.ready
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<29>(0h0)
connect _WIRE_76.bits.source, UInt<7>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
connect _WIRE_77.valid, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<29>(0h0)
connect _WIRE_78.bits.source, UInt<7>(0h0)
connect _WIRE_78.bits.size, UInt<3>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
connect _WIRE_79.ready, UInt<1>(0h1)
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_80.bits.corrupt, UInt<1>(0h0)
connect _WIRE_80.bits.data, UInt<64>(0h0)
connect _WIRE_80.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_80.bits.address, UInt<29>(0h0)
connect _WIRE_80.bits.source, UInt<7>(0h0)
connect _WIRE_80.bits.size, UInt<4>(0h0)
connect _WIRE_80.bits.param, UInt<3>(0h0)
connect _WIRE_80.bits.opcode, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.corrupt
invalidate _WIRE_81.bits.data
invalidate _WIRE_81.bits.user.amba_prot.fetch
invalidate _WIRE_81.bits.user.amba_prot.secure
invalidate _WIRE_81.bits.user.amba_prot.privileged
invalidate _WIRE_81.bits.user.amba_prot.writealloc
invalidate _WIRE_81.bits.user.amba_prot.readalloc
invalidate _WIRE_81.bits.user.amba_prot.modifiable
invalidate _WIRE_81.bits.user.amba_prot.bufferable
invalidate _WIRE_81.bits.address
invalidate _WIRE_81.bits.source
invalidate _WIRE_81.bits.size
invalidate _WIRE_81.bits.param
invalidate _WIRE_81.bits.opcode
invalidate _WIRE_81.valid
invalidate _WIRE_81.ready
wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_82.bits.corrupt, UInt<1>(0h0)
connect _WIRE_82.bits.data, UInt<64>(0h0)
connect _WIRE_82.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_82.bits.address, UInt<29>(0h0)
connect _WIRE_82.bits.source, UInt<7>(0h0)
connect _WIRE_82.bits.size, UInt<3>(0h0)
connect _WIRE_82.bits.param, UInt<3>(0h0)
connect _WIRE_82.bits.opcode, UInt<3>(0h0)
connect _WIRE_82.valid, UInt<1>(0h0)
connect _WIRE_82.ready, UInt<1>(0h0)
wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_83.bits, _WIRE_82.bits
connect _WIRE_83.valid, _WIRE_82.valid
connect _WIRE_83.ready, _WIRE_82.ready
invalidate _WIRE_83.bits.corrupt
invalidate _WIRE_83.bits.data
invalidate _WIRE_83.bits.user.amba_prot.fetch
invalidate _WIRE_83.bits.user.amba_prot.secure
invalidate _WIRE_83.bits.user.amba_prot.privileged
invalidate _WIRE_83.bits.user.amba_prot.writealloc
invalidate _WIRE_83.bits.user.amba_prot.readalloc
invalidate _WIRE_83.bits.user.amba_prot.modifiable
invalidate _WIRE_83.bits.user.amba_prot.bufferable
invalidate _WIRE_83.bits.address
invalidate _WIRE_83.bits.source
invalidate _WIRE_83.bits.size
invalidate _WIRE_83.bits.param
invalidate _WIRE_83.bits.opcode
invalidate _WIRE_83.valid
invalidate _WIRE_83.ready
wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_84.bits.corrupt, UInt<1>(0h0)
connect _WIRE_84.bits.data, UInt<64>(0h0)
connect _WIRE_84.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_84.bits.address, UInt<29>(0h0)
connect _WIRE_84.bits.source, UInt<7>(0h0)
connect _WIRE_84.bits.size, UInt<4>(0h0)
connect _WIRE_84.bits.param, UInt<3>(0h0)
connect _WIRE_84.bits.opcode, UInt<3>(0h0)
connect _WIRE_84.valid, UInt<1>(0h0)
connect _WIRE_84.ready, UInt<1>(0h0)
wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_85.bits, _WIRE_84.bits
connect _WIRE_85.valid, _WIRE_84.valid
connect _WIRE_85.ready, _WIRE_84.ready
connect _WIRE_85.ready, UInt<1>(0h1)
wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_86.bits.corrupt, UInt<1>(0h0)
connect _WIRE_86.bits.data, UInt<64>(0h0)
connect _WIRE_86.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_86.bits.address, UInt<29>(0h0)
connect _WIRE_86.bits.source, UInt<7>(0h0)
connect _WIRE_86.bits.size, UInt<3>(0h0)
connect _WIRE_86.bits.param, UInt<3>(0h0)
connect _WIRE_86.bits.opcode, UInt<3>(0h0)
connect _WIRE_86.valid, UInt<1>(0h0)
connect _WIRE_86.ready, UInt<1>(0h0)
wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_87.bits, _WIRE_86.bits
connect _WIRE_87.valid, _WIRE_86.valid
connect _WIRE_87.ready, _WIRE_86.ready
connect _WIRE_87.valid, UInt<1>(0h0)
connect out[2].d.bits.corrupt, x1_anonOut_1.d.bits.corrupt
connect out[2].d.bits.data, x1_anonOut_1.d.bits.data
connect out[2].d.bits.denied, x1_anonOut_1.d.bits.denied
connect out[2].d.bits.sink, x1_anonOut_1.d.bits.sink
connect out[2].d.bits.source, x1_anonOut_1.d.bits.source
connect out[2].d.bits.size, x1_anonOut_1.d.bits.size
connect out[2].d.bits.param, x1_anonOut_1.d.bits.param
connect out[2].d.bits.opcode, x1_anonOut_1.d.bits.opcode
connect out[2].d.valid, x1_anonOut_1.d.valid
connect x1_anonOut_1.d.ready, out[2].d.ready
node _out_2_d_bits_sink_T = or(x1_anonOut_1.d.bits.sink, UInt<1>(0h0))
connect out[2].d.bits.sink, _out_2_d_bits_sink_T
wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_88.bits.sink, UInt<1>(0h0)
connect _WIRE_88.valid, UInt<1>(0h0)
connect _WIRE_88.ready, UInt<1>(0h0)
wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_89.bits, _WIRE_88.bits
connect _WIRE_89.valid, _WIRE_88.valid
connect _WIRE_89.ready, _WIRE_88.ready
invalidate _WIRE_89.bits.sink
invalidate _WIRE_89.valid
invalidate _WIRE_89.ready
wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_90.bits.sink, UInt<1>(0h0)
connect _WIRE_90.valid, UInt<1>(0h0)
connect _WIRE_90.ready, UInt<1>(0h0)
wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_91.bits, _WIRE_90.bits
connect _WIRE_91.valid, _WIRE_90.valid
connect _WIRE_91.ready, _WIRE_90.ready
invalidate _WIRE_91.bits.sink
invalidate _WIRE_91.valid
invalidate _WIRE_91.ready
wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_92.bits.sink, UInt<1>(0h0)
connect _WIRE_92.valid, UInt<1>(0h0)
connect _WIRE_92.ready, UInt<1>(0h0)
wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_93.bits, _WIRE_92.bits
connect _WIRE_93.valid, _WIRE_92.valid
connect _WIRE_93.ready, _WIRE_92.ready
connect _WIRE_93.ready, UInt<1>(0h1)
wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_94.bits.sink, UInt<1>(0h0)
connect _WIRE_94.valid, UInt<1>(0h0)
connect _WIRE_94.ready, UInt<1>(0h0)
wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_95.bits, _WIRE_94.bits
connect _WIRE_95.valid, _WIRE_94.valid
connect _WIRE_95.ready, _WIRE_94.ready
connect _WIRE_95.valid, UInt<1>(0h0)
invalidate out[3].a.bits.user.amba_prot.fetch
invalidate out[3].a.bits.user.amba_prot.secure
invalidate out[3].a.bits.user.amba_prot.privileged
invalidate out[3].a.bits.user.amba_prot.writealloc
invalidate out[3].a.bits.user.amba_prot.readalloc
invalidate out[3].a.bits.user.amba_prot.modifiable
invalidate out[3].a.bits.user.amba_prot.bufferable
connect x1_anonOut_2.a.bits.corrupt, out[3].a.bits.corrupt
connect x1_anonOut_2.a.bits.data, out[3].a.bits.data
connect x1_anonOut_2.a.bits.mask, out[3].a.bits.mask
connect x1_anonOut_2.a.bits.address, out[3].a.bits.address
connect x1_anonOut_2.a.bits.source, out[3].a.bits.source
connect x1_anonOut_2.a.bits.size, out[3].a.bits.size
connect x1_anonOut_2.a.bits.param, out[3].a.bits.param
connect x1_anonOut_2.a.bits.opcode, out[3].a.bits.opcode
connect x1_anonOut_2.a.valid, out[3].a.valid
connect out[3].a.ready, x1_anonOut_2.a.ready
wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_96.bits.corrupt, UInt<1>(0h0)
connect _WIRE_96.bits.data, UInt<64>(0h0)
connect _WIRE_96.bits.mask, UInt<8>(0h0)
connect _WIRE_96.bits.address, UInt<29>(0h0)
connect _WIRE_96.bits.source, UInt<7>(0h0)
connect _WIRE_96.bits.size, UInt<4>(0h0)
connect _WIRE_96.bits.param, UInt<2>(0h0)
connect _WIRE_96.bits.opcode, UInt<3>(0h0)
connect _WIRE_96.valid, UInt<1>(0h0)
connect _WIRE_96.ready, UInt<1>(0h0)
wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_97.bits, _WIRE_96.bits
connect _WIRE_97.valid, _WIRE_96.valid
connect _WIRE_97.ready, _WIRE_96.ready
invalidate _WIRE_97.bits.corrupt
invalidate _WIRE_97.bits.data
invalidate _WIRE_97.bits.mask
invalidate _WIRE_97.bits.address
invalidate _WIRE_97.bits.source
invalidate _WIRE_97.bits.size
invalidate _WIRE_97.bits.param
invalidate _WIRE_97.bits.opcode
invalidate _WIRE_97.valid
invalidate _WIRE_97.ready
wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_98.bits.corrupt, UInt<1>(0h0)
connect _WIRE_98.bits.data, UInt<64>(0h0)
connect _WIRE_98.bits.mask, UInt<8>(0h0)
connect _WIRE_98.bits.address, UInt<26>(0h0)
connect _WIRE_98.bits.source, UInt<7>(0h0)
connect _WIRE_98.bits.size, UInt<3>(0h0)
connect _WIRE_98.bits.param, UInt<2>(0h0)
connect _WIRE_98.bits.opcode, UInt<3>(0h0)
connect _WIRE_98.valid, UInt<1>(0h0)
connect _WIRE_98.ready, UInt<1>(0h0)
wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_99.bits, _WIRE_98.bits
connect _WIRE_99.valid, _WIRE_98.valid
connect _WIRE_99.ready, _WIRE_98.ready
invalidate _WIRE_99.bits.corrupt
invalidate _WIRE_99.bits.data
invalidate _WIRE_99.bits.mask
invalidate _WIRE_99.bits.address
invalidate _WIRE_99.bits.source
invalidate _WIRE_99.bits.size
invalidate _WIRE_99.bits.param
invalidate _WIRE_99.bits.opcode
invalidate _WIRE_99.valid
invalidate _WIRE_99.ready
wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_100.bits.corrupt, UInt<1>(0h0)
connect _WIRE_100.bits.data, UInt<64>(0h0)
connect _WIRE_100.bits.mask, UInt<8>(0h0)
connect _WIRE_100.bits.address, UInt<29>(0h0)
connect _WIRE_100.bits.source, UInt<7>(0h0)
connect _WIRE_100.bits.size, UInt<4>(0h0)
connect _WIRE_100.bits.param, UInt<2>(0h0)
connect _WIRE_100.bits.opcode, UInt<3>(0h0)
connect _WIRE_100.valid, UInt<1>(0h0)
connect _WIRE_100.ready, UInt<1>(0h0)
wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_101.bits, _WIRE_100.bits
connect _WIRE_101.valid, _WIRE_100.valid
connect _WIRE_101.ready, _WIRE_100.ready
connect _WIRE_101.valid, UInt<1>(0h0)
wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_102.bits.corrupt, UInt<1>(0h0)
connect _WIRE_102.bits.data, UInt<64>(0h0)
connect _WIRE_102.bits.mask, UInt<8>(0h0)
connect _WIRE_102.bits.address, UInt<26>(0h0)
connect _WIRE_102.bits.source, UInt<7>(0h0)
connect _WIRE_102.bits.size, UInt<3>(0h0)
connect _WIRE_102.bits.param, UInt<2>(0h0)
connect _WIRE_102.bits.opcode, UInt<3>(0h0)
connect _WIRE_102.valid, UInt<1>(0h0)
connect _WIRE_102.ready, UInt<1>(0h0)
wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_103.bits, _WIRE_102.bits
connect _WIRE_103.valid, _WIRE_102.valid
connect _WIRE_103.ready, _WIRE_102.ready
connect _WIRE_103.ready, UInt<1>(0h1)
wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_104.bits.corrupt, UInt<1>(0h0)
connect _WIRE_104.bits.data, UInt<64>(0h0)
connect _WIRE_104.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_104.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_104.bits.address, UInt<29>(0h0)
connect _WIRE_104.bits.source, UInt<7>(0h0)
connect _WIRE_104.bits.size, UInt<4>(0h0)
connect _WIRE_104.bits.param, UInt<3>(0h0)
connect _WIRE_104.bits.opcode, UInt<3>(0h0)
connect _WIRE_104.valid, UInt<1>(0h0)
connect _WIRE_104.ready, UInt<1>(0h0)
wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_105.bits, _WIRE_104.bits
connect _WIRE_105.valid, _WIRE_104.valid
connect _WIRE_105.ready, _WIRE_104.ready
invalidate _WIRE_105.bits.corrupt
invalidate _WIRE_105.bits.data
invalidate _WIRE_105.bits.user.amba_prot.fetch
invalidate _WIRE_105.bits.user.amba_prot.secure
invalidate _WIRE_105.bits.user.amba_prot.privileged
invalidate _WIRE_105.bits.user.amba_prot.writealloc
invalidate _WIRE_105.bits.user.amba_prot.readalloc
invalidate _WIRE_105.bits.user.amba_prot.modifiable
invalidate _WIRE_105.bits.user.amba_prot.bufferable
invalidate _WIRE_105.bits.address
invalidate _WIRE_105.bits.source
invalidate _WIRE_105.bits.size
invalidate _WIRE_105.bits.param
invalidate _WIRE_105.bits.opcode
invalidate _WIRE_105.valid
invalidate _WIRE_105.ready
wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_106.bits.corrupt, UInt<1>(0h0)
connect _WIRE_106.bits.data, UInt<64>(0h0)
connect _WIRE_106.bits.address, UInt<26>(0h0)
connect _WIRE_106.bits.source, UInt<7>(0h0)
connect _WIRE_106.bits.size, UInt<3>(0h0)
connect _WIRE_106.bits.param, UInt<3>(0h0)
connect _WIRE_106.bits.opcode, UInt<3>(0h0)
connect _WIRE_106.valid, UInt<1>(0h0)
connect _WIRE_106.ready, UInt<1>(0h0)
wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_107.bits, _WIRE_106.bits
connect _WIRE_107.valid, _WIRE_106.valid
connect _WIRE_107.ready, _WIRE_106.ready
invalidate _WIRE_107.bits.corrupt
invalidate _WIRE_107.bits.data
invalidate _WIRE_107.bits.address
invalidate _WIRE_107.bits.source
invalidate _WIRE_107.bits.size
invalidate _WIRE_107.bits.param
invalidate _WIRE_107.bits.opcode
invalidate _WIRE_107.valid
invalidate _WIRE_107.ready
wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_108.bits.corrupt, UInt<1>(0h0)
connect _WIRE_108.bits.data, UInt<64>(0h0)
connect _WIRE_108.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_108.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_108.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_108.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_108.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_108.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_108.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_108.bits.address, UInt<29>(0h0)
connect _WIRE_108.bits.source, UInt<7>(0h0)
connect _WIRE_108.bits.size, UInt<4>(0h0)
connect _WIRE_108.bits.param, UInt<3>(0h0)
connect _WIRE_108.bits.opcode, UInt<3>(0h0)
connect _WIRE_108.valid, UInt<1>(0h0)
connect _WIRE_108.ready, UInt<1>(0h0)
wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_109.bits, _WIRE_108.bits
connect _WIRE_109.valid, _WIRE_108.valid
connect _WIRE_109.ready, _WIRE_108.ready
connect _WIRE_109.ready, UInt<1>(0h1)
wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_110.bits.corrupt, UInt<1>(0h0)
connect _WIRE_110.bits.data, UInt<64>(0h0)
connect _WIRE_110.bits.address, UInt<26>(0h0)
connect _WIRE_110.bits.source, UInt<7>(0h0)
connect _WIRE_110.bits.size, UInt<3>(0h0)
connect _WIRE_110.bits.param, UInt<3>(0h0)
connect _WIRE_110.bits.opcode, UInt<3>(0h0)
connect _WIRE_110.valid, UInt<1>(0h0)
connect _WIRE_110.ready, UInt<1>(0h0)
wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_111.bits, _WIRE_110.bits
connect _WIRE_111.valid, _WIRE_110.valid
connect _WIRE_111.ready, _WIRE_110.ready
connect _WIRE_111.valid, UInt<1>(0h0)
connect out[3].d.bits.corrupt, x1_anonOut_2.d.bits.corrupt
connect out[3].d.bits.data, x1_anonOut_2.d.bits.data
connect out[3].d.bits.denied, x1_anonOut_2.d.bits.denied
connect out[3].d.bits.sink, x1_anonOut_2.d.bits.sink
connect out[3].d.bits.source, x1_anonOut_2.d.bits.source
connect out[3].d.bits.size, x1_anonOut_2.d.bits.size
connect out[3].d.bits.param, x1_anonOut_2.d.bits.param
connect out[3].d.bits.opcode, x1_anonOut_2.d.bits.opcode
connect out[3].d.valid, x1_anonOut_2.d.valid
connect x1_anonOut_2.d.ready, out[3].d.ready
node _out_3_d_bits_sink_T = or(x1_anonOut_2.d.bits.sink, UInt<1>(0h0))
connect out[3].d.bits.sink, _out_3_d_bits_sink_T
wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_112.bits.sink, UInt<1>(0h0)
connect _WIRE_112.valid, UInt<1>(0h0)
connect _WIRE_112.ready, UInt<1>(0h0)
wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_113.bits, _WIRE_112.bits
connect _WIRE_113.valid, _WIRE_112.valid
connect _WIRE_113.ready, _WIRE_112.ready
invalidate _WIRE_113.bits.sink
invalidate _WIRE_113.valid
invalidate _WIRE_113.ready
wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_114.bits.sink, UInt<1>(0h0)
connect _WIRE_114.valid, UInt<1>(0h0)
connect _WIRE_114.ready, UInt<1>(0h0)
wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_115.bits, _WIRE_114.bits
connect _WIRE_115.valid, _WIRE_114.valid
connect _WIRE_115.ready, _WIRE_114.ready
invalidate _WIRE_115.bits.sink
invalidate _WIRE_115.valid
invalidate _WIRE_115.ready
wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_116.bits.sink, UInt<1>(0h0)
connect _WIRE_116.valid, UInt<1>(0h0)
connect _WIRE_116.ready, UInt<1>(0h0)
wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_117.bits, _WIRE_116.bits
connect _WIRE_117.valid, _WIRE_116.valid
connect _WIRE_117.ready, _WIRE_116.ready
connect _WIRE_117.ready, UInt<1>(0h1)
wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_118.bits.sink, UInt<1>(0h0)
connect _WIRE_118.valid, UInt<1>(0h0)
connect _WIRE_118.ready, UInt<1>(0h0)
wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_119.bits, _WIRE_118.bits
connect _WIRE_119.valid, _WIRE_118.valid
connect _WIRE_119.ready, _WIRE_118.ready
connect _WIRE_119.valid, UInt<1>(0h0)
invalidate out[4].a.bits.user.amba_prot.fetch
invalidate out[4].a.bits.user.amba_prot.secure
invalidate out[4].a.bits.user.amba_prot.privileged
invalidate out[4].a.bits.user.amba_prot.writealloc
invalidate out[4].a.bits.user.amba_prot.readalloc
invalidate out[4].a.bits.user.amba_prot.modifiable
invalidate out[4].a.bits.user.amba_prot.bufferable
connect x1_anonOut_3.a.bits.corrupt, out[4].a.bits.corrupt
connect x1_anonOut_3.a.bits.data, out[4].a.bits.data
connect x1_anonOut_3.a.bits.mask, out[4].a.bits.mask
connect x1_anonOut_3.a.bits.address, out[4].a.bits.address
connect x1_anonOut_3.a.bits.source, out[4].a.bits.source
connect x1_anonOut_3.a.bits.size, out[4].a.bits.size
connect x1_anonOut_3.a.bits.param, out[4].a.bits.param
connect x1_anonOut_3.a.bits.opcode, out[4].a.bits.opcode
connect x1_anonOut_3.a.valid, out[4].a.valid
connect out[4].a.ready, x1_anonOut_3.a.ready
wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_120.bits.corrupt, UInt<1>(0h0)
connect _WIRE_120.bits.data, UInt<64>(0h0)
connect _WIRE_120.bits.mask, UInt<8>(0h0)
connect _WIRE_120.bits.address, UInt<29>(0h0)
connect _WIRE_120.bits.source, UInt<7>(0h0)
connect _WIRE_120.bits.size, UInt<4>(0h0)
connect _WIRE_120.bits.param, UInt<2>(0h0)
connect _WIRE_120.bits.opcode, UInt<3>(0h0)
connect _WIRE_120.valid, UInt<1>(0h0)
connect _WIRE_120.ready, UInt<1>(0h0)
wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_121.bits, _WIRE_120.bits
connect _WIRE_121.valid, _WIRE_120.valid
connect _WIRE_121.ready, _WIRE_120.ready
invalidate _WIRE_121.bits.corrupt
invalidate _WIRE_121.bits.data
invalidate _WIRE_121.bits.mask
invalidate _WIRE_121.bits.address
invalidate _WIRE_121.bits.source
invalidate _WIRE_121.bits.size
invalidate _WIRE_121.bits.param
invalidate _WIRE_121.bits.opcode
invalidate _WIRE_121.valid
invalidate _WIRE_121.ready
wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_122.bits.corrupt, UInt<1>(0h0)
connect _WIRE_122.bits.data, UInt<64>(0h0)
connect _WIRE_122.bits.mask, UInt<8>(0h0)
connect _WIRE_122.bits.address, UInt<28>(0h0)
connect _WIRE_122.bits.source, UInt<7>(0h0)
connect _WIRE_122.bits.size, UInt<3>(0h0)
connect _WIRE_122.bits.param, UInt<2>(0h0)
connect _WIRE_122.bits.opcode, UInt<3>(0h0)
connect _WIRE_122.valid, UInt<1>(0h0)
connect _WIRE_122.ready, UInt<1>(0h0)
wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_123.bits, _WIRE_122.bits
connect _WIRE_123.valid, _WIRE_122.valid
connect _WIRE_123.ready, _WIRE_122.ready
invalidate _WIRE_123.bits.corrupt
invalidate _WIRE_123.bits.data
invalidate _WIRE_123.bits.mask
invalidate _WIRE_123.bits.address
invalidate _WIRE_123.bits.source
invalidate _WIRE_123.bits.size
invalidate _WIRE_123.bits.param
invalidate _WIRE_123.bits.opcode
invalidate _WIRE_123.valid
invalidate _WIRE_123.ready
wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_124.bits.corrupt, UInt<1>(0h0)
connect _WIRE_124.bits.data, UInt<64>(0h0)
connect _WIRE_124.bits.mask, UInt<8>(0h0)
connect _WIRE_124.bits.address, UInt<29>(0h0)
connect _WIRE_124.bits.source, UInt<7>(0h0)
connect _WIRE_124.bits.size, UInt<4>(0h0)
connect _WIRE_124.bits.param, UInt<2>(0h0)
connect _WIRE_124.bits.opcode, UInt<3>(0h0)
connect _WIRE_124.valid, UInt<1>(0h0)
connect _WIRE_124.ready, UInt<1>(0h0)
wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_125.bits, _WIRE_124.bits
connect _WIRE_125.valid, _WIRE_124.valid
connect _WIRE_125.ready, _WIRE_124.ready
connect _WIRE_125.valid, UInt<1>(0h0)
wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_126.bits.corrupt, UInt<1>(0h0)
connect _WIRE_126.bits.data, UInt<64>(0h0)
connect _WIRE_126.bits.mask, UInt<8>(0h0)
connect _WIRE_126.bits.address, UInt<28>(0h0)
connect _WIRE_126.bits.source, UInt<7>(0h0)
connect _WIRE_126.bits.size, UInt<3>(0h0)
connect _WIRE_126.bits.param, UInt<2>(0h0)
connect _WIRE_126.bits.opcode, UInt<3>(0h0)
connect _WIRE_126.valid, UInt<1>(0h0)
connect _WIRE_126.ready, UInt<1>(0h0)
wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_127.bits, _WIRE_126.bits
connect _WIRE_127.valid, _WIRE_126.valid
connect _WIRE_127.ready, _WIRE_126.ready
connect _WIRE_127.ready, UInt<1>(0h1)
wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_128.bits.corrupt, UInt<1>(0h0)
connect _WIRE_128.bits.data, UInt<64>(0h0)
connect _WIRE_128.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_128.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_128.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_128.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_128.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_128.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_128.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_128.bits.address, UInt<29>(0h0)
connect _WIRE_128.bits.source, UInt<7>(0h0)
connect _WIRE_128.bits.size, UInt<4>(0h0)
connect _WIRE_128.bits.param, UInt<3>(0h0)
connect _WIRE_128.bits.opcode, UInt<3>(0h0)
connect _WIRE_128.valid, UInt<1>(0h0)
connect _WIRE_128.ready, UInt<1>(0h0)
wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_129.bits, _WIRE_128.bits
connect _WIRE_129.valid, _WIRE_128.valid
connect _WIRE_129.ready, _WIRE_128.ready
invalidate _WIRE_129.bits.corrupt
invalidate _WIRE_129.bits.data
invalidate _WIRE_129.bits.user.amba_prot.fetch
invalidate _WIRE_129.bits.user.amba_prot.secure
invalidate _WIRE_129.bits.user.amba_prot.privileged
invalidate _WIRE_129.bits.user.amba_prot.writealloc
invalidate _WIRE_129.bits.user.amba_prot.readalloc
invalidate _WIRE_129.bits.user.amba_prot.modifiable
invalidate _WIRE_129.bits.user.amba_prot.bufferable
invalidate _WIRE_129.bits.address
invalidate _WIRE_129.bits.source
invalidate _WIRE_129.bits.size
invalidate _WIRE_129.bits.param
invalidate _WIRE_129.bits.opcode
invalidate _WIRE_129.valid
invalidate _WIRE_129.ready
wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_130.bits.corrupt, UInt<1>(0h0)
connect _WIRE_130.bits.data, UInt<64>(0h0)
connect _WIRE_130.bits.address, UInt<28>(0h0)
connect _WIRE_130.bits.source, UInt<7>(0h0)
connect _WIRE_130.bits.size, UInt<3>(0h0)
connect _WIRE_130.bits.param, UInt<3>(0h0)
connect _WIRE_130.bits.opcode, UInt<3>(0h0)
connect _WIRE_130.valid, UInt<1>(0h0)
connect _WIRE_130.ready, UInt<1>(0h0)
wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_131.bits, _WIRE_130.bits
connect _WIRE_131.valid, _WIRE_130.valid
connect _WIRE_131.ready, _WIRE_130.ready
invalidate _WIRE_131.bits.corrupt
invalidate _WIRE_131.bits.data
invalidate _WIRE_131.bits.address
invalidate _WIRE_131.bits.source
invalidate _WIRE_131.bits.size
invalidate _WIRE_131.bits.param
invalidate _WIRE_131.bits.opcode
invalidate _WIRE_131.valid
invalidate _WIRE_131.ready
wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_132.bits.corrupt, UInt<1>(0h0)
connect _WIRE_132.bits.data, UInt<64>(0h0)
connect _WIRE_132.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_132.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_132.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_132.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_132.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_132.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_132.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_132.bits.address, UInt<29>(0h0)
connect _WIRE_132.bits.source, UInt<7>(0h0)
connect _WIRE_132.bits.size, UInt<4>(0h0)
connect _WIRE_132.bits.param, UInt<3>(0h0)
connect _WIRE_132.bits.opcode, UInt<3>(0h0)
connect _WIRE_132.valid, UInt<1>(0h0)
connect _WIRE_132.ready, UInt<1>(0h0)
wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_133.bits, _WIRE_132.bits
connect _WIRE_133.valid, _WIRE_132.valid
connect _WIRE_133.ready, _WIRE_132.ready
connect _WIRE_133.ready, UInt<1>(0h1)
wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_134.bits.corrupt, UInt<1>(0h0)
connect _WIRE_134.bits.data, UInt<64>(0h0)
connect _WIRE_134.bits.address, UInt<28>(0h0)
connect _WIRE_134.bits.source, UInt<7>(0h0)
connect _WIRE_134.bits.size, UInt<3>(0h0)
connect _WIRE_134.bits.param, UInt<3>(0h0)
connect _WIRE_134.bits.opcode, UInt<3>(0h0)
connect _WIRE_134.valid, UInt<1>(0h0)
connect _WIRE_134.ready, UInt<1>(0h0)
wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_135.bits, _WIRE_134.bits
connect _WIRE_135.valid, _WIRE_134.valid
connect _WIRE_135.ready, _WIRE_134.ready
connect _WIRE_135.valid, UInt<1>(0h0)
connect out[4].d.bits.corrupt, x1_anonOut_3.d.bits.corrupt
connect out[4].d.bits.data, x1_anonOut_3.d.bits.data
connect out[4].d.bits.denied, x1_anonOut_3.d.bits.denied
connect out[4].d.bits.sink, x1_anonOut_3.d.bits.sink
connect out[4].d.bits.source, x1_anonOut_3.d.bits.source
connect out[4].d.bits.size, x1_anonOut_3.d.bits.size
connect out[4].d.bits.param, x1_anonOut_3.d.bits.param
connect out[4].d.bits.opcode, x1_anonOut_3.d.bits.opcode
connect out[4].d.valid, x1_anonOut_3.d.valid
connect x1_anonOut_3.d.ready, out[4].d.ready
node _out_4_d_bits_sink_T = or(x1_anonOut_3.d.bits.sink, UInt<1>(0h0))
connect out[4].d.bits.sink, _out_4_d_bits_sink_T
wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_136.bits.sink, UInt<1>(0h0)
connect _WIRE_136.valid, UInt<1>(0h0)
connect _WIRE_136.ready, UInt<1>(0h0)
wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_137.bits, _WIRE_136.bits
connect _WIRE_137.valid, _WIRE_136.valid
connect _WIRE_137.ready, _WIRE_136.ready
invalidate _WIRE_137.bits.sink
invalidate _WIRE_137.valid
invalidate _WIRE_137.ready
wire _WIRE_138 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_138.bits.sink, UInt<1>(0h0)
connect _WIRE_138.valid, UInt<1>(0h0)
connect _WIRE_138.ready, UInt<1>(0h0)
wire _WIRE_139 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_139.bits, _WIRE_138.bits
connect _WIRE_139.valid, _WIRE_138.valid
connect _WIRE_139.ready, _WIRE_138.ready
invalidate _WIRE_139.bits.sink
invalidate _WIRE_139.valid
invalidate _WIRE_139.ready
wire _WIRE_140 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_140.bits.sink, UInt<1>(0h0)
connect _WIRE_140.valid, UInt<1>(0h0)
connect _WIRE_140.ready, UInt<1>(0h0)
wire _WIRE_141 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_141.bits, _WIRE_140.bits
connect _WIRE_141.valid, _WIRE_140.valid
connect _WIRE_141.ready, _WIRE_140.ready
connect _WIRE_141.ready, UInt<1>(0h1)
wire _WIRE_142 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_142.bits.sink, UInt<1>(0h0)
connect _WIRE_142.valid, UInt<1>(0h0)
connect _WIRE_142.ready, UInt<1>(0h0)
wire _WIRE_143 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_143.bits, _WIRE_142.bits
connect _WIRE_143.valid, _WIRE_142.valid
connect _WIRE_143.ready, _WIRE_142.ready
connect _WIRE_143.valid, UInt<1>(0h0)
invalidate out[5].a.bits.user.amba_prot.fetch
invalidate out[5].a.bits.user.amba_prot.secure
invalidate out[5].a.bits.user.amba_prot.privileged
invalidate out[5].a.bits.user.amba_prot.writealloc
invalidate out[5].a.bits.user.amba_prot.readalloc
invalidate out[5].a.bits.user.amba_prot.modifiable
invalidate out[5].a.bits.user.amba_prot.bufferable
connect x1_anonOut_4.a.bits.corrupt, out[5].a.bits.corrupt
connect x1_anonOut_4.a.bits.data, out[5].a.bits.data
connect x1_anonOut_4.a.bits.mask, out[5].a.bits.mask
connect x1_anonOut_4.a.bits.address, out[5].a.bits.address
connect x1_anonOut_4.a.bits.source, out[5].a.bits.source
connect x1_anonOut_4.a.bits.size, out[5].a.bits.size
connect x1_anonOut_4.a.bits.param, out[5].a.bits.param
connect x1_anonOut_4.a.bits.opcode, out[5].a.bits.opcode
connect x1_anonOut_4.a.valid, out[5].a.valid
connect out[5].a.ready, x1_anonOut_4.a.ready
wire _WIRE_144 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_144.bits.corrupt, UInt<1>(0h0)
connect _WIRE_144.bits.data, UInt<64>(0h0)
connect _WIRE_144.bits.mask, UInt<8>(0h0)
connect _WIRE_144.bits.address, UInt<29>(0h0)
connect _WIRE_144.bits.source, UInt<7>(0h0)
connect _WIRE_144.bits.size, UInt<4>(0h0)
connect _WIRE_144.bits.param, UInt<2>(0h0)
connect _WIRE_144.bits.opcode, UInt<3>(0h0)
connect _WIRE_144.valid, UInt<1>(0h0)
connect _WIRE_144.ready, UInt<1>(0h0)
wire _WIRE_145 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_145.bits, _WIRE_144.bits
connect _WIRE_145.valid, _WIRE_144.valid
connect _WIRE_145.ready, _WIRE_144.ready
invalidate _WIRE_145.bits.corrupt
invalidate _WIRE_145.bits.data
invalidate _WIRE_145.bits.mask
invalidate _WIRE_145.bits.address
invalidate _WIRE_145.bits.source
invalidate _WIRE_145.bits.size
invalidate _WIRE_145.bits.param
invalidate _WIRE_145.bits.opcode
invalidate _WIRE_145.valid
invalidate _WIRE_145.ready
wire _WIRE_146 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_146.bits.corrupt, UInt<1>(0h0)
connect _WIRE_146.bits.data, UInt<64>(0h0)
connect _WIRE_146.bits.mask, UInt<8>(0h0)
connect _WIRE_146.bits.address, UInt<12>(0h0)
connect _WIRE_146.bits.source, UInt<7>(0h0)
connect _WIRE_146.bits.size, UInt<3>(0h0)
connect _WIRE_146.bits.param, UInt<2>(0h0)
connect _WIRE_146.bits.opcode, UInt<3>(0h0)
connect _WIRE_146.valid, UInt<1>(0h0)
connect _WIRE_146.ready, UInt<1>(0h0)
wire _WIRE_147 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_147.bits, _WIRE_146.bits
connect _WIRE_147.valid, _WIRE_146.valid
connect _WIRE_147.ready, _WIRE_146.ready
invalidate _WIRE_147.bits.corrupt
invalidate _WIRE_147.bits.data
invalidate _WIRE_147.bits.mask
invalidate _WIRE_147.bits.address
invalidate _WIRE_147.bits.source
invalidate _WIRE_147.bits.size
invalidate _WIRE_147.bits.param
invalidate _WIRE_147.bits.opcode
invalidate _WIRE_147.valid
invalidate _WIRE_147.ready
wire _WIRE_148 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_148.bits.corrupt, UInt<1>(0h0)
connect _WIRE_148.bits.data, UInt<64>(0h0)
connect _WIRE_148.bits.mask, UInt<8>(0h0)
connect _WIRE_148.bits.address, UInt<29>(0h0)
connect _WIRE_148.bits.source, UInt<7>(0h0)
connect _WIRE_148.bits.size, UInt<4>(0h0)
connect _WIRE_148.bits.param, UInt<2>(0h0)
connect _WIRE_148.bits.opcode, UInt<3>(0h0)
connect _WIRE_148.valid, UInt<1>(0h0)
connect _WIRE_148.ready, UInt<1>(0h0)
wire _WIRE_149 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_149.bits, _WIRE_148.bits
connect _WIRE_149.valid, _WIRE_148.valid
connect _WIRE_149.ready, _WIRE_148.ready
connect _WIRE_149.valid, UInt<1>(0h0)
wire _WIRE_150 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_150.bits.corrupt, UInt<1>(0h0)
connect _WIRE_150.bits.data, UInt<64>(0h0)
connect _WIRE_150.bits.mask, UInt<8>(0h0)
connect _WIRE_150.bits.address, UInt<12>(0h0)
connect _WIRE_150.bits.source, UInt<7>(0h0)
connect _WIRE_150.bits.size, UInt<3>(0h0)
connect _WIRE_150.bits.param, UInt<2>(0h0)
connect _WIRE_150.bits.opcode, UInt<3>(0h0)
connect _WIRE_150.valid, UInt<1>(0h0)
connect _WIRE_150.ready, UInt<1>(0h0)
wire _WIRE_151 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_151.bits, _WIRE_150.bits
connect _WIRE_151.valid, _WIRE_150.valid
connect _WIRE_151.ready, _WIRE_150.ready
connect _WIRE_151.ready, UInt<1>(0h1)
wire _WIRE_152 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_152.bits.corrupt, UInt<1>(0h0)
connect _WIRE_152.bits.data, UInt<64>(0h0)
connect _WIRE_152.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_152.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_152.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_152.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_152.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_152.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_152.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_152.bits.address, UInt<29>(0h0)
connect _WIRE_152.bits.source, UInt<7>(0h0)
connect _WIRE_152.bits.size, UInt<4>(0h0)
connect _WIRE_152.bits.param, UInt<3>(0h0)
connect _WIRE_152.bits.opcode, UInt<3>(0h0)
connect _WIRE_152.valid, UInt<1>(0h0)
connect _WIRE_152.ready, UInt<1>(0h0)
wire _WIRE_153 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_153.bits, _WIRE_152.bits
connect _WIRE_153.valid, _WIRE_152.valid
connect _WIRE_153.ready, _WIRE_152.ready
invalidate _WIRE_153.bits.corrupt
invalidate _WIRE_153.bits.data
invalidate _WIRE_153.bits.user.amba_prot.fetch
invalidate _WIRE_153.bits.user.amba_prot.secure
invalidate _WIRE_153.bits.user.amba_prot.privileged
invalidate _WIRE_153.bits.user.amba_prot.writealloc
invalidate _WIRE_153.bits.user.amba_prot.readalloc
invalidate _WIRE_153.bits.user.amba_prot.modifiable
invalidate _WIRE_153.bits.user.amba_prot.bufferable
invalidate _WIRE_153.bits.address
invalidate _WIRE_153.bits.source
invalidate _WIRE_153.bits.size
invalidate _WIRE_153.bits.param
invalidate _WIRE_153.bits.opcode
invalidate _WIRE_153.valid
invalidate _WIRE_153.ready
wire _WIRE_154 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_154.bits.corrupt, UInt<1>(0h0)
connect _WIRE_154.bits.data, UInt<64>(0h0)
connect _WIRE_154.bits.address, UInt<12>(0h0)
connect _WIRE_154.bits.source, UInt<7>(0h0)
connect _WIRE_154.bits.size, UInt<3>(0h0)
connect _WIRE_154.bits.param, UInt<3>(0h0)
connect _WIRE_154.bits.opcode, UInt<3>(0h0)
connect _WIRE_154.valid, UInt<1>(0h0)
connect _WIRE_154.ready, UInt<1>(0h0)
wire _WIRE_155 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_155.bits, _WIRE_154.bits
connect _WIRE_155.valid, _WIRE_154.valid
connect _WIRE_155.ready, _WIRE_154.ready
invalidate _WIRE_155.bits.corrupt
invalidate _WIRE_155.bits.data
invalidate _WIRE_155.bits.address
invalidate _WIRE_155.bits.source
invalidate _WIRE_155.bits.size
invalidate _WIRE_155.bits.param
invalidate _WIRE_155.bits.opcode
invalidate _WIRE_155.valid
invalidate _WIRE_155.ready
wire _WIRE_156 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_156.bits.corrupt, UInt<1>(0h0)
connect _WIRE_156.bits.data, UInt<64>(0h0)
connect _WIRE_156.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_156.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_156.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_156.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_156.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_156.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_156.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_156.bits.address, UInt<29>(0h0)
connect _WIRE_156.bits.source, UInt<7>(0h0)
connect _WIRE_156.bits.size, UInt<4>(0h0)
connect _WIRE_156.bits.param, UInt<3>(0h0)
connect _WIRE_156.bits.opcode, UInt<3>(0h0)
connect _WIRE_156.valid, UInt<1>(0h0)
connect _WIRE_156.ready, UInt<1>(0h0)
wire _WIRE_157 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_157.bits, _WIRE_156.bits
connect _WIRE_157.valid, _WIRE_156.valid
connect _WIRE_157.ready, _WIRE_156.ready
connect _WIRE_157.ready, UInt<1>(0h1)
wire _WIRE_158 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_158.bits.corrupt, UInt<1>(0h0)
connect _WIRE_158.bits.data, UInt<64>(0h0)
connect _WIRE_158.bits.address, UInt<12>(0h0)
connect _WIRE_158.bits.source, UInt<7>(0h0)
connect _WIRE_158.bits.size, UInt<3>(0h0)
connect _WIRE_158.bits.param, UInt<3>(0h0)
connect _WIRE_158.bits.opcode, UInt<3>(0h0)
connect _WIRE_158.valid, UInt<1>(0h0)
connect _WIRE_158.ready, UInt<1>(0h0)
wire _WIRE_159 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_159.bits, _WIRE_158.bits
connect _WIRE_159.valid, _WIRE_158.valid
connect _WIRE_159.ready, _WIRE_158.ready
connect _WIRE_159.valid, UInt<1>(0h0)
connect out[5].d.bits.corrupt, x1_anonOut_4.d.bits.corrupt
connect out[5].d.bits.data, x1_anonOut_4.d.bits.data
connect out[5].d.bits.denied, x1_anonOut_4.d.bits.denied
connect out[5].d.bits.sink, x1_anonOut_4.d.bits.sink
connect out[5].d.bits.source, x1_anonOut_4.d.bits.source
connect out[5].d.bits.size, x1_anonOut_4.d.bits.size
connect out[5].d.bits.param, x1_anonOut_4.d.bits.param
connect out[5].d.bits.opcode, x1_anonOut_4.d.bits.opcode
connect out[5].d.valid, x1_anonOut_4.d.valid
connect x1_anonOut_4.d.ready, out[5].d.ready
node _out_5_d_bits_sink_T = or(x1_anonOut_4.d.bits.sink, UInt<1>(0h0))
connect out[5].d.bits.sink, _out_5_d_bits_sink_T
wire _WIRE_160 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_160.bits.sink, UInt<1>(0h0)
connect _WIRE_160.valid, UInt<1>(0h0)
connect _WIRE_160.ready, UInt<1>(0h0)
wire _WIRE_161 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_161.bits, _WIRE_160.bits
connect _WIRE_161.valid, _WIRE_160.valid
connect _WIRE_161.ready, _WIRE_160.ready
invalidate _WIRE_161.bits.sink
invalidate _WIRE_161.valid
invalidate _WIRE_161.ready
wire _WIRE_162 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_162.bits.sink, UInt<1>(0h0)
connect _WIRE_162.valid, UInt<1>(0h0)
connect _WIRE_162.ready, UInt<1>(0h0)
wire _WIRE_163 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_163.bits, _WIRE_162.bits
connect _WIRE_163.valid, _WIRE_162.valid
connect _WIRE_163.ready, _WIRE_162.ready
invalidate _WIRE_163.bits.sink
invalidate _WIRE_163.valid
invalidate _WIRE_163.ready
wire _WIRE_164 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_164.bits.sink, UInt<1>(0h0)
connect _WIRE_164.valid, UInt<1>(0h0)
connect _WIRE_164.ready, UInt<1>(0h0)
wire _WIRE_165 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_165.bits, _WIRE_164.bits
connect _WIRE_165.valid, _WIRE_164.valid
connect _WIRE_165.ready, _WIRE_164.ready
connect _WIRE_165.ready, UInt<1>(0h1)
wire _WIRE_166 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_166.bits.sink, UInt<1>(0h0)
connect _WIRE_166.valid, UInt<1>(0h0)
connect _WIRE_166.ready, UInt<1>(0h0)
wire _WIRE_167 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_167.bits, _WIRE_166.bits
connect _WIRE_167.valid, _WIRE_166.valid
connect _WIRE_167.ready, _WIRE_166.ready
connect _WIRE_167.valid, UInt<1>(0h0)
invalidate out[6].a.bits.user.amba_prot.fetch
invalidate out[6].a.bits.user.amba_prot.secure
invalidate out[6].a.bits.user.amba_prot.privileged
invalidate out[6].a.bits.user.amba_prot.writealloc
invalidate out[6].a.bits.user.amba_prot.readalloc
invalidate out[6].a.bits.user.amba_prot.modifiable
invalidate out[6].a.bits.user.amba_prot.bufferable
connect x1_anonOut_5.a.bits.corrupt, out[6].a.bits.corrupt
connect x1_anonOut_5.a.bits.data, out[6].a.bits.data
connect x1_anonOut_5.a.bits.mask, out[6].a.bits.mask
connect x1_anonOut_5.a.bits.address, out[6].a.bits.address
connect x1_anonOut_5.a.bits.source, out[6].a.bits.source
connect x1_anonOut_5.a.bits.size, out[6].a.bits.size
connect x1_anonOut_5.a.bits.param, out[6].a.bits.param
connect x1_anonOut_5.a.bits.opcode, out[6].a.bits.opcode
connect x1_anonOut_5.a.valid, out[6].a.valid
connect out[6].a.ready, x1_anonOut_5.a.ready
wire _WIRE_168 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_168.bits.corrupt, UInt<1>(0h0)
connect _WIRE_168.bits.data, UInt<64>(0h0)
connect _WIRE_168.bits.mask, UInt<8>(0h0)
connect _WIRE_168.bits.address, UInt<29>(0h0)
connect _WIRE_168.bits.source, UInt<7>(0h0)
connect _WIRE_168.bits.size, UInt<4>(0h0)
connect _WIRE_168.bits.param, UInt<2>(0h0)
connect _WIRE_168.bits.opcode, UInt<3>(0h0)
connect _WIRE_168.valid, UInt<1>(0h0)
connect _WIRE_168.ready, UInt<1>(0h0)
wire _WIRE_169 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_169.bits, _WIRE_168.bits
connect _WIRE_169.valid, _WIRE_168.valid
connect _WIRE_169.ready, _WIRE_168.ready
invalidate _WIRE_169.bits.corrupt
invalidate _WIRE_169.bits.data
invalidate _WIRE_169.bits.mask
invalidate _WIRE_169.bits.address
invalidate _WIRE_169.bits.source
invalidate _WIRE_169.bits.size
invalidate _WIRE_169.bits.param
invalidate _WIRE_169.bits.opcode
invalidate _WIRE_169.valid
invalidate _WIRE_169.ready
wire _WIRE_170 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_170.bits.corrupt, UInt<1>(0h0)
connect _WIRE_170.bits.data, UInt<64>(0h0)
connect _WIRE_170.bits.mask, UInt<8>(0h0)
connect _WIRE_170.bits.address, UInt<17>(0h0)
connect _WIRE_170.bits.source, UInt<7>(0h0)
connect _WIRE_170.bits.size, UInt<3>(0h0)
connect _WIRE_170.bits.param, UInt<2>(0h0)
connect _WIRE_170.bits.opcode, UInt<3>(0h0)
connect _WIRE_170.valid, UInt<1>(0h0)
connect _WIRE_170.ready, UInt<1>(0h0)
wire _WIRE_171 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_171.bits, _WIRE_170.bits
connect _WIRE_171.valid, _WIRE_170.valid
connect _WIRE_171.ready, _WIRE_170.ready
invalidate _WIRE_171.bits.corrupt
invalidate _WIRE_171.bits.data
invalidate _WIRE_171.bits.mask
invalidate _WIRE_171.bits.address
invalidate _WIRE_171.bits.source
invalidate _WIRE_171.bits.size
invalidate _WIRE_171.bits.param
invalidate _WIRE_171.bits.opcode
invalidate _WIRE_171.valid
invalidate _WIRE_171.ready
wire _WIRE_172 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_172.bits.corrupt, UInt<1>(0h0)
connect _WIRE_172.bits.data, UInt<64>(0h0)
connect _WIRE_172.bits.mask, UInt<8>(0h0)
connect _WIRE_172.bits.address, UInt<29>(0h0)
connect _WIRE_172.bits.source, UInt<7>(0h0)
connect _WIRE_172.bits.size, UInt<4>(0h0)
connect _WIRE_172.bits.param, UInt<2>(0h0)
connect _WIRE_172.bits.opcode, UInt<3>(0h0)
connect _WIRE_172.valid, UInt<1>(0h0)
connect _WIRE_172.ready, UInt<1>(0h0)
wire _WIRE_173 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_173.bits, _WIRE_172.bits
connect _WIRE_173.valid, _WIRE_172.valid
connect _WIRE_173.ready, _WIRE_172.ready
connect _WIRE_173.valid, UInt<1>(0h0)
wire _WIRE_174 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_174.bits.corrupt, UInt<1>(0h0)
connect _WIRE_174.bits.data, UInt<64>(0h0)
connect _WIRE_174.bits.mask, UInt<8>(0h0)
connect _WIRE_174.bits.address, UInt<17>(0h0)
connect _WIRE_174.bits.source, UInt<7>(0h0)
connect _WIRE_174.bits.size, UInt<3>(0h0)
connect _WIRE_174.bits.param, UInt<2>(0h0)
connect _WIRE_174.bits.opcode, UInt<3>(0h0)
connect _WIRE_174.valid, UInt<1>(0h0)
connect _WIRE_174.ready, UInt<1>(0h0)
wire _WIRE_175 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_175.bits, _WIRE_174.bits
connect _WIRE_175.valid, _WIRE_174.valid
connect _WIRE_175.ready, _WIRE_174.ready
connect _WIRE_175.ready, UInt<1>(0h1)
wire _WIRE_176 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_176.bits.corrupt, UInt<1>(0h0)
connect _WIRE_176.bits.data, UInt<64>(0h0)
connect _WIRE_176.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_176.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_176.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_176.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_176.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_176.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_176.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_176.bits.address, UInt<29>(0h0)
connect _WIRE_176.bits.source, UInt<7>(0h0)
connect _WIRE_176.bits.size, UInt<4>(0h0)
connect _WIRE_176.bits.param, UInt<3>(0h0)
connect _WIRE_176.bits.opcode, UInt<3>(0h0)
connect _WIRE_176.valid, UInt<1>(0h0)
connect _WIRE_176.ready, UInt<1>(0h0)
wire _WIRE_177 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_177.bits, _WIRE_176.bits
connect _WIRE_177.valid, _WIRE_176.valid
connect _WIRE_177.ready, _WIRE_176.ready
invalidate _WIRE_177.bits.corrupt
invalidate _WIRE_177.bits.data
invalidate _WIRE_177.bits.user.amba_prot.fetch
invalidate _WIRE_177.bits.user.amba_prot.secure
invalidate _WIRE_177.bits.user.amba_prot.privileged
invalidate _WIRE_177.bits.user.amba_prot.writealloc
invalidate _WIRE_177.bits.user.amba_prot.readalloc
invalidate _WIRE_177.bits.user.amba_prot.modifiable
invalidate _WIRE_177.bits.user.amba_prot.bufferable
invalidate _WIRE_177.bits.address
invalidate _WIRE_177.bits.source
invalidate _WIRE_177.bits.size
invalidate _WIRE_177.bits.param
invalidate _WIRE_177.bits.opcode
invalidate _WIRE_177.valid
invalidate _WIRE_177.ready
wire _WIRE_178 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_178.bits.corrupt, UInt<1>(0h0)
connect _WIRE_178.bits.data, UInt<64>(0h0)
connect _WIRE_178.bits.address, UInt<17>(0h0)
connect _WIRE_178.bits.source, UInt<7>(0h0)
connect _WIRE_178.bits.size, UInt<3>(0h0)
connect _WIRE_178.bits.param, UInt<3>(0h0)
connect _WIRE_178.bits.opcode, UInt<3>(0h0)
connect _WIRE_178.valid, UInt<1>(0h0)
connect _WIRE_178.ready, UInt<1>(0h0)
wire _WIRE_179 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_179.bits, _WIRE_178.bits
connect _WIRE_179.valid, _WIRE_178.valid
connect _WIRE_179.ready, _WIRE_178.ready
invalidate _WIRE_179.bits.corrupt
invalidate _WIRE_179.bits.data
invalidate _WIRE_179.bits.address
invalidate _WIRE_179.bits.source
invalidate _WIRE_179.bits.size
invalidate _WIRE_179.bits.param
invalidate _WIRE_179.bits.opcode
invalidate _WIRE_179.valid
invalidate _WIRE_179.ready
wire _WIRE_180 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_180.bits.corrupt, UInt<1>(0h0)
connect _WIRE_180.bits.data, UInt<64>(0h0)
connect _WIRE_180.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_180.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_180.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_180.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_180.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_180.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_180.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_180.bits.address, UInt<29>(0h0)
connect _WIRE_180.bits.source, UInt<7>(0h0)
connect _WIRE_180.bits.size, UInt<4>(0h0)
connect _WIRE_180.bits.param, UInt<3>(0h0)
connect _WIRE_180.bits.opcode, UInt<3>(0h0)
connect _WIRE_180.valid, UInt<1>(0h0)
connect _WIRE_180.ready, UInt<1>(0h0)
wire _WIRE_181 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_181.bits, _WIRE_180.bits
connect _WIRE_181.valid, _WIRE_180.valid
connect _WIRE_181.ready, _WIRE_180.ready
connect _WIRE_181.ready, UInt<1>(0h1)
wire _WIRE_182 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_182.bits.corrupt, UInt<1>(0h0)
connect _WIRE_182.bits.data, UInt<64>(0h0)
connect _WIRE_182.bits.address, UInt<17>(0h0)
connect _WIRE_182.bits.source, UInt<7>(0h0)
connect _WIRE_182.bits.size, UInt<3>(0h0)
connect _WIRE_182.bits.param, UInt<3>(0h0)
connect _WIRE_182.bits.opcode, UInt<3>(0h0)
connect _WIRE_182.valid, UInt<1>(0h0)
connect _WIRE_182.ready, UInt<1>(0h0)
wire _WIRE_183 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_183.bits, _WIRE_182.bits
connect _WIRE_183.valid, _WIRE_182.valid
connect _WIRE_183.ready, _WIRE_182.ready
connect _WIRE_183.valid, UInt<1>(0h0)
connect out[6].d.bits.corrupt, x1_anonOut_5.d.bits.corrupt
connect out[6].d.bits.data, x1_anonOut_5.d.bits.data
connect out[6].d.bits.denied, x1_anonOut_5.d.bits.denied
connect out[6].d.bits.sink, x1_anonOut_5.d.bits.sink
connect out[6].d.bits.source, x1_anonOut_5.d.bits.source
connect out[6].d.bits.size, x1_anonOut_5.d.bits.size
connect out[6].d.bits.param, x1_anonOut_5.d.bits.param
connect out[6].d.bits.opcode, x1_anonOut_5.d.bits.opcode
connect out[6].d.valid, x1_anonOut_5.d.valid
connect x1_anonOut_5.d.ready, out[6].d.ready
node _out_6_d_bits_sink_T = or(x1_anonOut_5.d.bits.sink, UInt<1>(0h0))
connect out[6].d.bits.sink, _out_6_d_bits_sink_T
wire _WIRE_184 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_184.bits.sink, UInt<1>(0h0)
connect _WIRE_184.valid, UInt<1>(0h0)
connect _WIRE_184.ready, UInt<1>(0h0)
wire _WIRE_185 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_185.bits, _WIRE_184.bits
connect _WIRE_185.valid, _WIRE_184.valid
connect _WIRE_185.ready, _WIRE_184.ready
invalidate _WIRE_185.bits.sink
invalidate _WIRE_185.valid
invalidate _WIRE_185.ready
wire _WIRE_186 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_186.bits.sink, UInt<1>(0h0)
connect _WIRE_186.valid, UInt<1>(0h0)
connect _WIRE_186.ready, UInt<1>(0h0)
wire _WIRE_187 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_187.bits, _WIRE_186.bits
connect _WIRE_187.valid, _WIRE_186.valid
connect _WIRE_187.ready, _WIRE_186.ready
invalidate _WIRE_187.bits.sink
invalidate _WIRE_187.valid
invalidate _WIRE_187.ready
wire _WIRE_188 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_188.bits.sink, UInt<1>(0h0)
connect _WIRE_188.valid, UInt<1>(0h0)
connect _WIRE_188.ready, UInt<1>(0h0)
wire _WIRE_189 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_189.bits, _WIRE_188.bits
connect _WIRE_189.valid, _WIRE_188.valid
connect _WIRE_189.ready, _WIRE_188.ready
connect _WIRE_189.ready, UInt<1>(0h1)
wire _WIRE_190 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_190.bits.sink, UInt<1>(0h0)
connect _WIRE_190.valid, UInt<1>(0h0)
connect _WIRE_190.ready, UInt<1>(0h0)
wire _WIRE_191 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_191.bits, _WIRE_190.bits
connect _WIRE_191.valid, _WIRE_190.valid
connect _WIRE_191.ready, _WIRE_190.ready
connect _WIRE_191.valid, UInt<1>(0h0)
invalidate out[7].a.bits.user.amba_prot.fetch
invalidate out[7].a.bits.user.amba_prot.secure
invalidate out[7].a.bits.user.amba_prot.privileged
invalidate out[7].a.bits.user.amba_prot.writealloc
invalidate out[7].a.bits.user.amba_prot.readalloc
invalidate out[7].a.bits.user.amba_prot.modifiable
invalidate out[7].a.bits.user.amba_prot.bufferable
connect x1_anonOut_6.a.bits.corrupt, out[7].a.bits.corrupt
connect x1_anonOut_6.a.bits.data, out[7].a.bits.data
connect x1_anonOut_6.a.bits.mask, out[7].a.bits.mask
connect x1_anonOut_6.a.bits.address, out[7].a.bits.address
connect x1_anonOut_6.a.bits.source, out[7].a.bits.source
connect x1_anonOut_6.a.bits.size, out[7].a.bits.size
connect x1_anonOut_6.a.bits.param, out[7].a.bits.param
connect x1_anonOut_6.a.bits.opcode, out[7].a.bits.opcode
connect x1_anonOut_6.a.valid, out[7].a.valid
connect out[7].a.ready, x1_anonOut_6.a.ready
wire _WIRE_192 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_192.bits.corrupt, UInt<1>(0h0)
connect _WIRE_192.bits.data, UInt<64>(0h0)
connect _WIRE_192.bits.mask, UInt<8>(0h0)
connect _WIRE_192.bits.address, UInt<29>(0h0)
connect _WIRE_192.bits.source, UInt<7>(0h0)
connect _WIRE_192.bits.size, UInt<4>(0h0)
connect _WIRE_192.bits.param, UInt<2>(0h0)
connect _WIRE_192.bits.opcode, UInt<3>(0h0)
connect _WIRE_192.valid, UInt<1>(0h0)
connect _WIRE_192.ready, UInt<1>(0h0)
wire _WIRE_193 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_193.bits, _WIRE_192.bits
connect _WIRE_193.valid, _WIRE_192.valid
connect _WIRE_193.ready, _WIRE_192.ready
invalidate _WIRE_193.bits.corrupt
invalidate _WIRE_193.bits.data
invalidate _WIRE_193.bits.mask
invalidate _WIRE_193.bits.address
invalidate _WIRE_193.bits.source
invalidate _WIRE_193.bits.size
invalidate _WIRE_193.bits.param
invalidate _WIRE_193.bits.opcode
invalidate _WIRE_193.valid
invalidate _WIRE_193.ready
wire _WIRE_194 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_194.bits.corrupt, UInt<1>(0h0)
connect _WIRE_194.bits.data, UInt<64>(0h0)
connect _WIRE_194.bits.mask, UInt<8>(0h0)
connect _WIRE_194.bits.address, UInt<21>(0h0)
connect _WIRE_194.bits.source, UInt<7>(0h0)
connect _WIRE_194.bits.size, UInt<3>(0h0)
connect _WIRE_194.bits.param, UInt<2>(0h0)
connect _WIRE_194.bits.opcode, UInt<3>(0h0)
connect _WIRE_194.valid, UInt<1>(0h0)
connect _WIRE_194.ready, UInt<1>(0h0)
wire _WIRE_195 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_195.bits, _WIRE_194.bits
connect _WIRE_195.valid, _WIRE_194.valid
connect _WIRE_195.ready, _WIRE_194.ready
invalidate _WIRE_195.bits.corrupt
invalidate _WIRE_195.bits.data
invalidate _WIRE_195.bits.mask
invalidate _WIRE_195.bits.address
invalidate _WIRE_195.bits.source
invalidate _WIRE_195.bits.size
invalidate _WIRE_195.bits.param
invalidate _WIRE_195.bits.opcode
invalidate _WIRE_195.valid
invalidate _WIRE_195.ready
wire _WIRE_196 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_196.bits.corrupt, UInt<1>(0h0)
connect _WIRE_196.bits.data, UInt<64>(0h0)
connect _WIRE_196.bits.mask, UInt<8>(0h0)
connect _WIRE_196.bits.address, UInt<29>(0h0)
connect _WIRE_196.bits.source, UInt<7>(0h0)
connect _WIRE_196.bits.size, UInt<4>(0h0)
connect _WIRE_196.bits.param, UInt<2>(0h0)
connect _WIRE_196.bits.opcode, UInt<3>(0h0)
connect _WIRE_196.valid, UInt<1>(0h0)
connect _WIRE_196.ready, UInt<1>(0h0)
wire _WIRE_197 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_197.bits, _WIRE_196.bits
connect _WIRE_197.valid, _WIRE_196.valid
connect _WIRE_197.ready, _WIRE_196.ready
connect _WIRE_197.valid, UInt<1>(0h0)
wire _WIRE_198 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_198.bits.corrupt, UInt<1>(0h0)
connect _WIRE_198.bits.data, UInt<64>(0h0)
connect _WIRE_198.bits.mask, UInt<8>(0h0)
connect _WIRE_198.bits.address, UInt<21>(0h0)
connect _WIRE_198.bits.source, UInt<7>(0h0)
connect _WIRE_198.bits.size, UInt<3>(0h0)
connect _WIRE_198.bits.param, UInt<2>(0h0)
connect _WIRE_198.bits.opcode, UInt<3>(0h0)
connect _WIRE_198.valid, UInt<1>(0h0)
connect _WIRE_198.ready, UInt<1>(0h0)
wire _WIRE_199 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_199.bits, _WIRE_198.bits
connect _WIRE_199.valid, _WIRE_198.valid
connect _WIRE_199.ready, _WIRE_198.ready
connect _WIRE_199.ready, UInt<1>(0h1)
wire _WIRE_200 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_200.bits.corrupt, UInt<1>(0h0)
connect _WIRE_200.bits.data, UInt<64>(0h0)
connect _WIRE_200.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_200.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_200.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_200.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_200.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_200.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_200.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_200.bits.address, UInt<29>(0h0)
connect _WIRE_200.bits.source, UInt<7>(0h0)
connect _WIRE_200.bits.size, UInt<4>(0h0)
connect _WIRE_200.bits.param, UInt<3>(0h0)
connect _WIRE_200.bits.opcode, UInt<3>(0h0)
connect _WIRE_200.valid, UInt<1>(0h0)
connect _WIRE_200.ready, UInt<1>(0h0)
wire _WIRE_201 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_201.bits, _WIRE_200.bits
connect _WIRE_201.valid, _WIRE_200.valid
connect _WIRE_201.ready, _WIRE_200.ready
invalidate _WIRE_201.bits.corrupt
invalidate _WIRE_201.bits.data
invalidate _WIRE_201.bits.user.amba_prot.fetch
invalidate _WIRE_201.bits.user.amba_prot.secure
invalidate _WIRE_201.bits.user.amba_prot.privileged
invalidate _WIRE_201.bits.user.amba_prot.writealloc
invalidate _WIRE_201.bits.user.amba_prot.readalloc
invalidate _WIRE_201.bits.user.amba_prot.modifiable
invalidate _WIRE_201.bits.user.amba_prot.bufferable
invalidate _WIRE_201.bits.address
invalidate _WIRE_201.bits.source
invalidate _WIRE_201.bits.size
invalidate _WIRE_201.bits.param
invalidate _WIRE_201.bits.opcode
invalidate _WIRE_201.valid
invalidate _WIRE_201.ready
wire _WIRE_202 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_202.bits.corrupt, UInt<1>(0h0)
connect _WIRE_202.bits.data, UInt<64>(0h0)
connect _WIRE_202.bits.address, UInt<21>(0h0)
connect _WIRE_202.bits.source, UInt<7>(0h0)
connect _WIRE_202.bits.size, UInt<3>(0h0)
connect _WIRE_202.bits.param, UInt<3>(0h0)
connect _WIRE_202.bits.opcode, UInt<3>(0h0)
connect _WIRE_202.valid, UInt<1>(0h0)
connect _WIRE_202.ready, UInt<1>(0h0)
wire _WIRE_203 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_203.bits, _WIRE_202.bits
connect _WIRE_203.valid, _WIRE_202.valid
connect _WIRE_203.ready, _WIRE_202.ready
invalidate _WIRE_203.bits.corrupt
invalidate _WIRE_203.bits.data
invalidate _WIRE_203.bits.address
invalidate _WIRE_203.bits.source
invalidate _WIRE_203.bits.size
invalidate _WIRE_203.bits.param
invalidate _WIRE_203.bits.opcode
invalidate _WIRE_203.valid
invalidate _WIRE_203.ready
wire _WIRE_204 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_204.bits.corrupt, UInt<1>(0h0)
connect _WIRE_204.bits.data, UInt<64>(0h0)
connect _WIRE_204.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_204.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_204.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_204.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_204.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_204.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_204.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_204.bits.address, UInt<29>(0h0)
connect _WIRE_204.bits.source, UInt<7>(0h0)
connect _WIRE_204.bits.size, UInt<4>(0h0)
connect _WIRE_204.bits.param, UInt<3>(0h0)
connect _WIRE_204.bits.opcode, UInt<3>(0h0)
connect _WIRE_204.valid, UInt<1>(0h0)
connect _WIRE_204.ready, UInt<1>(0h0)
wire _WIRE_205 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_205.bits, _WIRE_204.bits
connect _WIRE_205.valid, _WIRE_204.valid
connect _WIRE_205.ready, _WIRE_204.ready
connect _WIRE_205.ready, UInt<1>(0h1)
wire _WIRE_206 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_206.bits.corrupt, UInt<1>(0h0)
connect _WIRE_206.bits.data, UInt<64>(0h0)
connect _WIRE_206.bits.address, UInt<21>(0h0)
connect _WIRE_206.bits.source, UInt<7>(0h0)
connect _WIRE_206.bits.size, UInt<3>(0h0)
connect _WIRE_206.bits.param, UInt<3>(0h0)
connect _WIRE_206.bits.opcode, UInt<3>(0h0)
connect _WIRE_206.valid, UInt<1>(0h0)
connect _WIRE_206.ready, UInt<1>(0h0)
wire _WIRE_207 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_207.bits, _WIRE_206.bits
connect _WIRE_207.valid, _WIRE_206.valid
connect _WIRE_207.ready, _WIRE_206.ready
connect _WIRE_207.valid, UInt<1>(0h0)
connect out[7].d.bits.corrupt, x1_anonOut_6.d.bits.corrupt
connect out[7].d.bits.data, x1_anonOut_6.d.bits.data
connect out[7].d.bits.denied, x1_anonOut_6.d.bits.denied
connect out[7].d.bits.sink, x1_anonOut_6.d.bits.sink
connect out[7].d.bits.source, x1_anonOut_6.d.bits.source
connect out[7].d.bits.size, x1_anonOut_6.d.bits.size
connect out[7].d.bits.param, x1_anonOut_6.d.bits.param
connect out[7].d.bits.opcode, x1_anonOut_6.d.bits.opcode
connect out[7].d.valid, x1_anonOut_6.d.valid
connect x1_anonOut_6.d.ready, out[7].d.ready
node _out_7_d_bits_sink_T = or(x1_anonOut_6.d.bits.sink, UInt<1>(0h0))
connect out[7].d.bits.sink, _out_7_d_bits_sink_T
wire _WIRE_208 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_208.bits.sink, UInt<1>(0h0)
connect _WIRE_208.valid, UInt<1>(0h0)
connect _WIRE_208.ready, UInt<1>(0h0)
wire _WIRE_209 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_209.bits, _WIRE_208.bits
connect _WIRE_209.valid, _WIRE_208.valid
connect _WIRE_209.ready, _WIRE_208.ready
invalidate _WIRE_209.bits.sink
invalidate _WIRE_209.valid
invalidate _WIRE_209.ready
wire _WIRE_210 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_210.bits.sink, UInt<1>(0h0)
connect _WIRE_210.valid, UInt<1>(0h0)
connect _WIRE_210.ready, UInt<1>(0h0)
wire _WIRE_211 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_211.bits, _WIRE_210.bits
connect _WIRE_211.valid, _WIRE_210.valid
connect _WIRE_211.ready, _WIRE_210.ready
invalidate _WIRE_211.bits.sink
invalidate _WIRE_211.valid
invalidate _WIRE_211.ready
wire _WIRE_212 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_212.bits.sink, UInt<1>(0h0)
connect _WIRE_212.valid, UInt<1>(0h0)
connect _WIRE_212.ready, UInt<1>(0h0)
wire _WIRE_213 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_213.bits, _WIRE_212.bits
connect _WIRE_213.valid, _WIRE_212.valid
connect _WIRE_213.ready, _WIRE_212.ready
connect _WIRE_213.ready, UInt<1>(0h1)
wire _WIRE_214 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_214.bits.sink, UInt<1>(0h0)
connect _WIRE_214.valid, UInt<1>(0h0)
connect _WIRE_214.ready, UInt<1>(0h0)
wire _WIRE_215 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_215.bits, _WIRE_214.bits
connect _WIRE_215.valid, _WIRE_214.valid
connect _WIRE_215.ready, _WIRE_214.ready
connect _WIRE_215.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE.bits.address, UInt<29>(0h0)
connect _addressC_WIRE.bits.source, UInt<7>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<14>(0h3000))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<30>(0h1a117000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<26>(0h2010000))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<30>(0h1a117000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9)
node _requestAIO_T_10 = xor(in[0].a.bits.address, UInt<13>(0h1000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<30>(0h1a117000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node _requestAIO_T_15 = xor(in[0].a.bits.address, UInt<15>(0h4000))
node _requestAIO_T_16 = cvt(_requestAIO_T_15)
node _requestAIO_T_17 = and(_requestAIO_T_16, asSInt(UInt<30>(0h1a117000)))
node _requestAIO_T_18 = asSInt(_requestAIO_T_17)
node _requestAIO_T_19 = eq(_requestAIO_T_18, asSInt(UInt<1>(0h0)))
node _requestAIO_T_20 = xor(in[0].a.bits.address, UInt<29>(0h10000000))
node _requestAIO_T_21 = cvt(_requestAIO_T_20)
node _requestAIO_T_22 = and(_requestAIO_T_21, asSInt(UInt<30>(0h1a117000)))
node _requestAIO_T_23 = asSInt(_requestAIO_T_22)
node _requestAIO_T_24 = eq(_requestAIO_T_23, asSInt(UInt<1>(0h0)))
node _requestAIO_T_25 = or(_requestAIO_T_14, _requestAIO_T_19)
node _requestAIO_T_26 = or(_requestAIO_T_25, _requestAIO_T_24)
node requestAIO_0_2 = or(UInt<1>(0h0), _requestAIO_T_26)
node _requestAIO_T_27 = xor(in[0].a.bits.address, UInt<26>(0h2000000))
node _requestAIO_T_28 = cvt(_requestAIO_T_27)
node _requestAIO_T_29 = and(_requestAIO_T_28, asSInt(UInt<30>(0h1a110000)))
node _requestAIO_T_30 = asSInt(_requestAIO_T_29)
node _requestAIO_T_31 = eq(_requestAIO_T_30, asSInt(UInt<1>(0h0)))
node requestAIO_0_3 = or(UInt<1>(0h0), _requestAIO_T_31)
node _requestAIO_T_32 = xor(in[0].a.bits.address, UInt<28>(0h8000000))
node _requestAIO_T_33 = cvt(_requestAIO_T_32)
node _requestAIO_T_34 = and(_requestAIO_T_33, asSInt(UInt<30>(0h18000000)))
node _requestAIO_T_35 = asSInt(_requestAIO_T_34)
node _requestAIO_T_36 = eq(_requestAIO_T_35, asSInt(UInt<1>(0h0)))
node requestAIO_0_4 = or(UInt<1>(0h0), _requestAIO_T_36)
node _requestAIO_T_37 = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_38 = cvt(_requestAIO_T_37)
node _requestAIO_T_39 = and(_requestAIO_T_38, asSInt(UInt<30>(0h1a117000)))
node _requestAIO_T_40 = asSInt(_requestAIO_T_39)
node _requestAIO_T_41 = eq(_requestAIO_T_40, asSInt(UInt<1>(0h0)))
node requestAIO_0_5 = or(UInt<1>(0h0), _requestAIO_T_41)
node _requestAIO_T_42 = xor(in[0].a.bits.address, UInt<17>(0h10000))
node _requestAIO_T_43 = cvt(_requestAIO_T_42)
node _requestAIO_T_44 = and(_requestAIO_T_43, asSInt(UInt<30>(0h1a110000)))
node _requestAIO_T_45 = asSInt(_requestAIO_T_44)
node _requestAIO_T_46 = eq(_requestAIO_T_45, asSInt(UInt<1>(0h0)))
node requestAIO_0_6 = or(UInt<1>(0h0), _requestAIO_T_46)
node _requestAIO_T_47 = xor(in[0].a.bits.address, UInt<21>(0h100000))
node _requestAIO_T_48 = cvt(_requestAIO_T_47)
node _requestAIO_T_49 = and(_requestAIO_T_48, asSInt(UInt<30>(0h1a107000)))
node _requestAIO_T_50 = asSInt(_requestAIO_T_49)
node _requestAIO_T_51 = eq(_requestAIO_T_50, asSInt(UInt<1>(0h0)))
node requestAIO_0_7 = or(UInt<1>(0h0), _requestAIO_T_51)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_0_2 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestCIO_T_15 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_16 = cvt(_requestCIO_T_15)
node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0)))
node _requestCIO_T_18 = asSInt(_requestCIO_T_17)
node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0)))
node requestCIO_0_3 = or(UInt<1>(0h1), _requestCIO_T_19)
node _requestCIO_T_20 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_21 = cvt(_requestCIO_T_20)
node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0)))
node _requestCIO_T_23 = asSInt(_requestCIO_T_22)
node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0)))
node requestCIO_0_4 = or(UInt<1>(0h1), _requestCIO_T_24)
node _requestCIO_T_25 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_26 = cvt(_requestCIO_T_25)
node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0)))
node _requestCIO_T_28 = asSInt(_requestCIO_T_27)
node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0)))
node requestCIO_0_5 = or(UInt<1>(0h1), _requestCIO_T_29)
node _requestCIO_T_30 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_31 = cvt(_requestCIO_T_30)
node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0)))
node _requestCIO_T_33 = asSInt(_requestCIO_T_32)
node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0)))
node requestCIO_0_6 = or(UInt<1>(0h1), _requestCIO_T_34)
node _requestCIO_T_35 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_36 = cvt(_requestCIO_T_35)
node _requestCIO_T_37 = and(_requestCIO_T_36, asSInt(UInt<1>(0h0)))
node _requestCIO_T_38 = asSInt(_requestCIO_T_37)
node _requestCIO_T_39 = eq(_requestCIO_T_38, asSInt(UInt<1>(0h0)))
node requestCIO_0_7 = or(UInt<1>(0h1), _requestCIO_T_39)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 6, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 7)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<7>(0h7f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 6, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 7)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<7>(0h7f))
node requestBOI_1_0 = and(_requestBOI_T_8, _requestBOI_T_9)
wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_4.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_4.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_4.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_4.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_4.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits
connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid
connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready
node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 6, 0)
node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 7)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h0))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<7>(0h7f))
node requestBOI_2_0 = and(_requestBOI_T_13, _requestBOI_T_14)
wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_6.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_6.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_6.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_6.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_6.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_6.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_6.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits
connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid
connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready
node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 6, 0)
node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 7)
node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<1>(0h0))
node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3)
node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17)
node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<7>(0h7f))
node requestBOI_3_0 = and(_requestBOI_T_18, _requestBOI_T_19)
wire _requestBOI_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_8.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_8.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_8.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_8.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_8.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_8.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_8.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_8.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_8.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_9.bits, _requestBOI_WIRE_8.bits
connect _requestBOI_WIRE_9.valid, _requestBOI_WIRE_8.valid
connect _requestBOI_WIRE_9.ready, _requestBOI_WIRE_8.ready
node _requestBOI_uncommonBits_T_4 = or(_requestBOI_WIRE_9.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 6, 0)
node _requestBOI_T_20 = shr(_requestBOI_WIRE_9.bits.source, 7)
node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<1>(0h0))
node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4)
node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22)
node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<7>(0h7f))
node requestBOI_4_0 = and(_requestBOI_T_23, _requestBOI_T_24)
wire _requestBOI_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_10.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_10.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_10.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_10.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_10.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_10.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_10.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_10.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_10.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_11.bits, _requestBOI_WIRE_10.bits
connect _requestBOI_WIRE_11.valid, _requestBOI_WIRE_10.valid
connect _requestBOI_WIRE_11.ready, _requestBOI_WIRE_10.ready
node _requestBOI_uncommonBits_T_5 = or(_requestBOI_WIRE_11.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 6, 0)
node _requestBOI_T_25 = shr(_requestBOI_WIRE_11.bits.source, 7)
node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<1>(0h0))
node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5)
node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27)
node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<7>(0h7f))
node requestBOI_5_0 = and(_requestBOI_T_28, _requestBOI_T_29)
wire _requestBOI_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_12.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_12.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_12.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_12.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_12.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_12.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_12.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_12.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_12.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_13.bits, _requestBOI_WIRE_12.bits
connect _requestBOI_WIRE_13.valid, _requestBOI_WIRE_12.valid
connect _requestBOI_WIRE_13.ready, _requestBOI_WIRE_12.ready
node _requestBOI_uncommonBits_T_6 = or(_requestBOI_WIRE_13.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 6, 0)
node _requestBOI_T_30 = shr(_requestBOI_WIRE_13.bits.source, 7)
node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<1>(0h0))
node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6)
node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32)
node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<7>(0h7f))
node requestBOI_6_0 = and(_requestBOI_T_33, _requestBOI_T_34)
wire _requestBOI_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_14.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_14.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_14.bits.address, UInt<29>(0h0)
connect _requestBOI_WIRE_14.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_14.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_14.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_14.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_14.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_14.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_15.bits, _requestBOI_WIRE_14.bits
connect _requestBOI_WIRE_15.valid, _requestBOI_WIRE_14.valid
connect _requestBOI_WIRE_15.ready, _requestBOI_WIRE_14.ready
node _requestBOI_uncommonBits_T_7 = or(_requestBOI_WIRE_15.bits.source, UInt<7>(0h0))
node requestBOI_uncommonBits_7 = bits(_requestBOI_uncommonBits_T_7, 6, 0)
node _requestBOI_T_35 = shr(_requestBOI_WIRE_15.bits.source, 7)
node _requestBOI_T_36 = eq(_requestBOI_T_35, UInt<1>(0h0))
node _requestBOI_T_37 = leq(UInt<1>(0h0), requestBOI_uncommonBits_7)
node _requestBOI_T_38 = and(_requestBOI_T_36, _requestBOI_T_37)
node _requestBOI_T_39 = leq(requestBOI_uncommonBits_7, UInt<7>(0h7f))
node requestBOI_7_0 = and(_requestBOI_T_38, _requestBOI_T_39)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 6, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 7)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<7>(0h7f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[1].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 6, 0)
node _requestDOI_T_5 = shr(out[1].d.bits.source, 7)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<7>(0h7f))
node requestDOI_1_0 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[2].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 6, 0)
node _requestDOI_T_10 = shr(out[2].d.bits.source, 7)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h0))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<7>(0h7f))
node requestDOI_2_0 = and(_requestDOI_T_13, _requestDOI_T_14)
node _requestDOI_uncommonBits_T_3 = or(out[3].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 6, 0)
node _requestDOI_T_15 = shr(out[3].d.bits.source, 7)
node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<1>(0h0))
node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3)
node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17)
node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<7>(0h7f))
node requestDOI_3_0 = and(_requestDOI_T_18, _requestDOI_T_19)
node _requestDOI_uncommonBits_T_4 = or(out[4].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 6, 0)
node _requestDOI_T_20 = shr(out[4].d.bits.source, 7)
node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<1>(0h0))
node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4)
node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22)
node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<7>(0h7f))
node requestDOI_4_0 = and(_requestDOI_T_23, _requestDOI_T_24)
node _requestDOI_uncommonBits_T_5 = or(out[5].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 6, 0)
node _requestDOI_T_25 = shr(out[5].d.bits.source, 7)
node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<1>(0h0))
node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5)
node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27)
node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<7>(0h7f))
node requestDOI_5_0 = and(_requestDOI_T_28, _requestDOI_T_29)
node _requestDOI_uncommonBits_T_6 = or(out[6].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 6, 0)
node _requestDOI_T_30 = shr(out[6].d.bits.source, 7)
node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<1>(0h0))
node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6)
node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32)
node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<7>(0h7f))
node requestDOI_6_0 = and(_requestDOI_T_33, _requestDOI_T_34)
node _requestDOI_uncommonBits_T_7 = or(out[7].d.bits.source, UInt<7>(0h0))
node requestDOI_uncommonBits_7 = bits(_requestDOI_uncommonBits_T_7, 6, 0)
node _requestDOI_T_35 = shr(out[7].d.bits.source, 7)
node _requestDOI_T_36 = eq(_requestDOI_T_35, UInt<1>(0h0))
node _requestDOI_T_37 = leq(UInt<1>(0h0), requestDOI_uncommonBits_7)
node _requestDOI_T_38 = and(_requestDOI_T_36, _requestDOI_T_37)
node _requestDOI_T_39 = leq(requestDOI_uncommonBits_7, UInt<7>(0h7f))
node requestDOI_7_0 = and(_requestDOI_T_38, _requestDOI_T_39)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_4.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_4.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits
connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid
connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready
wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_6.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_6.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_6.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits
connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid
connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready
wire _requestEIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_8.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_8.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_8.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_9.bits, _requestEIO_WIRE_8.bits
connect _requestEIO_WIRE_9.valid, _requestEIO_WIRE_8.valid
connect _requestEIO_WIRE_9.ready, _requestEIO_WIRE_8.ready
wire _requestEIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_10.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_10.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_10.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_11.bits, _requestEIO_WIRE_10.bits
connect _requestEIO_WIRE_11.valid, _requestEIO_WIRE_10.valid
connect _requestEIO_WIRE_11.ready, _requestEIO_WIRE_10.ready
wire _requestEIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_12.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_12.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_12.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_13.bits, _requestEIO_WIRE_12.bits
connect _requestEIO_WIRE_13.valid, _requestEIO_WIRE_12.valid
connect _requestEIO_WIRE_13.ready, _requestEIO_WIRE_12.ready
wire _requestEIO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_14.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_14.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_14.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_15.bits, _requestEIO_WIRE_14.bits
connect _requestEIO_WIRE_15.valid, _requestEIO_WIRE_14.valid
connect _requestEIO_WIRE_15.ready, _requestEIO_WIRE_14.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_2.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_2.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_2.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits
connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid
connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_4.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_4.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_4.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_4.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_4.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_4.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_4.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_4.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_5.bits, _beatsBO_WIRE_4.bits
connect _beatsBO_WIRE_5.valid, _beatsBO_WIRE_4.valid
connect _beatsBO_WIRE_5.ready, _beatsBO_WIRE_4.ready
node _beatsBO_decode_T_6 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_5.bits.size)
node _beatsBO_decode_T_7 = bits(_beatsBO_decode_T_6, 5, 0)
node _beatsBO_decode_T_8 = not(_beatsBO_decode_T_7)
node beatsBO_decode_2 = shr(_beatsBO_decode_T_8, 3)
node _beatsBO_opdata_T_2 = bits(_beatsBO_WIRE_5.bits.opcode, 2, 2)
node beatsBO_opdata_2 = eq(_beatsBO_opdata_T_2, UInt<1>(0h0))
node beatsBO_2 = mux(UInt<1>(0h0), beatsBO_decode_2, UInt<1>(0h0))
wire _beatsBO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_6.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_6.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_6.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_6.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_6.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_6.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_6.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_6.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_7.bits, _beatsBO_WIRE_6.bits
connect _beatsBO_WIRE_7.valid, _beatsBO_WIRE_6.valid
connect _beatsBO_WIRE_7.ready, _beatsBO_WIRE_6.ready
node _beatsBO_decode_T_9 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_7.bits.size)
node _beatsBO_decode_T_10 = bits(_beatsBO_decode_T_9, 5, 0)
node _beatsBO_decode_T_11 = not(_beatsBO_decode_T_10)
node beatsBO_decode_3 = shr(_beatsBO_decode_T_11, 3)
node _beatsBO_opdata_T_3 = bits(_beatsBO_WIRE_7.bits.opcode, 2, 2)
node beatsBO_opdata_3 = eq(_beatsBO_opdata_T_3, UInt<1>(0h0))
node beatsBO_3 = mux(UInt<1>(0h0), beatsBO_decode_3, UInt<1>(0h0))
wire _beatsBO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_8.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_8.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_8.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_8.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_8.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_8.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_8.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_8.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_8.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_9.bits, _beatsBO_WIRE_8.bits
connect _beatsBO_WIRE_9.valid, _beatsBO_WIRE_8.valid
connect _beatsBO_WIRE_9.ready, _beatsBO_WIRE_8.ready
node _beatsBO_decode_T_12 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_9.bits.size)
node _beatsBO_decode_T_13 = bits(_beatsBO_decode_T_12, 5, 0)
node _beatsBO_decode_T_14 = not(_beatsBO_decode_T_13)
node beatsBO_decode_4 = shr(_beatsBO_decode_T_14, 3)
node _beatsBO_opdata_T_4 = bits(_beatsBO_WIRE_9.bits.opcode, 2, 2)
node beatsBO_opdata_4 = eq(_beatsBO_opdata_T_4, UInt<1>(0h0))
node beatsBO_4 = mux(UInt<1>(0h0), beatsBO_decode_4, UInt<1>(0h0))
wire _beatsBO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_10.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_10.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_10.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_10.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_10.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_10.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_10.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_10.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_10.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_11.bits, _beatsBO_WIRE_10.bits
connect _beatsBO_WIRE_11.valid, _beatsBO_WIRE_10.valid
connect _beatsBO_WIRE_11.ready, _beatsBO_WIRE_10.ready
node _beatsBO_decode_T_15 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_11.bits.size)
node _beatsBO_decode_T_16 = bits(_beatsBO_decode_T_15, 5, 0)
node _beatsBO_decode_T_17 = not(_beatsBO_decode_T_16)
node beatsBO_decode_5 = shr(_beatsBO_decode_T_17, 3)
node _beatsBO_opdata_T_5 = bits(_beatsBO_WIRE_11.bits.opcode, 2, 2)
node beatsBO_opdata_5 = eq(_beatsBO_opdata_T_5, UInt<1>(0h0))
node beatsBO_5 = mux(UInt<1>(0h0), beatsBO_decode_5, UInt<1>(0h0))
wire _beatsBO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_12.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_12.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_12.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_12.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_12.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_12.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_12.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_12.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_12.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_13.bits, _beatsBO_WIRE_12.bits
connect _beatsBO_WIRE_13.valid, _beatsBO_WIRE_12.valid
connect _beatsBO_WIRE_13.ready, _beatsBO_WIRE_12.ready
node _beatsBO_decode_T_18 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_13.bits.size)
node _beatsBO_decode_T_19 = bits(_beatsBO_decode_T_18, 5, 0)
node _beatsBO_decode_T_20 = not(_beatsBO_decode_T_19)
node beatsBO_decode_6 = shr(_beatsBO_decode_T_20, 3)
node _beatsBO_opdata_T_6 = bits(_beatsBO_WIRE_13.bits.opcode, 2, 2)
node beatsBO_opdata_6 = eq(_beatsBO_opdata_T_6, UInt<1>(0h0))
node beatsBO_6 = mux(UInt<1>(0h0), beatsBO_decode_6, UInt<1>(0h0))
wire _beatsBO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_14.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_14.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_14.bits.address, UInt<29>(0h0)
connect _beatsBO_WIRE_14.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_14.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE_14.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_14.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_14.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_14.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_15.bits, _beatsBO_WIRE_14.bits
connect _beatsBO_WIRE_15.valid, _beatsBO_WIRE_14.valid
connect _beatsBO_WIRE_15.ready, _beatsBO_WIRE_14.ready
node _beatsBO_decode_T_21 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_15.bits.size)
node _beatsBO_decode_T_22 = bits(_beatsBO_decode_T_21, 5, 0)
node _beatsBO_decode_T_23 = not(_beatsBO_decode_T_22)
node beatsBO_decode_7 = shr(_beatsBO_decode_T_23, 3)
node _beatsBO_opdata_T_7 = bits(_beatsBO_WIRE_15.bits.opcode, 2, 2)
node beatsBO_opdata_7 = eq(_beatsBO_opdata_T_7, UInt<1>(0h0))
node beatsBO_7 = mux(UInt<1>(0h0), beatsBO_decode_7, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<29>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(beatsCI_opdata, beatsCI_decode, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T_6 = dshl(UInt<6>(0h3f), out[2].d.bits.size)
node _beatsDO_decode_T_7 = bits(_beatsDO_decode_T_6, 5, 0)
node _beatsDO_decode_T_8 = not(_beatsDO_decode_T_7)
node beatsDO_decode_2 = shr(_beatsDO_decode_T_8, 3)
node beatsDO_opdata_2 = bits(out[2].d.bits.opcode, 0, 0)
node beatsDO_2 = mux(beatsDO_opdata_2, beatsDO_decode_2, UInt<1>(0h0))
node _beatsDO_decode_T_9 = dshl(UInt<6>(0h3f), out[3].d.bits.size)
node _beatsDO_decode_T_10 = bits(_beatsDO_decode_T_9, 5, 0)
node _beatsDO_decode_T_11 = not(_beatsDO_decode_T_10)
node beatsDO_decode_3 = shr(_beatsDO_decode_T_11, 3)
node beatsDO_opdata_3 = bits(out[3].d.bits.opcode, 0, 0)
node beatsDO_3 = mux(beatsDO_opdata_3, beatsDO_decode_3, UInt<1>(0h0))
node _beatsDO_decode_T_12 = dshl(UInt<6>(0h3f), out[4].d.bits.size)
node _beatsDO_decode_T_13 = bits(_beatsDO_decode_T_12, 5, 0)
node _beatsDO_decode_T_14 = not(_beatsDO_decode_T_13)
node beatsDO_decode_4 = shr(_beatsDO_decode_T_14, 3)
node beatsDO_opdata_4 = bits(out[4].d.bits.opcode, 0, 0)
node beatsDO_4 = mux(beatsDO_opdata_4, beatsDO_decode_4, UInt<1>(0h0))
node _beatsDO_decode_T_15 = dshl(UInt<6>(0h3f), out[5].d.bits.size)
node _beatsDO_decode_T_16 = bits(_beatsDO_decode_T_15, 5, 0)
node _beatsDO_decode_T_17 = not(_beatsDO_decode_T_16)
node beatsDO_decode_5 = shr(_beatsDO_decode_T_17, 3)
node beatsDO_opdata_5 = bits(out[5].d.bits.opcode, 0, 0)
node beatsDO_5 = mux(beatsDO_opdata_5, beatsDO_decode_5, UInt<1>(0h0))
node _beatsDO_decode_T_18 = dshl(UInt<6>(0h3f), out[6].d.bits.size)
node _beatsDO_decode_T_19 = bits(_beatsDO_decode_T_18, 5, 0)
node _beatsDO_decode_T_20 = not(_beatsDO_decode_T_19)
node beatsDO_decode_6 = shr(_beatsDO_decode_T_20, 3)
node beatsDO_opdata_6 = bits(out[6].d.bits.opcode, 0, 0)
node beatsDO_6 = mux(UInt<1>(0h1), beatsDO_decode_6, UInt<1>(0h0))
node _beatsDO_decode_T_21 = dshl(UInt<6>(0h3f), out[7].d.bits.size)
node _beatsDO_decode_T_22 = bits(_beatsDO_decode_T_21, 5, 0)
node _beatsDO_decode_T_23 = not(_beatsDO_decode_T_22)
node beatsDO_decode_7 = shr(_beatsDO_decode_T_23, 3)
node beatsDO_opdata_7 = bits(out[7].d.bits.opcode, 0, 0)
node beatsDO_7 = mux(beatsDO_opdata_7, beatsDO_decode_7, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[8]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
connect portsAOI_filtered[2].bits, in[0].a.bits
node _portsAOI_filtered_2_valid_T = or(requestAIO_0_2, UInt<1>(0h0))
node _portsAOI_filtered_2_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_2_valid_T)
connect portsAOI_filtered[2].valid, _portsAOI_filtered_2_valid_T_1
connect portsAOI_filtered[3].bits, in[0].a.bits
node _portsAOI_filtered_3_valid_T = or(requestAIO_0_3, UInt<1>(0h0))
node _portsAOI_filtered_3_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_3_valid_T)
connect portsAOI_filtered[3].valid, _portsAOI_filtered_3_valid_T_1
connect portsAOI_filtered[4].bits, in[0].a.bits
node _portsAOI_filtered_4_valid_T = or(requestAIO_0_4, UInt<1>(0h0))
node _portsAOI_filtered_4_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_4_valid_T)
connect portsAOI_filtered[4].valid, _portsAOI_filtered_4_valid_T_1
connect portsAOI_filtered[5].bits, in[0].a.bits
node _portsAOI_filtered_5_valid_T = or(requestAIO_0_5, UInt<1>(0h0))
node _portsAOI_filtered_5_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_5_valid_T)
connect portsAOI_filtered[5].valid, _portsAOI_filtered_5_valid_T_1
connect portsAOI_filtered[6].bits, in[0].a.bits
node _portsAOI_filtered_6_valid_T = or(requestAIO_0_6, UInt<1>(0h0))
node _portsAOI_filtered_6_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_6_valid_T)
connect portsAOI_filtered[6].valid, _portsAOI_filtered_6_valid_T_1
connect portsAOI_filtered[7].bits, in[0].a.bits
node _portsAOI_filtered_7_valid_T = or(requestAIO_0_7, UInt<1>(0h0))
node _portsAOI_filtered_7_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_7_valid_T)
connect portsAOI_filtered[7].valid, _portsAOI_filtered_7_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = mux(requestAIO_0_2, portsAOI_filtered[2].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_3 = mux(requestAIO_0_3, portsAOI_filtered[3].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_4 = mux(requestAIO_0_4, portsAOI_filtered[4].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_5 = mux(requestAIO_0_5, portsAOI_filtered[5].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_6 = mux(requestAIO_0_6, portsAOI_filtered[6].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_7 = mux(requestAIO_0_7, portsAOI_filtered[7].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_8 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
node _portsAOI_in_0_a_ready_T_9 = or(_portsAOI_in_0_a_ready_T_8, _portsAOI_in_0_a_ready_T_2)
node _portsAOI_in_0_a_ready_T_10 = or(_portsAOI_in_0_a_ready_T_9, _portsAOI_in_0_a_ready_T_3)
node _portsAOI_in_0_a_ready_T_11 = or(_portsAOI_in_0_a_ready_T_10, _portsAOI_in_0_a_ready_T_4)
node _portsAOI_in_0_a_ready_T_12 = or(_portsAOI_in_0_a_ready_T_11, _portsAOI_in_0_a_ready_T_5)
node _portsAOI_in_0_a_ready_T_13 = or(_portsAOI_in_0_a_ready_T_12, _portsAOI_in_0_a_ready_T_6)
node _portsAOI_in_0_a_ready_T_14 = or(_portsAOI_in_0_a_ready_T_13, _portsAOI_in_0_a_ready_T_7)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_14
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect _portsBIO_WIRE_1.ready, portsBIO_filtered[0].ready
wire _portsBIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_2.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_2.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_2.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_2.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_2.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_3.bits, _portsBIO_WIRE_2.bits
connect _portsBIO_WIRE_3.valid, _portsBIO_WIRE_2.valid
connect _portsBIO_WIRE_3.ready, _portsBIO_WIRE_2.ready
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_3.bits
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_3.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect _portsBIO_WIRE_3.ready, portsBIO_filtered_1[0].ready
wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_4.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_4.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_4.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_4.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_4.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_4.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_4.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_4.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_5.bits, _portsBIO_WIRE_4.bits
connect _portsBIO_WIRE_5.valid, _portsBIO_WIRE_4.valid
connect _portsBIO_WIRE_5.ready, _portsBIO_WIRE_4.ready
wire portsBIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_2[0].bits, _portsBIO_WIRE_5.bits
node _portsBIO_filtered_0_valid_T_4 = or(requestBOI_2_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_5 = and(_portsBIO_WIRE_5.valid, _portsBIO_filtered_0_valid_T_4)
connect portsBIO_filtered_2[0].valid, _portsBIO_filtered_0_valid_T_5
connect _portsBIO_WIRE_5.ready, portsBIO_filtered_2[0].ready
wire _portsBIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_6.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_6.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_6.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_6.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_6.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_6.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_6.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_6.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_7.bits, _portsBIO_WIRE_6.bits
connect _portsBIO_WIRE_7.valid, _portsBIO_WIRE_6.valid
connect _portsBIO_WIRE_7.ready, _portsBIO_WIRE_6.ready
wire portsBIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_3[0].bits, _portsBIO_WIRE_7.bits
node _portsBIO_filtered_0_valid_T_6 = or(requestBOI_3_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_7 = and(_portsBIO_WIRE_7.valid, _portsBIO_filtered_0_valid_T_6)
connect portsBIO_filtered_3[0].valid, _portsBIO_filtered_0_valid_T_7
connect _portsBIO_WIRE_7.ready, portsBIO_filtered_3[0].ready
wire _portsBIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_8.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_8.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_8.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_8.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_8.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_8.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_8.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_8.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_8.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_9.bits, _portsBIO_WIRE_8.bits
connect _portsBIO_WIRE_9.valid, _portsBIO_WIRE_8.valid
connect _portsBIO_WIRE_9.ready, _portsBIO_WIRE_8.ready
wire portsBIO_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_4[0].bits, _portsBIO_WIRE_9.bits
node _portsBIO_filtered_0_valid_T_8 = or(requestBOI_4_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_9 = and(_portsBIO_WIRE_9.valid, _portsBIO_filtered_0_valid_T_8)
connect portsBIO_filtered_4[0].valid, _portsBIO_filtered_0_valid_T_9
connect _portsBIO_WIRE_9.ready, portsBIO_filtered_4[0].ready
wire _portsBIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_10.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_10.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_10.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_10.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_10.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_10.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_10.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_10.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_10.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_11.bits, _portsBIO_WIRE_10.bits
connect _portsBIO_WIRE_11.valid, _portsBIO_WIRE_10.valid
connect _portsBIO_WIRE_11.ready, _portsBIO_WIRE_10.ready
wire portsBIO_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_5[0].bits, _portsBIO_WIRE_11.bits
node _portsBIO_filtered_0_valid_T_10 = or(requestBOI_5_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_11 = and(_portsBIO_WIRE_11.valid, _portsBIO_filtered_0_valid_T_10)
connect portsBIO_filtered_5[0].valid, _portsBIO_filtered_0_valid_T_11
connect _portsBIO_WIRE_11.ready, portsBIO_filtered_5[0].ready
wire _portsBIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_12.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_12.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_12.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_12.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_12.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_12.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_12.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_12.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_12.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_13.bits, _portsBIO_WIRE_12.bits
connect _portsBIO_WIRE_13.valid, _portsBIO_WIRE_12.valid
connect _portsBIO_WIRE_13.ready, _portsBIO_WIRE_12.ready
wire portsBIO_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_6[0].bits, _portsBIO_WIRE_13.bits
node _portsBIO_filtered_0_valid_T_12 = or(requestBOI_6_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_13 = and(_portsBIO_WIRE_13.valid, _portsBIO_filtered_0_valid_T_12)
connect portsBIO_filtered_6[0].valid, _portsBIO_filtered_0_valid_T_13
connect _portsBIO_WIRE_13.ready, portsBIO_filtered_6[0].ready
wire _portsBIO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_14.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_14.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_14.bits.address, UInt<29>(0h0)
connect _portsBIO_WIRE_14.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_14.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE_14.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_14.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_14.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_14.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_15.bits, _portsBIO_WIRE_14.bits
connect _portsBIO_WIRE_15.valid, _portsBIO_WIRE_14.valid
connect _portsBIO_WIRE_15.ready, _portsBIO_WIRE_14.ready
wire portsBIO_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsBIO_filtered_7[0].bits, _portsBIO_WIRE_15.bits
node _portsBIO_filtered_0_valid_T_14 = or(requestBOI_7_0, UInt<1>(0h1))
node _portsBIO_filtered_0_valid_T_15 = and(_portsBIO_WIRE_15.valid, _portsBIO_filtered_0_valid_T_14)
connect portsBIO_filtered_7[0].valid, _portsBIO_filtered_0_valid_T_15
connect _portsBIO_WIRE_15.ready, portsBIO_filtered_7[0].ready
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<29>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[8]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
connect portsCOI_filtered[2].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_2_valid_T = or(requestCIO_0_2, UInt<1>(0h0))
node _portsCOI_filtered_2_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_2_valid_T)
connect portsCOI_filtered[2].valid, _portsCOI_filtered_2_valid_T_1
connect portsCOI_filtered[3].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_3_valid_T = or(requestCIO_0_3, UInt<1>(0h0))
node _portsCOI_filtered_3_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_3_valid_T)
connect portsCOI_filtered[3].valid, _portsCOI_filtered_3_valid_T_1
connect portsCOI_filtered[4].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_4_valid_T = or(requestCIO_0_4, UInt<1>(0h0))
node _portsCOI_filtered_4_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_4_valid_T)
connect portsCOI_filtered[4].valid, _portsCOI_filtered_4_valid_T_1
connect portsCOI_filtered[5].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_5_valid_T = or(requestCIO_0_5, UInt<1>(0h0))
node _portsCOI_filtered_5_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_5_valid_T)
connect portsCOI_filtered[5].valid, _portsCOI_filtered_5_valid_T_1
connect portsCOI_filtered[6].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_6_valid_T = or(requestCIO_0_6, UInt<1>(0h0))
node _portsCOI_filtered_6_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_6_valid_T)
connect portsCOI_filtered[6].valid, _portsCOI_filtered_6_valid_T_1
connect portsCOI_filtered[7].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_7_valid_T = or(requestCIO_0_7, UInt<1>(0h0))
node _portsCOI_filtered_7_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_7_valid_T)
connect portsCOI_filtered[7].valid, _portsCOI_filtered_7_valid_T_1
node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_T_2 = mux(requestCIO_0_2, portsCOI_filtered[2].ready, UInt<1>(0h0))
node _portsCOI_T_3 = mux(requestCIO_0_3, portsCOI_filtered[3].ready, UInt<1>(0h0))
node _portsCOI_T_4 = mux(requestCIO_0_4, portsCOI_filtered[4].ready, UInt<1>(0h0))
node _portsCOI_T_5 = mux(requestCIO_0_5, portsCOI_filtered[5].ready, UInt<1>(0h0))
node _portsCOI_T_6 = mux(requestCIO_0_6, portsCOI_filtered[6].ready, UInt<1>(0h0))
node _portsCOI_T_7 = mux(requestCIO_0_7, portsCOI_filtered[7].ready, UInt<1>(0h0))
node _portsCOI_T_8 = or(_portsCOI_T, _portsCOI_T_1)
node _portsCOI_T_9 = or(_portsCOI_T_8, _portsCOI_T_2)
node _portsCOI_T_10 = or(_portsCOI_T_9, _portsCOI_T_3)
node _portsCOI_T_11 = or(_portsCOI_T_10, _portsCOI_T_4)
node _portsCOI_T_12 = or(_portsCOI_T_11, _portsCOI_T_5)
node _portsCOI_T_13 = or(_portsCOI_T_12, _portsCOI_T_6)
node _portsCOI_T_14 = or(_portsCOI_T_13, _portsCOI_T_7)
wire _portsCOI_WIRE_2 : UInt<1>
connect _portsCOI_WIRE_2, _portsCOI_T_14
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect out[0].d.ready, portsDIO_filtered[0].ready
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect out[1].d.ready, portsDIO_filtered_1[0].ready
wire portsDIO_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_2[0].bits.corrupt, out[2].d.bits.corrupt
connect portsDIO_filtered_2[0].bits.data, out[2].d.bits.data
connect portsDIO_filtered_2[0].bits.denied, out[2].d.bits.denied
connect portsDIO_filtered_2[0].bits.sink, out[2].d.bits.sink
connect portsDIO_filtered_2[0].bits.source, out[2].d.bits.source
connect portsDIO_filtered_2[0].bits.size, out[2].d.bits.size
connect portsDIO_filtered_2[0].bits.param, out[2].d.bits.param
connect portsDIO_filtered_2[0].bits.opcode, out[2].d.bits.opcode
node _portsDIO_filtered_0_valid_T_4 = or(requestDOI_2_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_5 = and(out[2].d.valid, _portsDIO_filtered_0_valid_T_4)
connect portsDIO_filtered_2[0].valid, _portsDIO_filtered_0_valid_T_5
connect out[2].d.ready, portsDIO_filtered_2[0].ready
wire portsDIO_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_3[0].bits.corrupt, out[3].d.bits.corrupt
connect portsDIO_filtered_3[0].bits.data, out[3].d.bits.data
connect portsDIO_filtered_3[0].bits.denied, out[3].d.bits.denied
connect portsDIO_filtered_3[0].bits.sink, out[3].d.bits.sink
connect portsDIO_filtered_3[0].bits.source, out[3].d.bits.source
connect portsDIO_filtered_3[0].bits.size, out[3].d.bits.size
connect portsDIO_filtered_3[0].bits.param, out[3].d.bits.param
connect portsDIO_filtered_3[0].bits.opcode, out[3].d.bits.opcode
node _portsDIO_filtered_0_valid_T_6 = or(requestDOI_3_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_7 = and(out[3].d.valid, _portsDIO_filtered_0_valid_T_6)
connect portsDIO_filtered_3[0].valid, _portsDIO_filtered_0_valid_T_7
connect out[3].d.ready, portsDIO_filtered_3[0].ready
wire portsDIO_filtered_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_4[0].bits.corrupt, out[4].d.bits.corrupt
connect portsDIO_filtered_4[0].bits.data, out[4].d.bits.data
connect portsDIO_filtered_4[0].bits.denied, out[4].d.bits.denied
connect portsDIO_filtered_4[0].bits.sink, out[4].d.bits.sink
connect portsDIO_filtered_4[0].bits.source, out[4].d.bits.source
connect portsDIO_filtered_4[0].bits.size, out[4].d.bits.size
connect portsDIO_filtered_4[0].bits.param, out[4].d.bits.param
connect portsDIO_filtered_4[0].bits.opcode, out[4].d.bits.opcode
node _portsDIO_filtered_0_valid_T_8 = or(requestDOI_4_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_9 = and(out[4].d.valid, _portsDIO_filtered_0_valid_T_8)
connect portsDIO_filtered_4[0].valid, _portsDIO_filtered_0_valid_T_9
connect out[4].d.ready, portsDIO_filtered_4[0].ready
wire portsDIO_filtered_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_5[0].bits.corrupt, out[5].d.bits.corrupt
connect portsDIO_filtered_5[0].bits.data, out[5].d.bits.data
connect portsDIO_filtered_5[0].bits.denied, out[5].d.bits.denied
connect portsDIO_filtered_5[0].bits.sink, out[5].d.bits.sink
connect portsDIO_filtered_5[0].bits.source, out[5].d.bits.source
connect portsDIO_filtered_5[0].bits.size, out[5].d.bits.size
connect portsDIO_filtered_5[0].bits.param, out[5].d.bits.param
connect portsDIO_filtered_5[0].bits.opcode, out[5].d.bits.opcode
node _portsDIO_filtered_0_valid_T_10 = or(requestDOI_5_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_11 = and(out[5].d.valid, _portsDIO_filtered_0_valid_T_10)
connect portsDIO_filtered_5[0].valid, _portsDIO_filtered_0_valid_T_11
connect out[5].d.ready, portsDIO_filtered_5[0].ready
wire portsDIO_filtered_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_6[0].bits.corrupt, out[6].d.bits.corrupt
connect portsDIO_filtered_6[0].bits.data, out[6].d.bits.data
connect portsDIO_filtered_6[0].bits.denied, out[6].d.bits.denied
connect portsDIO_filtered_6[0].bits.sink, out[6].d.bits.sink
connect portsDIO_filtered_6[0].bits.source, out[6].d.bits.source
connect portsDIO_filtered_6[0].bits.size, out[6].d.bits.size
connect portsDIO_filtered_6[0].bits.param, out[6].d.bits.param
connect portsDIO_filtered_6[0].bits.opcode, out[6].d.bits.opcode
node _portsDIO_filtered_0_valid_T_12 = or(requestDOI_6_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_13 = and(out[6].d.valid, _portsDIO_filtered_0_valid_T_12)
connect portsDIO_filtered_6[0].valid, _portsDIO_filtered_0_valid_T_13
connect out[6].d.ready, portsDIO_filtered_6[0].ready
wire portsDIO_filtered_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsDIO_filtered_7[0].bits.corrupt, out[7].d.bits.corrupt
connect portsDIO_filtered_7[0].bits.data, out[7].d.bits.data
connect portsDIO_filtered_7[0].bits.denied, out[7].d.bits.denied
connect portsDIO_filtered_7[0].bits.sink, out[7].d.bits.sink
connect portsDIO_filtered_7[0].bits.source, out[7].d.bits.source
connect portsDIO_filtered_7[0].bits.size, out[7].d.bits.size
connect portsDIO_filtered_7[0].bits.param, out[7].d.bits.param
connect portsDIO_filtered_7[0].bits.opcode, out[7].d.bits.opcode
node _portsDIO_filtered_0_valid_T_14 = or(requestDOI_7_0, UInt<1>(0h1))
node _portsDIO_filtered_0_valid_T_15 = and(out[7].d.valid, _portsDIO_filtered_0_valid_T_14)
connect portsDIO_filtered_7[0].valid, _portsDIO_filtered_0_valid_T_15
connect out[7].d.ready, portsDIO_filtered_7[0].ready
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[8]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
connect portsEOI_filtered[2].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_2_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_2_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_2_valid_T)
connect portsEOI_filtered[2].valid, _portsEOI_filtered_2_valid_T_1
connect portsEOI_filtered[3].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_3_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_3_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_3_valid_T)
connect portsEOI_filtered[3].valid, _portsEOI_filtered_3_valid_T_1
connect portsEOI_filtered[4].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_4_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_4_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_4_valid_T)
connect portsEOI_filtered[4].valid, _portsEOI_filtered_4_valid_T_1
connect portsEOI_filtered[5].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_5_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_5_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_5_valid_T)
connect portsEOI_filtered[5].valid, _portsEOI_filtered_5_valid_T_1
connect portsEOI_filtered[6].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_6_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_6_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_6_valid_T)
connect portsEOI_filtered[6].valid, _portsEOI_filtered_6_valid_T_1
connect portsEOI_filtered[7].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_7_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_7_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_7_valid_T)
connect portsEOI_filtered[7].valid, _portsEOI_filtered_7_valid_T_1
node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_T_2 = mux(UInt<1>(0h0), portsEOI_filtered[2].ready, UInt<1>(0h0))
node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered[3].ready, UInt<1>(0h0))
node _portsEOI_T_4 = mux(UInt<1>(0h0), portsEOI_filtered[4].ready, UInt<1>(0h0))
node _portsEOI_T_5 = mux(UInt<1>(0h0), portsEOI_filtered[5].ready, UInt<1>(0h0))
node _portsEOI_T_6 = mux(UInt<1>(0h0), portsEOI_filtered[6].ready, UInt<1>(0h0))
node _portsEOI_T_7 = mux(UInt<1>(0h0), portsEOI_filtered[7].ready, UInt<1>(0h0))
node _portsEOI_T_8 = or(_portsEOI_T, _portsEOI_T_1)
node _portsEOI_T_9 = or(_portsEOI_T_8, _portsEOI_T_2)
node _portsEOI_T_10 = or(_portsEOI_T_9, _portsEOI_T_3)
node _portsEOI_T_11 = or(_portsEOI_T_10, _portsEOI_T_4)
node _portsEOI_T_12 = or(_portsEOI_T_11, _portsEOI_T_5)
node _portsEOI_T_13 = or(_portsEOI_T_12, _portsEOI_T_6)
node _portsEOI_T_14 = or(_portsEOI_T_13, _portsEOI_T_7)
wire _portsEOI_WIRE_2 : UInt<1>
connect _portsEOI_WIRE_2, _portsEOI_T_14
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2
connect out[0].a, portsAOI_filtered[0]
wire _WIRE_216 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_216.bits.corrupt, UInt<1>(0h0)
connect _WIRE_216.bits.data, UInt<64>(0h0)
connect _WIRE_216.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_216.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_216.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_216.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_216.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_216.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_216.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_216.bits.address, UInt<29>(0h0)
connect _WIRE_216.bits.source, UInt<7>(0h0)
connect _WIRE_216.bits.size, UInt<4>(0h0)
connect _WIRE_216.bits.param, UInt<3>(0h0)
connect _WIRE_216.bits.opcode, UInt<3>(0h0)
connect _WIRE_216.valid, UInt<1>(0h0)
connect _WIRE_216.ready, UInt<1>(0h0)
wire _WIRE_217 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_217.bits, _WIRE_216.bits
connect _WIRE_217.valid, _WIRE_216.valid
connect _WIRE_217.ready, _WIRE_216.ready
invalidate _WIRE_217.bits.corrupt
invalidate _WIRE_217.bits.data
invalidate _WIRE_217.bits.user.amba_prot.fetch
invalidate _WIRE_217.bits.user.amba_prot.secure
invalidate _WIRE_217.bits.user.amba_prot.privileged
invalidate _WIRE_217.bits.user.amba_prot.writealloc
invalidate _WIRE_217.bits.user.amba_prot.readalloc
invalidate _WIRE_217.bits.user.amba_prot.modifiable
invalidate _WIRE_217.bits.user.amba_prot.bufferable
invalidate _WIRE_217.bits.address
invalidate _WIRE_217.bits.source
invalidate _WIRE_217.bits.size
invalidate _WIRE_217.bits.param
invalidate _WIRE_217.bits.opcode
wire _WIRE_218 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_218.bits.sink, UInt<1>(0h0)
connect _WIRE_218.valid, UInt<1>(0h0)
connect _WIRE_218.ready, UInt<1>(0h0)
wire _WIRE_219 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_219.bits, _WIRE_218.bits
connect _WIRE_219.valid, _WIRE_218.valid
connect _WIRE_219.ready, _WIRE_218.ready
invalidate _WIRE_219.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect out[1].a, portsAOI_filtered[1]
wire _WIRE_220 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_220.bits.corrupt, UInt<1>(0h0)
connect _WIRE_220.bits.data, UInt<64>(0h0)
connect _WIRE_220.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_220.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_220.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_220.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_220.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_220.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_220.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_220.bits.address, UInt<29>(0h0)
connect _WIRE_220.bits.source, UInt<7>(0h0)
connect _WIRE_220.bits.size, UInt<4>(0h0)
connect _WIRE_220.bits.param, UInt<3>(0h0)
connect _WIRE_220.bits.opcode, UInt<3>(0h0)
connect _WIRE_220.valid, UInt<1>(0h0)
connect _WIRE_220.ready, UInt<1>(0h0)
wire _WIRE_221 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_221.bits, _WIRE_220.bits
connect _WIRE_221.valid, _WIRE_220.valid
connect _WIRE_221.ready, _WIRE_220.ready
invalidate _WIRE_221.bits.corrupt
invalidate _WIRE_221.bits.data
invalidate _WIRE_221.bits.user.amba_prot.fetch
invalidate _WIRE_221.bits.user.amba_prot.secure
invalidate _WIRE_221.bits.user.amba_prot.privileged
invalidate _WIRE_221.bits.user.amba_prot.writealloc
invalidate _WIRE_221.bits.user.amba_prot.readalloc
invalidate _WIRE_221.bits.user.amba_prot.modifiable
invalidate _WIRE_221.bits.user.amba_prot.bufferable
invalidate _WIRE_221.bits.address
invalidate _WIRE_221.bits.source
invalidate _WIRE_221.bits.size
invalidate _WIRE_221.bits.param
invalidate _WIRE_221.bits.opcode
wire _WIRE_222 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_222.bits.sink, UInt<1>(0h0)
connect _WIRE_222.valid, UInt<1>(0h0)
connect _WIRE_222.ready, UInt<1>(0h0)
wire _WIRE_223 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_223.bits, _WIRE_222.bits
connect _WIRE_223.valid, _WIRE_222.valid
connect _WIRE_223.ready, _WIRE_222.ready
invalidate _WIRE_223.bits.sink
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
connect out[2].a, portsAOI_filtered[2]
wire _WIRE_224 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_224.bits.corrupt, UInt<1>(0h0)
connect _WIRE_224.bits.data, UInt<64>(0h0)
connect _WIRE_224.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_224.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_224.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_224.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_224.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_224.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_224.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_224.bits.address, UInt<29>(0h0)
connect _WIRE_224.bits.source, UInt<7>(0h0)
connect _WIRE_224.bits.size, UInt<4>(0h0)
connect _WIRE_224.bits.param, UInt<3>(0h0)
connect _WIRE_224.bits.opcode, UInt<3>(0h0)
connect _WIRE_224.valid, UInt<1>(0h0)
connect _WIRE_224.ready, UInt<1>(0h0)
wire _WIRE_225 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_225.bits, _WIRE_224.bits
connect _WIRE_225.valid, _WIRE_224.valid
connect _WIRE_225.ready, _WIRE_224.ready
invalidate _WIRE_225.bits.corrupt
invalidate _WIRE_225.bits.data
invalidate _WIRE_225.bits.user.amba_prot.fetch
invalidate _WIRE_225.bits.user.amba_prot.secure
invalidate _WIRE_225.bits.user.amba_prot.privileged
invalidate _WIRE_225.bits.user.amba_prot.writealloc
invalidate _WIRE_225.bits.user.amba_prot.readalloc
invalidate _WIRE_225.bits.user.amba_prot.modifiable
invalidate _WIRE_225.bits.user.amba_prot.bufferable
invalidate _WIRE_225.bits.address
invalidate _WIRE_225.bits.source
invalidate _WIRE_225.bits.size
invalidate _WIRE_225.bits.param
invalidate _WIRE_225.bits.opcode
wire _WIRE_226 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_226.bits.sink, UInt<1>(0h0)
connect _WIRE_226.valid, UInt<1>(0h0)
connect _WIRE_226.ready, UInt<1>(0h0)
wire _WIRE_227 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_227.bits, _WIRE_226.bits
connect _WIRE_227.valid, _WIRE_226.valid
connect _WIRE_227.ready, _WIRE_226.ready
invalidate _WIRE_227.bits.sink
connect portsCOI_filtered[2].ready, UInt<1>(0h0)
connect portsEOI_filtered[2].ready, UInt<1>(0h0)
connect out[3].a, portsAOI_filtered[3]
wire _WIRE_228 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_228.bits.corrupt, UInt<1>(0h0)
connect _WIRE_228.bits.data, UInt<64>(0h0)
connect _WIRE_228.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_228.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_228.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_228.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_228.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_228.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_228.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_228.bits.address, UInt<29>(0h0)
connect _WIRE_228.bits.source, UInt<7>(0h0)
connect _WIRE_228.bits.size, UInt<4>(0h0)
connect _WIRE_228.bits.param, UInt<3>(0h0)
connect _WIRE_228.bits.opcode, UInt<3>(0h0)
connect _WIRE_228.valid, UInt<1>(0h0)
connect _WIRE_228.ready, UInt<1>(0h0)
wire _WIRE_229 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_229.bits, _WIRE_228.bits
connect _WIRE_229.valid, _WIRE_228.valid
connect _WIRE_229.ready, _WIRE_228.ready
invalidate _WIRE_229.bits.corrupt
invalidate _WIRE_229.bits.data
invalidate _WIRE_229.bits.user.amba_prot.fetch
invalidate _WIRE_229.bits.user.amba_prot.secure
invalidate _WIRE_229.bits.user.amba_prot.privileged
invalidate _WIRE_229.bits.user.amba_prot.writealloc
invalidate _WIRE_229.bits.user.amba_prot.readalloc
invalidate _WIRE_229.bits.user.amba_prot.modifiable
invalidate _WIRE_229.bits.user.amba_prot.bufferable
invalidate _WIRE_229.bits.address
invalidate _WIRE_229.bits.source
invalidate _WIRE_229.bits.size
invalidate _WIRE_229.bits.param
invalidate _WIRE_229.bits.opcode
wire _WIRE_230 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_230.bits.sink, UInt<1>(0h0)
connect _WIRE_230.valid, UInt<1>(0h0)
connect _WIRE_230.ready, UInt<1>(0h0)
wire _WIRE_231 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_231.bits, _WIRE_230.bits
connect _WIRE_231.valid, _WIRE_230.valid
connect _WIRE_231.ready, _WIRE_230.ready
invalidate _WIRE_231.bits.sink
connect portsCOI_filtered[3].ready, UInt<1>(0h0)
connect portsEOI_filtered[3].ready, UInt<1>(0h0)
connect out[4].a, portsAOI_filtered[4]
wire _WIRE_232 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_232.bits.corrupt, UInt<1>(0h0)
connect _WIRE_232.bits.data, UInt<64>(0h0)
connect _WIRE_232.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_232.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_232.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_232.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_232.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_232.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_232.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_232.bits.address, UInt<29>(0h0)
connect _WIRE_232.bits.source, UInt<7>(0h0)
connect _WIRE_232.bits.size, UInt<4>(0h0)
connect _WIRE_232.bits.param, UInt<3>(0h0)
connect _WIRE_232.bits.opcode, UInt<3>(0h0)
connect _WIRE_232.valid, UInt<1>(0h0)
connect _WIRE_232.ready, UInt<1>(0h0)
wire _WIRE_233 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_233.bits, _WIRE_232.bits
connect _WIRE_233.valid, _WIRE_232.valid
connect _WIRE_233.ready, _WIRE_232.ready
invalidate _WIRE_233.bits.corrupt
invalidate _WIRE_233.bits.data
invalidate _WIRE_233.bits.user.amba_prot.fetch
invalidate _WIRE_233.bits.user.amba_prot.secure
invalidate _WIRE_233.bits.user.amba_prot.privileged
invalidate _WIRE_233.bits.user.amba_prot.writealloc
invalidate _WIRE_233.bits.user.amba_prot.readalloc
invalidate _WIRE_233.bits.user.amba_prot.modifiable
invalidate _WIRE_233.bits.user.amba_prot.bufferable
invalidate _WIRE_233.bits.address
invalidate _WIRE_233.bits.source
invalidate _WIRE_233.bits.size
invalidate _WIRE_233.bits.param
invalidate _WIRE_233.bits.opcode
wire _WIRE_234 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_234.bits.sink, UInt<1>(0h0)
connect _WIRE_234.valid, UInt<1>(0h0)
connect _WIRE_234.ready, UInt<1>(0h0)
wire _WIRE_235 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_235.bits, _WIRE_234.bits
connect _WIRE_235.valid, _WIRE_234.valid
connect _WIRE_235.ready, _WIRE_234.ready
invalidate _WIRE_235.bits.sink
connect portsCOI_filtered[4].ready, UInt<1>(0h0)
connect portsEOI_filtered[4].ready, UInt<1>(0h0)
connect out[5].a, portsAOI_filtered[5]
wire _WIRE_236 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_236.bits.corrupt, UInt<1>(0h0)
connect _WIRE_236.bits.data, UInt<64>(0h0)
connect _WIRE_236.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_236.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_236.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_236.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_236.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_236.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_236.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_236.bits.address, UInt<29>(0h0)
connect _WIRE_236.bits.source, UInt<7>(0h0)
connect _WIRE_236.bits.size, UInt<4>(0h0)
connect _WIRE_236.bits.param, UInt<3>(0h0)
connect _WIRE_236.bits.opcode, UInt<3>(0h0)
connect _WIRE_236.valid, UInt<1>(0h0)
connect _WIRE_236.ready, UInt<1>(0h0)
wire _WIRE_237 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_237.bits, _WIRE_236.bits
connect _WIRE_237.valid, _WIRE_236.valid
connect _WIRE_237.ready, _WIRE_236.ready
invalidate _WIRE_237.bits.corrupt
invalidate _WIRE_237.bits.data
invalidate _WIRE_237.bits.user.amba_prot.fetch
invalidate _WIRE_237.bits.user.amba_prot.secure
invalidate _WIRE_237.bits.user.amba_prot.privileged
invalidate _WIRE_237.bits.user.amba_prot.writealloc
invalidate _WIRE_237.bits.user.amba_prot.readalloc
invalidate _WIRE_237.bits.user.amba_prot.modifiable
invalidate _WIRE_237.bits.user.amba_prot.bufferable
invalidate _WIRE_237.bits.address
invalidate _WIRE_237.bits.source
invalidate _WIRE_237.bits.size
invalidate _WIRE_237.bits.param
invalidate _WIRE_237.bits.opcode
wire _WIRE_238 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_238.bits.sink, UInt<1>(0h0)
connect _WIRE_238.valid, UInt<1>(0h0)
connect _WIRE_238.ready, UInt<1>(0h0)
wire _WIRE_239 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_239.bits, _WIRE_238.bits
connect _WIRE_239.valid, _WIRE_238.valid
connect _WIRE_239.ready, _WIRE_238.ready
invalidate _WIRE_239.bits.sink
connect portsCOI_filtered[5].ready, UInt<1>(0h0)
connect portsEOI_filtered[5].ready, UInt<1>(0h0)
connect out[6].a, portsAOI_filtered[6]
wire _WIRE_240 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_240.bits.corrupt, UInt<1>(0h0)
connect _WIRE_240.bits.data, UInt<64>(0h0)
connect _WIRE_240.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_240.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_240.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_240.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_240.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_240.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_240.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_240.bits.address, UInt<29>(0h0)
connect _WIRE_240.bits.source, UInt<7>(0h0)
connect _WIRE_240.bits.size, UInt<4>(0h0)
connect _WIRE_240.bits.param, UInt<3>(0h0)
connect _WIRE_240.bits.opcode, UInt<3>(0h0)
connect _WIRE_240.valid, UInt<1>(0h0)
connect _WIRE_240.ready, UInt<1>(0h0)
wire _WIRE_241 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_241.bits, _WIRE_240.bits
connect _WIRE_241.valid, _WIRE_240.valid
connect _WIRE_241.ready, _WIRE_240.ready
invalidate _WIRE_241.bits.corrupt
invalidate _WIRE_241.bits.data
invalidate _WIRE_241.bits.user.amba_prot.fetch
invalidate _WIRE_241.bits.user.amba_prot.secure
invalidate _WIRE_241.bits.user.amba_prot.privileged
invalidate _WIRE_241.bits.user.amba_prot.writealloc
invalidate _WIRE_241.bits.user.amba_prot.readalloc
invalidate _WIRE_241.bits.user.amba_prot.modifiable
invalidate _WIRE_241.bits.user.amba_prot.bufferable
invalidate _WIRE_241.bits.address
invalidate _WIRE_241.bits.source
invalidate _WIRE_241.bits.size
invalidate _WIRE_241.bits.param
invalidate _WIRE_241.bits.opcode
wire _WIRE_242 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_242.bits.sink, UInt<1>(0h0)
connect _WIRE_242.valid, UInt<1>(0h0)
connect _WIRE_242.ready, UInt<1>(0h0)
wire _WIRE_243 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_243.bits, _WIRE_242.bits
connect _WIRE_243.valid, _WIRE_242.valid
connect _WIRE_243.ready, _WIRE_242.ready
invalidate _WIRE_243.bits.sink
connect portsCOI_filtered[6].ready, UInt<1>(0h0)
connect portsEOI_filtered[6].ready, UInt<1>(0h0)
connect out[7].a, portsAOI_filtered[7]
wire _WIRE_244 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_244.bits.corrupt, UInt<1>(0h0)
connect _WIRE_244.bits.data, UInt<64>(0h0)
connect _WIRE_244.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_244.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_244.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_244.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_244.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_244.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_244.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_244.bits.address, UInt<29>(0h0)
connect _WIRE_244.bits.source, UInt<7>(0h0)
connect _WIRE_244.bits.size, UInt<4>(0h0)
connect _WIRE_244.bits.param, UInt<3>(0h0)
connect _WIRE_244.bits.opcode, UInt<3>(0h0)
connect _WIRE_244.valid, UInt<1>(0h0)
connect _WIRE_244.ready, UInt<1>(0h0)
wire _WIRE_245 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_245.bits, _WIRE_244.bits
connect _WIRE_245.valid, _WIRE_244.valid
connect _WIRE_245.ready, _WIRE_244.ready
invalidate _WIRE_245.bits.corrupt
invalidate _WIRE_245.bits.data
invalidate _WIRE_245.bits.user.amba_prot.fetch
invalidate _WIRE_245.bits.user.amba_prot.secure
invalidate _WIRE_245.bits.user.amba_prot.privileged
invalidate _WIRE_245.bits.user.amba_prot.writealloc
invalidate _WIRE_245.bits.user.amba_prot.readalloc
invalidate _WIRE_245.bits.user.amba_prot.modifiable
invalidate _WIRE_245.bits.user.amba_prot.bufferable
invalidate _WIRE_245.bits.address
invalidate _WIRE_245.bits.source
invalidate _WIRE_245.bits.size
invalidate _WIRE_245.bits.param
invalidate _WIRE_245.bits.opcode
wire _WIRE_246 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_246.bits.sink, UInt<1>(0h0)
connect _WIRE_246.valid, UInt<1>(0h0)
connect _WIRE_246.ready, UInt<1>(0h0)
wire _WIRE_247 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_247.bits, _WIRE_246.bits
connect _WIRE_247.valid, _WIRE_246.valid
connect _WIRE_247.ready, _WIRE_246.ready
invalidate _WIRE_247.bits.sink
connect portsCOI_filtered[7].ready, UInt<1>(0h0)
connect portsEOI_filtered[7].ready, UInt<1>(0h0)
wire _WIRE_248 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_248.bits.corrupt, UInt<1>(0h0)
connect _WIRE_248.bits.data, UInt<64>(0h0)
connect _WIRE_248.bits.mask, UInt<8>(0h0)
connect _WIRE_248.bits.address, UInt<29>(0h0)
connect _WIRE_248.bits.source, UInt<7>(0h0)
connect _WIRE_248.bits.size, UInt<4>(0h0)
connect _WIRE_248.bits.param, UInt<2>(0h0)
connect _WIRE_248.bits.opcode, UInt<3>(0h0)
connect _WIRE_248.valid, UInt<1>(0h0)
connect _WIRE_248.ready, UInt<1>(0h0)
wire _WIRE_249 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_249.bits, _WIRE_248.bits
connect _WIRE_249.valid, _WIRE_248.valid
connect _WIRE_249.ready, _WIRE_248.ready
invalidate _WIRE_249.bits.corrupt
invalidate _WIRE_249.bits.data
invalidate _WIRE_249.bits.mask
invalidate _WIRE_249.bits.address
invalidate _WIRE_249.bits.source
invalidate _WIRE_249.bits.size
invalidate _WIRE_249.bits.param
invalidate _WIRE_249.bits.opcode
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, in[0].d.ready)
node readys_lo_lo = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_lo_hi = cat(portsDIO_filtered_3[0].valid, portsDIO_filtered_2[0].valid)
node readys_lo = cat(readys_lo_hi, readys_lo_lo)
node readys_hi_lo = cat(portsDIO_filtered_5[0].valid, portsDIO_filtered_4[0].valid)
node readys_hi_hi = cat(portsDIO_filtered_7[0].valid, portsDIO_filtered_6[0].valid)
node readys_hi = cat(readys_hi_hi, readys_hi_lo)
node _readys_T = cat(readys_hi, readys_lo)
node readys_valid = bits(_readys_T, 7, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<8>, clock, reset, UInt<8>(0hff)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = shr(_readys_unready_T_3, 4)
node _readys_unready_T_5 = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_unready_T_6 = bits(_readys_unready_T_5, 15, 0)
node _readys_unready_T_7 = shr(_readys_unready_T_6, 1)
node _readys_unready_T_8 = shl(readys_mask, 8)
node readys_unready = or(_readys_unready_T_7, _readys_unready_T_8)
node _readys_readys_T = shr(readys_unready, 8)
node _readys_readys_T_1 = bits(readys_unready, 7, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 7, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 7, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = shl(_readys_mask_T_6, 4)
node _readys_mask_T_8 = bits(_readys_mask_T_7, 7, 0)
node _readys_mask_T_9 = or(_readys_mask_T_6, _readys_mask_T_8)
node _readys_mask_T_10 = bits(_readys_mask_T_9, 7, 0)
connect readys_mask, _readys_mask_T_10
node _readys_T_7 = bits(readys_readys, 7, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
node _readys_T_11 = bits(_readys_T_7, 3, 3)
node _readys_T_12 = bits(_readys_T_7, 4, 4)
node _readys_T_13 = bits(_readys_T_7, 5, 5)
node _readys_T_14 = bits(_readys_T_7, 6, 6)
node _readys_T_15 = bits(_readys_T_7, 7, 7)
wire readys : UInt<1>[8]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
connect readys[3], _readys_T_11
connect readys[4], _readys_T_12
connect readys[5], _readys_T_13
connect readys[6], _readys_T_14
connect readys[7], _readys_T_15
node _winner_T = and(readys[0], portsDIO_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsDIO_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsDIO_filtered_2[0].valid)
node _winner_T_3 = and(readys[3], portsDIO_filtered_3[0].valid)
node _winner_T_4 = and(readys[4], portsDIO_filtered_4[0].valid)
node _winner_T_5 = and(readys[5], portsDIO_filtered_5[0].valid)
node _winner_T_6 = and(readys[6], portsDIO_filtered_6[0].valid)
node _winner_T_7 = and(readys[7], portsDIO_filtered_7[0].valid)
wire winner : UInt<1>[8]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
connect winner[3], _winner_T_3
connect winner[4], _winner_T_4
connect winner[5], _winner_T_5
connect winner[6], _winner_T_6
connect winner[7], _winner_T_7
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node prefixOR_3 = or(prefixOR_2, winner[2])
node prefixOR_4 = or(prefixOR_3, winner[3])
node prefixOR_5 = or(prefixOR_4, winner[4])
node prefixOR_6 = or(prefixOR_5, winner[5])
node prefixOR_7 = or(prefixOR_6, winner[6])
node _prefixOR_T = or(prefixOR_7, winner[7])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = eq(prefixOR_3, UInt<1>(0h0))
node _T_10 = eq(winner[3], UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = eq(prefixOR_4, UInt<1>(0h0))
node _T_13 = eq(winner[4], UInt<1>(0h0))
node _T_14 = or(_T_12, _T_13)
node _T_15 = eq(prefixOR_5, UInt<1>(0h0))
node _T_16 = eq(winner[5], UInt<1>(0h0))
node _T_17 = or(_T_15, _T_16)
node _T_18 = eq(prefixOR_6, UInt<1>(0h0))
node _T_19 = eq(winner[6], UInt<1>(0h0))
node _T_20 = or(_T_18, _T_19)
node _T_21 = eq(prefixOR_7, UInt<1>(0h0))
node _T_22 = eq(winner[7], UInt<1>(0h0))
node _T_23 = or(_T_21, _T_22)
node _T_24 = and(_T_2, _T_5)
node _T_25 = and(_T_24, _T_8)
node _T_26 = and(_T_25, _T_11)
node _T_27 = and(_T_26, _T_14)
node _T_28 = and(_T_27, _T_17)
node _T_29 = and(_T_28, _T_20)
node _T_30 = and(_T_29, _T_23)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_30, UInt<1>(0h1), "") : assert
node _T_34 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_35 = or(_T_34, portsDIO_filtered_2[0].valid)
node _T_36 = or(_T_35, portsDIO_filtered_3[0].valid)
node _T_37 = or(_T_36, portsDIO_filtered_4[0].valid)
node _T_38 = or(_T_37, portsDIO_filtered_5[0].valid)
node _T_39 = or(_T_38, portsDIO_filtered_6[0].valid)
node _T_40 = or(_T_39, portsDIO_filtered_7[0].valid)
node _T_41 = eq(_T_40, UInt<1>(0h0))
node _T_42 = or(winner[0], winner[1])
node _T_43 = or(_T_42, winner[2])
node _T_44 = or(_T_43, winner[3])
node _T_45 = or(_T_44, winner[4])
node _T_46 = or(_T_45, winner[5])
node _T_47 = or(_T_46, winner[6])
node _T_48 = or(_T_47, winner[7])
node _T_49 = or(_T_41, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_49, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsDO_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsDO_2, UInt<1>(0h0))
node maskedBeats_3 = mux(winner[3], beatsDO_3, UInt<1>(0h0))
node maskedBeats_4 = mux(winner[4], beatsDO_4, UInt<1>(0h0))
node maskedBeats_5 = mux(winner[5], beatsDO_5, UInt<1>(0h0))
node maskedBeats_6 = mux(winner[6], beatsDO_6, UInt<1>(0h0))
node maskedBeats_7 = mux(winner[7], beatsDO_7, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2)
node _initBeats_T_2 = or(_initBeats_T_1, maskedBeats_3)
node _initBeats_T_3 = or(_initBeats_T_2, maskedBeats_4)
node _initBeats_T_4 = or(_initBeats_T_3, maskedBeats_5)
node _initBeats_T_5 = or(_initBeats_T_4, maskedBeats_6)
node initBeats = or(_initBeats_T_5, maskedBeats_7)
node _beatsLeft_T = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[8]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
connect _state_WIRE[3], UInt<1>(0h0)
connect _state_WIRE[4], UInt<1>(0h0)
connect _state_WIRE[5], UInt<1>(0h0)
connect _state_WIRE[6], UInt<1>(0h0)
connect _state_WIRE[7], UInt<1>(0h0)
regreset state : UInt<1>[8], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(in[0].d.ready, allowed[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(in[0].d.ready, allowed[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(in[0].d.ready, allowed[2])
connect portsDIO_filtered_2[0].ready, _filtered_0_ready_T_2
node _filtered_0_ready_T_3 = and(in[0].d.ready, allowed[3])
connect portsDIO_filtered_3[0].ready, _filtered_0_ready_T_3
node _filtered_0_ready_T_4 = and(in[0].d.ready, allowed[4])
connect portsDIO_filtered_4[0].ready, _filtered_0_ready_T_4
node _filtered_0_ready_T_5 = and(in[0].d.ready, allowed[5])
connect portsDIO_filtered_5[0].ready, _filtered_0_ready_T_5
node _filtered_0_ready_T_6 = and(in[0].d.ready, allowed[6])
connect portsDIO_filtered_6[0].ready, _filtered_0_ready_T_6
node _filtered_0_ready_T_7 = and(in[0].d.ready, allowed[7])
connect portsDIO_filtered_7[0].ready, _filtered_0_ready_T_7
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = or(_in_0_d_valid_T, portsDIO_filtered_2[0].valid)
node _in_0_d_valid_T_2 = or(_in_0_d_valid_T_1, portsDIO_filtered_3[0].valid)
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_2, portsDIO_filtered_4[0].valid)
node _in_0_d_valid_T_4 = or(_in_0_d_valid_T_3, portsDIO_filtered_5[0].valid)
node _in_0_d_valid_T_5 = or(_in_0_d_valid_T_4, portsDIO_filtered_6[0].valid)
node _in_0_d_valid_T_6 = or(_in_0_d_valid_T_5, portsDIO_filtered_7[0].valid)
node _in_0_d_valid_T_7 = mux(state[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_8 = mux(state[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_9 = mux(state[2], portsDIO_filtered_2[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_10 = mux(state[3], portsDIO_filtered_3[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_11 = mux(state[4], portsDIO_filtered_4[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_12 = mux(state[5], portsDIO_filtered_5[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_13 = mux(state[6], portsDIO_filtered_6[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_14 = mux(state[7], portsDIO_filtered_7[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_15 = or(_in_0_d_valid_T_7, _in_0_d_valid_T_8)
node _in_0_d_valid_T_16 = or(_in_0_d_valid_T_15, _in_0_d_valid_T_9)
node _in_0_d_valid_T_17 = or(_in_0_d_valid_T_16, _in_0_d_valid_T_10)
node _in_0_d_valid_T_18 = or(_in_0_d_valid_T_17, _in_0_d_valid_T_11)
node _in_0_d_valid_T_19 = or(_in_0_d_valid_T_18, _in_0_d_valid_T_12)
node _in_0_d_valid_T_20 = or(_in_0_d_valid_T_19, _in_0_d_valid_T_13)
node _in_0_d_valid_T_21 = or(_in_0_d_valid_T_20, _in_0_d_valid_T_14)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_21
node _in_0_d_valid_T_22 = mux(idle, _in_0_d_valid_T_6, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_22
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = mux(muxState[2], portsDIO_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_3 = mux(muxState[3], portsDIO_filtered_3[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState[4], portsDIO_filtered_4[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_5 = mux(muxState[5], portsDIO_filtered_5[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_6 = mux(muxState[6], portsDIO_filtered_6[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState[7], portsDIO_filtered_7[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
node _in_0_d_bits_T_9 = or(_in_0_d_bits_T_8, _in_0_d_bits_T_2)
node _in_0_d_bits_T_10 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_3)
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_10, _in_0_d_bits_T_4)
node _in_0_d_bits_T_12 = or(_in_0_d_bits_T_11, _in_0_d_bits_T_5)
node _in_0_d_bits_T_13 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_6)
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_13, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_15 = mux(muxState[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_17 = mux(muxState[2], portsDIO_filtered_2[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_18 = mux(muxState[3], portsDIO_filtered_3[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState[4], portsDIO_filtered_4[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_20 = mux(muxState[5], portsDIO_filtered_5[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_21 = mux(muxState[6], portsDIO_filtered_6[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState[7], portsDIO_filtered_7[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
node _in_0_d_bits_T_24 = or(_in_0_d_bits_T_23, _in_0_d_bits_T_17)
node _in_0_d_bits_T_25 = or(_in_0_d_bits_T_24, _in_0_d_bits_T_18)
node _in_0_d_bits_T_26 = or(_in_0_d_bits_T_25, _in_0_d_bits_T_19)
node _in_0_d_bits_T_27 = or(_in_0_d_bits_T_26, _in_0_d_bits_T_20)
node _in_0_d_bits_T_28 = or(_in_0_d_bits_T_27, _in_0_d_bits_T_21)
node _in_0_d_bits_T_29 = or(_in_0_d_bits_T_28, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_29
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_30 = mux(muxState[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_31 = mux(muxState[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_32 = mux(muxState[2], portsDIO_filtered_2[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_33 = mux(muxState[3], portsDIO_filtered_3[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_34 = mux(muxState[4], portsDIO_filtered_4[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_35 = mux(muxState[5], portsDIO_filtered_5[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_36 = mux(muxState[6], portsDIO_filtered_6[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_37 = mux(muxState[7], portsDIO_filtered_7[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_38 = or(_in_0_d_bits_T_30, _in_0_d_bits_T_31)
node _in_0_d_bits_T_39 = or(_in_0_d_bits_T_38, _in_0_d_bits_T_32)
node _in_0_d_bits_T_40 = or(_in_0_d_bits_T_39, _in_0_d_bits_T_33)
node _in_0_d_bits_T_41 = or(_in_0_d_bits_T_40, _in_0_d_bits_T_34)
node _in_0_d_bits_T_42 = or(_in_0_d_bits_T_41, _in_0_d_bits_T_35)
node _in_0_d_bits_T_43 = or(_in_0_d_bits_T_42, _in_0_d_bits_T_36)
node _in_0_d_bits_T_44 = or(_in_0_d_bits_T_43, _in_0_d_bits_T_37)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_44
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_45 = mux(muxState[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_46 = mux(muxState[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_47 = mux(muxState[2], portsDIO_filtered_2[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_48 = mux(muxState[3], portsDIO_filtered_3[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_49 = mux(muxState[4], portsDIO_filtered_4[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_50 = mux(muxState[5], portsDIO_filtered_5[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_51 = mux(muxState[6], portsDIO_filtered_6[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_52 = mux(muxState[7], portsDIO_filtered_7[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_53 = or(_in_0_d_bits_T_45, _in_0_d_bits_T_46)
node _in_0_d_bits_T_54 = or(_in_0_d_bits_T_53, _in_0_d_bits_T_47)
node _in_0_d_bits_T_55 = or(_in_0_d_bits_T_54, _in_0_d_bits_T_48)
node _in_0_d_bits_T_56 = or(_in_0_d_bits_T_55, _in_0_d_bits_T_49)
node _in_0_d_bits_T_57 = or(_in_0_d_bits_T_56, _in_0_d_bits_T_50)
node _in_0_d_bits_T_58 = or(_in_0_d_bits_T_57, _in_0_d_bits_T_51)
node _in_0_d_bits_T_59 = or(_in_0_d_bits_T_58, _in_0_d_bits_T_52)
wire _in_0_d_bits_WIRE_6 : UInt<1>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_59
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_60 = mux(muxState[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_61 = mux(muxState[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_62 = mux(muxState[2], portsDIO_filtered_2[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_63 = mux(muxState[3], portsDIO_filtered_3[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_64 = mux(muxState[4], portsDIO_filtered_4[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_65 = mux(muxState[5], portsDIO_filtered_5[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_66 = mux(muxState[6], portsDIO_filtered_6[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_67 = mux(muxState[7], portsDIO_filtered_7[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_68 = or(_in_0_d_bits_T_60, _in_0_d_bits_T_61)
node _in_0_d_bits_T_69 = or(_in_0_d_bits_T_68, _in_0_d_bits_T_62)
node _in_0_d_bits_T_70 = or(_in_0_d_bits_T_69, _in_0_d_bits_T_63)
node _in_0_d_bits_T_71 = or(_in_0_d_bits_T_70, _in_0_d_bits_T_64)
node _in_0_d_bits_T_72 = or(_in_0_d_bits_T_71, _in_0_d_bits_T_65)
node _in_0_d_bits_T_73 = or(_in_0_d_bits_T_72, _in_0_d_bits_T_66)
node _in_0_d_bits_T_74 = or(_in_0_d_bits_T_73, _in_0_d_bits_T_67)
wire _in_0_d_bits_WIRE_7 : UInt<7>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_74
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_75 = mux(muxState[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_76 = mux(muxState[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_77 = mux(muxState[2], portsDIO_filtered_2[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_78 = mux(muxState[3], portsDIO_filtered_3[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_79 = mux(muxState[4], portsDIO_filtered_4[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_80 = mux(muxState[5], portsDIO_filtered_5[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_81 = mux(muxState[6], portsDIO_filtered_6[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_82 = mux(muxState[7], portsDIO_filtered_7[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_83 = or(_in_0_d_bits_T_75, _in_0_d_bits_T_76)
node _in_0_d_bits_T_84 = or(_in_0_d_bits_T_83, _in_0_d_bits_T_77)
node _in_0_d_bits_T_85 = or(_in_0_d_bits_T_84, _in_0_d_bits_T_78)
node _in_0_d_bits_T_86 = or(_in_0_d_bits_T_85, _in_0_d_bits_T_79)
node _in_0_d_bits_T_87 = or(_in_0_d_bits_T_86, _in_0_d_bits_T_80)
node _in_0_d_bits_T_88 = or(_in_0_d_bits_T_87, _in_0_d_bits_T_81)
node _in_0_d_bits_T_89 = or(_in_0_d_bits_T_88, _in_0_d_bits_T_82)
wire _in_0_d_bits_WIRE_8 : UInt<4>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_89
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_90 = mux(muxState[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_91 = mux(muxState[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_92 = mux(muxState[2], portsDIO_filtered_2[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_93 = mux(muxState[3], portsDIO_filtered_3[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_94 = mux(muxState[4], portsDIO_filtered_4[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_95 = mux(muxState[5], portsDIO_filtered_5[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_96 = mux(muxState[6], portsDIO_filtered_6[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_97 = mux(muxState[7], portsDIO_filtered_7[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_98 = or(_in_0_d_bits_T_90, _in_0_d_bits_T_91)
node _in_0_d_bits_T_99 = or(_in_0_d_bits_T_98, _in_0_d_bits_T_92)
node _in_0_d_bits_T_100 = or(_in_0_d_bits_T_99, _in_0_d_bits_T_93)
node _in_0_d_bits_T_101 = or(_in_0_d_bits_T_100, _in_0_d_bits_T_94)
node _in_0_d_bits_T_102 = or(_in_0_d_bits_T_101, _in_0_d_bits_T_95)
node _in_0_d_bits_T_103 = or(_in_0_d_bits_T_102, _in_0_d_bits_T_96)
node _in_0_d_bits_T_104 = or(_in_0_d_bits_T_103, _in_0_d_bits_T_97)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_104
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_105 = mux(muxState[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_106 = mux(muxState[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_107 = mux(muxState[2], portsDIO_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_108 = mux(muxState[3], portsDIO_filtered_3[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_109 = mux(muxState[4], portsDIO_filtered_4[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_110 = mux(muxState[5], portsDIO_filtered_5[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_111 = mux(muxState[6], portsDIO_filtered_6[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_112 = mux(muxState[7], portsDIO_filtered_7[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_113 = or(_in_0_d_bits_T_105, _in_0_d_bits_T_106)
node _in_0_d_bits_T_114 = or(_in_0_d_bits_T_113, _in_0_d_bits_T_107)
node _in_0_d_bits_T_115 = or(_in_0_d_bits_T_114, _in_0_d_bits_T_108)
node _in_0_d_bits_T_116 = or(_in_0_d_bits_T_115, _in_0_d_bits_T_109)
node _in_0_d_bits_T_117 = or(_in_0_d_bits_T_116, _in_0_d_bits_T_110)
node _in_0_d_bits_T_118 = or(_in_0_d_bits_T_117, _in_0_d_bits_T_111)
node _in_0_d_bits_T_119 = or(_in_0_d_bits_T_118, _in_0_d_bits_T_112)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_119
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_2[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_3[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_4[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_5[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_6[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_7[0].ready, UInt<1>(0h0)
extmodule plusarg_reader_38 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_39 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_cbus_out_i1_o8_a29d64s7k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire requestAIO_0_0 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[14], ~(auto_anon_in_a_bits_address[13:12])} == 8'h0; // @[Xbar.scala:222:41]
wire [9:0] _GEN = auto_anon_in_a_bits_address[25:16] ^ 10'h201; // @[Xbar.scala:222:41]
wire requestAIO_0_1 = {auto_anon_in_a_bits_address[28:27], _GEN[9], auto_anon_in_a_bits_address[20], _GEN[0], auto_anon_in_a_bits_address[14:12]} == 8'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_2 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[14:13], ~(auto_anon_in_a_bits_address[12])} == 8'h0 | {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[14:12] ^ 3'h4} == 8'h0 | {auto_anon_in_a_bits_address[28:27] ^ 2'h2, auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[14:12]} == 8'h0; // @[Xbar.scala:291:92]
wire requestAIO_0_3 = {auto_anon_in_a_bits_address[28:27], ~(auto_anon_in_a_bits_address[25]), auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16]} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_4 = {auto_anon_in_a_bits_address[28], ~(auto_anon_in_a_bits_address[27])} == 2'h0; // @[Xbar.scala:222:41]
wire requestAIO_0_5 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[14:12]} == 8'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_6 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], ~(auto_anon_in_a_bits_address[16])} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_7 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], ~(auto_anon_in_a_bits_address[20]), auto_anon_in_a_bits_address[14:12]} == 7'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire _portsAOI_in_0_a_ready_T_14 = requestAIO_0_0 & auto_anon_out_0_a_ready | requestAIO_0_1 & auto_anon_out_1_a_ready | requestAIO_0_2 & auto_anon_out_2_a_ready | requestAIO_0_3 & auto_anon_out_3_a_ready | requestAIO_0_4 & auto_anon_out_4_a_ready | requestAIO_0_5 & auto_anon_out_5_a_ready | requestAIO_0_6 & auto_anon_out_6_a_ready | requestAIO_0_7 & auto_anon_out_7_a_ready; // @[Mux.scala:30:73]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [7:0] readys_valid = {auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51]
reg [7:0] readys_mask; // @[Arbiter.scala:23:23]
wire [7:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [13:0] _GEN_0 = {_readys_filter_T_1[6:0], auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid} | {_readys_filter_T_1, auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid}; // @[package.scala:262:{43,48}]
wire [12:0] _GEN_1 = _GEN_0[12:0] | {_readys_filter_T_1[7], _GEN_0[13:2]}; // @[package.scala:262:{43,48}]
wire [10:0] _GEN_2 = _GEN_1[10:0] | {_readys_filter_T_1[7], _GEN_0[13], _GEN_1[12:4]}; // @[package.scala:262:{43,48}]
wire [7:0] readys_readys = ~({readys_mask[7], _readys_filter_T_1[7] | readys_mask[6], _GEN_0[13] | readys_mask[5], _GEN_1[12:11] | readys_mask[4:3], _GEN_2[10:8] | readys_mask[2:0]} & _GEN_2[7:0]); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_2 = readys_readys[2] & auto_anon_out_2_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_3 = readys_readys[3] & auto_anon_out_3_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_4 = readys_readys[4] & auto_anon_out_4_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_5 = readys_readys[5] & auto_anon_out_5_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_6 = readys_readys[6] & auto_anon_out_6_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_7 = readys_readys[7] & auto_anon_out_7_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31] |
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_SerialRAM :
input clock : Clock
input reset : Reset
output auto : { flip manager_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}}
wire managerNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate managerNodeIn.d.bits.corrupt
invalidate managerNodeIn.d.bits.data
invalidate managerNodeIn.d.bits.denied
invalidate managerNodeIn.d.bits.sink
invalidate managerNodeIn.d.bits.source
invalidate managerNodeIn.d.bits.size
invalidate managerNodeIn.d.bits.param
invalidate managerNodeIn.d.bits.opcode
invalidate managerNodeIn.d.valid
invalidate managerNodeIn.d.ready
invalidate managerNodeIn.a.bits.corrupt
invalidate managerNodeIn.a.bits.data
invalidate managerNodeIn.a.bits.mask
invalidate managerNodeIn.a.bits.address
invalidate managerNodeIn.a.bits.source
invalidate managerNodeIn.a.bits.size
invalidate managerNodeIn.a.bits.param
invalidate managerNodeIn.a.bits.opcode
invalidate managerNodeIn.a.valid
invalidate managerNodeIn.a.ready
inst monitor of TLMonitor_105
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, managerNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, managerNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, managerNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, managerNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, managerNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, managerNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, managerNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, managerNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, managerNodeIn.d.valid
connect monitor.io.in.d.ready, managerNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, managerNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, managerNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, managerNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, managerNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, managerNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, managerNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, managerNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, managerNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, managerNodeIn.a.valid
connect monitor.io.in.a.ready, managerNodeIn.a.ready
connect managerNodeIn, auto.manager_in
wire client_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}}
connect client_tl.e.bits.sink, UInt<8>(0h0)
connect client_tl.e.valid, UInt<1>(0h0)
connect client_tl.e.ready, UInt<1>(0h0)
connect client_tl.d.bits.corrupt, UInt<1>(0h0)
connect client_tl.d.bits.data, UInt<64>(0h0)
connect client_tl.d.bits.denied, UInt<1>(0h0)
connect client_tl.d.bits.sink, UInt<8>(0h0)
connect client_tl.d.bits.source, UInt<8>(0h0)
connect client_tl.d.bits.size, UInt<8>(0h0)
connect client_tl.d.bits.param, UInt<2>(0h0)
connect client_tl.d.bits.opcode, UInt<3>(0h0)
connect client_tl.d.valid, UInt<1>(0h0)
connect client_tl.d.ready, UInt<1>(0h0)
connect client_tl.c.bits.corrupt, UInt<1>(0h0)
connect client_tl.c.bits.data, UInt<64>(0h0)
connect client_tl.c.bits.address, UInt<64>(0h0)
connect client_tl.c.bits.source, UInt<8>(0h0)
connect client_tl.c.bits.size, UInt<8>(0h0)
connect client_tl.c.bits.param, UInt<3>(0h0)
connect client_tl.c.bits.opcode, UInt<3>(0h0)
connect client_tl.c.valid, UInt<1>(0h0)
connect client_tl.c.ready, UInt<1>(0h0)
connect client_tl.b.bits.corrupt, UInt<1>(0h0)
connect client_tl.b.bits.data, UInt<64>(0h0)
connect client_tl.b.bits.mask, UInt<8>(0h0)
connect client_tl.b.bits.address, UInt<64>(0h0)
connect client_tl.b.bits.source, UInt<8>(0h0)
connect client_tl.b.bits.size, UInt<8>(0h0)
connect client_tl.b.bits.param, UInt<2>(0h0)
connect client_tl.b.bits.opcode, UInt<3>(0h0)
connect client_tl.b.valid, UInt<1>(0h0)
connect client_tl.b.ready, UInt<1>(0h0)
connect client_tl.a.bits.corrupt, UInt<1>(0h0)
connect client_tl.a.bits.data, UInt<64>(0h0)
connect client_tl.a.bits.mask, UInt<8>(0h0)
connect client_tl.a.bits.address, UInt<64>(0h0)
connect client_tl.a.bits.source, UInt<8>(0h0)
connect client_tl.a.bits.size, UInt<8>(0h0)
connect client_tl.a.bits.param, UInt<3>(0h0)
connect client_tl.a.bits.opcode, UInt<3>(0h0)
connect client_tl.a.valid, UInt<1>(0h0)
connect client_tl.a.ready, UInt<1>(0h0)
wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}
connect _out_channels_WIRE.bits.sink, UInt<7>(0h0)
connect _out_channels_WIRE.valid, UInt<1>(0h0)
connect _out_channels_WIRE.ready, UInt<1>(0h0)
wire out_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}
connect out_channels_0_1.bits, _out_channels_WIRE.bits
connect out_channels_0_1.valid, _out_channels_WIRE.valid
connect out_channels_0_1.ready, _out_channels_WIRE.ready
inst out_channels_0_2 of TLEToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_0_2.clock, clock
connect out_channels_0_2.reset, reset
wire _out_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _out_channels_WIRE_1.bits.corrupt, UInt<1>(0h0)
connect _out_channels_WIRE_1.bits.data, UInt<64>(0h0)
connect _out_channels_WIRE_1.bits.address, UInt<32>(0h0)
connect _out_channels_WIRE_1.bits.source, UInt<1>(0h0)
connect _out_channels_WIRE_1.bits.size, UInt<4>(0h0)
connect _out_channels_WIRE_1.bits.param, UInt<3>(0h0)
connect _out_channels_WIRE_1.bits.opcode, UInt<3>(0h0)
connect _out_channels_WIRE_1.valid, UInt<1>(0h0)
connect _out_channels_WIRE_1.ready, UInt<1>(0h0)
wire out_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect out_channels_2_1.bits, _out_channels_WIRE_1.bits
connect out_channels_2_1.valid, _out_channels_WIRE_1.valid
connect out_channels_2_1.ready, _out_channels_WIRE_1.ready
inst out_channels_2_2 of TLCToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_2_2.clock, clock
connect out_channels_2_2.reset, reset
inst out_channels_4_2 of TLAToBeat_SerialRAM_a64d64s8k8z8c
connect out_channels_4_2.clock, clock
connect out_channels_4_2.reset, reset
connect io.ser[0].out.valid, UInt<1>(0h0)
connect io.ser[1].out.valid, UInt<1>(0h0)
connect io.ser[2].out.valid, UInt<1>(0h0)
connect io.ser[3].out.valid, UInt<1>(0h0)
connect io.ser[4].out.valid, UInt<1>(0h0)
invalidate io.ser[0].out.bits.flit
invalidate io.ser[1].out.bits.flit
invalidate io.ser[2].out.bits.flit
invalidate io.ser[3].out.bits.flit
invalidate io.ser[4].out.bits.flit
connect out_channels_0_2.io.protocol, out_channels_0_1
inst ser_0 of GenericSerializer_TLBeatw10_f32
connect ser_0.clock, clock
connect ser_0.reset, reset
connect ser_0.io.in, out_channels_0_2.io.beat
connect io.ser[0].out.bits, ser_0.io.out.bits
connect io.ser[0].out.valid, ser_0.io.out.valid
connect ser_0.io.out.ready, io.ser[0].out.ready
connect out_channels_2_2.io.protocol, out_channels_2_1
inst ser_2 of GenericSerializer_TLBeatw88_f32
connect ser_2.clock, clock
connect ser_2.reset, reset
connect ser_2.io.in, out_channels_2_2.io.beat
connect io.ser[2].out.bits, ser_2.io.out.bits
connect io.ser[2].out.valid, ser_2.io.out.valid
connect ser_2.io.out.ready, io.ser[2].out.ready
connect out_channels_4_2.io.protocol, managerNodeIn.a
inst ser_4 of GenericSerializer_TLBeatw88_f32_1
connect ser_4.clock, clock
connect ser_4.reset, reset
connect ser_4.io.in, out_channels_4_2.io.beat
connect io.ser[4].out.bits, ser_4.io.out.bits
connect io.ser[4].out.valid, ser_4.io.out.valid
connect ser_4.io.out.ready, io.ser[4].out.ready
node _io_debug_ser_busy_T = or(ser_0.io.busy, ser_2.io.busy)
node _io_debug_ser_busy_T_1 = or(_io_debug_ser_busy_T, ser_4.io.busy)
connect io.debug.ser_busy, _io_debug_ser_busy_T_1
inst in_channels_0_2 of TLEFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_0_2.clock, clock
connect in_channels_0_2.reset, reset
inst in_channels_1_2 of TLDFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_1_2.clock, clock
connect in_channels_1_2.reset, reset
inst in_channels_2_2 of TLCFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_2_2.clock, clock
connect in_channels_2_2.reset, reset
wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _in_channels_WIRE.bits.corrupt, UInt<1>(0h0)
connect _in_channels_WIRE.bits.data, UInt<64>(0h0)
connect _in_channels_WIRE.bits.mask, UInt<8>(0h0)
connect _in_channels_WIRE.bits.address, UInt<32>(0h0)
connect _in_channels_WIRE.bits.source, UInt<1>(0h0)
connect _in_channels_WIRE.bits.size, UInt<4>(0h0)
connect _in_channels_WIRE.bits.param, UInt<2>(0h0)
connect _in_channels_WIRE.bits.opcode, UInt<3>(0h0)
connect _in_channels_WIRE.valid, UInt<1>(0h0)
connect _in_channels_WIRE.ready, UInt<1>(0h0)
wire in_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect in_channels_3_1.bits, _in_channels_WIRE.bits
connect in_channels_3_1.valid, _in_channels_WIRE.valid
connect in_channels_3_1.ready, _in_channels_WIRE.ready
inst in_channels_3_2 of TLBFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_3_2.clock, clock
connect in_channels_3_2.reset, reset
inst in_channels_4_2 of TLAFromBeat_SerialRAM_a64d64s8k8z8c
connect in_channels_4_2.clock, clock
connect in_channels_4_2.reset, reset
connect client_tl.e.bits.sink, in_channels_0_2.io.protocol.bits.sink
connect client_tl.e.valid, in_channels_0_2.io.protocol.valid
connect in_channels_0_2.io.protocol.ready, client_tl.e.ready
inst des_0 of GenericDeserializer_TLBeatw10_f32_1
connect des_0.clock, clock
connect des_0.reset, reset
connect des_0.io.in, io.ser[0].in
connect in_channels_0_2.io.beat, des_0.io.out
connect managerNodeIn.d.bits, in_channels_1_2.io.protocol.bits
connect managerNodeIn.d.valid, in_channels_1_2.io.protocol.valid
connect in_channels_1_2.io.protocol.ready, managerNodeIn.d.ready
inst des_1 of GenericDeserializer_TLBeatw67_f32_1
connect des_1.clock, clock
connect des_1.reset, reset
connect des_1.io.in, io.ser[1].in
connect in_channels_1_2.io.beat, des_1.io.out
connect client_tl.c.bits.corrupt, in_channels_2_2.io.protocol.bits.corrupt
connect client_tl.c.bits.data, in_channels_2_2.io.protocol.bits.data
connect client_tl.c.bits.address, in_channels_2_2.io.protocol.bits.address
connect client_tl.c.bits.source, in_channels_2_2.io.protocol.bits.source
connect client_tl.c.bits.size, in_channels_2_2.io.protocol.bits.size
connect client_tl.c.bits.param, in_channels_2_2.io.protocol.bits.param
connect client_tl.c.bits.opcode, in_channels_2_2.io.protocol.bits.opcode
connect client_tl.c.valid, in_channels_2_2.io.protocol.valid
connect in_channels_2_2.io.protocol.ready, client_tl.c.ready
inst des_2 of GenericDeserializer_TLBeatw88_f32_2
connect des_2.clock, clock
connect des_2.reset, reset
connect des_2.io.in, io.ser[2].in
connect in_channels_2_2.io.beat, des_2.io.out
connect in_channels_3_1.bits, in_channels_3_2.io.protocol.bits
connect in_channels_3_1.valid, in_channels_3_2.io.protocol.valid
connect in_channels_3_2.io.protocol.ready, in_channels_3_1.ready
inst des_3 of GenericDeserializer_TLBeatw87_f32_1
connect des_3.clock, clock
connect des_3.reset, reset
connect des_3.io.in, io.ser[3].in
connect in_channels_3_2.io.beat, des_3.io.out
connect client_tl.a.bits.corrupt, in_channels_4_2.io.protocol.bits.corrupt
connect client_tl.a.bits.data, in_channels_4_2.io.protocol.bits.data
connect client_tl.a.bits.mask, in_channels_4_2.io.protocol.bits.mask
connect client_tl.a.bits.address, in_channels_4_2.io.protocol.bits.address
connect client_tl.a.bits.source, in_channels_4_2.io.protocol.bits.source
connect client_tl.a.bits.size, in_channels_4_2.io.protocol.bits.size
connect client_tl.a.bits.param, in_channels_4_2.io.protocol.bits.param
connect client_tl.a.bits.opcode, in_channels_4_2.io.protocol.bits.opcode
connect client_tl.a.valid, in_channels_4_2.io.protocol.valid
connect in_channels_4_2.io.protocol.ready, client_tl.a.ready
inst des_4 of GenericDeserializer_TLBeatw88_f32_3
connect des_4.clock, clock
connect des_4.reset, reset
connect des_4.io.in, io.ser[4].in
connect in_channels_4_2.io.beat, des_4.io.out
node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy)
node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy)
node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy)
node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy)
connect io.debug.des_busy, _io_debug_des_busy_T_3 | module TLSerdesser_SerialRAM( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
output auto_manager_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_manager_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_manager_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_manager_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_manager_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_manager_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_manager_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_manager_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_manager_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_manager_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_manager_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_manager_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_manager_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_0_out_ready, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_0_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_2_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_2_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_2_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_4_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_4_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_4_out_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_4_io_busy; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_busy; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_size; // @[TLSerdes.scala:81:28]
wire [7:0] _in_channels_3_2_io_protocol_bits_source; // @[TLSerdes.scala:81:28]
wire [63:0] _in_channels_3_2_io_protocol_bits_address; // @[TLSerdes.scala:81:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_size; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_source; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_1_2_io_protocol_bits_sink; // @[TLSerdes.scala:79:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_4_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_4_io_busy; // @[TLSerdes.scala:69:23]
wire _ser_2_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_0_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_4_2_io_beat_valid; // @[TLSerdes.scala:63:50]
wire [85:0] _out_channels_4_2_io_beat_bits_payload; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_head; // @[TLSerdes.scala:63:50]
wire _out_channels_4_2_io_beat_bits_tail; // @[TLSerdes.scala:63:50]
wire _out_channels_2_2_io_beat_bits_head; // @[TLSerdes.scala:61:50]
wire _out_channels_0_2_io_beat_bits_head; // @[TLSerdes.scala:59:50]
wire auto_manager_in_a_valid_0 = auto_manager_in_a_valid; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_opcode_0 = auto_manager_in_a_bits_opcode; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_a_bits_param_0 = auto_manager_in_a_bits_param; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_a_bits_size_0 = auto_manager_in_a_bits_size; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_source_0 = auto_manager_in_a_bits_source; // @[TLSerdes.scala:39:9]
wire [31:0] auto_manager_in_a_bits_address_0 = auto_manager_in_a_bits_address; // @[TLSerdes.scala:39:9]
wire [7:0] auto_manager_in_a_bits_mask_0 = auto_manager_in_a_bits_mask; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_a_bits_data_0 = auto_manager_in_a_bits_data; // @[TLSerdes.scala:39:9]
wire auto_manager_in_a_bits_corrupt_0 = auto_manager_in_a_bits_corrupt; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_ready_0 = auto_manager_in_d_ready; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_0_out_ready_0 = io_ser_0_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_ready_0 = io_ser_2_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_ready_0 = io_ser_4_out_ready; // @[TLSerdes.scala:39:9]
wire [6:0] _out_channels_WIRE_bits_sink = 7'h0; // @[Bundles.scala:267:74]
wire [6:0] out_channels_0_1_bits_sink = 7'h0; // @[Bundles.scala:267:61]
wire [2:0] client_tl_b_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_d_bits_opcode = 3'h0; // @[TLSerdes.scala:45:71]
wire [2:0] _out_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _out_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] out_channels_2_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] out_channels_2_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _in_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [1:0] client_tl_b_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] client_tl_d_bits_param = 2'h0; // @[TLSerdes.scala:45:71]
wire [1:0] _in_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [3:0] _out_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] out_channels_2_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _in_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [7:0] client_tl_b_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_b_bits_mask = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_size = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_source = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_d_bits_sink = 8'h0; // @[TLSerdes.scala:45:71]
wire [7:0] _in_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [63:0] client_tl_b_bits_address = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_b_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_d_bits_data = 64'h0; // @[TLSerdes.scala:45:71]
wire [63:0] _out_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] out_channels_2_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _in_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [31:0] io_ser_1_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] _out_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] out_channels_2_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _in_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire io_ser_1_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_3_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_0_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire out_channels_2_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :59:50, :61:50]
wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire client_tl_a_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_b_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_c_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_valid = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_denied = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_d_bits_corrupt = 1'h0; // @[TLSerdes.scala:45:71]
wire client_tl_e_ready = 1'h0; // @[TLSerdes.scala:45:71]
wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire out_channels_0_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _out_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _out_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire out_channels_2_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire out_channels_2_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _in_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire in_channels_3_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire managerNodeIn_a_valid = auto_manager_in_a_valid_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_opcode = auto_manager_in_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [2:0] managerNodeIn_a_bits_param = auto_manager_in_a_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] managerNodeIn_a_bits_size = auto_manager_in_a_bits_size_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_source = auto_manager_in_a_bits_source_0; // @[TLSerdes.scala:39:9]
wire [31:0] managerNodeIn_a_bits_address = auto_manager_in_a_bits_address_0; // @[TLSerdes.scala:39:9]
wire [7:0] managerNodeIn_a_bits_mask = auto_manager_in_a_bits_mask_0; // @[TLSerdes.scala:39:9]
wire [63:0] managerNodeIn_a_bits_data = auto_manager_in_a_bits_data_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_a_bits_corrupt = auto_manager_in_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_ready = auto_manager_in_d_ready_0; // @[TLSerdes.scala:39:9]
wire managerNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] managerNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] managerNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] managerNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [6:0] managerNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] managerNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire managerNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire _io_debug_ser_busy_T_1; // @[package.scala:81:59]
wire _io_debug_des_busy_T_3; // @[package.scala:81:59]
wire auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
wire [2:0] auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [1:0] auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
wire [6:0] auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
wire [63:0] auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_debug_ser_busy; // @[TLSerdes.scala:39:9]
wire io_debug_des_busy; // @[TLSerdes.scala:39:9]
assign auto_manager_in_a_ready_0 = managerNodeIn_a_ready; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid_0 = managerNodeIn_d_valid; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode_0 = managerNodeIn_d_bits_opcode; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param_0 = managerNodeIn_d_bits_param; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size_0 = managerNodeIn_d_bits_size; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source_0 = managerNodeIn_d_bits_source; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink_0 = managerNodeIn_d_bits_sink; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied_0 = managerNodeIn_d_bits_denied; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data_0 = managerNodeIn_d_bits_data; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt_0 = managerNodeIn_d_bits_corrupt; // @[TLSerdes.scala:39:9]
wire [2:0] client_tl_a_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_a_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_address; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_a_bits_mask; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_a_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_a_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_a_valid; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_opcode; // @[TLSerdes.scala:45:71]
wire [2:0] client_tl_c_bits_param; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_size; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_c_bits_source; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_address; // @[TLSerdes.scala:45:71]
wire [63:0] client_tl_c_bits_data; // @[TLSerdes.scala:45:71]
wire client_tl_c_bits_corrupt; // @[TLSerdes.scala:45:71]
wire client_tl_c_valid; // @[TLSerdes.scala:45:71]
wire [7:0] client_tl_e_bits_sink; // @[TLSerdes.scala:45:71]
wire client_tl_e_valid; // @[TLSerdes.scala:45:71]
wire _io_debug_ser_busy_T; // @[package.scala:81:59]
assign _io_debug_ser_busy_T_1 = _io_debug_ser_busy_T | _ser_4_io_busy; // @[TLSerdes.scala:69:23]
assign io_debug_ser_busy = _io_debug_ser_busy_T_1; // @[TLSerdes.scala:39:9]
wire [2:0] in_channels_3_1_bits_opcode; // @[Bundles.scala:264:61]
wire [1:0] in_channels_3_1_bits_param; // @[Bundles.scala:264:61]
wire [3:0] in_channels_3_1_bits_size; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_source; // @[Bundles.scala:264:61]
wire [31:0] in_channels_3_1_bits_address; // @[Bundles.scala:264:61]
wire [7:0] in_channels_3_1_bits_mask; // @[Bundles.scala:264:61]
wire [63:0] in_channels_3_1_bits_data; // @[Bundles.scala:264:61]
wire in_channels_3_1_bits_corrupt; // @[Bundles.scala:264:61]
wire in_channels_3_1_valid; // @[Bundles.scala:264:61]
assign managerNodeIn_d_bits_size = _in_channels_1_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_source = _in_channels_1_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:79:28, :85:9]
assign managerNodeIn_d_bits_sink = _in_channels_1_2_io_protocol_bits_sink[6:0]; // @[TLSerdes.scala:79:28, :85:9]
assign in_channels_3_1_bits_size = _in_channels_3_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_source = _in_channels_3_2_io_protocol_bits_source[0]; // @[TLSerdes.scala:81:28, :85:9]
assign in_channels_3_1_bits_address = _in_channels_3_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:81:28, :85:9]
wire _io_debug_des_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23]
assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23]
assign io_debug_des_busy = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9]
TLMonitor_105 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (managerNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (managerNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (managerNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (managerNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (managerNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (managerNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (managerNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (managerNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (managerNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (managerNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (managerNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (managerNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (managerNodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLEToBeat_SerialRAM_a64d64s8k8z8c out_channels_0_2 ( // @[TLSerdes.scala:59:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_0_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_0_2_io_beat_bits_head)
); // @[TLSerdes.scala:59:50]
TLCToBeat_SerialRAM_a64d64s8k8z8c out_channels_2_2 ( // @[TLSerdes.scala:61:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_2_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_2_2_io_beat_bits_head)
); // @[TLSerdes.scala:61:50]
TLAToBeat_SerialRAM_a64d64s8k8z8c out_channels_4_2 ( // @[TLSerdes.scala:63:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_a_ready),
.io_protocol_valid (managerNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_protocol_bits_opcode (managerNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_protocol_bits_param (managerNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_protocol_bits_size ({4'h0, managerNodeIn_a_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({7'h0, managerNodeIn_a_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_address ({32'h0, managerNodeIn_a_bits_address}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_mask (managerNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_protocol_bits_data (managerNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_protocol_bits_corrupt (managerNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_beat_ready (_ser_4_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_4_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_4_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_4_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_4_2_io_beat_bits_tail)
); // @[TLSerdes.scala:63:50]
GenericSerializer_TLBeatw10_f32 ser_0 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_0_io_in_ready),
.io_in_bits_head (_out_channels_0_2_io_beat_bits_head), // @[TLSerdes.scala:59:50]
.io_out_ready (io_ser_0_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_bits_flit (io_ser_0_out_bits_flit_0)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32 ser_2 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_2_io_in_ready),
.io_in_bits_head (_out_channels_2_2_io_beat_bits_head), // @[TLSerdes.scala:61:50]
.io_out_ready (io_ser_2_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_2_out_valid_0),
.io_out_bits_flit (io_ser_2_out_bits_flit_0),
.io_busy (_io_debug_ser_busy_T)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw88_f32_1 ser_4 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_4_io_in_ready),
.io_in_valid (_out_channels_4_2_io_beat_valid), // @[TLSerdes.scala:63:50]
.io_in_bits_payload (_out_channels_4_2_io_beat_bits_payload), // @[TLSerdes.scala:63:50]
.io_in_bits_head (_out_channels_4_2_io_beat_bits_head), // @[TLSerdes.scala:63:50]
.io_in_bits_tail (_out_channels_4_2_io_beat_bits_tail), // @[TLSerdes.scala:63:50]
.io_out_ready (io_ser_4_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_4_out_valid_0),
.io_out_bits_flit (io_ser_4_out_bits_flit_0),
.io_busy (_ser_4_io_busy)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_SerialRAM_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_e_valid),
.io_protocol_bits_sink (client_tl_e_bits_sink),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_SerialRAM_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (managerNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_protocol_valid (managerNodeIn_d_valid),
.io_protocol_bits_opcode (managerNodeIn_d_bits_opcode),
.io_protocol_bits_param (managerNodeIn_d_bits_param),
.io_protocol_bits_size (_in_channels_1_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_1_2_io_protocol_bits_source),
.io_protocol_bits_sink (_in_channels_1_2_io_protocol_bits_sink),
.io_protocol_bits_denied (managerNodeIn_d_bits_denied),
.io_protocol_bits_data (managerNodeIn_d_bits_data),
.io_protocol_bits_corrupt (managerNodeIn_d_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_SerialRAM_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_c_valid),
.io_protocol_bits_opcode (client_tl_c_bits_opcode),
.io_protocol_bits_param (client_tl_c_bits_param),
.io_protocol_bits_size (client_tl_c_bits_size),
.io_protocol_bits_source (client_tl_c_bits_source),
.io_protocol_bits_address (client_tl_c_bits_address),
.io_protocol_bits_data (client_tl_c_bits_data),
.io_protocol_bits_corrupt (client_tl_c_bits_corrupt),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_SerialRAM_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_3_1_valid),
.io_protocol_bits_opcode (in_channels_3_1_bits_opcode),
.io_protocol_bits_param (in_channels_3_1_bits_param),
.io_protocol_bits_size (_in_channels_3_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_3_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_3_2_io_protocol_bits_address),
.io_protocol_bits_mask (in_channels_3_1_bits_mask),
.io_protocol_bits_data (in_channels_3_1_bits_data),
.io_protocol_bits_corrupt (in_channels_3_1_bits_corrupt),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_SerialRAM_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (client_tl_a_valid),
.io_protocol_bits_opcode (client_tl_a_bits_opcode),
.io_protocol_bits_param (client_tl_a_bits_param),
.io_protocol_bits_size (client_tl_a_bits_size),
.io_protocol_bits_source (client_tl_a_bits_source),
.io_protocol_bits_address (client_tl_a_bits_address),
.io_protocol_bits_mask (client_tl_a_bits_mask),
.io_protocol_bits_data (client_tl_a_bits_data),
.io_protocol_bits_corrupt (client_tl_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32_1 des_0 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_0_in_ready_0),
.io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_payload (_des_0_io_out_bits_payload),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32_1 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready_0),
.io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail),
.io_busy (_io_debug_des_busy_T)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_2 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready_0),
.io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (_des_2_io_out_bits_payload),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail),
.io_busy (_des_2_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32_1 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready_0),
.io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_payload (_des_3_io_out_bits_payload),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail),
.io_busy (_des_3_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_3 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready_0),
.io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail),
.io_busy (_des_4_io_busy)
); // @[TLSerdes.scala:86:23]
assign auto_manager_in_a_ready = auto_manager_in_a_ready_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_valid = auto_manager_in_d_valid_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_opcode = auto_manager_in_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_param = auto_manager_in_d_bits_param_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_size = auto_manager_in_d_bits_size_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_source = auto_manager_in_d_bits_source_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_sink = auto_manager_in_d_bits_sink_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_denied = auto_manager_in_d_bits_denied_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_data = auto_manager_in_d_bits_data_0; // @[TLSerdes.scala:39:9]
assign auto_manager_in_d_bits_corrupt = auto_manager_in_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_out_bits_flit = io_ser_0_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_valid = io_ser_2_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_out_bits_flit = io_ser_2_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_valid = io_ser_4_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_out_bits_flit = io_ser_4_out_bits_flit_0; // @[TLSerdes.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNPipe_l2_e11_s53_7 :
input clock : Clock
input reset : Reset
output io : { flip validin : UInt<1>, flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, validout : UInt<1>}
inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e11_s53_7
inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e11_s53_7
connect mulAddRecFNToRaw_preMul.io.op, io.op
connect mulAddRecFNToRaw_preMul.io.a, io.a
connect mulAddRecFNToRaw_preMul.io.b, io.b
connect mulAddRecFNToRaw_preMul.io.c, io.c
node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB)
node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC)
wire valid_stage0 : UInt<1>
wire roundingMode_stage0 : UInt<3>
wire detectTininess_stage0 : UInt<1>
regreset mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b, mulAddRecFNToRaw_preMul.io.toPostMul
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out : { valid : UInt<1>, bits : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}}
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.valid, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v
connect mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b
connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.bit0AlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.highAlignedSigC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CDom_CAlignDist
connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.CIsDominant
connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.doSubMags
connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.sExpSum
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNC
connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.signProd
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isZeroA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isInfA
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isNaNAOrB
connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out.bits.isSigNaNAny
regreset mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b : UInt<107>, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b, mulAddResult
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out : { valid : UInt<1>, bits : UInt<107>}
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.valid, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v
connect mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b
connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out.bits
regreset mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v, io.validin
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b : UInt<3>, clock
when io.validin :
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b, io.roundingMode
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.valid, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v
connect mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b
connect mulAddRecFNToRaw_postMul.io.roundingMode, mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out.bits
regreset roundingMode_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundingMode_stage0_pipe_v, io.validin
reg roundingMode_stage0_pipe_b : UInt<3>, clock
when io.validin :
connect roundingMode_stage0_pipe_b, io.roundingMode
wire roundingMode_stage0_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect roundingMode_stage0_pipe_out.valid, roundingMode_stage0_pipe_v
connect roundingMode_stage0_pipe_out.bits, roundingMode_stage0_pipe_b
connect roundingMode_stage0, roundingMode_stage0_pipe_out.bits
regreset detectTininess_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect detectTininess_stage0_pipe_v, io.validin
reg detectTininess_stage0_pipe_b : UInt<1>, clock
when io.validin :
connect detectTininess_stage0_pipe_b, io.detectTininess
wire detectTininess_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect detectTininess_stage0_pipe_out.valid, detectTininess_stage0_pipe_v
connect detectTininess_stage0_pipe_out.bits, detectTininess_stage0_pipe_b
connect detectTininess_stage0, detectTininess_stage0_pipe_out.bits
regreset valid_stage0_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect valid_stage0_pipe_v, io.validin
reg valid_stage0_pipe_b : UInt<1>, clock
when io.validin :
connect valid_stage0_pipe_b, UInt<1>(0h0)
wire valid_stage0_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect valid_stage0_pipe_out.valid, valid_stage0_pipe_v
connect valid_stage0_pipe_out.bits, valid_stage0_pipe_b
connect valid_stage0, valid_stage0_pipe_out.valid
inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_14
regreset roundRawFNToRecFN_io_invalidExc_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_invalidExc_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_invalidExc_pipe_b : UInt<1>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_invalidExc_pipe_b, mulAddRecFNToRaw_postMul.io.invalidExc
wire roundRawFNToRecFN_io_invalidExc_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect roundRawFNToRecFN_io_invalidExc_pipe_out.valid, roundRawFNToRecFN_io_invalidExc_pipe_v
connect roundRawFNToRecFN_io_invalidExc_pipe_out.bits, roundRawFNToRecFN_io_invalidExc_pipe_b
connect roundRawFNToRecFN.io.invalidExc, roundRawFNToRecFN_io_invalidExc_pipe_out.bits
regreset roundRawFNToRecFN_io_in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_in_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_in_pipe_b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_in_pipe_b, mulAddRecFNToRaw_postMul.io.rawOut
wire roundRawFNToRecFN_io_in_pipe_out : { valid : UInt<1>, bits : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}}
connect roundRawFNToRecFN_io_in_pipe_out.valid, roundRawFNToRecFN_io_in_pipe_v
connect roundRawFNToRecFN_io_in_pipe_out.bits, roundRawFNToRecFN_io_in_pipe_b
connect roundRawFNToRecFN.io.in.sig, roundRawFNToRecFN_io_in_pipe_out.bits.sig
connect roundRawFNToRecFN.io.in.sExp, roundRawFNToRecFN_io_in_pipe_out.bits.sExp
connect roundRawFNToRecFN.io.in.sign, roundRawFNToRecFN_io_in_pipe_out.bits.sign
connect roundRawFNToRecFN.io.in.isZero, roundRawFNToRecFN_io_in_pipe_out.bits.isZero
connect roundRawFNToRecFN.io.in.isInf, roundRawFNToRecFN_io_in_pipe_out.bits.isInf
connect roundRawFNToRecFN.io.in.isNaN, roundRawFNToRecFN_io_in_pipe_out.bits.isNaN
regreset roundRawFNToRecFN_io_roundingMode_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_roundingMode_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_roundingMode_pipe_b : UInt<3>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_roundingMode_pipe_b, roundingMode_stage0
wire roundRawFNToRecFN_io_roundingMode_pipe_out : { valid : UInt<1>, bits : UInt<3>}
connect roundRawFNToRecFN_io_roundingMode_pipe_out.valid, roundRawFNToRecFN_io_roundingMode_pipe_v
connect roundRawFNToRecFN_io_roundingMode_pipe_out.bits, roundRawFNToRecFN_io_roundingMode_pipe_b
connect roundRawFNToRecFN.io.roundingMode, roundRawFNToRecFN_io_roundingMode_pipe_out.bits
regreset roundRawFNToRecFN_io_detectTininess_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect roundRawFNToRecFN_io_detectTininess_pipe_v, valid_stage0
reg roundRawFNToRecFN_io_detectTininess_pipe_b : UInt<1>, clock
when valid_stage0 :
connect roundRawFNToRecFN_io_detectTininess_pipe_b, detectTininess_stage0
wire roundRawFNToRecFN_io_detectTininess_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect roundRawFNToRecFN_io_detectTininess_pipe_out.valid, roundRawFNToRecFN_io_detectTininess_pipe_v
connect roundRawFNToRecFN_io_detectTininess_pipe_out.bits, roundRawFNToRecFN_io_detectTininess_pipe_b
connect roundRawFNToRecFN.io.detectTininess, roundRawFNToRecFN_io_detectTininess_pipe_out.bits
regreset io_validout_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_validout_pipe_v, valid_stage0
reg io_validout_pipe_b : UInt<1>, clock
when valid_stage0 :
connect io_validout_pipe_b, UInt<1>(0h0)
wire io_validout_pipe_out : { valid : UInt<1>, bits : UInt<1>}
connect io_validout_pipe_out.valid, io_validout_pipe_v
connect io_validout_pipe_out.bits, io_validout_pipe_b
connect io.validout, io_validout_pipe_out.valid
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulAddRecFNPipe_l2_e11_s53_7( // @[FPU.scala:633:7]
input clock, // @[FPU.scala:633:7]
input reset, // @[FPU.scala:633:7]
input io_validin, // @[FPU.scala:638:16]
input [1:0] io_op, // @[FPU.scala:638:16]
input [64:0] io_a, // @[FPU.scala:638:16]
input [64:0] io_b, // @[FPU.scala:638:16]
input [64:0] io_c, // @[FPU.scala:638:16]
input [2:0] io_roundingMode, // @[FPU.scala:638:16]
output [64:0] io_out, // @[FPU.scala:638:16]
output [4:0] io_exceptionFlags, // @[FPU.scala:638:16]
output io_validout // @[FPU.scala:638:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[FPU.scala:655:42]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[FPU.scala:655:42]
wire [12:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[FPU.scala:655:42]
wire [55:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[FPU.scala:655:42]
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[FPU.scala:654:41]
wire [52:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[FPU.scala:654:41]
wire [105:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[FPU.scala:654:41]
wire [12:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[FPU.scala:654:41]
wire [5:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[FPU.scala:654:41]
wire [54:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[FPU.scala:654:41]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[FPU.scala:654:41]
wire io_validin_0 = io_validin; // @[FPU.scala:633:7]
wire [1:0] io_op_0 = io_op; // @[FPU.scala:633:7]
wire [64:0] io_a_0 = io_a; // @[FPU.scala:633:7]
wire [64:0] io_b_0 = io_b; // @[FPU.scala:633:7]
wire [64:0] io_c_0 = io_c; // @[FPU.scala:633:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[FPU.scala:633:7]
wire io_detectTininess = 1'h1; // @[FPU.scala:633:7]
wire detectTininess_stage0 = 1'h1; // @[FPU.scala:669:37]
wire detectTininess_stage0_pipe_out_bits = 1'h1; // @[Valid.scala:135:21]
wire valid_stage0_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_bits = 1'h0; // @[Valid.scala:135:21]
wire io_validout_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_0; // @[FPU.scala:633:7]
wire [4:0] io_exceptionFlags_0; // @[FPU.scala:633:7]
wire io_validout_0; // @[FPU.scala:633:7]
wire [105:0] _mulAddResult_T = {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {53'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[FPU.scala:654:41, :663:45]
wire [106:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[FPU.scala:654:41, :663:45, :664:50]
wire valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
wire valid_stage0; // @[FPU.scala:667:28]
wire [2:0] roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
wire [2:0] roundingMode_stage0; // @[FPU.scala:668:35]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_valid = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v; // @[Valid.scala:135:21, :141:24]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC; // @[Valid.scala:135:21, :142:26]
reg [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:142:26]
wire [12:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant; // @[Valid.scala:135:21, :142:26]
reg [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:142:26]
wire [5:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist; // @[Valid.scala:135:21, :142:26]
reg [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:142:26]
wire [54:0] mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:142:26]
wire mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC = mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_valid = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:142:26]
wire [106:0] mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits = mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b; // @[Valid.scala:135:21, :142:26]
reg mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_valid = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits = mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundingMode_stage0_pipe_v; // @[Valid.scala:141:24]
wire roundingMode_stage0_pipe_out_valid = roundingMode_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundingMode_stage0_pipe_b; // @[Valid.scala:142:26]
assign roundingMode_stage0_pipe_out_bits = roundingMode_stage0_pipe_b; // @[Valid.scala:135:21, :142:26]
assign roundingMode_stage0 = roundingMode_stage0_pipe_out_bits; // @[Valid.scala:135:21]
reg detectTininess_stage0_pipe_v; // @[Valid.scala:141:24]
wire detectTininess_stage0_pipe_out_valid = detectTininess_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
reg valid_stage0_pipe_v; // @[Valid.scala:141:24]
assign valid_stage0_pipe_out_valid = valid_stage0_pipe_v; // @[Valid.scala:135:21, :141:24]
assign valid_stage0 = valid_stage0_pipe_out_valid; // @[Valid.scala:135:21]
reg roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_valid = roundRawFNToRecFN_io_invalidExc_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_invalidExc_pipe_out_bits = roundRawFNToRecFN_io_invalidExc_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_in_pipe_out_valid = roundRawFNToRecFN_io_in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isNaN = roundRawFNToRecFN_io_in_pipe_b_isNaN; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isInf = roundRawFNToRecFN_io_in_pipe_b_isInf; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_isZero = roundRawFNToRecFN_io_in_pipe_b_isZero; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_in_pipe_out_bits_sign = roundRawFNToRecFN_io_in_pipe_b_sign; // @[Valid.scala:135:21, :142:26]
reg [12:0] roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:142:26]
wire [12:0] roundRawFNToRecFN_io_in_pipe_out_bits_sExp = roundRawFNToRecFN_io_in_pipe_b_sExp; // @[Valid.scala:135:21, :142:26]
reg [55:0] roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:142:26]
wire [55:0] roundRawFNToRecFN_io_in_pipe_out_bits_sig = roundRawFNToRecFN_io_in_pipe_b_sig; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_roundingMode_pipe_out_valid = roundRawFNToRecFN_io_roundingMode_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [2:0] roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:142:26]
wire [2:0] roundRawFNToRecFN_io_roundingMode_pipe_out_bits = roundRawFNToRecFN_io_roundingMode_pipe_b; // @[Valid.scala:135:21, :142:26]
reg roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:141:24]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_valid = roundRawFNToRecFN_io_detectTininess_pipe_v; // @[Valid.scala:135:21, :141:24]
reg roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
wire roundRawFNToRecFN_io_detectTininess_pipe_out_bits = roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:135:21, :142:26]
reg io_validout_pipe_v; // @[Valid.scala:141:24]
assign io_validout_pipe_out_valid = io_validout_pipe_v; // @[Valid.scala:135:21, :141:24]
assign io_validout_0 = io_validout_pipe_out_valid; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:633:7]
if (reset) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= 1'h0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= 1'h0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_validout_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundingMode_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
detectTininess_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
valid_stage0_pipe_v <= io_validin_0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_invalidExc_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_in_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_roundingMode_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
roundRawFNToRecFN_io_detectTininess_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
io_validout_pipe_v <= valid_stage0; // @[Valid.scala:141:24]
end
if (io_validin_0) begin // @[FPU.scala:633:7]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isSigNaNAny <= _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNAOrB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroA <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroB <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_signProd <= _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isNaNC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isInfC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_isZeroC <= _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_sExpSum <= _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_doSubMags <= _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CIsDominant <= _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_CDom_CAlignDist <= _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_highAlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_b_bit0AlignedSigC <= _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b <= mulAddResult; // @[Valid.scala:142:26]
mulAddRecFNToRaw_postMul_io_roundingMode_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
roundingMode_stage0_pipe_b <= io_roundingMode_0; // @[Valid.scala:142:26]
end
if (valid_stage0) begin // @[FPU.scala:667:28]
roundRawFNToRecFN_io_invalidExc_pipe_b <= _mulAddRecFNToRaw_postMul_io_invalidExc; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isNaN <= _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isInf <= _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_isZero <= _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sign <= _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sExp <= _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_in_pipe_b_sig <= _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[Valid.scala:142:26]
roundRawFNToRecFN_io_roundingMode_pipe_b <= roundingMode_stage0; // @[Valid.scala:142:26]
end
roundRawFNToRecFN_io_detectTininess_pipe_b <= valid_stage0 | roundRawFNToRecFN_io_detectTininess_pipe_b; // @[Valid.scala:142:26]
always @(posedge)
MulAddRecFNToRaw_preMul_e11_s53_7 mulAddRecFNToRaw_preMul ( // @[FPU.scala:654:41]
.io_op (io_op_0), // @[FPU.scala:633:7]
.io_a (io_a_0), // @[FPU.scala:633:7]
.io_b (io_b_0), // @[FPU.scala:633:7]
.io_c (io_c_0), // @[FPU.scala:633:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[FPU.scala:654:41]
MulAddRecFNToRaw_postMul_e11_s53_7 mulAddRecFNToRaw_postMul ( // @[FPU.scala:655:42]
.io_fromPreMul_isSigNaNAny (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isSigNaNAny), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNAOrB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNAOrB), // @[Valid.scala:135:21]
.io_fromPreMul_isInfA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfA), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroA (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroA), // @[Valid.scala:135:21]
.io_fromPreMul_isInfB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfB), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroB (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroB), // @[Valid.scala:135:21]
.io_fromPreMul_signProd (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_signProd), // @[Valid.scala:135:21]
.io_fromPreMul_isNaNC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isNaNC), // @[Valid.scala:135:21]
.io_fromPreMul_isInfC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isInfC), // @[Valid.scala:135:21]
.io_fromPreMul_isZeroC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_isZeroC), // @[Valid.scala:135:21]
.io_fromPreMul_sExpSum (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_sExpSum), // @[Valid.scala:135:21]
.io_fromPreMul_doSubMags (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_doSubMags), // @[Valid.scala:135:21]
.io_fromPreMul_CIsDominant (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CIsDominant), // @[Valid.scala:135:21]
.io_fromPreMul_CDom_CAlignDist (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_CDom_CAlignDist), // @[Valid.scala:135:21]
.io_fromPreMul_highAlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_highAlignedSigC), // @[Valid.scala:135:21]
.io_fromPreMul_bit0AlignedSigC (mulAddRecFNToRaw_postMul_io_fromPreMul_pipe_out_bits_bit0AlignedSigC), // @[Valid.scala:135:21]
.io_mulAddResult (mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_out_bits), // @[Valid.scala:135:21]
.io_roundingMode (mulAddRecFNToRaw_postMul_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[FPU.scala:655:42]
RoundRawFNToRecFN_e11_s53_14 roundRawFNToRecFN ( // @[FPU.scala:682:35]
.io_invalidExc (roundRawFNToRecFN_io_invalidExc_pipe_out_bits), // @[Valid.scala:135:21]
.io_in_isNaN (roundRawFNToRecFN_io_in_pipe_out_bits_isNaN), // @[Valid.scala:135:21]
.io_in_isInf (roundRawFNToRecFN_io_in_pipe_out_bits_isInf), // @[Valid.scala:135:21]
.io_in_isZero (roundRawFNToRecFN_io_in_pipe_out_bits_isZero), // @[Valid.scala:135:21]
.io_in_sign (roundRawFNToRecFN_io_in_pipe_out_bits_sign), // @[Valid.scala:135:21]
.io_in_sExp (roundRawFNToRecFN_io_in_pipe_out_bits_sExp), // @[Valid.scala:135:21]
.io_in_sig (roundRawFNToRecFN_io_in_pipe_out_bits_sig), // @[Valid.scala:135:21]
.io_roundingMode (roundRawFNToRecFN_io_roundingMode_pipe_out_bits), // @[Valid.scala:135:21]
.io_detectTininess (roundRawFNToRecFN_io_detectTininess_pipe_out_bits), // @[Valid.scala:135:21]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[FPU.scala:682:35]
assign io_out = io_out_0; // @[FPU.scala:633:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[FPU.scala:633:7]
assign io_validout = io_validout_0; // @[FPU.scala:633:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_133 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_148
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_133( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_148 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e5_s11_6 :
output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 63, 63)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2)
node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3)
node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4)
node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5)
node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6)
node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7)
node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8)
node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9)
node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10)
node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11)
node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12)
node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13)
node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14)
node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15)
node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16)
node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17)
node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18)
node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19)
node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20)
node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21)
node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22)
node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23)
node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24)
node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25)
node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26)
node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27)
node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28)
node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29)
node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30)
node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31)
node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32)
node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33)
node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34)
node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35)
node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36)
node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37)
node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38)
node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39)
node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40)
node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41)
node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42)
node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43)
node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44)
node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45)
node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46)
node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47)
node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48)
node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49)
node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50)
node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51)
node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52)
node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53)
node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54)
node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55)
node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56)
node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57)
node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58)
node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59)
node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60)
node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61)
node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62)
node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63)
node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f))
node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64)
node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65)
node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66)
node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67)
node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68)
node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69)
node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70)
node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71)
node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72)
node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73)
node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74)
node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75)
node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76)
node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77)
node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78)
node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79)
node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80)
node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81)
node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82)
node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83)
node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84)
node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85)
node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86)
node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87)
node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88)
node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89)
node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90)
node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91)
node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92)
node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93)
node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94)
node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95)
node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96)
node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97)
node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98)
node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99)
node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100)
node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101)
node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102)
node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103)
node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104)
node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105)
node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106)
node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107)
node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108)
node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109)
node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110)
node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111)
node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112)
node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113)
node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114)
node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115)
node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116)
node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117)
node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118)
node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119)
node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120)
node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121)
node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122)
node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123)
node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125)
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe5_os11_6
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i64_e5_s11_6( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [16:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7]
wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [16:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70]
wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie7_is64_oe5_os11_6 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_31 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_48
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_31( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_48 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_64 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_320
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_64( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_320 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_154 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_154( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_46 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_21 = and(_T_19, _T_20)
node _T_22 = or(UInt<1>(0h0), _T_21)
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = and(_T_22, _T_27)
node _T_29 = or(UInt<1>(0h0), _T_28)
node _T_30 = and(_T_18, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_30, UInt<1>(0h1), "") : assert_2
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = or(UInt<1>(0h0), _T_36)
node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = and(_T_37, _T_42)
node _T_44 = or(UInt<1>(0h0), _T_43)
node _T_45 = and(UInt<1>(0h0), _T_44)
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_T_45, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_45, UInt<1>(0h1), "") : assert_3
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_52, UInt<1>(0h1), "") : assert_5
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(is_aligned, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_60 = asUInt(reset)
node _T_61 = eq(_T_60, UInt<1>(0h0))
when _T_61 :
node _T_62 = eq(_T_59, UInt<1>(0h0))
when _T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_59, UInt<1>(0h1), "") : assert_7
node _T_63 = not(io.in.a.bits.mask)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_64, UInt<1>(0h1), "") : assert_8
node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_68, UInt<1>(0h1), "") : assert_9
node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_72 :
node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_74 = and(UInt<1>(0h0), _T_73)
node _T_75 = or(UInt<1>(0h0), _T_74)
node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_78 = and(_T_76, _T_77)
node _T_79 = or(UInt<1>(0h0), _T_78)
node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = and(_T_79, _T_84)
node _T_86 = or(UInt<1>(0h0), _T_85)
node _T_87 = and(_T_75, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_87, UInt<1>(0h1), "") : assert_10
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_102, UInt<1>(0h1), "") : assert_11
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_109, UInt<1>(0h1), "") : assert_13
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_116, UInt<1>(0h1), "") : assert_15
node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_120, UInt<1>(0h1), "") : assert_16
node _T_124 = not(io.in.a.bits.mask)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_125, UInt<1>(0h1), "") : assert_17
node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_129, UInt<1>(0h1), "") : assert_18
node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_133 :
node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = or(UInt<1>(0h0), _T_136)
node _T_138 = asUInt(reset)
node _T_139 = eq(_T_138, UInt<1>(0h0))
when _T_139 :
node _T_140 = eq(_T_137, UInt<1>(0h0))
when _T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_137, UInt<1>(0h1), "") : assert_19
node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_143 = and(_T_141, _T_142)
node _T_144 = or(UInt<1>(0h0), _T_143)
node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = and(_T_144, _T_149)
node _T_151 = or(UInt<1>(0h0), _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_151, UInt<1>(0h1), "") : assert_20
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_158 = asUInt(reset)
node _T_159 = eq(_T_158, UInt<1>(0h0))
when _T_159 :
node _T_160 = eq(is_aligned, UInt<1>(0h0))
when _T_160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(_T_161, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_161, UInt<1>(0h1), "") : assert_23
node _T_165 = eq(io.in.a.bits.mask, mask)
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(_T_165, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_165, UInt<1>(0h1), "") : assert_24
node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_169, UInt<1>(0h1), "") : assert_25
node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_176 = and(_T_174, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_180 = and(_T_178, _T_179)
node _T_181 = or(UInt<1>(0h0), _T_180)
node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = and(_T_181, _T_186)
node _T_188 = or(UInt<1>(0h0), _T_187)
node _T_189 = and(_T_177, _T_188)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_189, UInt<1>(0h1), "") : assert_26
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(is_aligned, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_200 = asUInt(reset)
node _T_201 = eq(_T_200, UInt<1>(0h0))
when _T_201 :
node _T_202 = eq(_T_199, UInt<1>(0h0))
when _T_202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_199, UInt<1>(0h1), "") : assert_29
node _T_203 = eq(io.in.a.bits.mask, mask)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_203, UInt<1>(0h1), "") : assert_30
node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_207 :
node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_209 = and(UInt<1>(0h0), _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_213 = and(_T_211, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = and(_T_214, _T_219)
node _T_221 = or(UInt<1>(0h0), _T_220)
node _T_222 = and(_T_210, _T_221)
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_222, UInt<1>(0h1), "") : assert_31
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(is_aligned, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_232, UInt<1>(0h1), "") : assert_34
node _T_236 = not(mask)
node _T_237 = and(io.in.a.bits.mask, _T_236)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_238, UInt<1>(0h1), "") : assert_35
node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_242 :
node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_244 = and(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), _T_244)
node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_248 = cvt(_T_247)
node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_250 = asSInt(_T_249)
node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0)))
node _T_252 = and(_T_246, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_245, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_254, UInt<1>(0h1), "") : assert_36
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_264, UInt<1>(0h1), "") : assert_39
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_268, UInt<1>(0h1), "") : assert_40
node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_272 :
node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_274 = and(UInt<1>(0h0), _T_273)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = and(_T_276, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = and(_T_275, _T_283)
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_284, UInt<1>(0h1), "") : assert_41
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(is_aligned, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_294, UInt<1>(0h1), "") : assert_44
node _T_298 = eq(io.in.a.bits.mask, mask)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_298, UInt<1>(0h1), "") : assert_45
node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_302 :
node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_304 = and(UInt<1>(0h0), _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_308 = and(_T_306, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = and(_T_309, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = and(_T_305, _T_316)
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_317, UInt<1>(0h1), "") : assert_46
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(is_aligned, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_327, UInt<1>(0h1), "") : assert_49
node _T_331 = eq(io.in.a.bits.mask, mask)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_331, UInt<1>(0h1), "") : assert_50
node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_336 = asUInt(reset)
node _T_337 = eq(_T_336, UInt<1>(0h0))
when _T_337 :
node _T_338 = eq(_T_335, UInt<1>(0h0))
when _T_338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_335, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_339, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1))
node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_343 :
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_347, UInt<1>(0h1), "") : assert_54
node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_351, UInt<1>(0h1), "") : assert_55
node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_355, UInt<1>(0h1), "") : assert_56
node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_359, UInt<1>(0h1), "") : assert_57
node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_363 :
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(sink_ok, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_370, UInt<1>(0h1), "") : assert_60
node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_374, UInt<1>(0h1), "") : assert_61
node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_378, UInt<1>(0h1), "") : assert_62
node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_382, UInt<1>(0h1), "") : assert_63
node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_387 = or(UInt<1>(0h1), _T_386)
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_387, UInt<1>(0h1), "") : assert_64
node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_391 :
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(sink_ok, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_398, UInt<1>(0h1), "") : assert_67
node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_402, UInt<1>(0h1), "") : assert_68
node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_406, UInt<1>(0h1), "") : assert_69
node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_411 = or(_T_410, io.in.d.bits.corrupt)
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_411, UInt<1>(0h1), "") : assert_70
node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_416 = or(UInt<1>(0h1), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_416, UInt<1>(0h1), "") : assert_71
node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_420 :
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_424, UInt<1>(0h1), "") : assert_73
node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_428, UInt<1>(0h1), "") : assert_74
node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_433 = or(UInt<1>(0h1), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_433, UInt<1>(0h1), "") : assert_75
node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_437 :
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_441, UInt<1>(0h1), "") : assert_77
node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_446 = or(_T_445, io.in.d.bits.corrupt)
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_446, UInt<1>(0h1), "") : assert_78
node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_451 = or(UInt<1>(0h1), _T_450)
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_451, UInt<1>(0h1), "") : assert_79
node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_455 :
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_459, UInt<1>(0h1), "") : assert_81
node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_463, UInt<1>(0h1), "") : assert_82
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h1), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_468, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<128>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_472, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<128>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_476, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_480, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_484 = eq(a_first, UInt<1>(0h0))
node _T_485 = and(io.in.a.valid, _T_484)
when _T_485 :
node _T_486 = eq(io.in.a.bits.opcode, opcode)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_486, UInt<1>(0h1), "") : assert_87
node _T_490 = eq(io.in.a.bits.param, param)
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_490, UInt<1>(0h1), "") : assert_88
node _T_494 = eq(io.in.a.bits.size, size)
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_494, UInt<1>(0h1), "") : assert_89
node _T_498 = eq(io.in.a.bits.source, source)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_498, UInt<1>(0h1), "") : assert_90
node _T_502 = eq(io.in.a.bits.address, address)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_502, UInt<1>(0h1), "") : assert_91
node _T_506 = and(io.in.a.ready, io.in.a.valid)
node _T_507 = and(_T_506, a_first)
when _T_507 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_508 = eq(d_first, UInt<1>(0h0))
node _T_509 = and(io.in.d.valid, _T_508)
when _T_509 :
node _T_510 = eq(io.in.d.bits.opcode, opcode_1)
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_510, UInt<1>(0h1), "") : assert_92
node _T_514 = eq(io.in.d.bits.param, param_1)
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(_T_514, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_514, UInt<1>(0h1), "") : assert_93
node _T_518 = eq(io.in.d.bits.size, size_1)
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_518, UInt<1>(0h1), "") : assert_94
node _T_522 = eq(io.in.d.bits.source, source_1)
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_522, UInt<1>(0h1), "") : assert_95
node _T_526 = eq(io.in.d.bits.sink, sink)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_526, UInt<1>(0h1), "") : assert_96
node _T_530 = eq(io.in.d.bits.denied, denied)
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_530, UInt<1>(0h1), "") : assert_97
node _T_534 = and(io.in.d.ready, io.in.d.valid)
node _T_535 = and(_T_534, d_first)
when _T_535 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_536 = and(io.in.a.valid, a_first_1)
node _T_537 = and(_T_536, UInt<1>(0h1))
when _T_537 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_538 = and(io.in.a.ready, io.in.a.valid)
node _T_539 = and(_T_538, a_first_1)
node _T_540 = and(_T_539, UInt<1>(0h1))
when _T_540 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_541 = dshr(inflight, io.in.a.bits.source)
node _T_542 = bits(_T_541, 0, 0)
node _T_543 = eq(_T_542, UInt<1>(0h0))
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(_T_543, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_543, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_551 = and(io.in.d.ready, io.in.d.valid)
node _T_552 = and(_T_551, d_first_1)
node _T_553 = and(_T_552, UInt<1>(0h1))
node _T_554 = eq(d_release_ack, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
when _T_555 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_556 = and(io.in.d.valid, d_first_1)
node _T_557 = and(_T_556, UInt<1>(0h1))
node _T_558 = eq(d_release_ack, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
when _T_559 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_560 = dshr(inflight, io.in.d.bits.source)
node _T_561 = bits(_T_560, 0, 0)
node _T_562 = or(_T_561, same_cycle_resp)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_562, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_568 = or(_T_566, _T_567)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_568, UInt<1>(0h1), "") : assert_100
node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_572, UInt<1>(0h1), "") : assert_101
else :
node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_578 = or(_T_576, _T_577)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_578, UInt<1>(0h1), "") : assert_102
node _T_582 = eq(io.in.d.bits.size, a_size_lookup)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_582, UInt<1>(0h1), "") : assert_103
node _T_586 = and(io.in.d.valid, d_first_1)
node _T_587 = and(_T_586, a_first_1)
node _T_588 = and(_T_587, io.in.a.valid)
node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(d_release_ack, UInt<1>(0h0))
node _T_592 = and(_T_590, _T_591)
when _T_592 :
node _T_593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_594 = or(_T_593, io.in.a.ready)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_594, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_93
node _T_598 = orr(inflight)
node _T_599 = eq(_T_598, UInt<1>(0h0))
node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_601 = or(_T_599, _T_600)
node _T_602 = lt(watchdog, plusarg_reader.out)
node _T_603 = or(_T_601, _T_602)
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_603, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_607 = and(io.in.a.ready, io.in.a.valid)
node _T_608 = and(io.in.d.ready, io.in.d.valid)
node _T_609 = or(_T_607, _T_608)
when _T_609 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<128>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<128>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_610 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<128>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_613 = and(_T_611, _T_612)
node _T_614 = and(_T_610, _T_613)
when _T_614 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<128>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_616 = and(_T_615, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<128>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_619 = and(_T_617, _T_618)
node _T_620 = and(_T_616, _T_619)
when _T_620 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<128>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_621 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_622 = bits(_T_621, 0, 0)
node _T_623 = eq(_T_622, UInt<1>(0h0))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_623, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_627 = and(io.in.d.valid, d_first_2)
node _T_628 = and(_T_627, UInt<1>(0h1))
node _T_629 = and(_T_628, d_release_ack_1)
when _T_629 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_630 = and(io.in.d.ready, io.in.d.valid)
node _T_631 = and(_T_630, d_first_2)
node _T_632 = and(_T_631, UInt<1>(0h1))
node _T_633 = and(_T_632, d_release_ack_1)
when _T_633 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_634 = and(io.in.d.valid, d_first_2)
node _T_635 = and(_T_634, UInt<1>(0h1))
node _T_636 = and(_T_635, d_release_ack_1)
when _T_636 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_637 = dshr(inflight_1, io.in.d.bits.source)
node _T_638 = bits(_T_637, 0, 0)
node _T_639 = or(_T_638, same_cycle_resp_1)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_639, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<128>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_643, UInt<1>(0h1), "") : assert_108
else :
node _T_647 = eq(io.in.d.bits.size, c_size_lookup)
node _T_648 = asUInt(reset)
node _T_649 = eq(_T_648, UInt<1>(0h0))
when _T_649 :
node _T_650 = eq(_T_647, UInt<1>(0h0))
when _T_650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_647, UInt<1>(0h1), "") : assert_109
node _T_651 = and(io.in.d.valid, d_first_2)
node _T_652 = and(_T_651, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<128>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_653 = and(_T_652, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<128>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_655 = and(_T_653, _T_654)
node _T_656 = and(_T_655, d_release_ack_1)
node _T_657 = eq(c_probe_ack, UInt<1>(0h0))
node _T_658 = and(_T_656, _T_657)
when _T_658 :
node _T_659 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<128>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_660 = or(_T_659, _WIRE_23.ready)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_660, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_94
node _T_664 = orr(inflight_1)
node _T_665 = eq(_T_664, UInt<1>(0h0))
node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_667 = or(_T_665, _T_666)
node _T_668 = lt(watchdog_1, plusarg_reader_1.out)
node _T_669 = or(_T_667, _T_668)
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_669, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_674 = and(io.in.d.ready, io.in.d.valid)
node _T_675 = or(_T_673, _T_674)
when _T_675 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_46( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [127:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_30 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_274
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_275
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_276
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_277
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_30( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_274 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_275 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_276 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_277 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_22 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_218
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_22( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_217 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_218 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_220 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_199 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_199( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_16 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_16( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_56 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_66
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_56( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_66 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s7k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_18
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a29d64s7k1z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a29d64s7k1z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_38 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_39 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a29d64s7k1z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [6:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [28:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_18 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a29d64s7k1z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a29d64s7k1z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_28 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_28( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_7 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_7( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_73 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_34 = and(_T_32, _T_33)
node _T_35 = or(UInt<1>(0h0), _T_34)
node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_37 = cvt(_T_36)
node _T_38 = and(_T_37, asSInt(UInt<17>(0h101c0)))
node _T_39 = asSInt(_T_38)
node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0)))
node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_42 = cvt(_T_41)
node _T_43 = and(_T_42, asSInt(UInt<29>(0h100001c0)))
node _T_44 = asSInt(_T_43)
node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0)))
node _T_46 = or(_T_40, _T_45)
node _T_47 = and(_T_35, _T_46)
node _T_48 = or(UInt<1>(0h0), _T_47)
node _T_49 = and(_T_31, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_49, UInt<1>(0h1), "") : assert_2
node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_56 = and(_T_54, _T_55)
node _T_57 = or(UInt<1>(0h0), _T_56)
node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<17>(0h101c0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<29>(0h100001c0)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_62, _T_67)
node _T_69 = and(_T_57, _T_68)
node _T_70 = or(UInt<1>(0h0), _T_69)
node _T_71 = and(_T_53, _T_70)
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_71, UInt<1>(0h1), "") : assert_3
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_78, UInt<1>(0h1), "") : assert_5
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(is_aligned, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_85, UInt<1>(0h1), "") : assert_7
node _T_89 = not(io.in.a.bits.mask)
node _T_90 = eq(_T_89, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_90, UInt<1>(0h1), "") : assert_8
node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_98 :
node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_101 = and(_T_99, _T_100)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_102 = shr(io.in.a.bits.source, 4)
node _T_103 = eq(_T_102, UInt<1>(0h0))
node _T_104 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_105 = and(_T_103, _T_104)
node _T_106 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_107 = and(_T_105, _T_106)
node _T_108 = and(_T_101, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_112 = and(_T_110, _T_111)
node _T_113 = or(UInt<1>(0h0), _T_112)
node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<17>(0h101c0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<29>(0h100001c0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = and(_T_113, _T_124)
node _T_126 = or(UInt<1>(0h0), _T_125)
node _T_127 = and(_T_109, _T_126)
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(_T_127, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_127, UInt<1>(0h1), "") : assert_10
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_134 = and(_T_132, _T_133)
node _T_135 = or(UInt<1>(0h0), _T_134)
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h101c0)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<29>(0h100001c0)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = or(_T_140, _T_145)
node _T_147 = and(_T_135, _T_146)
node _T_148 = or(UInt<1>(0h0), _T_147)
node _T_149 = and(_T_131, _T_148)
node _T_150 = asUInt(reset)
node _T_151 = eq(_T_150, UInt<1>(0h0))
when _T_151 :
node _T_152 = eq(_T_149, UInt<1>(0h0))
when _T_152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_149, UInt<1>(0h1), "") : assert_11
node _T_153 = asUInt(reset)
node _T_154 = eq(_T_153, UInt<1>(0h0))
when _T_154 :
node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_156, UInt<1>(0h1), "") : assert_13
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(is_aligned, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_163, UInt<1>(0h1), "") : assert_15
node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_168 = asUInt(reset)
node _T_169 = eq(_T_168, UInt<1>(0h0))
when _T_169 :
node _T_170 = eq(_T_167, UInt<1>(0h0))
when _T_170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_167, UInt<1>(0h1), "") : assert_16
node _T_171 = not(io.in.a.bits.mask)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_172, UInt<1>(0h1), "") : assert_17
node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_176, UInt<1>(0h1), "") : assert_18
node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_180 :
node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_183 = and(_T_181, _T_182)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_184 = shr(io.in.a.bits.source, 4)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_187 = and(_T_185, _T_186)
node _T_188 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_189 = and(_T_187, _T_188)
node _T_190 = and(_T_183, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_191, UInt<1>(0h1), "") : assert_19
node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_197 = and(_T_195, _T_196)
node _T_198 = or(UInt<1>(0h0), _T_197)
node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<17>(0h101c0)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<29>(0h100001c0)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_203, _T_208)
node _T_210 = and(_T_198, _T_209)
node _T_211 = or(UInt<1>(0h0), _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_211, UInt<1>(0h1), "") : assert_20
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(is_aligned, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_221, UInt<1>(0h1), "") : assert_23
node _T_225 = eq(io.in.a.bits.mask, mask)
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_225, UInt<1>(0h1), "") : assert_24
node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_229, UInt<1>(0h1), "") : assert_25
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_237 = shr(io.in.a.bits.source, 4)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_247 = and(_T_245, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<17>(0h101c0)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<29>(0h100001c0)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = or(_T_253, _T_258)
node _T_260 = and(_T_248, _T_259)
node _T_261 = or(UInt<1>(0h0), _T_260)
node _T_262 = and(_T_244, _T_261)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_262, UInt<1>(0h1), "") : assert_26
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(is_aligned, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_272, UInt<1>(0h1), "") : assert_29
node _T_276 = eq(io.in.a.bits.mask, mask)
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_276, UInt<1>(0h1), "") : assert_30
node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_280 :
node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_284 = shr(io.in.a.bits.source, 4)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_289 = and(_T_287, _T_288)
node _T_290 = and(_T_283, _T_289)
node _T_291 = or(UInt<1>(0h0), _T_290)
node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_294 = and(_T_292, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h101c0)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h100001c0)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_307)
node _T_309 = and(_T_291, _T_308)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_309, UInt<1>(0h1), "") : assert_31
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(is_aligned, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_320 = asUInt(reset)
node _T_321 = eq(_T_320, UInt<1>(0h0))
when _T_321 :
node _T_322 = eq(_T_319, UInt<1>(0h0))
when _T_322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_319, UInt<1>(0h1), "") : assert_34
node _T_323 = not(mask)
node _T_324 = and(io.in.a.bits.mask, _T_323)
node _T_325 = eq(_T_324, UInt<1>(0h0))
node _T_326 = asUInt(reset)
node _T_327 = eq(_T_326, UInt<1>(0h0))
when _T_327 :
node _T_328 = eq(_T_325, UInt<1>(0h0))
when _T_328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_325, UInt<1>(0h1), "") : assert_35
node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_329 :
node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_333 = shr(io.in.a.bits.source, 4)
node _T_334 = eq(_T_333, UInt<1>(0h0))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_338 = and(_T_336, _T_337)
node _T_339 = and(_T_332, _T_338)
node _T_340 = or(UInt<1>(0h0), _T_339)
node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h101c0)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<29>(0h100001c0)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = or(_T_346, _T_351)
node _T_353 = and(_T_341, _T_352)
node _T_354 = or(UInt<1>(0h0), _T_353)
node _T_355 = and(_T_340, _T_354)
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_355, UInt<1>(0h1), "") : assert_36
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(is_aligned, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_365, UInt<1>(0h1), "") : assert_39
node _T_369 = eq(io.in.a.bits.mask, mask)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_369, UInt<1>(0h1), "") : assert_40
node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_373 :
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_377 = shr(io.in.a.bits.source, 4)
node _T_378 = eq(_T_377, UInt<1>(0h0))
node _T_379 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_380 = and(_T_378, _T_379)
node _T_381 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_382 = and(_T_380, _T_381)
node _T_383 = and(_T_376, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_387 = cvt(_T_386)
node _T_388 = and(_T_387, asSInt(UInt<17>(0h101c0)))
node _T_389 = asSInt(_T_388)
node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0)))
node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_392 = cvt(_T_391)
node _T_393 = and(_T_392, asSInt(UInt<29>(0h100001c0)))
node _T_394 = asSInt(_T_393)
node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0)))
node _T_396 = or(_T_390, _T_395)
node _T_397 = and(_T_385, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = and(_T_384, _T_398)
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_399, UInt<1>(0h1), "") : assert_41
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(is_aligned, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_409, UInt<1>(0h1), "") : assert_44
node _T_413 = eq(io.in.a.bits.mask, mask)
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_413, UInt<1>(0h1), "") : assert_45
node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_417 :
node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_420 = and(_T_418, _T_419)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_421 = shr(io.in.a.bits.source, 4)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_426 = and(_T_424, _T_425)
node _T_427 = and(_T_420, _T_426)
node _T_428 = or(UInt<1>(0h0), _T_427)
node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h80001c0))
node _T_431 = cvt(_T_430)
node _T_432 = and(_T_431, asSInt(UInt<17>(0h101c0)))
node _T_433 = asSInt(_T_432)
node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0)))
node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h800001c0))
node _T_436 = cvt(_T_435)
node _T_437 = and(_T_436, asSInt(UInt<29>(0h100001c0)))
node _T_438 = asSInt(_T_437)
node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0)))
node _T_440 = or(_T_434, _T_439)
node _T_441 = and(_T_429, _T_440)
node _T_442 = or(UInt<1>(0h0), _T_441)
node _T_443 = and(_T_428, _T_442)
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_443, UInt<1>(0h1), "") : assert_46
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(is_aligned, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_453, UInt<1>(0h1), "") : assert_49
node _T_457 = eq(io.in.a.bits.mask, mask)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_457, UInt<1>(0h1), "") : assert_50
node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_461, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_465, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_469 :
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_473, UInt<1>(0h1), "") : assert_54
node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_477, UInt<1>(0h1), "") : assert_55
node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_481, UInt<1>(0h1), "") : assert_56
node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_485, UInt<1>(0h1), "") : assert_57
node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(sink_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_496, UInt<1>(0h1), "") : assert_60
node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_500, UInt<1>(0h1), "") : assert_61
node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_504, UInt<1>(0h1), "") : assert_62
node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_508, UInt<1>(0h1), "") : assert_63
node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_513 = or(UInt<1>(0h1), _T_512)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_513, UInt<1>(0h1), "") : assert_64
node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_517 :
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(sink_ok, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_524, UInt<1>(0h1), "") : assert_67
node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_528, UInt<1>(0h1), "") : assert_68
node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_532, UInt<1>(0h1), "") : assert_69
node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_537 = or(_T_536, io.in.d.bits.corrupt)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_537, UInt<1>(0h1), "") : assert_70
node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_542 = or(UInt<1>(0h1), _T_541)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_542, UInt<1>(0h1), "") : assert_71
node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_546 :
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_550, UInt<1>(0h1), "") : assert_73
node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_554, UInt<1>(0h1), "") : assert_74
node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_559 = or(UInt<1>(0h1), _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_559, UInt<1>(0h1), "") : assert_75
node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_563 :
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_567, UInt<1>(0h1), "") : assert_77
node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_572 = or(_T_571, io.in.d.bits.corrupt)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_572, UInt<1>(0h1), "") : assert_78
node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_577 = or(UInt<1>(0h1), _T_576)
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_577, UInt<1>(0h1), "") : assert_79
node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_581 :
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_585, UInt<1>(0h1), "") : assert_81
node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_589, UInt<1>(0h1), "") : assert_82
node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_594 = or(UInt<1>(0h1), _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_594, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_598, UInt<1>(0h1), "") : assert_84
node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<4>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0)
node _T_602 = shr(io.in.b.bits.source, 4)
node _T_603 = eq(_T_602, UInt<1>(0h0))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_9, UInt<4>(0h9))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(_T_607, UInt<1>(0h0))
node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<1>(0h0)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_608, _T_613)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_614, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h101c0)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h100001c0)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0)
node _legal_source_T = shr(io.in.b.bits.source, 4)
node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0))
node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2)
node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h9))
node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4)
wire _legal_source_WIRE : UInt<1>[1]
connect _legal_source_WIRE[0], _legal_source_T_5
node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source)
node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_618 :
node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_622 = and(_T_620, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h101c0)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<29>(0h100001c0)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = or(_T_628, _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = or(UInt<1>(0h0), _T_635)
node _T_637 = and(_T_619, _T_636)
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(_T_637, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_637, UInt<1>(0h1), "") : assert_86
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(address_ok, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(legal_source, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(is_aligned_1, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_650, UInt<1>(0h1), "") : assert_90
node _T_654 = eq(io.in.b.bits.mask, mask_1)
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_T_654, UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_654, UInt<1>(0h1), "") : assert_91
node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_659 = asUInt(reset)
node _T_660 = eq(_T_659, UInt<1>(0h0))
when _T_660 :
node _T_661 = eq(_T_658, UInt<1>(0h0))
when _T_661 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_658, UInt<1>(0h1), "") : assert_92
node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_662 :
node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_665 = and(_T_663, _T_664)
node _T_666 = or(UInt<1>(0h0), _T_665)
node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<17>(0h101c0)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_673 = cvt(_T_672)
node _T_674 = and(_T_673, asSInt(UInt<29>(0h100001c0)))
node _T_675 = asSInt(_T_674)
node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0)))
node _T_677 = or(_T_671, _T_676)
node _T_678 = and(_T_666, _T_677)
node _T_679 = or(UInt<1>(0h0), _T_678)
node _T_680 = and(UInt<1>(0h0), _T_679)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_680, UInt<1>(0h1), "") : assert_93
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(address_ok, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(legal_source, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(is_aligned_1, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_693, UInt<1>(0h1), "") : assert_97
node _T_697 = eq(io.in.b.bits.mask, mask_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_697, UInt<1>(0h1), "") : assert_98
node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_701, UInt<1>(0h1), "") : assert_99
node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_705 :
node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_708 = and(_T_706, _T_707)
node _T_709 = or(UInt<1>(0h0), _T_708)
node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<17>(0h101c0)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<29>(0h100001c0)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = or(_T_714, _T_719)
node _T_721 = and(_T_709, _T_720)
node _T_722 = or(UInt<1>(0h0), _T_721)
node _T_723 = and(UInt<1>(0h0), _T_722)
node _T_724 = asUInt(reset)
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(_T_723, UInt<1>(0h0))
when _T_726 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_723, UInt<1>(0h1), "") : assert_100
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(address_ok, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(legal_source, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned_1, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_736, UInt<1>(0h1), "") : assert_104
node _T_740 = eq(io.in.b.bits.mask, mask_1)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_740, UInt<1>(0h1), "") : assert_105
node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = or(UInt<1>(0h0), _T_747)
node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<17>(0h101c0)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<29>(0h100001c0)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = or(_T_753, _T_758)
node _T_760 = and(_T_748, _T_759)
node _T_761 = or(UInt<1>(0h0), _T_760)
node _T_762 = and(UInt<1>(0h0), _T_761)
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(_T_762, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_762, UInt<1>(0h1), "") : assert_106
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(address_ok, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(legal_source, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(is_aligned_1, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_775, UInt<1>(0h1), "") : assert_110
node _T_779 = not(mask_1)
node _T_780 = and(io.in.b.bits.mask, _T_779)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_781, UInt<1>(0h1), "") : assert_111
node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_785 :
node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<17>(0h101c0)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h100001c0)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_794, _T_799)
node _T_801 = and(_T_789, _T_800)
node _T_802 = or(UInt<1>(0h0), _T_801)
node _T_803 = and(UInt<1>(0h0), _T_802)
node _T_804 = asUInt(reset)
node _T_805 = eq(_T_804, UInt<1>(0h0))
when _T_805 :
node _T_806 = eq(_T_803, UInt<1>(0h0))
when _T_806 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_803, UInt<1>(0h1), "") : assert_112
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(address_ok, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(legal_source, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(is_aligned_1, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_816, UInt<1>(0h1), "") : assert_116
node _T_820 = eq(io.in.b.bits.mask, mask_1)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_820, UInt<1>(0h1), "") : assert_117
node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_824 :
node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_827 = and(_T_825, _T_826)
node _T_828 = or(UInt<1>(0h0), _T_827)
node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<17>(0h101c0)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<29>(0h100001c0)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = or(_T_833, _T_838)
node _T_840 = and(_T_828, _T_839)
node _T_841 = or(UInt<1>(0h0), _T_840)
node _T_842 = and(UInt<1>(0h0), _T_841)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_842, UInt<1>(0h1), "") : assert_118
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(address_ok, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_849 = asUInt(reset)
node _T_850 = eq(_T_849, UInt<1>(0h0))
when _T_850 :
node _T_851 = eq(legal_source, UInt<1>(0h0))
when _T_851 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(is_aligned_1, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_855, UInt<1>(0h1), "") : assert_122
node _T_859 = eq(io.in.b.bits.mask, mask_1)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_859, UInt<1>(0h1), "") : assert_123
node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_863 :
node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_866 = and(_T_864, _T_865)
node _T_867 = or(UInt<1>(0h0), _T_866)
node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h80001c0))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<17>(0h101c0)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h800001c0))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<29>(0h100001c0)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = or(_T_872, _T_877)
node _T_879 = and(_T_867, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_879)
node _T_881 = and(UInt<1>(0h0), _T_880)
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_881, UInt<1>(0h1), "") : assert_124
node _T_885 = asUInt(reset)
node _T_886 = eq(_T_885, UInt<1>(0h0))
when _T_886 :
node _T_887 = eq(address_ok, UInt<1>(0h0))
when _T_887 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(legal_source, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(is_aligned_1, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_894 = eq(io.in.b.bits.mask, mask_1)
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_894, UInt<1>(0h1), "") : assert_128
node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_898, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_903 = asUInt(reset)
node _T_904 = eq(_T_903, UInt<1>(0h0))
when _T_904 :
node _T_905 = eq(_T_902, UInt<1>(0h0))
when _T_905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_902, UInt<1>(0h1), "") : assert_130
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0)
node _source_ok_T_12 = shr(io.in.c.bits.source, 4)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
wire _source_ok_WIRE_2 : UInt<1>[1]
connect _source_ok_WIRE_2[0], _source_ok_T_17
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h101c0)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h100001c0)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_906 = shr(io.in.c.bits.source, 4)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_909 = and(_T_907, _T_908)
node _T_910 = leq(uncommonBits_10, UInt<4>(0h9))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_914 = cvt(_T_913)
node _T_915 = and(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = asSInt(_T_915)
node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0)))
node _T_918 = or(_T_912, _T_917)
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_T_918, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_918, UInt<1>(0h1), "") : assert_131
node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_922 :
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(address_ok_1, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133
node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_929, UInt<1>(0h1), "") : assert_134
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(is_aligned_2, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_936, UInt<1>(0h1), "") : assert_136
node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_940, UInt<1>(0h1), "") : assert_137
node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_944 :
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(address_ok_1, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139
node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_951, UInt<1>(0h1), "") : assert_140
node _T_955 = asUInt(reset)
node _T_956 = eq(_T_955, UInt<1>(0h0))
when _T_956 :
node _T_957 = eq(is_aligned_2, UInt<1>(0h0))
when _T_957 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_958, UInt<1>(0h1), "") : assert_142
node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_962 :
node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_965 = and(_T_963, _T_964)
node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_966 = shr(io.in.c.bits.source, 4)
node _T_967 = eq(_T_966, UInt<1>(0h0))
node _T_968 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_969 = and(_T_967, _T_968)
node _T_970 = leq(uncommonBits_11, UInt<4>(0h9))
node _T_971 = and(_T_969, _T_970)
node _T_972 = and(_T_965, _T_971)
node _T_973 = or(UInt<1>(0h0), _T_972)
node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_976 = and(_T_974, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_979 = cvt(_T_978)
node _T_980 = and(_T_979, asSInt(UInt<17>(0h101c0)))
node _T_981 = asSInt(_T_980)
node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0)))
node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_984 = cvt(_T_983)
node _T_985 = and(_T_984, asSInt(UInt<29>(0h100001c0)))
node _T_986 = asSInt(_T_985)
node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0)))
node _T_988 = or(_T_982, _T_987)
node _T_989 = and(_T_977, _T_988)
node _T_990 = or(UInt<1>(0h0), _T_989)
node _T_991 = and(_T_973, _T_990)
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_991, UInt<1>(0h1), "") : assert_143
node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_998 = and(_T_996, _T_997)
node _T_999 = or(UInt<1>(0h0), _T_998)
node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1001 = cvt(_T_1000)
node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h101c0)))
node _T_1003 = asSInt(_T_1002)
node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0)))
node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1006 = cvt(_T_1005)
node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h100001c0)))
node _T_1008 = asSInt(_T_1007)
node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0)))
node _T_1010 = or(_T_1004, _T_1009)
node _T_1011 = and(_T_999, _T_1010)
node _T_1012 = or(UInt<1>(0h0), _T_1011)
node _T_1013 = and(_T_995, _T_1012)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145
node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1021 = asUInt(reset)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
when _T_1022 :
node _T_1023 = eq(_T_1020, UInt<1>(0h0))
when _T_1023 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148
node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149
node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1035 :
node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1038 = and(_T_1036, _T_1037)
node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0)
node _T_1039 = shr(io.in.c.bits.source, 4)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = leq(uncommonBits_12, UInt<4>(0h9))
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = and(_T_1038, _T_1044)
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6))
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1052 = cvt(_T_1051)
node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h101c0)))
node _T_1054 = asSInt(_T_1053)
node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0)))
node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1057 = cvt(_T_1056)
node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h100001c0)))
node _T_1059 = asSInt(_T_1058)
node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0)))
node _T_1061 = or(_T_1055, _T_1060)
node _T_1062 = and(_T_1050, _T_1061)
node _T_1063 = or(UInt<1>(0h0), _T_1062)
node _T_1064 = and(_T_1046, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150
node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = or(UInt<1>(0h0), _T_1071)
node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h80001c0))
node _T_1074 = cvt(_T_1073)
node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h101c0)))
node _T_1076 = asSInt(_T_1075)
node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0)))
node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h800001c0))
node _T_1079 = cvt(_T_1078)
node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h100001c0)))
node _T_1081 = asSInt(_T_1080)
node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0)))
node _T_1083 = or(_T_1077, _T_1082)
node _T_1084 = and(_T_1072, _T_1083)
node _T_1085 = or(UInt<1>(0h0), _T_1084)
node _T_1086 = and(_T_1068, _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152
node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155
node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(address_ok_1, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159
node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160
node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_1122 :
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(address_ok_1, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164
node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_1136 :
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(address_ok_1, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168
node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(sink_ok_1, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1157 = eq(a_first, UInt<1>(0h0))
node _T_1158 = and(io.in.a.valid, _T_1157)
when _T_1158 :
node _T_1159 = eq(io.in.a.bits.opcode, opcode)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171
node _T_1163 = eq(io.in.a.bits.param, param)
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(_T_1163, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172
node _T_1167 = eq(io.in.a.bits.size, size)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173
node _T_1171 = eq(io.in.a.bits.source, source)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174
node _T_1175 = eq(io.in.a.bits.address, address)
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175
node _T_1179 = and(io.in.a.ready, io.in.a.valid)
node _T_1180 = and(_T_1179, a_first)
when _T_1180 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1181 = eq(d_first, UInt<1>(0h0))
node _T_1182 = and(io.in.d.valid, _T_1181)
when _T_1182 :
node _T_1183 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(_T_1183, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176
node _T_1187 = eq(io.in.d.bits.param, param_1)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177
node _T_1191 = eq(io.in.d.bits.size, size_1)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178
node _T_1195 = eq(io.in.d.bits.source, source_1)
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179
node _T_1199 = eq(io.in.d.bits.sink, sink)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180
node _T_1203 = eq(io.in.d.bits.denied, denied)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181
node _T_1207 = and(io.in.d.ready, io.in.d.valid)
node _T_1208 = and(_T_1207, d_first)
when _T_1208 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_1209 = eq(b_first, UInt<1>(0h0))
node _T_1210 = and(io.in.b.valid, _T_1209)
when _T_1210 :
node _T_1211 = eq(io.in.b.bits.opcode, opcode_2)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182
node _T_1215 = eq(io.in.b.bits.param, param_2)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183
node _T_1219 = eq(io.in.b.bits.size, size_2)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184
node _T_1223 = eq(io.in.b.bits.source, source_2)
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185
node _T_1227 = eq(io.in.b.bits.address, address_1)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186
node _T_1231 = and(io.in.b.ready, io.in.b.valid)
node _T_1232 = and(_T_1231, b_first)
when _T_1232 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_1233 = eq(c_first, UInt<1>(0h0))
node _T_1234 = and(io.in.c.valid, _T_1233)
when _T_1234 :
node _T_1235 = eq(io.in.c.bits.opcode, opcode_3)
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187
node _T_1239 = eq(io.in.c.bits.param, param_3)
node _T_1240 = asUInt(reset)
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(_T_1239, UInt<1>(0h0))
when _T_1242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188
node _T_1243 = eq(io.in.c.bits.size, size_3)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189
node _T_1247 = eq(io.in.c.bits.source, source_3)
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(_T_1247, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190
node _T_1251 = eq(io.in.c.bits.address, address_2)
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191
node _T_1255 = and(io.in.c.ready, io.in.c.valid)
node _T_1256 = and(_T_1255, c_first)
when _T_1256 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1257 = and(io.in.a.valid, a_first_1)
node _T_1258 = and(_T_1257, UInt<1>(0h1))
when _T_1258 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1259 = and(io.in.a.ready, io.in.a.valid)
node _T_1260 = and(_T_1259, a_first_1)
node _T_1261 = and(_T_1260, UInt<1>(0h1))
when _T_1261 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1262 = dshr(inflight, io.in.a.bits.source)
node _T_1263 = bits(_T_1262, 0, 0)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1268 = and(io.in.d.valid, d_first_1)
node _T_1269 = and(_T_1268, UInt<1>(0h1))
node _T_1270 = eq(d_release_ack, UInt<1>(0h0))
node _T_1271 = and(_T_1269, _T_1270)
when _T_1271 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1272 = and(io.in.d.ready, io.in.d.valid)
node _T_1273 = and(_T_1272, d_first_1)
node _T_1274 = and(_T_1273, UInt<1>(0h1))
node _T_1275 = eq(d_release_ack, UInt<1>(0h0))
node _T_1276 = and(_T_1274, _T_1275)
when _T_1276 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1277 = and(io.in.d.valid, d_first_1)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = eq(d_release_ack, UInt<1>(0h0))
node _T_1280 = and(_T_1278, _T_1279)
when _T_1280 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1281 = dshr(inflight, io.in.d.bits.source)
node _T_1282 = bits(_T_1281, 0, 0)
node _T_1283 = or(_T_1282, same_cycle_resp)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194
node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195
else :
node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1299 = or(_T_1297, _T_1298)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196
node _T_1303 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(_T_1303, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197
node _T_1307 = and(io.in.d.valid, d_first_1)
node _T_1308 = and(_T_1307, a_first_1)
node _T_1309 = and(_T_1308, io.in.a.valid)
node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = eq(d_release_ack, UInt<1>(0h0))
node _T_1313 = and(_T_1311, _T_1312)
when _T_1313 :
node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1315 = or(_T_1314, io.in.a.ready)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198
node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1320 = orr(a_set_wo_ready)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
node _T_1322 = or(_T_1319, _T_1321)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_146
node _T_1326 = orr(inflight)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1329 = or(_T_1327, _T_1328)
node _T_1330 = lt(watchdog, plusarg_reader.out)
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(io.in.d.ready, io.in.d.valid)
node _T_1337 = or(_T_1335, _T_1336)
when _T_1337 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_1338 = and(io.in.c.valid, c_first_1)
node _T_1339 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1340 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1341 = and(_T_1339, _T_1340)
node _T_1342 = and(_T_1338, _T_1341)
when _T_1342 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_1343 = and(io.in.c.ready, io.in.c.valid)
node _T_1344 = and(_T_1343, c_first_1)
node _T_1345 = bits(io.in.c.bits.opcode, 2, 2)
node _T_1346 = bits(io.in.c.bits.opcode, 1, 1)
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = and(_T_1344, _T_1347)
when _T_1348 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_1349 = dshr(inflight_1, io.in.c.bits.source)
node _T_1350 = bits(_T_1349, 0, 0)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1355 = and(io.in.d.valid, d_first_2)
node _T_1356 = and(_T_1355, UInt<1>(0h1))
node _T_1357 = and(_T_1356, d_release_ack_1)
when _T_1357 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1358 = and(io.in.d.ready, io.in.d.valid)
node _T_1359 = and(_T_1358, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1362 = and(io.in.d.valid, d_first_2)
node _T_1363 = and(_T_1362, UInt<1>(0h1))
node _T_1364 = and(_T_1363, d_release_ack_1)
when _T_1364 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1365 = dshr(inflight_1, io.in.d.bits.source)
node _T_1366 = bits(_T_1365, 0, 0)
node _T_1367 = or(_T_1366, same_cycle_resp_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203
else :
node _T_1375 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204
node _T_1379 = and(io.in.d.valid, d_first_2)
node _T_1380 = and(_T_1379, c_first_1)
node _T_1381 = and(_T_1380, io.in.c.valid)
node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_1383 = and(_T_1381, _T_1382)
node _T_1384 = and(_T_1383, d_release_ack_1)
node _T_1385 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1386 = and(_T_1384, _T_1385)
when _T_1386 :
node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1388 = or(_T_1387, io.in.c.ready)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205
node _T_1392 = orr(c_set_wo_ready)
when _T_1392 :
node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_147
node _T_1397 = orr(inflight_1)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1400 = or(_T_1398, _T_1399)
node _T_1401 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_1406 = and(io.in.c.ready, io.in.c.valid)
node _T_1407 = and(io.in.d.ready, io.in.d.valid)
node _T_1408 = or(_T_1406, _T_1407)
when _T_1408 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = and(_T_1409, d_first_3)
node _T_1411 = bits(io.in.d.bits.opcode, 2, 2)
node _T_1412 = bits(io.in.d.bits.opcode, 1, 1)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
node _T_1414 = and(_T_1411, _T_1413)
node _T_1415 = and(_T_1410, _T_1414)
when _T_1415 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_1416 = dshr(inflight_2, io.in.d.bits.sink)
node _T_1417 = bits(_T_1416, 0, 0)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_1422 = and(io.in.e.ready, io.in.e.valid)
node _T_1423 = and(_T_1422, UInt<1>(0h1))
node _T_1424 = and(_T_1423, UInt<1>(0h1))
when _T_1424 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_1425 = or(d_set, inflight_2)
node _T_1426 = dshr(_T_1425, io.in.e.bits.sink)
node _T_1427 = bits(_T_1426, 0, 0)
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_73( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34]
wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59]
wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59]
wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40]
wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40]
wire address_ok = 1'h0; // @[Parameters.scala:636:64]
wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29]
wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26]
wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29]
wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27]
wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29]
wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10]
wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire b_first_done = 1'h0; // @[Edges.scala:233:22]
wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24]
wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27]
wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28]
wire b_first = 1'h1; // @[Edges.scala:231:25]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16]
wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] uncommonBits_9 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10]
wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49]
wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27]
wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10]
wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12]
wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10]
wire [32:0] _address_ok_T_6 = 33'h800001C0; // @[Parameters.scala:137:41]
wire [32:0] _address_ok_T_7 = 33'h800001C0; // @[Parameters.scala:137:46]
wire [32:0] _address_ok_T_8 = 33'h800001C0; // @[Parameters.scala:137:46]
wire [31:0] _address_ok_T_5 = 32'h800001C0; // @[Parameters.scala:137:31]
wire [32:0] _address_ok_T_1 = 33'h80001C0; // @[Parameters.scala:137:41]
wire [32:0] _address_ok_T_2 = 33'h80001C0; // @[Parameters.scala:137:46]
wire [32:0] _address_ok_T_3 = 33'h80001C0; // @[Parameters.scala:137:46]
wire [31:0] _address_ok_T = 32'h80001C0; // @[Parameters.scala:137:31]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h80001C0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF01C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h800001C0; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F00001C0; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}]
wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [3:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_4 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1261 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46]
wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_7 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1276 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [2:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] c_set; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [15:0] _GEN_8 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_1348 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [6:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [6:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77]
wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [130:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1361 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35]
assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_27 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h20))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<6>(0h21))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<6>(0h22))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<6>(0h23))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_164 = shr(io.in.a.bits.source, 6)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_170 = shr(io.in.a.bits.source, 6)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_177 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_178 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_179 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<27>(0h4000000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = and(_T_192, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_191, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<6>(0h20))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<6>(0h21))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<6>(0h22))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<6>(0h23))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_229 = shr(io.in.a.bits.source, 6)
node _T_230 = eq(_T_229, UInt<1>(0h1))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_235 = shr(io.in.a.bits.source, 6)
node _T_236 = eq(_T_235, UInt<1>(0h0))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_242 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_243 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_244 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_234
connect _WIRE[6], _T_240
connect _WIRE[7], _T_241
connect _WIRE[8], _T_242
connect _WIRE[9], _T_243
connect _WIRE[10], _T_244
node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[7], _T_245, UInt<1>(0h0))
node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = or(_T_246, _T_247)
node _T_258 = or(_T_257, _T_248)
node _T_259 = or(_T_258, _T_249)
node _T_260 = or(_T_259, _T_250)
node _T_261 = or(_T_260, _T_251)
node _T_262 = or(_T_261, _T_252)
node _T_263 = or(_T_262, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_266
node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_269 = and(_T_267, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<27>(0h4000000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<6>(0h20))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<6>(0h21))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<6>(0h22))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<6>(0h23))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_334 = shr(io.in.a.bits.source, 6)
node _T_335 = eq(_T_334, UInt<1>(0h1))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_340 = shr(io.in.a.bits.source, 6)
node _T_341 = eq(_T_340, UInt<1>(0h0))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_347 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_348 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_349 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_350 = or(_T_309, _T_315)
node _T_351 = or(_T_350, _T_321)
node _T_352 = or(_T_351, _T_327)
node _T_353 = or(_T_352, _T_333)
node _T_354 = or(_T_353, _T_339)
node _T_355 = or(_T_354, _T_345)
node _T_356 = or(_T_355, _T_346)
node _T_357 = or(_T_356, _T_347)
node _T_358 = or(_T_357, _T_348)
node _T_359 = or(_T_358, _T_349)
node _T_360 = and(_T_308, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<27>(0h4000000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = and(_T_362, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = and(_T_361, _T_369)
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_370, UInt<1>(0h1), "") : assert_10
node _T_374 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<6>(0h20))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<6>(0h21))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<6>(0h22))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<6>(0h23))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_399 = shr(io.in.a.bits.source, 6)
node _T_400 = eq(_T_399, UInt<1>(0h1))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_405 = shr(io.in.a.bits.source, 6)
node _T_406 = eq(_T_405, UInt<1>(0h0))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_412 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_413 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_414 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_374
connect _WIRE_2[1], _T_380
connect _WIRE_2[2], _T_386
connect _WIRE_2[3], _T_392
connect _WIRE_2[4], _T_398
connect _WIRE_2[5], _T_404
connect _WIRE_2[6], _T_410
connect _WIRE_2[7], _T_411
connect _WIRE_2[8], _T_412
connect _WIRE_2[9], _T_413
connect _WIRE_2[10], _T_414
node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE_2[7], _T_415, UInt<1>(0h0))
node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = or(_T_416, _T_417)
node _T_428 = or(_T_427, _T_418)
node _T_429 = or(_T_428, _T_419)
node _T_430 = or(_T_429, _T_420)
node _T_431 = or(_T_430, _T_421)
node _T_432 = or(_T_431, _T_422)
node _T_433 = or(_T_432, _T_423)
node _T_434 = or(_T_433, _T_424)
node _T_435 = or(_T_434, _T_425)
node _T_436 = or(_T_435, _T_426)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_436
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<27>(0h4000000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = and(_WIRE_3, _T_447)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_448, UInt<1>(0h1), "") : assert_11
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(source_ok, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_455, UInt<1>(0h1), "") : assert_13
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(is_aligned, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_462, UInt<1>(0h1), "") : assert_15
node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_466, UInt<1>(0h1), "") : assert_16
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_471, UInt<1>(0h1), "") : assert_17
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_475, UInt<1>(0h1), "") : assert_18
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<6>(0h20))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<6>(0h21))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<6>(0h22))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<6>(0h23))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_508 = shr(io.in.a.bits.source, 6)
node _T_509 = eq(_T_508, UInt<1>(0h1))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_514 = shr(io.in.a.bits.source, 6)
node _T_515 = eq(_T_514, UInt<1>(0h0))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_521 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_522 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_523 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_524 = or(_T_483, _T_489)
node _T_525 = or(_T_524, _T_495)
node _T_526 = or(_T_525, _T_501)
node _T_527 = or(_T_526, _T_507)
node _T_528 = or(_T_527, _T_513)
node _T_529 = or(_T_528, _T_519)
node _T_530 = or(_T_529, _T_520)
node _T_531 = or(_T_530, _T_521)
node _T_532 = or(_T_531, _T_522)
node _T_533 = or(_T_532, _T_523)
node _T_534 = and(_T_482, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_535, UInt<1>(0h1), "") : assert_19
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<27>(0h4000000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_549, UInt<1>(0h1), "") : assert_20
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(source_ok, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(is_aligned, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_559, UInt<1>(0h1), "") : assert_23
node _T_563 = eq(io.in.a.bits.mask, mask)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_563, UInt<1>(0h1), "") : assert_24
node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_567, UInt<1>(0h1), "") : assert_25
node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_571 :
node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<6>(0h20))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<6>(0h21))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<6>(0h22))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<6>(0h23))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_600 = shr(io.in.a.bits.source, 6)
node _T_601 = eq(_T_600, UInt<1>(0h1))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_605 = and(_T_603, _T_604)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_606 = shr(io.in.a.bits.source, 6)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_613 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_614 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_615 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_616 = or(_T_575, _T_581)
node _T_617 = or(_T_616, _T_587)
node _T_618 = or(_T_617, _T_593)
node _T_619 = or(_T_618, _T_599)
node _T_620 = or(_T_619, _T_605)
node _T_621 = or(_T_620, _T_611)
node _T_622 = or(_T_621, _T_612)
node _T_623 = or(_T_622, _T_613)
node _T_624 = or(_T_623, _T_614)
node _T_625 = or(_T_624, _T_615)
node _T_626 = and(_T_574, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_633 = cvt(_T_632)
node _T_634 = and(_T_633, asSInt(UInt<27>(0h4000000)))
node _T_635 = asSInt(_T_634)
node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0)))
node _T_637 = and(_T_631, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = and(_T_627, _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_639, UInt<1>(0h1), "") : assert_26
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_649, UInt<1>(0h1), "") : assert_29
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_653, UInt<1>(0h1), "") : assert_30
node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<6>(0h20))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<6>(0h21))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<6>(0h22))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<6>(0h23))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_686 = shr(io.in.a.bits.source, 6)
node _T_687 = eq(_T_686, UInt<1>(0h1))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_691 = and(_T_689, _T_690)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_692 = shr(io.in.a.bits.source, 6)
node _T_693 = eq(_T_692, UInt<1>(0h0))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_699 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_700 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_701 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_702 = or(_T_661, _T_667)
node _T_703 = or(_T_702, _T_673)
node _T_704 = or(_T_703, _T_679)
node _T_705 = or(_T_704, _T_685)
node _T_706 = or(_T_705, _T_691)
node _T_707 = or(_T_706, _T_697)
node _T_708 = or(_T_707, _T_698)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_700)
node _T_711 = or(_T_710, _T_701)
node _T_712 = and(_T_660, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_716 = and(_T_714, _T_715)
node _T_717 = or(UInt<1>(0h0), _T_716)
node _T_718 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<27>(0h4000000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = and(_T_713, _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_725, UInt<1>(0h1), "") : assert_31
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(source_ok, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(is_aligned, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_735, UInt<1>(0h1), "") : assert_34
node _T_739 = not(mask)
node _T_740 = and(io.in.a.bits.mask, _T_739)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_741, UInt<1>(0h1), "") : assert_35
node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<6>(0h20))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<6>(0h21))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<6>(0h22))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<6>(0h23))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_774 = shr(io.in.a.bits.source, 6)
node _T_775 = eq(_T_774, UInt<1>(0h1))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_780 = shr(io.in.a.bits.source, 6)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_787 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_788 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_789 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_790 = or(_T_749, _T_755)
node _T_791 = or(_T_790, _T_761)
node _T_792 = or(_T_791, _T_767)
node _T_793 = or(_T_792, _T_773)
node _T_794 = or(_T_793, _T_779)
node _T_795 = or(_T_794, _T_785)
node _T_796 = or(_T_795, _T_786)
node _T_797 = or(_T_796, _T_787)
node _T_798 = or(_T_797, _T_788)
node _T_799 = or(_T_798, _T_789)
node _T_800 = and(_T_748, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<27>(0h4000000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = and(_T_801, _T_809)
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(_T_810, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_810, UInt<1>(0h1), "") : assert_36
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(source_ok, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(is_aligned, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_820, UInt<1>(0h1), "") : assert_39
node _T_824 = eq(io.in.a.bits.mask, mask)
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_824, UInt<1>(0h1), "") : assert_40
node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_828 :
node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<6>(0h20))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<6>(0h21))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<6>(0h22))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<6>(0h23))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_857 = shr(io.in.a.bits.source, 6)
node _T_858 = eq(_T_857, UInt<1>(0h1))
node _T_859 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_860 = and(_T_858, _T_859)
node _T_861 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_862 = and(_T_860, _T_861)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_863 = shr(io.in.a.bits.source, 6)
node _T_864 = eq(_T_863, UInt<1>(0h0))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_868 = and(_T_866, _T_867)
node _T_869 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_870 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_871 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_872 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_873 = or(_T_832, _T_838)
node _T_874 = or(_T_873, _T_844)
node _T_875 = or(_T_874, _T_850)
node _T_876 = or(_T_875, _T_856)
node _T_877 = or(_T_876, _T_862)
node _T_878 = or(_T_877, _T_868)
node _T_879 = or(_T_878, _T_869)
node _T_880 = or(_T_879, _T_870)
node _T_881 = or(_T_880, _T_871)
node _T_882 = or(_T_881, _T_872)
node _T_883 = and(_T_831, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_886 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<27>(0h4000000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = and(_T_885, _T_890)
node _T_892 = or(UInt<1>(0h0), _T_891)
node _T_893 = and(_T_884, _T_892)
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_893, UInt<1>(0h1), "") : assert_41
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(source_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(is_aligned, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_903, UInt<1>(0h1), "") : assert_44
node _T_907 = eq(io.in.a.bits.mask, mask)
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_907, UInt<1>(0h1), "") : assert_45
node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_911 :
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_916 = shr(io.in.a.bits.source, 2)
node _T_917 = eq(_T_916, UInt<6>(0h20))
node _T_918 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_919 = and(_T_917, _T_918)
node _T_920 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_921 = and(_T_919, _T_920)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_922 = shr(io.in.a.bits.source, 2)
node _T_923 = eq(_T_922, UInt<6>(0h21))
node _T_924 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_925 = and(_T_923, _T_924)
node _T_926 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_928 = shr(io.in.a.bits.source, 2)
node _T_929 = eq(_T_928, UInt<6>(0h22))
node _T_930 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_931 = and(_T_929, _T_930)
node _T_932 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_934 = shr(io.in.a.bits.source, 2)
node _T_935 = eq(_T_934, UInt<6>(0h23))
node _T_936 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_937 = and(_T_935, _T_936)
node _T_938 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_939 = and(_T_937, _T_938)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_940 = shr(io.in.a.bits.source, 6)
node _T_941 = eq(_T_940, UInt<1>(0h1))
node _T_942 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_943 = and(_T_941, _T_942)
node _T_944 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_945 = and(_T_943, _T_944)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_946 = shr(io.in.a.bits.source, 6)
node _T_947 = eq(_T_946, UInt<1>(0h0))
node _T_948 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_949 = and(_T_947, _T_948)
node _T_950 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_951 = and(_T_949, _T_950)
node _T_952 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_953 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_954 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_955 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_956 = or(_T_915, _T_921)
node _T_957 = or(_T_956, _T_927)
node _T_958 = or(_T_957, _T_933)
node _T_959 = or(_T_958, _T_939)
node _T_960 = or(_T_959, _T_945)
node _T_961 = or(_T_960, _T_951)
node _T_962 = or(_T_961, _T_952)
node _T_963 = or(_T_962, _T_953)
node _T_964 = or(_T_963, _T_954)
node _T_965 = or(_T_964, _T_955)
node _T_966 = and(_T_914, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_969 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<27>(0h4000000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = and(_T_968, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = and(_T_967, _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_976, UInt<1>(0h1), "") : assert_46
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(is_aligned, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_986, UInt<1>(0h1), "") : assert_49
node _T_990 = eq(io.in.a.bits.mask, mask)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_990, UInt<1>(0h1), "") : assert_50
node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_994, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_998, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<6>(0h20))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<6>(0h21))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<6>(0h22))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<6>(0h23))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 6)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 6)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<8>(0ha1))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<8>(0ha2))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54
node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55
node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57
node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1022 :
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(source_ok_1, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(sink_ok, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(_T_1029, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60
node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61
node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62
node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64
node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1050 :
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok_1, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(sink_ok, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67
node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68
node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69
node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1070 = or(_T_1069, io.in.d.bits.corrupt)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70
node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1075 = or(UInt<1>(0h0), _T_1074)
node _T_1076 = asUInt(reset)
node _T_1077 = eq(_T_1076, UInt<1>(0h0))
when _T_1077 :
node _T_1078 = eq(_T_1075, UInt<1>(0h0))
when _T_1078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71
node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(source_ok_1, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(_T_1083, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73
node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(_T_1087, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74
node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1092 = or(UInt<1>(0h0), _T_1091)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75
node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1096 :
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(source_ok_1, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(_T_1104, io.in.d.bits.corrupt)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h0), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79
node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81
node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82
node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1127 = or(UInt<1>(0h0), _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<28>(0h0)
connect _WIRE_4.bits.source, UInt<9>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1143 = eq(a_first, UInt<1>(0h0))
node _T_1144 = and(io.in.a.valid, _T_1143)
when _T_1144 :
node _T_1145 = eq(io.in.a.bits.opcode, opcode)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87
node _T_1149 = eq(io.in.a.bits.param, param)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88
node _T_1153 = eq(io.in.a.bits.size, size)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89
node _T_1157 = eq(io.in.a.bits.source, source)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90
node _T_1161 = eq(io.in.a.bits.address, address)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91
node _T_1165 = and(io.in.a.ready, io.in.a.valid)
node _T_1166 = and(_T_1165, a_first)
when _T_1166 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1167 = eq(d_first, UInt<1>(0h0))
node _T_1168 = and(io.in.d.valid, _T_1167)
when _T_1168 :
node _T_1169 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92
node _T_1173 = eq(io.in.d.bits.param, param_1)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93
node _T_1177 = eq(io.in.d.bits.size, size_1)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94
node _T_1181 = eq(io.in.d.bits.source, source_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95
node _T_1185 = eq(io.in.d.bits.sink, sink)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96
node _T_1189 = eq(io.in.d.bits.denied, denied)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97
node _T_1193 = and(io.in.d.ready, io.in.d.valid)
node _T_1194 = and(_T_1193, d_first)
when _T_1194 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes : UInt<1028>, clock, reset, UInt<1028>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<257>
connect a_set, UInt<257>(0h0)
wire a_set_wo_ready : UInt<257>
connect a_set_wo_ready, UInt<257>(0h0)
wire a_opcodes_set : UInt<1028>
connect a_opcodes_set, UInt<1028>(0h0)
wire a_sizes_set : UInt<1028>
connect a_sizes_set, UInt<1028>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1195 = and(io.in.a.valid, a_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
when _T_1196 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1197 = and(io.in.a.ready, io.in.a.valid)
node _T_1198 = and(_T_1197, a_first_1)
node _T_1199 = and(_T_1198, UInt<1>(0h1))
when _T_1199 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1200 = dshr(inflight, io.in.a.bits.source)
node _T_1201 = bits(_T_1200, 0, 0)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<257>
connect d_clr, UInt<257>(0h0)
wire d_clr_wo_ready : UInt<257>
connect d_clr_wo_ready, UInt<257>(0h0)
wire d_opcodes_clr : UInt<1028>
connect d_opcodes_clr, UInt<1028>(0h0)
wire d_sizes_clr : UInt<1028>
connect d_sizes_clr, UInt<1028>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1206 = and(io.in.d.valid, d_first_1)
node _T_1207 = and(_T_1206, UInt<1>(0h1))
node _T_1208 = eq(d_release_ack, UInt<1>(0h0))
node _T_1209 = and(_T_1207, _T_1208)
when _T_1209 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1210 = and(io.in.d.ready, io.in.d.valid)
node _T_1211 = and(_T_1210, d_first_1)
node _T_1212 = and(_T_1211, UInt<1>(0h1))
node _T_1213 = eq(d_release_ack, UInt<1>(0h0))
node _T_1214 = and(_T_1212, _T_1213)
when _T_1214 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1219 = dshr(inflight, io.in.d.bits.source)
node _T_1220 = bits(_T_1219, 0, 0)
node _T_1221 = or(_T_1220, same_cycle_resp)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1227 = or(_T_1225, _T_1226)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100
node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101
else :
node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1237 = or(_T_1235, _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102
node _T_1241 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103
node _T_1245 = and(io.in.d.valid, d_first_1)
node _T_1246 = and(_T_1245, a_first_1)
node _T_1247 = and(_T_1246, io.in.a.valid)
node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1253 = or(_T_1252, io.in.a.ready)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104
node _T_1257 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1258 = orr(a_set_wo_ready)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
node _T_1260 = or(_T_1257, _T_1259)
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_54
node _T_1264 = orr(inflight)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
node _T_1266 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1267 = or(_T_1265, _T_1266)
node _T_1268 = lt(watchdog, plusarg_reader.out)
node _T_1269 = or(_T_1267, _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1273 = and(io.in.a.ready, io.in.a.valid)
node _T_1274 = and(io.in.d.ready, io.in.d.valid)
node _T_1275 = or(_T_1273, _T_1274)
when _T_1275 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<9>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<257>
connect c_set, UInt<257>(0h0)
wire c_set_wo_ready : UInt<257>
connect c_set_wo_ready, UInt<257>(0h0)
wire c_opcodes_set : UInt<1028>
connect c_opcodes_set, UInt<1028>(0h0)
wire c_sizes_set : UInt<1028>
connect c_sizes_set, UInt<1028>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<9>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1276 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<9>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1277 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1278 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = and(_T_1276, _T_1279)
when _T_1280 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<9>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1281 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1282 = and(_T_1281, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<9>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1283 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1284 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = and(_T_1282, _T_1285)
when _T_1286 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<9>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1287 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<257>
connect d_clr_1, UInt<257>(0h0)
wire d_clr_wo_ready_1 : UInt<257>
connect d_clr_wo_ready_1, UInt<257>(0h0)
wire d_opcodes_clr_1 : UInt<1028>
connect d_opcodes_clr_1, UInt<1028>(0h0)
wire d_sizes_clr_1 : UInt<1028>
connect d_sizes_clr_1, UInt<1028>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1296 = and(io.in.d.ready, io.in.d.valid)
node _T_1297 = and(_T_1296, d_first_2)
node _T_1298 = and(_T_1297, UInt<1>(0h1))
node _T_1299 = and(_T_1298, d_release_ack_1)
when _T_1299 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1300 = and(io.in.d.valid, d_first_2)
node _T_1301 = and(_T_1300, UInt<1>(0h1))
node _T_1302 = and(_T_1301, d_release_ack_1)
when _T_1302 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1303 = dshr(inflight_1, io.in.d.bits.source)
node _T_1304 = bits(_T_1303, 0, 0)
node _T_1305 = or(_T_1304, same_cycle_resp_1)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<9>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1309 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1310 = asUInt(reset)
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(_T_1309, UInt<1>(0h0))
when _T_1312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1309, UInt<1>(0h1), "") : assert_109
else :
node _T_1313 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(_T_1313, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1313, UInt<1>(0h1), "") : assert_110
node _T_1317 = and(io.in.d.valid, d_first_2)
node _T_1318 = and(_T_1317, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<9>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1319 = and(_T_1318, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<9>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1320 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = and(_T_1321, d_release_ack_1)
node _T_1323 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1324 = and(_T_1322, _T_1323)
when _T_1324 :
node _T_1325 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<28>(0h0)
connect _WIRE_26.bits.source, UInt<9>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1326 = or(_T_1325, _WIRE_27.ready)
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_111
node _T_1330 = orr(c_set_wo_ready)
when _T_1330 :
node _T_1331 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_55
node _T_1335 = orr(inflight_1)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
node _T_1337 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1338 = or(_T_1336, _T_1337)
node _T_1339 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1340 = or(_T_1338, _T_1339)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<28>(0h0)
connect _WIRE_28.bits.source, UInt<9>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1344 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1345 = and(io.in.d.ready, io.in.d.valid)
node _T_1346 = or(_T_1344, _T_1345)
when _T_1346 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_27( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1273 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1273; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1273; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_1346 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1346; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1346; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1346; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1199 = _T_1273 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1199 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1214 = _T_1346 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1214 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1317 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1317 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1299 = _T_1346 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1299 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1299 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1299 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncSyncCrossingSink_n1x1_9 :
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn.sync | module IntSyncSyncCrossingSink_n1x1_9(); // @[Crossing.scala:96:9]
wire auto_in_sync_0 = 1'h0; // @[Crossing.scala:96:9]
wire auto_out_0 = 1'h0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_189 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_189( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_216( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_4 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<8>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<8>(0ha0))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<8>(0ha0))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<8>(0ha0))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_4( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [7:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 8'hA0; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0)
node _source_ok_T_27 = shr(io.in.a.bits.source, 4)
node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1))
node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf))
node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0)
node _source_ok_T_33 = shr(io.in.a.bits.source, 4)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<5>(0h10))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<5>(0h11))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<5>(0h12))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<5>(0h13))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_80 = shr(io.in.a.bits.source, 4)
node _T_81 = eq(_T_80, UInt<1>(0h1))
node _T_82 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_83 = and(_T_81, _T_82)
node _T_84 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_93 = shr(io.in.a.bits.source, 4)
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_96 = and(_T_94, _T_95)
node _T_97 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_98 = and(_T_96, _T_97)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_71)
node _T_127 = and(_T_126, _T_79)
node _T_128 = and(_T_127, _T_92)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<5>(0h10))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<5>(0h11))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<5>(0h12))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<5>(0h13))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_166 = shr(io.in.a.bits.source, 4)
node _T_167 = eq(_T_166, UInt<1>(0h1))
node _T_168 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_169 = and(_T_167, _T_168)
node _T_170 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_171 = and(_T_169, _T_170)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_172 = shr(io.in.a.bits.source, 4)
node _T_173 = eq(_T_172, UInt<1>(0h0))
node _T_174 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_175 = and(_T_173, _T_174)
node _T_176 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_164)
node _T_185 = or(_T_184, _T_165)
node _T_186 = or(_T_185, _T_171)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<27>(0h4000000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = and(_T_192, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_191, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<5>(0h10))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<5>(0h11))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<5>(0h12))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<5>(0h13))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_230 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_231 = shr(io.in.a.bits.source, 4)
node _T_232 = eq(_T_231, UInt<1>(0h1))
node _T_233 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_234 = and(_T_232, _T_233)
node _T_235 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_237 = shr(io.in.a.bits.source, 4)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_242 = and(_T_240, _T_241)
node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_229
connect _WIRE[6], _T_230
connect _WIRE[7], _T_236
connect _WIRE[8], _T_242
connect _WIRE[9], _T_243
connect _WIRE[10], _T_244
node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[5], _T_245, UInt<1>(0h0))
node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = or(_T_246, _T_247)
node _T_258 = or(_T_257, _T_248)
node _T_259 = or(_T_258, _T_249)
node _T_260 = or(_T_259, _T_250)
node _T_261 = or(_T_260, _T_251)
node _T_262 = or(_T_261, _T_252)
node _T_263 = or(_T_262, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_266
node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_269 = and(_T_267, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<27>(0h4000000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<5>(0h10))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<5>(0h11))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<5>(0h12))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<5>(0h13))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0)
node _T_336 = shr(io.in.a.bits.source, 4)
node _T_337 = eq(_T_336, UInt<1>(0h1))
node _T_338 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_339 = and(_T_337, _T_338)
node _T_340 = leq(uncommonBits_22, UInt<4>(0hf))
node _T_341 = and(_T_339, _T_340)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0)
node _T_342 = shr(io.in.a.bits.source, 4)
node _T_343 = eq(_T_342, UInt<1>(0h0))
node _T_344 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_345 = and(_T_343, _T_344)
node _T_346 = leq(uncommonBits_23, UInt<4>(0hf))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_350 = or(_T_309, _T_315)
node _T_351 = or(_T_350, _T_321)
node _T_352 = or(_T_351, _T_327)
node _T_353 = or(_T_352, _T_333)
node _T_354 = or(_T_353, _T_334)
node _T_355 = or(_T_354, _T_335)
node _T_356 = or(_T_355, _T_341)
node _T_357 = or(_T_356, _T_347)
node _T_358 = or(_T_357, _T_348)
node _T_359 = or(_T_358, _T_349)
node _T_360 = and(_T_308, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<27>(0h4000000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = and(_T_362, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = and(_T_361, _T_369)
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_370, UInt<1>(0h1), "") : assert_10
node _T_374 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<5>(0h10))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<5>(0h11))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<5>(0h12))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<5>(0h13))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0)
node _T_401 = shr(io.in.a.bits.source, 4)
node _T_402 = eq(_T_401, UInt<1>(0h1))
node _T_403 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_404 = and(_T_402, _T_403)
node _T_405 = leq(uncommonBits_28, UInt<4>(0hf))
node _T_406 = and(_T_404, _T_405)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0)
node _T_407 = shr(io.in.a.bits.source, 4)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_410 = and(_T_408, _T_409)
node _T_411 = leq(uncommonBits_29, UInt<4>(0hf))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_374
connect _WIRE_2[1], _T_380
connect _WIRE_2[2], _T_386
connect _WIRE_2[3], _T_392
connect _WIRE_2[4], _T_398
connect _WIRE_2[5], _T_399
connect _WIRE_2[6], _T_400
connect _WIRE_2[7], _T_406
connect _WIRE_2[8], _T_412
connect _WIRE_2[9], _T_413
connect _WIRE_2[10], _T_414
node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE_2[5], _T_415, UInt<1>(0h0))
node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = or(_T_416, _T_417)
node _T_428 = or(_T_427, _T_418)
node _T_429 = or(_T_428, _T_419)
node _T_430 = or(_T_429, _T_420)
node _T_431 = or(_T_430, _T_421)
node _T_432 = or(_T_431, _T_422)
node _T_433 = or(_T_432, _T_423)
node _T_434 = or(_T_433, _T_424)
node _T_435 = or(_T_434, _T_425)
node _T_436 = or(_T_435, _T_426)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_436
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<27>(0h4000000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = and(_WIRE_3, _T_447)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_448, UInt<1>(0h1), "") : assert_11
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(source_ok, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_455, UInt<1>(0h1), "") : assert_13
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(is_aligned, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_462, UInt<1>(0h1), "") : assert_15
node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_466, UInt<1>(0h1), "") : assert_16
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_471, UInt<1>(0h1), "") : assert_17
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_475, UInt<1>(0h1), "") : assert_18
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<5>(0h10))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<5>(0h11))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<5>(0h12))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<5>(0h13))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0)
node _T_510 = shr(io.in.a.bits.source, 4)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_34, UInt<4>(0hf))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0)
node _T_516 = shr(io.in.a.bits.source, 4)
node _T_517 = eq(_T_516, UInt<1>(0h0))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_35, UInt<4>(0hf))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_524 = or(_T_483, _T_489)
node _T_525 = or(_T_524, _T_495)
node _T_526 = or(_T_525, _T_501)
node _T_527 = or(_T_526, _T_507)
node _T_528 = or(_T_527, _T_508)
node _T_529 = or(_T_528, _T_509)
node _T_530 = or(_T_529, _T_515)
node _T_531 = or(_T_530, _T_521)
node _T_532 = or(_T_531, _T_522)
node _T_533 = or(_T_532, _T_523)
node _T_534 = and(_T_482, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_535, UInt<1>(0h1), "") : assert_19
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<27>(0h4000000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_549, UInt<1>(0h1), "") : assert_20
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(source_ok, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(is_aligned, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_559, UInt<1>(0h1), "") : assert_23
node _T_563 = eq(io.in.a.bits.mask, mask)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_563, UInt<1>(0h1), "") : assert_24
node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_567, UInt<1>(0h1), "") : assert_25
node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_571 :
node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<5>(0h10))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<5>(0h11))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<5>(0h12))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<5>(0h13))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0)
node _T_602 = shr(io.in.a.bits.source, 4)
node _T_603 = eq(_T_602, UInt<1>(0h1))
node _T_604 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_605 = and(_T_603, _T_604)
node _T_606 = leq(uncommonBits_40, UInt<4>(0hf))
node _T_607 = and(_T_605, _T_606)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0)
node _T_608 = shr(io.in.a.bits.source, 4)
node _T_609 = eq(_T_608, UInt<1>(0h0))
node _T_610 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_611 = and(_T_609, _T_610)
node _T_612 = leq(uncommonBits_41, UInt<4>(0hf))
node _T_613 = and(_T_611, _T_612)
node _T_614 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_616 = or(_T_575, _T_581)
node _T_617 = or(_T_616, _T_587)
node _T_618 = or(_T_617, _T_593)
node _T_619 = or(_T_618, _T_599)
node _T_620 = or(_T_619, _T_600)
node _T_621 = or(_T_620, _T_601)
node _T_622 = or(_T_621, _T_607)
node _T_623 = or(_T_622, _T_613)
node _T_624 = or(_T_623, _T_614)
node _T_625 = or(_T_624, _T_615)
node _T_626 = and(_T_574, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_633 = cvt(_T_632)
node _T_634 = and(_T_633, asSInt(UInt<27>(0h4000000)))
node _T_635 = asSInt(_T_634)
node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0)))
node _T_637 = and(_T_631, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = and(_T_627, _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_639, UInt<1>(0h1), "") : assert_26
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_649, UInt<1>(0h1), "") : assert_29
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_653, UInt<1>(0h1), "") : assert_30
node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<5>(0h10))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<5>(0h11))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<5>(0h12))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<5>(0h13))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_687 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0)
node _T_688 = shr(io.in.a.bits.source, 4)
node _T_689 = eq(_T_688, UInt<1>(0h1))
node _T_690 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_691 = and(_T_689, _T_690)
node _T_692 = leq(uncommonBits_46, UInt<4>(0hf))
node _T_693 = and(_T_691, _T_692)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0)
node _T_694 = shr(io.in.a.bits.source, 4)
node _T_695 = eq(_T_694, UInt<1>(0h0))
node _T_696 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_697 = and(_T_695, _T_696)
node _T_698 = leq(uncommonBits_47, UInt<4>(0hf))
node _T_699 = and(_T_697, _T_698)
node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_702 = or(_T_661, _T_667)
node _T_703 = or(_T_702, _T_673)
node _T_704 = or(_T_703, _T_679)
node _T_705 = or(_T_704, _T_685)
node _T_706 = or(_T_705, _T_686)
node _T_707 = or(_T_706, _T_687)
node _T_708 = or(_T_707, _T_693)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_700)
node _T_711 = or(_T_710, _T_701)
node _T_712 = and(_T_660, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_716 = and(_T_714, _T_715)
node _T_717 = or(UInt<1>(0h0), _T_716)
node _T_718 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<27>(0h4000000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = and(_T_713, _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_725, UInt<1>(0h1), "") : assert_31
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(source_ok, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(is_aligned, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_735, UInt<1>(0h1), "") : assert_34
node _T_739 = not(mask)
node _T_740 = and(io.in.a.bits.mask, _T_739)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_741, UInt<1>(0h1), "") : assert_35
node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<5>(0h10))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<5>(0h11))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<5>(0h12))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<5>(0h13))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_775 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0)
node _T_776 = shr(io.in.a.bits.source, 4)
node _T_777 = eq(_T_776, UInt<1>(0h1))
node _T_778 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_779 = and(_T_777, _T_778)
node _T_780 = leq(uncommonBits_52, UInt<4>(0hf))
node _T_781 = and(_T_779, _T_780)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0)
node _T_782 = shr(io.in.a.bits.source, 4)
node _T_783 = eq(_T_782, UInt<1>(0h0))
node _T_784 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_785 = and(_T_783, _T_784)
node _T_786 = leq(uncommonBits_53, UInt<4>(0hf))
node _T_787 = and(_T_785, _T_786)
node _T_788 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_790 = or(_T_749, _T_755)
node _T_791 = or(_T_790, _T_761)
node _T_792 = or(_T_791, _T_767)
node _T_793 = or(_T_792, _T_773)
node _T_794 = or(_T_793, _T_774)
node _T_795 = or(_T_794, _T_775)
node _T_796 = or(_T_795, _T_781)
node _T_797 = or(_T_796, _T_787)
node _T_798 = or(_T_797, _T_788)
node _T_799 = or(_T_798, _T_789)
node _T_800 = and(_T_748, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<27>(0h4000000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = and(_T_801, _T_809)
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(_T_810, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_810, UInt<1>(0h1), "") : assert_36
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(source_ok, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(is_aligned, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_820, UInt<1>(0h1), "") : assert_39
node _T_824 = eq(io.in.a.bits.mask, mask)
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_824, UInt<1>(0h1), "") : assert_40
node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_828 :
node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<5>(0h10))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<5>(0h11))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<5>(0h12))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<5>(0h13))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0)
node _T_859 = shr(io.in.a.bits.source, 4)
node _T_860 = eq(_T_859, UInt<1>(0h1))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_58, UInt<4>(0hf))
node _T_864 = and(_T_862, _T_863)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0)
node _T_865 = shr(io.in.a.bits.source, 4)
node _T_866 = eq(_T_865, UInt<1>(0h0))
node _T_867 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_868 = and(_T_866, _T_867)
node _T_869 = leq(uncommonBits_59, UInt<4>(0hf))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_873 = or(_T_832, _T_838)
node _T_874 = or(_T_873, _T_844)
node _T_875 = or(_T_874, _T_850)
node _T_876 = or(_T_875, _T_856)
node _T_877 = or(_T_876, _T_857)
node _T_878 = or(_T_877, _T_858)
node _T_879 = or(_T_878, _T_864)
node _T_880 = or(_T_879, _T_870)
node _T_881 = or(_T_880, _T_871)
node _T_882 = or(_T_881, _T_872)
node _T_883 = and(_T_831, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_886 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<27>(0h4000000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = and(_T_885, _T_890)
node _T_892 = or(UInt<1>(0h0), _T_891)
node _T_893 = and(_T_884, _T_892)
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_893, UInt<1>(0h1), "") : assert_41
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(source_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(is_aligned, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_903, UInt<1>(0h1), "") : assert_44
node _T_907 = eq(io.in.a.bits.mask, mask)
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_907, UInt<1>(0h1), "") : assert_45
node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_911 :
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_916 = shr(io.in.a.bits.source, 2)
node _T_917 = eq(_T_916, UInt<5>(0h10))
node _T_918 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_919 = and(_T_917, _T_918)
node _T_920 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_921 = and(_T_919, _T_920)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_922 = shr(io.in.a.bits.source, 2)
node _T_923 = eq(_T_922, UInt<5>(0h11))
node _T_924 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_925 = and(_T_923, _T_924)
node _T_926 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_928 = shr(io.in.a.bits.source, 2)
node _T_929 = eq(_T_928, UInt<5>(0h12))
node _T_930 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_931 = and(_T_929, _T_930)
node _T_932 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_934 = shr(io.in.a.bits.source, 2)
node _T_935 = eq(_T_934, UInt<5>(0h13))
node _T_936 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_937 = and(_T_935, _T_936)
node _T_938 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_939 = and(_T_937, _T_938)
node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0)
node _T_942 = shr(io.in.a.bits.source, 4)
node _T_943 = eq(_T_942, UInt<1>(0h1))
node _T_944 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_945 = and(_T_943, _T_944)
node _T_946 = leq(uncommonBits_64, UInt<4>(0hf))
node _T_947 = and(_T_945, _T_946)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0)
node _T_948 = shr(io.in.a.bits.source, 4)
node _T_949 = eq(_T_948, UInt<1>(0h0))
node _T_950 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_951 = and(_T_949, _T_950)
node _T_952 = leq(uncommonBits_65, UInt<4>(0hf))
node _T_953 = and(_T_951, _T_952)
node _T_954 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_956 = or(_T_915, _T_921)
node _T_957 = or(_T_956, _T_927)
node _T_958 = or(_T_957, _T_933)
node _T_959 = or(_T_958, _T_939)
node _T_960 = or(_T_959, _T_940)
node _T_961 = or(_T_960, _T_941)
node _T_962 = or(_T_961, _T_947)
node _T_963 = or(_T_962, _T_953)
node _T_964 = or(_T_963, _T_954)
node _T_965 = or(_T_964, _T_955)
node _T_966 = and(_T_914, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_969 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<27>(0h4000000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = and(_T_968, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = and(_T_967, _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_976, UInt<1>(0h1), "") : assert_46
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(is_aligned, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_986, UInt<1>(0h1), "") : assert_49
node _T_990 = eq(io.in.a.bits.mask, mask)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_990, UInt<1>(0h1), "") : assert_50
node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_994, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_998, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 4)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0)
node _source_ok_T_83 = shr(io.in.d.bits.source, 4)
node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0))
node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf))
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_75
connect _source_ok_WIRE_1[6], _source_ok_T_76
connect _source_ok_WIRE_1[7], _source_ok_T_82
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54
node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55
node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57
node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1022 :
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(source_ok_1, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(sink_ok, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(_T_1029, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60
node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61
node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62
node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64
node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1050 :
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok_1, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(sink_ok, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67
node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68
node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69
node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1070 = or(_T_1069, io.in.d.bits.corrupt)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70
node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1075 = or(UInt<1>(0h0), _T_1074)
node _T_1076 = asUInt(reset)
node _T_1077 = eq(_T_1076, UInt<1>(0h0))
when _T_1077 :
node _T_1078 = eq(_T_1075, UInt<1>(0h0))
when _T_1078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71
node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(source_ok_1, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(_T_1083, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73
node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(_T_1087, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74
node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1092 = or(UInt<1>(0h0), _T_1091)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75
node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1096 :
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(source_ok_1, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(_T_1104, io.in.d.bits.corrupt)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h0), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79
node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81
node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82
node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1127 = or(UInt<1>(0h0), _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<28>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1143 = eq(a_first, UInt<1>(0h0))
node _T_1144 = and(io.in.a.valid, _T_1143)
when _T_1144 :
node _T_1145 = eq(io.in.a.bits.opcode, opcode)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87
node _T_1149 = eq(io.in.a.bits.param, param)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88
node _T_1153 = eq(io.in.a.bits.size, size)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89
node _T_1157 = eq(io.in.a.bits.source, source)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90
node _T_1161 = eq(io.in.a.bits.address, address)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91
node _T_1165 = and(io.in.a.ready, io.in.a.valid)
node _T_1166 = and(_T_1165, a_first)
when _T_1166 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1167 = eq(d_first, UInt<1>(0h0))
node _T_1168 = and(io.in.d.valid, _T_1167)
when _T_1168 :
node _T_1169 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92
node _T_1173 = eq(io.in.d.bits.param, param_1)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93
node _T_1177 = eq(io.in.d.bits.size, size_1)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94
node _T_1181 = eq(io.in.d.bits.source, source_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95
node _T_1185 = eq(io.in.d.bits.sink, sink)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96
node _T_1189 = eq(io.in.d.bits.denied, denied)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97
node _T_1193 = and(io.in.d.ready, io.in.d.valid)
node _T_1194 = and(_T_1193, d_first)
when _T_1194 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1195 = and(io.in.a.valid, a_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
when _T_1196 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1197 = and(io.in.a.ready, io.in.a.valid)
node _T_1198 = and(_T_1197, a_first_1)
node _T_1199 = and(_T_1198, UInt<1>(0h1))
when _T_1199 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1200 = dshr(inflight, io.in.a.bits.source)
node _T_1201 = bits(_T_1200, 0, 0)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1206 = and(io.in.d.valid, d_first_1)
node _T_1207 = and(_T_1206, UInt<1>(0h1))
node _T_1208 = eq(d_release_ack, UInt<1>(0h0))
node _T_1209 = and(_T_1207, _T_1208)
when _T_1209 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1210 = and(io.in.d.ready, io.in.d.valid)
node _T_1211 = and(_T_1210, d_first_1)
node _T_1212 = and(_T_1211, UInt<1>(0h1))
node _T_1213 = eq(d_release_ack, UInt<1>(0h0))
node _T_1214 = and(_T_1212, _T_1213)
when _T_1214 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1219 = dshr(inflight, io.in.d.bits.source)
node _T_1220 = bits(_T_1219, 0, 0)
node _T_1221 = or(_T_1220, same_cycle_resp)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1227 = or(_T_1225, _T_1226)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100
node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101
else :
node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1237 = or(_T_1235, _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102
node _T_1241 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103
node _T_1245 = and(io.in.d.valid, d_first_1)
node _T_1246 = and(_T_1245, a_first_1)
node _T_1247 = and(_T_1246, io.in.a.valid)
node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1253 = or(_T_1252, io.in.a.ready)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104
node _T_1257 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1258 = orr(a_set_wo_ready)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
node _T_1260 = or(_T_1257, _T_1259)
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_52
node _T_1264 = orr(inflight)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
node _T_1266 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1267 = or(_T_1265, _T_1266)
node _T_1268 = lt(watchdog, plusarg_reader.out)
node _T_1269 = or(_T_1267, _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1273 = and(io.in.a.ready, io.in.a.valid)
node _T_1274 = and(io.in.d.ready, io.in.d.valid)
node _T_1275 = or(_T_1273, _T_1274)
when _T_1275 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1276 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1277 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1278 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = and(_T_1276, _T_1279)
when _T_1280 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1281 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1282 = and(_T_1281, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1283 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1284 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = and(_T_1282, _T_1285)
when _T_1286 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1287 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1296 = and(io.in.d.ready, io.in.d.valid)
node _T_1297 = and(_T_1296, d_first_2)
node _T_1298 = and(_T_1297, UInt<1>(0h1))
node _T_1299 = and(_T_1298, d_release_ack_1)
when _T_1299 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1300 = and(io.in.d.valid, d_first_2)
node _T_1301 = and(_T_1300, UInt<1>(0h1))
node _T_1302 = and(_T_1301, d_release_ack_1)
when _T_1302 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1303 = dshr(inflight_1, io.in.d.bits.source)
node _T_1304 = bits(_T_1303, 0, 0)
node _T_1305 = or(_T_1304, same_cycle_resp_1)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1309 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1310 = asUInt(reset)
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(_T_1309, UInt<1>(0h0))
when _T_1312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1309, UInt<1>(0h1), "") : assert_109
else :
node _T_1313 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(_T_1313, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1313, UInt<1>(0h1), "") : assert_110
node _T_1317 = and(io.in.d.valid, d_first_2)
node _T_1318 = and(_T_1317, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1319 = and(_T_1318, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1320 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = and(_T_1321, d_release_ack_1)
node _T_1323 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1324 = and(_T_1322, _T_1323)
when _T_1324 :
node _T_1325 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<28>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1326 = or(_T_1325, _WIRE_27.ready)
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_111
node _T_1330 = orr(c_set_wo_ready)
when _T_1330 :
node _T_1331 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_53
node _T_1335 = orr(inflight_1)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
node _T_1337 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1338 = or(_T_1336, _T_1337)
node _T_1339 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1340 = or(_T_1338, _T_1339)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:97)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<28>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1344 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1345 = and(io.in.d.ready, io.in.d.valid)
node _T_1346 = or(_T_1344, _T_1345)
when _T_1346 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_26( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1273 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1273; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1273; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_1346 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1346; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1346; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1346; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1199 = _T_1273 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1214 = _T_1346 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1317 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1317 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1299 = _T_1346 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1299 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1299 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1299 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AXI4Buffer :
input clock : Clock
input reset : Reset
output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}}
wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate nodeIn.r.bits.last
invalidate nodeIn.r.bits.resp
invalidate nodeIn.r.bits.data
invalidate nodeIn.r.bits.id
invalidate nodeIn.r.valid
invalidate nodeIn.r.ready
invalidate nodeIn.ar.bits.qos
invalidate nodeIn.ar.bits.prot
invalidate nodeIn.ar.bits.cache
invalidate nodeIn.ar.bits.lock
invalidate nodeIn.ar.bits.burst
invalidate nodeIn.ar.bits.size
invalidate nodeIn.ar.bits.len
invalidate nodeIn.ar.bits.addr
invalidate nodeIn.ar.bits.id
invalidate nodeIn.ar.valid
invalidate nodeIn.ar.ready
invalidate nodeIn.b.bits.resp
invalidate nodeIn.b.bits.id
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.w.bits.last
invalidate nodeIn.w.bits.strb
invalidate nodeIn.w.bits.data
invalidate nodeIn.w.valid
invalidate nodeIn.w.ready
invalidate nodeIn.aw.bits.qos
invalidate nodeIn.aw.bits.prot
invalidate nodeIn.aw.bits.cache
invalidate nodeIn.aw.bits.lock
invalidate nodeIn.aw.bits.burst
invalidate nodeIn.aw.bits.size
invalidate nodeIn.aw.bits.len
invalidate nodeIn.aw.bits.addr
invalidate nodeIn.aw.bits.id
invalidate nodeIn.aw.valid
invalidate nodeIn.aw.ready
wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate nodeOut.r.bits.last
invalidate nodeOut.r.bits.resp
invalidate nodeOut.r.bits.data
invalidate nodeOut.r.bits.id
invalidate nodeOut.r.valid
invalidate nodeOut.r.ready
invalidate nodeOut.ar.bits.qos
invalidate nodeOut.ar.bits.prot
invalidate nodeOut.ar.bits.cache
invalidate nodeOut.ar.bits.lock
invalidate nodeOut.ar.bits.burst
invalidate nodeOut.ar.bits.size
invalidate nodeOut.ar.bits.len
invalidate nodeOut.ar.bits.addr
invalidate nodeOut.ar.bits.id
invalidate nodeOut.ar.valid
invalidate nodeOut.ar.ready
invalidate nodeOut.b.bits.resp
invalidate nodeOut.b.bits.id
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.w.bits.last
invalidate nodeOut.w.bits.strb
invalidate nodeOut.w.bits.data
invalidate nodeOut.w.valid
invalidate nodeOut.w.ready
invalidate nodeOut.aw.bits.qos
invalidate nodeOut.aw.bits.prot
invalidate nodeOut.aw.bits.cache
invalidate nodeOut.aw.bits.lock
invalidate nodeOut.aw.bits.burst
invalidate nodeOut.aw.bits.size
invalidate nodeOut.aw.bits.len
invalidate nodeOut.aw.bits.addr
invalidate nodeOut.aw.bits.id
invalidate nodeOut.aw.valid
invalidate nodeOut.aw.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_aw_deq_q of Queue2_AXI4BundleAW
connect nodeOut_aw_deq_q.clock, clock
connect nodeOut_aw_deq_q.reset, reset
connect nodeOut_aw_deq_q.io.enq.valid, nodeIn.aw.valid
connect nodeOut_aw_deq_q.io.enq.bits.qos, nodeIn.aw.bits.qos
connect nodeOut_aw_deq_q.io.enq.bits.prot, nodeIn.aw.bits.prot
connect nodeOut_aw_deq_q.io.enq.bits.cache, nodeIn.aw.bits.cache
connect nodeOut_aw_deq_q.io.enq.bits.lock, nodeIn.aw.bits.lock
connect nodeOut_aw_deq_q.io.enq.bits.burst, nodeIn.aw.bits.burst
connect nodeOut_aw_deq_q.io.enq.bits.size, nodeIn.aw.bits.size
connect nodeOut_aw_deq_q.io.enq.bits.len, nodeIn.aw.bits.len
connect nodeOut_aw_deq_q.io.enq.bits.addr, nodeIn.aw.bits.addr
connect nodeOut_aw_deq_q.io.enq.bits.id, nodeIn.aw.bits.id
connect nodeIn.aw.ready, nodeOut_aw_deq_q.io.enq.ready
wire nodeOut_aw_irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}
connect nodeOut_aw_irr.bits, nodeOut_aw_deq_q.io.deq.bits
connect nodeOut_aw_irr.valid, nodeOut_aw_deq_q.io.deq.valid
connect nodeOut_aw_deq_q.io.deq.ready, nodeOut_aw_irr.ready
connect nodeOut.aw, nodeOut_aw_irr
inst nodeOut_w_deq_q of Queue2_AXI4BundleW
connect nodeOut_w_deq_q.clock, clock
connect nodeOut_w_deq_q.reset, reset
connect nodeOut_w_deq_q.io.enq.valid, nodeIn.w.valid
connect nodeOut_w_deq_q.io.enq.bits.last, nodeIn.w.bits.last
connect nodeOut_w_deq_q.io.enq.bits.strb, nodeIn.w.bits.strb
connect nodeOut_w_deq_q.io.enq.bits.data, nodeIn.w.bits.data
connect nodeIn.w.ready, nodeOut_w_deq_q.io.enq.ready
wire nodeOut_w_irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}
connect nodeOut_w_irr.bits, nodeOut_w_deq_q.io.deq.bits
connect nodeOut_w_irr.valid, nodeOut_w_deq_q.io.deq.valid
connect nodeOut_w_deq_q.io.deq.ready, nodeOut_w_irr.ready
connect nodeOut.w, nodeOut_w_irr
inst nodeIn_b_deq_q of Queue2_AXI4BundleB
connect nodeIn_b_deq_q.clock, clock
connect nodeIn_b_deq_q.reset, reset
connect nodeIn_b_deq_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_deq_q.io.enq.bits.resp, nodeOut.b.bits.resp
connect nodeIn_b_deq_q.io.enq.bits.id, nodeOut.b.bits.id
connect nodeOut.b.ready, nodeIn_b_deq_q.io.enq.ready
wire nodeIn_b_irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}
connect nodeIn_b_irr.bits, nodeIn_b_deq_q.io.deq.bits
connect nodeIn_b_irr.valid, nodeIn_b_deq_q.io.deq.valid
connect nodeIn_b_deq_q.io.deq.ready, nodeIn_b_irr.ready
connect nodeIn.b, nodeIn_b_irr
inst nodeOut_ar_deq_q of Queue2_AXI4BundleAR
connect nodeOut_ar_deq_q.clock, clock
connect nodeOut_ar_deq_q.reset, reset
connect nodeOut_ar_deq_q.io.enq.valid, nodeIn.ar.valid
connect nodeOut_ar_deq_q.io.enq.bits.qos, nodeIn.ar.bits.qos
connect nodeOut_ar_deq_q.io.enq.bits.prot, nodeIn.ar.bits.prot
connect nodeOut_ar_deq_q.io.enq.bits.cache, nodeIn.ar.bits.cache
connect nodeOut_ar_deq_q.io.enq.bits.lock, nodeIn.ar.bits.lock
connect nodeOut_ar_deq_q.io.enq.bits.burst, nodeIn.ar.bits.burst
connect nodeOut_ar_deq_q.io.enq.bits.size, nodeIn.ar.bits.size
connect nodeOut_ar_deq_q.io.enq.bits.len, nodeIn.ar.bits.len
connect nodeOut_ar_deq_q.io.enq.bits.addr, nodeIn.ar.bits.addr
connect nodeOut_ar_deq_q.io.enq.bits.id, nodeIn.ar.bits.id
connect nodeIn.ar.ready, nodeOut_ar_deq_q.io.enq.ready
wire nodeOut_ar_irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<31>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}
connect nodeOut_ar_irr.bits, nodeOut_ar_deq_q.io.deq.bits
connect nodeOut_ar_irr.valid, nodeOut_ar_deq_q.io.deq.valid
connect nodeOut_ar_deq_q.io.deq.ready, nodeOut_ar_irr.ready
connect nodeOut.ar, nodeOut_ar_irr
inst nodeIn_r_deq_q of Queue2_AXI4BundleR
connect nodeIn_r_deq_q.clock, clock
connect nodeIn_r_deq_q.reset, reset
connect nodeIn_r_deq_q.io.enq.valid, nodeOut.r.valid
connect nodeIn_r_deq_q.io.enq.bits.last, nodeOut.r.bits.last
connect nodeIn_r_deq_q.io.enq.bits.resp, nodeOut.r.bits.resp
connect nodeIn_r_deq_q.io.enq.bits.data, nodeOut.r.bits.data
connect nodeIn_r_deq_q.io.enq.bits.id, nodeOut.r.bits.id
connect nodeOut.r.ready, nodeIn_r_deq_q.io.enq.ready
wire nodeIn_r_irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}
connect nodeIn_r_irr.bits, nodeIn_r_deq_q.io.deq.bits
connect nodeIn_r_irr.valid, nodeIn_r_deq_q.io.deq.valid
connect nodeIn_r_deq_q.io.deq.ready, nodeIn_r_irr.ready
connect nodeIn.r, nodeIn_r_irr | module AXI4Buffer( // @[Buffer.scala:37:9]
input clock, // @[Buffer.scala:37:9]
input reset, // @[Buffer.scala:37:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [30:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [30:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [30:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [30:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[Buffer.scala:37:9]
wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[Buffer.scala:37:9]
wire [30:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[Buffer.scala:37:9]
wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[Buffer.scala:37:9]
wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[Buffer.scala:37:9]
wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[Buffer.scala:37:9]
wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[Buffer.scala:37:9]
wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[Buffer.scala:37:9]
wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[Buffer.scala:37:9]
wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[Buffer.scala:37:9]
wire auto_in_w_valid_0 = auto_in_w_valid; // @[Buffer.scala:37:9]
wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[Buffer.scala:37:9]
wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[Buffer.scala:37:9]
wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[Buffer.scala:37:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:37:9]
wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[Buffer.scala:37:9]
wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[Buffer.scala:37:9]
wire [30:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[Buffer.scala:37:9]
wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[Buffer.scala:37:9]
wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[Buffer.scala:37:9]
wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[Buffer.scala:37:9]
wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[Buffer.scala:37:9]
wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[Buffer.scala:37:9]
wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[Buffer.scala:37:9]
wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[Buffer.scala:37:9]
wire auto_in_r_ready_0 = auto_in_r_ready; // @[Buffer.scala:37:9]
wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[Buffer.scala:37:9]
wire auto_out_w_ready_0 = auto_out_w_ready; // @[Buffer.scala:37:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:37:9]
wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[Buffer.scala:37:9]
wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[Buffer.scala:37:9]
wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[Buffer.scala:37:9]
wire auto_out_r_valid_0 = auto_out_r_valid; // @[Buffer.scala:37:9]
wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[Buffer.scala:37:9]
wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[Buffer.scala:37:9]
wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[Buffer.scala:37:9]
wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[Buffer.scala:37:9]
wire nodeIn_aw_ready; // @[MixedNode.scala:551:17]
wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[Buffer.scala:37:9]
wire [30:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[Buffer.scala:37:9]
wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[Buffer.scala:37:9]
wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[Buffer.scala:37:9]
wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[Buffer.scala:37:9]
wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[Buffer.scala:37:9]
wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[Buffer.scala:37:9]
wire nodeIn_w_ready; // @[MixedNode.scala:551:17]
wire nodeIn_w_valid = auto_in_w_valid_0; // @[Buffer.scala:37:9]
wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[Buffer.scala:37:9]
wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[Buffer.scala:37:9]
wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[Buffer.scala:37:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:37:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_ar_ready; // @[MixedNode.scala:551:17]
wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[Buffer.scala:37:9]
wire [30:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[Buffer.scala:37:9]
wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[Buffer.scala:37:9]
wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[Buffer.scala:37:9]
wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[Buffer.scala:37:9]
wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[Buffer.scala:37:9]
wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[Buffer.scala:37:9]
wire nodeIn_r_ready = auto_in_r_ready_0; // @[Buffer.scala:37:9]
wire nodeIn_r_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17]
wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[Buffer.scala:37:9]
wire nodeOut_aw_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17]
wire [30:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_aw_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_w_ready = auto_out_w_ready_0; // @[Buffer.scala:37:9]
wire nodeOut_w_valid; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17]
wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[Buffer.scala:37:9]
wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[Buffer.scala:37:9]
wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[Buffer.scala:37:9]
wire nodeOut_ar_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17]
wire [30:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_len; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_r_ready; // @[MixedNode.scala:542:17]
wire nodeOut_r_valid = auto_out_r_valid_0; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[Buffer.scala:37:9]
wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[Buffer.scala:37:9]
wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[Buffer.scala:37:9]
wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[Buffer.scala:37:9]
wire auto_in_aw_ready_0; // @[Buffer.scala:37:9]
wire auto_in_w_ready_0; // @[Buffer.scala:37:9]
wire [3:0] auto_in_b_bits_id_0; // @[Buffer.scala:37:9]
wire [1:0] auto_in_b_bits_resp_0; // @[Buffer.scala:37:9]
wire auto_in_b_valid_0; // @[Buffer.scala:37:9]
wire auto_in_ar_ready_0; // @[Buffer.scala:37:9]
wire [3:0] auto_in_r_bits_id_0; // @[Buffer.scala:37:9]
wire [63:0] auto_in_r_bits_data_0; // @[Buffer.scala:37:9]
wire [1:0] auto_in_r_bits_resp_0; // @[Buffer.scala:37:9]
wire auto_in_r_bits_last_0; // @[Buffer.scala:37:9]
wire auto_in_r_valid_0; // @[Buffer.scala:37:9]
wire [3:0] auto_out_aw_bits_id_0; // @[Buffer.scala:37:9]
wire [30:0] auto_out_aw_bits_addr_0; // @[Buffer.scala:37:9]
wire [7:0] auto_out_aw_bits_len_0; // @[Buffer.scala:37:9]
wire [2:0] auto_out_aw_bits_size_0; // @[Buffer.scala:37:9]
wire [1:0] auto_out_aw_bits_burst_0; // @[Buffer.scala:37:9]
wire auto_out_aw_bits_lock_0; // @[Buffer.scala:37:9]
wire [3:0] auto_out_aw_bits_cache_0; // @[Buffer.scala:37:9]
wire [2:0] auto_out_aw_bits_prot_0; // @[Buffer.scala:37:9]
wire [3:0] auto_out_aw_bits_qos_0; // @[Buffer.scala:37:9]
wire auto_out_aw_valid_0; // @[Buffer.scala:37:9]
wire [63:0] auto_out_w_bits_data_0; // @[Buffer.scala:37:9]
wire [7:0] auto_out_w_bits_strb_0; // @[Buffer.scala:37:9]
wire auto_out_w_bits_last_0; // @[Buffer.scala:37:9]
wire auto_out_w_valid_0; // @[Buffer.scala:37:9]
wire auto_out_b_ready_0; // @[Buffer.scala:37:9]
wire [3:0] auto_out_ar_bits_id_0; // @[Buffer.scala:37:9]
wire [30:0] auto_out_ar_bits_addr_0; // @[Buffer.scala:37:9]
wire [7:0] auto_out_ar_bits_len_0; // @[Buffer.scala:37:9]
wire [2:0] auto_out_ar_bits_size_0; // @[Buffer.scala:37:9]
wire [1:0] auto_out_ar_bits_burst_0; // @[Buffer.scala:37:9]
wire auto_out_ar_bits_lock_0; // @[Buffer.scala:37:9]
wire [3:0] auto_out_ar_bits_cache_0; // @[Buffer.scala:37:9]
wire [2:0] auto_out_ar_bits_prot_0; // @[Buffer.scala:37:9]
wire [3:0] auto_out_ar_bits_qos_0; // @[Buffer.scala:37:9]
wire auto_out_ar_valid_0; // @[Buffer.scala:37:9]
wire auto_out_r_ready_0; // @[Buffer.scala:37:9]
assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[Buffer.scala:37:9]
assign auto_in_w_ready_0 = nodeIn_w_ready; // @[Buffer.scala:37:9]
wire nodeIn_b_irr_ready = nodeIn_b_ready; // @[Decoupled.scala:401:19]
wire nodeIn_b_irr_valid; // @[Decoupled.scala:401:19]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_b_irr_bits_id; // @[Decoupled.scala:401:19]
assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[Buffer.scala:37:9]
wire [1:0] nodeIn_b_irr_bits_resp; // @[Decoupled.scala:401:19]
assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[Buffer.scala:37:9]
assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[Buffer.scala:37:9]
wire nodeIn_r_irr_ready = nodeIn_r_ready; // @[Decoupled.scala:401:19]
wire nodeIn_r_irr_valid; // @[Decoupled.scala:401:19]
assign auto_in_r_valid_0 = nodeIn_r_valid; // @[Buffer.scala:37:9]
wire [3:0] nodeIn_r_irr_bits_id; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[Buffer.scala:37:9]
wire [63:0] nodeIn_r_irr_bits_data; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[Buffer.scala:37:9]
wire [1:0] nodeIn_r_irr_bits_resp; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[Buffer.scala:37:9]
wire nodeIn_r_irr_bits_last; // @[Decoupled.scala:401:19]
assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[Buffer.scala:37:9]
wire nodeOut_aw_irr_ready = nodeOut_aw_ready; // @[Decoupled.scala:401:19]
wire nodeOut_aw_irr_valid; // @[Decoupled.scala:401:19]
assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_aw_irr_bits_id; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[Buffer.scala:37:9]
wire [30:0] nodeOut_aw_irr_bits_addr; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[Buffer.scala:37:9]
wire [7:0] nodeOut_aw_irr_bits_len; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_len_0 = nodeOut_aw_bits_len; // @[Buffer.scala:37:9]
wire [2:0] nodeOut_aw_irr_bits_size; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[Buffer.scala:37:9]
wire [1:0] nodeOut_aw_irr_bits_burst; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[Buffer.scala:37:9]
wire nodeOut_aw_irr_bits_lock; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_aw_irr_bits_cache; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[Buffer.scala:37:9]
wire [2:0] nodeOut_aw_irr_bits_prot; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_aw_irr_bits_qos; // @[Decoupled.scala:401:19]
assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[Buffer.scala:37:9]
wire nodeOut_w_irr_ready = nodeOut_w_ready; // @[Decoupled.scala:401:19]
wire nodeOut_w_irr_valid; // @[Decoupled.scala:401:19]
assign auto_out_w_valid_0 = nodeOut_w_valid; // @[Buffer.scala:37:9]
wire [63:0] nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[Buffer.scala:37:9]
wire [7:0] nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[Buffer.scala:37:9]
wire nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[Buffer.scala:37:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:37:9]
wire nodeOut_ar_irr_ready = nodeOut_ar_ready; // @[Decoupled.scala:401:19]
wire nodeOut_ar_irr_valid; // @[Decoupled.scala:401:19]
assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_ar_irr_bits_id; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[Buffer.scala:37:9]
wire [30:0] nodeOut_ar_irr_bits_addr; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[Buffer.scala:37:9]
wire [7:0] nodeOut_ar_irr_bits_len; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_len_0 = nodeOut_ar_bits_len; // @[Buffer.scala:37:9]
wire [2:0] nodeOut_ar_irr_bits_size; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[Buffer.scala:37:9]
wire [1:0] nodeOut_ar_irr_bits_burst; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[Buffer.scala:37:9]
wire nodeOut_ar_irr_bits_lock; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_ar_irr_bits_cache; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[Buffer.scala:37:9]
wire [2:0] nodeOut_ar_irr_bits_prot; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[Buffer.scala:37:9]
wire [3:0] nodeOut_ar_irr_bits_qos; // @[Decoupled.scala:401:19]
assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[Buffer.scala:37:9]
assign auto_out_r_ready_0 = nodeOut_r_ready; // @[Buffer.scala:37:9]
assign nodeOut_aw_valid = nodeOut_aw_irr_valid; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_id = nodeOut_aw_irr_bits_id; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_addr = nodeOut_aw_irr_bits_addr; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_len = nodeOut_aw_irr_bits_len; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_size = nodeOut_aw_irr_bits_size; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_burst = nodeOut_aw_irr_bits_burst; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_lock = nodeOut_aw_irr_bits_lock; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_cache = nodeOut_aw_irr_bits_cache; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_prot = nodeOut_aw_irr_bits_prot; // @[Decoupled.scala:401:19]
assign nodeOut_aw_bits_qos = nodeOut_aw_irr_bits_qos; // @[Decoupled.scala:401:19]
assign nodeOut_w_valid = nodeOut_w_irr_valid; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_data = nodeOut_w_irr_bits_data; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_strb = nodeOut_w_irr_bits_strb; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_last = nodeOut_w_irr_bits_last; // @[Decoupled.scala:401:19]
assign nodeIn_b_valid = nodeIn_b_irr_valid; // @[Decoupled.scala:401:19]
assign nodeIn_b_bits_id = nodeIn_b_irr_bits_id; // @[Decoupled.scala:401:19]
assign nodeIn_b_bits_resp = nodeIn_b_irr_bits_resp; // @[Decoupled.scala:401:19]
assign nodeOut_ar_valid = nodeOut_ar_irr_valid; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_id = nodeOut_ar_irr_bits_id; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_addr = nodeOut_ar_irr_bits_addr; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_len = nodeOut_ar_irr_bits_len; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_size = nodeOut_ar_irr_bits_size; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_burst = nodeOut_ar_irr_bits_burst; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_lock = nodeOut_ar_irr_bits_lock; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_cache = nodeOut_ar_irr_bits_cache; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_prot = nodeOut_ar_irr_bits_prot; // @[Decoupled.scala:401:19]
assign nodeOut_ar_bits_qos = nodeOut_ar_irr_bits_qos; // @[Decoupled.scala:401:19]
assign nodeIn_r_valid = nodeIn_r_irr_valid; // @[Decoupled.scala:401:19]
assign nodeIn_r_bits_id = nodeIn_r_irr_bits_id; // @[Decoupled.scala:401:19]
assign nodeIn_r_bits_data = nodeIn_r_irr_bits_data; // @[Decoupled.scala:401:19]
assign nodeIn_r_bits_resp = nodeIn_r_irr_bits_resp; // @[Decoupled.scala:401:19]
assign nodeIn_r_bits_last = nodeIn_r_irr_bits_last; // @[Decoupled.scala:401:19]
Queue2_AXI4BundleAW nodeOut_aw_deq_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_aw_ready),
.io_enq_valid (nodeIn_aw_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_id (nodeIn_aw_bits_id), // @[MixedNode.scala:551:17]
.io_enq_bits_addr (nodeIn_aw_bits_addr), // @[MixedNode.scala:551:17]
.io_enq_bits_len (nodeIn_aw_bits_len), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_aw_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_burst (nodeIn_aw_bits_burst), // @[MixedNode.scala:551:17]
.io_enq_bits_lock (nodeIn_aw_bits_lock), // @[MixedNode.scala:551:17]
.io_enq_bits_cache (nodeIn_aw_bits_cache), // @[MixedNode.scala:551:17]
.io_enq_bits_prot (nodeIn_aw_bits_prot), // @[MixedNode.scala:551:17]
.io_enq_bits_qos (nodeIn_aw_bits_qos), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_aw_irr_ready), // @[Decoupled.scala:401:19]
.io_deq_valid (nodeOut_aw_irr_valid),
.io_deq_bits_id (nodeOut_aw_irr_bits_id),
.io_deq_bits_addr (nodeOut_aw_irr_bits_addr),
.io_deq_bits_len (nodeOut_aw_irr_bits_len),
.io_deq_bits_size (nodeOut_aw_irr_bits_size),
.io_deq_bits_burst (nodeOut_aw_irr_bits_burst),
.io_deq_bits_lock (nodeOut_aw_irr_bits_lock),
.io_deq_bits_cache (nodeOut_aw_irr_bits_cache),
.io_deq_bits_prot (nodeOut_aw_irr_bits_prot),
.io_deq_bits_qos (nodeOut_aw_irr_bits_qos)
); // @[Decoupled.scala:362:21]
Queue2_AXI4BundleW nodeOut_w_deq_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_w_ready),
.io_enq_valid (nodeIn_w_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_w_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_strb (nodeIn_w_bits_strb), // @[MixedNode.scala:551:17]
.io_enq_bits_last (nodeIn_w_bits_last), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_w_irr_ready), // @[Decoupled.scala:401:19]
.io_deq_valid (nodeOut_w_irr_valid),
.io_deq_bits_data (nodeOut_w_irr_bits_data),
.io_deq_bits_strb (nodeOut_w_irr_bits_strb),
.io_deq_bits_last (nodeOut_w_irr_bits_last)
); // @[Decoupled.scala:362:21]
Queue2_AXI4BundleB nodeIn_b_deq_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_id (nodeOut_b_bits_id), // @[MixedNode.scala:542:17]
.io_enq_bits_resp (nodeOut_b_bits_resp), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_irr_ready), // @[Decoupled.scala:401:19]
.io_deq_valid (nodeIn_b_irr_valid),
.io_deq_bits_id (nodeIn_b_irr_bits_id),
.io_deq_bits_resp (nodeIn_b_irr_bits_resp)
); // @[Decoupled.scala:362:21]
Queue2_AXI4BundleAR nodeOut_ar_deq_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_ar_ready),
.io_enq_valid (nodeIn_ar_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_id (nodeIn_ar_bits_id), // @[MixedNode.scala:551:17]
.io_enq_bits_addr (nodeIn_ar_bits_addr), // @[MixedNode.scala:551:17]
.io_enq_bits_len (nodeIn_ar_bits_len), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_ar_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_burst (nodeIn_ar_bits_burst), // @[MixedNode.scala:551:17]
.io_enq_bits_lock (nodeIn_ar_bits_lock), // @[MixedNode.scala:551:17]
.io_enq_bits_cache (nodeIn_ar_bits_cache), // @[MixedNode.scala:551:17]
.io_enq_bits_prot (nodeIn_ar_bits_prot), // @[MixedNode.scala:551:17]
.io_enq_bits_qos (nodeIn_ar_bits_qos), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_ar_irr_ready), // @[Decoupled.scala:401:19]
.io_deq_valid (nodeOut_ar_irr_valid),
.io_deq_bits_id (nodeOut_ar_irr_bits_id),
.io_deq_bits_addr (nodeOut_ar_irr_bits_addr),
.io_deq_bits_len (nodeOut_ar_irr_bits_len),
.io_deq_bits_size (nodeOut_ar_irr_bits_size),
.io_deq_bits_burst (nodeOut_ar_irr_bits_burst),
.io_deq_bits_lock (nodeOut_ar_irr_bits_lock),
.io_deq_bits_cache (nodeOut_ar_irr_bits_cache),
.io_deq_bits_prot (nodeOut_ar_irr_bits_prot),
.io_deq_bits_qos (nodeOut_ar_irr_bits_qos)
); // @[Decoupled.scala:362:21]
Queue2_AXI4BundleR nodeIn_r_deq_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_r_ready),
.io_enq_valid (nodeOut_r_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_id (nodeOut_r_bits_id), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_r_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_resp (nodeOut_r_bits_resp), // @[MixedNode.scala:542:17]
.io_enq_bits_last (nodeOut_r_bits_last), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_r_irr_ready), // @[Decoupled.scala:401:19]
.io_deq_valid (nodeIn_r_irr_valid),
.io_deq_bits_id (nodeIn_r_irr_bits_id),
.io_deq_bits_data (nodeIn_r_irr_bits_data),
.io_deq_bits_resp (nodeIn_r_irr_bits_resp),
.io_deq_bits_last (nodeIn_r_irr_bits_last)
); // @[Decoupled.scala:362:21]
assign auto_in_aw_ready = auto_in_aw_ready_0; // @[Buffer.scala:37:9]
assign auto_in_w_ready = auto_in_w_ready_0; // @[Buffer.scala:37:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:37:9]
assign auto_in_b_bits_id = auto_in_b_bits_id_0; // @[Buffer.scala:37:9]
assign auto_in_b_bits_resp = auto_in_b_bits_resp_0; // @[Buffer.scala:37:9]
assign auto_in_ar_ready = auto_in_ar_ready_0; // @[Buffer.scala:37:9]
assign auto_in_r_valid = auto_in_r_valid_0; // @[Buffer.scala:37:9]
assign auto_in_r_bits_id = auto_in_r_bits_id_0; // @[Buffer.scala:37:9]
assign auto_in_r_bits_data = auto_in_r_bits_data_0; // @[Buffer.scala:37:9]
assign auto_in_r_bits_resp = auto_in_r_bits_resp_0; // @[Buffer.scala:37:9]
assign auto_in_r_bits_last = auto_in_r_bits_last_0; // @[Buffer.scala:37:9]
assign auto_out_aw_valid = auto_out_aw_valid_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_id = auto_out_aw_bits_id_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_addr = auto_out_aw_bits_addr_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_len = auto_out_aw_bits_len_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_size = auto_out_aw_bits_size_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_burst = auto_out_aw_bits_burst_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_lock = auto_out_aw_bits_lock_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_cache = auto_out_aw_bits_cache_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_prot = auto_out_aw_bits_prot_0; // @[Buffer.scala:37:9]
assign auto_out_aw_bits_qos = auto_out_aw_bits_qos_0; // @[Buffer.scala:37:9]
assign auto_out_w_valid = auto_out_w_valid_0; // @[Buffer.scala:37:9]
assign auto_out_w_bits_data = auto_out_w_bits_data_0; // @[Buffer.scala:37:9]
assign auto_out_w_bits_strb = auto_out_w_bits_strb_0; // @[Buffer.scala:37:9]
assign auto_out_w_bits_last = auto_out_w_bits_last_0; // @[Buffer.scala:37:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:37:9]
assign auto_out_ar_valid = auto_out_ar_valid_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_id = auto_out_ar_bits_id_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_addr = auto_out_ar_bits_addr_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_len = auto_out_ar_bits_len_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_size = auto_out_ar_bits_size_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_burst = auto_out_ar_bits_burst_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_lock = auto_out_ar_bits_lock_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_cache = auto_out_ar_bits_cache_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_prot = auto_out_ar_bits_prot_0; // @[Buffer.scala:37:9]
assign auto_out_ar_bits_qos = auto_out_ar_bits_qos_0; // @[Buffer.scala:37:9]
assign auto_out_r_ready = auto_out_r_ready_0; // @[Buffer.scala:37:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PTW_7 :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}}
regreset state : UInt<3>, clock, reset, UInt<3>(0h0)
wire l2_refill_wire : UInt<1>
inst arb of Arbiter2_Valid_PTWReq_7
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], io.requestor[0].req
connect arb.io.in[1], io.requestor[1].req
node _arb_io_out_ready_T = eq(state, UInt<3>(0h0))
node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0))
node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1)
connect arb.io.out.ready, _arb_io_out_ready_T_2
wire _resp_valid_WIRE : UInt<1>[2]
connect _resp_valid_WIRE[0], UInt<1>(0h0)
connect _resp_valid_WIRE[1], UInt<1>(0h0)
reg resp_valid : UInt<1>[2], clock
connect resp_valid, _resp_valid_WIRE
node _clock_en_T = neq(state, UInt<3>(0h0))
node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire)
node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid)
node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid)
node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0)
node clock_en = or(_clock_en_T_3, _clock_en_T_4)
node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en)
connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T
reg invalidated : UInt<1>, clock
reg count : UInt<2>, clock
reg resp_ae_ptw : UInt<1>, clock
reg resp_ae_final : UInt<1>, clock
reg resp_pf : UInt<1>, clock
reg resp_gf : UInt<1>, clock
reg resp_hr : UInt<1>, clock
reg resp_hw : UInt<1>, clock
reg resp_hx : UInt<1>, clock
reg resp_fragmented_superpage : UInt<1>, clock
reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock
reg r_req_dest : UInt, clock
reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg aux_count : UInt<2>, clock
reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock
reg gpa_pgoff : UInt<12>, clock
reg stage2 : UInt<1>, clock
reg stage2_final : UInt<1>, clock
node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr)
node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1)
node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0))
node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1)
node do_both_stages = and(r_req.vstage1, r_req.stage2)
node _max_count_T = lt(count, aux_count)
node max_count = mux(_max_count_T, aux_count, count)
node _vpn_T = and(r_req.vstage1, stage2)
node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr)
reg mem_resp_valid : UInt<1>, clock
connect mem_resp_valid, io.mem.resp.valid
reg mem_resp_data : UInt, clock
connect mem_resp_data, io.mem.resp.bits.data
wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
wire _tmp_WIRE : UInt<64>
connect _tmp_WIRE, mem_resp_data
node _tmp_T = bits(_tmp_WIRE, 0, 0)
connect tmp.v, _tmp_T
node _tmp_T_1 = bits(_tmp_WIRE, 1, 1)
connect tmp.r, _tmp_T_1
node _tmp_T_2 = bits(_tmp_WIRE, 2, 2)
connect tmp.w, _tmp_T_2
node _tmp_T_3 = bits(_tmp_WIRE, 3, 3)
connect tmp.x, _tmp_T_3
node _tmp_T_4 = bits(_tmp_WIRE, 4, 4)
connect tmp.u, _tmp_T_4
node _tmp_T_5 = bits(_tmp_WIRE, 5, 5)
connect tmp.g, _tmp_T_5
node _tmp_T_6 = bits(_tmp_WIRE, 6, 6)
connect tmp.a, _tmp_T_6
node _tmp_T_7 = bits(_tmp_WIRE, 7, 7)
connect tmp.d, _tmp_T_7
node _tmp_T_8 = bits(_tmp_WIRE, 9, 8)
connect tmp.reserved_for_software, _tmp_T_8
node _tmp_T_9 = bits(_tmp_WIRE, 53, 10)
connect tmp.ppn, _tmp_T_9
node _tmp_T_10 = bits(_tmp_WIRE, 63, 54)
connect tmp.reserved_for_future, _tmp_T_10
wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect pte, tmp
node _res_ppn_T = eq(stage2, UInt<1>(0h0))
node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T)
node _res_ppn_T_2 = bits(tmp.ppn, 26, 0)
node _res_ppn_T_3 = bits(tmp.ppn, 19, 0)
node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3)
connect pte.ppn, _res_ppn_T_4
node _T = or(tmp.r, tmp.w)
node _T_1 = or(_T, tmp.x)
when _T_1 :
node _T_2 = leq(count, UInt<1>(0h0))
node _T_3 = bits(tmp.ppn, 17, 9)
node _T_4 = neq(_T_3, UInt<1>(0h0))
node _T_5 = and(_T_2, _T_4)
when _T_5 :
connect pte.v, UInt<1>(0h0)
node _T_6 = leq(count, UInt<1>(0h1))
node _T_7 = bits(tmp.ppn, 8, 0)
node _T_8 = neq(_T_7, UInt<1>(0h0))
node _T_9 = and(_T_6, _T_8)
when _T_9 :
connect pte.v, UInt<1>(0h0)
node _T_10 = eq(stage2, UInt<1>(0h0))
node _T_11 = and(do_both_stages, _T_10)
node _T_12 = shr(tmp.ppn, 27)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = shr(tmp.ppn, 20)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node invalid_paddr = mux(_T_11, _T_13, _T_15)
node _T_16 = eq(stage2, UInt<1>(0h0))
node _T_17 = and(do_both_stages, _T_16)
node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _count_T_1 = tail(_count_T, 1)
node _count_T_2 = sub(_count_T_1, UInt<1>(0h0))
node count_1 = tail(_count_T_2, 1)
node idxs_0 = shr(tmp.ppn, 29)
wire _WIRE : UInt<15>[1]
connect _WIRE[0], idxs_0
node _T_18 = or(count_1, UInt<0>(0h0))
node _T_19 = neq(_WIRE[0], UInt<1>(0h0))
node invalid_gpa = and(_T_17, _T_19)
node _traverse_T = eq(pte.r, UInt<1>(0h0))
node _traverse_T_1 = and(pte.v, _traverse_T)
node _traverse_T_2 = eq(pte.w, UInt<1>(0h0))
node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2)
node _traverse_T_4 = eq(pte.x, UInt<1>(0h0))
node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4)
node _traverse_T_6 = eq(pte.d, UInt<1>(0h0))
node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6)
node _traverse_T_8 = eq(pte.a, UInt<1>(0h0))
node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8)
node _traverse_T_10 = eq(pte.u, UInt<1>(0h0))
node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10)
node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12)
node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0))
node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14)
node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0))
node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16)
node _traverse_T_18 = lt(count, UInt<2>(0h2))
node traverse = and(_traverse_T_17, _traverse_T_18)
node _pte_addr_vpn_idxs_T = shr(vpn, 18)
node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0)
node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9)
node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0)
node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0)
node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0)
node _pte_addr_mask_T = eq(count, r_hgatp_initial_count)
node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T)
node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff))
node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1))
node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0)
node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2))
node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1)
node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3))
node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3)
node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask)
node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9)
node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx)
node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3)
node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags : UInt<32>[8], clock
reg data : UInt<20>[8], clock
node _can_hit_T = lt(count, UInt<2>(0h2))
node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0))
node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1)
node can_hit = and(_can_hit_T, _can_hit_T_2)
node tag = cat(r_req.vstage1, pte_addr)
node _hits_T = eq(tags[0], tag)
node _hits_T_1 = eq(tags[1], tag)
node _hits_T_2 = eq(tags[2], tag)
node _hits_T_3 = eq(tags[3], tag)
node _hits_T_4 = eq(tags[4], tag)
node _hits_T_5 = eq(tags[5], tag)
node _hits_T_6 = eq(tags[6], tag)
node _hits_T_7 = eq(tags[7], tag)
node hits_lo_lo = cat(_hits_T_1, _hits_T)
node hits_lo_hi = cat(_hits_T_3, _hits_T_2)
node hits_lo = cat(hits_lo_hi, hits_lo_lo)
node hits_hi_lo = cat(_hits_T_5, _hits_T_4)
node hits_hi_hi = cat(_hits_T_7, _hits_T_6)
node hits_hi = cat(hits_hi_hi, hits_hi_lo)
node _hits_T_8 = cat(hits_hi, hits_lo)
node hits = and(_hits_T_8, valid)
node _hit_T = orr(hits)
node pte_cache_hit = and(_hit_T, can_hit)
node _T_20 = and(mem_resp_valid, traverse)
node _T_21 = and(_T_20, can_hit)
node _T_22 = orr(hits)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = and(_T_21, _T_23)
node _T_25 = eq(invalidated, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
when _T_26 :
node _r_T = andr(valid)
node r_left_subtree_older = bits(state_reg, 6, 6)
node r_left_subtree_state = bits(state_reg, 5, 3)
node r_right_subtree_state = bits(state_reg, 2, 0)
node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2)
node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1)
node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0)
node _r_T_1 = bits(r_left_subtree_state_1, 0, 0)
node _r_T_2 = bits(r_right_subtree_state_1, 0, 0)
node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2)
node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3)
node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2)
node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1)
node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0)
node _r_T_5 = bits(r_left_subtree_state_2, 0, 0)
node _r_T_6 = bits(r_right_subtree_state_2, 0, 0)
node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6)
node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7)
node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8)
node _r_T_10 = cat(r_left_subtree_older, _r_T_9)
node _r_T_11 = not(valid)
node _r_T_12 = bits(_r_T_11, 0, 0)
node _r_T_13 = bits(_r_T_11, 1, 1)
node _r_T_14 = bits(_r_T_11, 2, 2)
node _r_T_15 = bits(_r_T_11, 3, 3)
node _r_T_16 = bits(_r_T_11, 4, 4)
node _r_T_17 = bits(_r_T_11, 5, 5)
node _r_T_18 = bits(_r_T_11, 6, 6)
node _r_T_19 = bits(_r_T_11, 7, 7)
node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20)
node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21)
node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22)
node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23)
node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24)
node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25)
node r = mux(_r_T, _r_T_10, _r_T_26)
node _valid_T = dshl(UInt<1>(0h1), r)
node _valid_T_1 = or(valid, _valid_T)
connect valid, _valid_T_1
connect tags[r], tag
connect data[r], pte.ppn
node state_reg_touch_way_sized = bits(r, 2, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg, 5, 3)
node state_reg_right_subtree_state = bits(state_reg, 2, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1)
node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0))
node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1)
node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0))
node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3)
node _state_reg_T_5 = bits(_state_reg_T, 0, 0)
node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0)
node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0))
node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1)
node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4)
node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8)
node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9)
node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1)
node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0))
node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1)
node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0)
node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0)
node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0))
node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14)
node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0)
node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0))
node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2)
node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15)
node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19)
node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state)
node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10)
node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21)
connect state_reg, _state_reg_T_22
node _T_27 = eq(state, UInt<3>(0h1))
node _T_28 = and(pte_cache_hit, _T_27)
when _T_28 :
node hi = bits(hits, 7, 4)
node lo = bits(hits, 3, 0)
node _T_29 = orr(hi)
node _T_30 = or(hi, lo)
node hi_1 = bits(_T_30, 3, 2)
node lo_1 = bits(_T_30, 1, 0)
node _T_31 = orr(hi_1)
node _T_32 = or(hi_1, lo_1)
node _T_33 = bits(_T_32, 1, 1)
node _T_34 = cat(_T_31, _T_33)
node _T_35 = cat(_T_29, _T_34)
node state_reg_touch_way_sized_1 = bits(_T_35, 2, 0)
node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2)
node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0))
node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3)
node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0)
node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1)
node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0))
node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0)
node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0)
node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0))
node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26)
node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0)
node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0))
node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4)
node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27)
node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31)
node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32)
node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0)
node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1)
node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0))
node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0)
node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0)
node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0))
node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37)
node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0)
node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0)
node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0))
node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5)
node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38)
node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42)
node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3)
node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33)
node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44)
connect state_reg, _state_reg_T_45
node _T_36 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_37 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_38 = or(_T_36, _T_37)
node _T_39 = and(io.dpath.sfence.valid, _T_38)
when _T_39 :
connect valid, UInt<1>(0h0)
node _T_40 = eq(state, UInt<3>(0h1))
node _T_41 = and(pte_cache_hit, _T_40)
node _T_42 = eq(count, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(state, UInt<3>(0h1))
node _T_45 = and(pte_cache_hit, _T_44)
node _T_46 = eq(count, UInt<1>(0h1))
node _T_47 = and(_T_45, _T_46)
node _T_48 = bits(hits, 0, 0)
node _T_49 = bits(hits, 1, 1)
node _T_50 = bits(hits, 2, 2)
node _T_51 = bits(hits, 3, 3)
node _T_52 = bits(hits, 4, 4)
node _T_53 = bits(hits, 5, 5)
node _T_54 = bits(hits, 6, 6)
node _T_55 = bits(hits, 7, 7)
node _T_56 = mux(_T_48, data[0], UInt<1>(0h0))
node _T_57 = mux(_T_49, data[1], UInt<1>(0h0))
node _T_58 = mux(_T_50, data[2], UInt<1>(0h0))
node _T_59 = mux(_T_51, data[3], UInt<1>(0h0))
node _T_60 = mux(_T_52, data[4], UInt<1>(0h0))
node _T_61 = mux(_T_53, data[5], UInt<1>(0h0))
node _T_62 = mux(_T_54, data[6], UInt<1>(0h0))
node _T_63 = mux(_T_55, data[7], UInt<1>(0h0))
node _T_64 = or(_T_56, _T_57)
node _T_65 = or(_T_64, _T_58)
node _T_66 = or(_T_65, _T_59)
node _T_67 = or(_T_66, _T_60)
node _T_68 = or(_T_67, _T_61)
node _T_69 = or(_T_68, _T_62)
node _T_70 = or(_T_69, _T_63)
wire pte_cache_data : UInt<20>
connect pte_cache_data, _T_70
regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0)
regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0)
reg tags_1 : UInt<32>[8], clock
reg data_1 : UInt<20>[8], clock
node _can_hit_T_3 = eq(count, r_hgatp_initial_count)
node _can_hit_T_4 = lt(aux_count, UInt<2>(0h2))
node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4)
node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1)
node _can_hit_T_7 = and(_can_hit_T_6, stage2)
node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0))
node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8)
node _can_refill_T = eq(stage2, UInt<1>(0h0))
node _can_refill_T_1 = and(do_both_stages, _can_refill_T)
node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0))
node can_refill = and(_can_refill_T_1, _can_refill_T_2)
node _tag_T = cat(UInt<38>(0h0), UInt<1>(0h0))
node tag_1 = cat(UInt<1>(0h1), _tag_T)
node _hits_T_9 = eq(tags_1[0], tag_1)
node _hits_T_10 = eq(tags_1[1], tag_1)
node _hits_T_11 = eq(tags_1[2], tag_1)
node _hits_T_12 = eq(tags_1[3], tag_1)
node _hits_T_13 = eq(tags_1[4], tag_1)
node _hits_T_14 = eq(tags_1[5], tag_1)
node _hits_T_15 = eq(tags_1[6], tag_1)
node _hits_T_16 = eq(tags_1[7], tag_1)
node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9)
node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11)
node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1)
node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13)
node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15)
node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1)
node _hits_T_17 = cat(hits_hi_1, hits_lo_1)
node hits_1 = and(_hits_T_17, valid_1)
node _hit_T_1 = orr(hits_1)
node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1)
node _T_71 = and(mem_resp_valid, traverse)
node _T_72 = and(_T_71, can_refill)
node _T_73 = orr(hits_1)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = and(_T_72, _T_74)
node _T_76 = eq(invalidated, UInt<1>(0h0))
node _T_77 = and(_T_75, _T_76)
when _T_77 :
node _r_T_27 = andr(valid_1)
node r_left_subtree_older_3 = bits(state_reg_1, 6, 6)
node r_left_subtree_state_3 = bits(state_reg_1, 5, 3)
node r_right_subtree_state_3 = bits(state_reg_1, 2, 0)
node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2)
node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1)
node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0)
node _r_T_28 = bits(r_left_subtree_state_4, 0, 0)
node _r_T_29 = bits(r_right_subtree_state_4, 0, 0)
node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29)
node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30)
node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2)
node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1)
node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0)
node _r_T_32 = bits(r_left_subtree_state_5, 0, 0)
node _r_T_33 = bits(r_right_subtree_state_5, 0, 0)
node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33)
node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34)
node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35)
node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36)
node _r_T_38 = not(valid_1)
node _r_T_39 = bits(_r_T_38, 0, 0)
node _r_T_40 = bits(_r_T_38, 1, 1)
node _r_T_41 = bits(_r_T_38, 2, 2)
node _r_T_42 = bits(_r_T_38, 3, 3)
node _r_T_43 = bits(_r_T_38, 4, 4)
node _r_T_44 = bits(_r_T_38, 5, 5)
node _r_T_45 = bits(_r_T_38, 6, 6)
node _r_T_46 = bits(_r_T_38, 7, 7)
node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7))
node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47)
node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48)
node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49)
node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50)
node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51)
node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52)
node r_1 = mux(_r_T_27, _r_T_37, _r_T_53)
node _valid_T_2 = dshl(UInt<1>(0h1), r_1)
node _valid_T_3 = or(valid_1, _valid_T_2)
connect valid_1, _valid_T_3
connect tags_1[r_1], tag_1
connect data_1[r_1], pte.ppn
node state_reg_touch_way_sized_2 = bits(r_1, 2, 0)
node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2)
node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0))
node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0)
node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1)
node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0))
node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0)
node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0)
node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0))
node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49)
node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0)
node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0))
node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7)
node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50)
node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54)
node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55)
node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0)
node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1)
node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0))
node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1)
node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0)
node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0)
node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0))
node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60)
node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0)
node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0))
node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8)
node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61)
node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65)
node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6)
node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56)
node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67)
connect state_reg_1, _state_reg_T_68
node _T_78 = eq(state, UInt<3>(0h1))
node _T_79 = and(stage2_pte_cache_hit, _T_78)
when _T_79 :
node hi_2 = bits(hits_1, 7, 4)
node lo_2 = bits(hits_1, 3, 0)
node _T_80 = orr(hi_2)
node _T_81 = or(hi_2, lo_2)
node hi_3 = bits(_T_81, 3, 2)
node lo_3 = bits(_T_81, 1, 0)
node _T_82 = orr(hi_3)
node _T_83 = or(hi_3, lo_3)
node _T_84 = bits(_T_83, 1, 1)
node _T_85 = cat(_T_82, _T_84)
node _T_86 = cat(_T_80, _T_85)
node state_reg_touch_way_sized_3 = bits(_T_86, 2, 0)
node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2)
node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0))
node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3)
node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0)
node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1)
node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0))
node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0)
node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0)
node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0))
node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72)
node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0)
node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0)
node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0))
node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10)
node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73)
node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77)
node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78)
node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0)
node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1)
node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0))
node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1)
node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0)
node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0)
node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0))
node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83)
node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0)
node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0)
node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0))
node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11)
node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84)
node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88)
node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9)
node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79)
node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90)
connect state_reg_1, _state_reg_T_91
node _T_87 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0))
node _T_88 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg)
node _T_89 = or(_T_87, _T_88)
node _T_90 = and(io.dpath.sfence.valid, _T_89)
when _T_90 :
connect valid_1, UInt<1>(0h0)
node _T_91 = eq(state, UInt<3>(0h1))
node _T_92 = and(stage2_pte_cache_hit, _T_91)
node _T_93 = eq(aux_count, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(state, UInt<3>(0h1))
node _T_96 = and(stage2_pte_cache_hit, _T_95)
node _T_97 = eq(aux_count, UInt<1>(0h1))
node _T_98 = and(_T_96, _T_97)
node _T_99 = bits(hits_1, 0, 0)
node _T_100 = bits(hits_1, 1, 1)
node _T_101 = bits(hits_1, 2, 2)
node _T_102 = bits(hits_1, 3, 3)
node _T_103 = bits(hits_1, 4, 4)
node _T_104 = bits(hits_1, 5, 5)
node _T_105 = bits(hits_1, 6, 6)
node _T_106 = bits(hits_1, 7, 7)
node _T_107 = mux(_T_99, data_1[0], UInt<1>(0h0))
node _T_108 = mux(_T_100, data_1[1], UInt<1>(0h0))
node _T_109 = mux(_T_101, data_1[2], UInt<1>(0h0))
node _T_110 = mux(_T_102, data_1[3], UInt<1>(0h0))
node _T_111 = mux(_T_103, data_1[4], UInt<1>(0h0))
node _T_112 = mux(_T_104, data_1[5], UInt<1>(0h0))
node _T_113 = mux(_T_105, data_1[6], UInt<1>(0h0))
node _T_114 = mux(_T_106, data_1[7], UInt<1>(0h0))
node _T_115 = or(_T_107, _T_108)
node _T_116 = or(_T_115, _T_109)
node _T_117 = or(_T_116, _T_110)
node _T_118 = or(_T_117, _T_111)
node _T_119 = or(_T_118, _T_112)
node _T_120 = or(_T_119, _T_113)
node _T_121 = or(_T_120, _T_114)
wire stage2_pte_cache_data : UInt<20>
connect stage2_pte_cache_data, _T_121
reg pte_hit : UInt<1>, clock
connect pte_hit, UInt<1>(0h0)
connect io.dpath.perf.pte_miss, UInt<1>(0h0)
node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1))
node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T)
node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0))
node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2)
connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3
node _T_122 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit)
node _T_123 = and(io.dpath.perf.l2hit, _T_122)
node _T_124 = eq(_T_123, UInt<1>(0h0))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf
assert(clock, _T_124, UInt<1>(0h1), "") : assert
reg l2_refill : UInt<1>, clock
connect l2_refill, UInt<1>(0h0)
connect l2_refill_wire, l2_refill
connect io.dpath.perf.l2miss, UInt<1>(0h0)
connect io.dpath.perf.l2hit, UInt<1>(0h0)
wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect _WIRE_1.v, UInt<1>(0h0)
connect _WIRE_1.r, UInt<1>(0h0)
connect _WIRE_1.w, UInt<1>(0h0)
connect _WIRE_1.x, UInt<1>(0h0)
connect _WIRE_1.u, UInt<1>(0h0)
connect _WIRE_1.g, UInt<1>(0h0)
connect _WIRE_1.a, UInt<1>(0h0)
connect _WIRE_1.d, UInt<1>(0h0)
connect _WIRE_1.reserved_for_software, UInt<2>(0h0)
connect _WIRE_1.ppn, UInt<44>(0h0)
connect _WIRE_1.reserved_for_future, UInt<10>(0h0)
wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect l2_pte, _WIRE_1
node _invalidated_T = neq(state, UInt<3>(0h0))
node _invalidated_T_1 = and(invalidated, _invalidated_T)
node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1)
connect invalidated, _invalidated_T_2
connect io.mem.keep_clock_enabled, UInt<1>(0h0)
node _io_mem_req_valid_T = eq(state, UInt<3>(0h1))
node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3))
node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1)
connect io.mem.req.valid, _io_mem_req_valid_T_2
connect io.mem.req.bits.phys, UInt<1>(0h1)
connect io.mem.req.bits.cmd, UInt<1>(0h0)
connect io.mem.req.bits.size, UInt<2>(0h3)
connect io.mem.req.bits.signed, UInt<1>(0h0)
connect io.mem.req.bits.addr, pte_addr
connect io.mem.req.bits.dprv, UInt<1>(0h1)
node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0))
node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T)
connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1
invalidate io.mem.req.bits.tag
connect io.mem.req.bits.no_resp, UInt<1>(0h0)
invalidate io.mem.req.bits.no_alloc
invalidate io.mem.req.bits.no_xcpt
invalidate io.mem.req.bits.data
invalidate io.mem.req.bits.mask
node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2))
node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T)
node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf)
connect io.mem.s1_kill, _io_mem_s1_kill_T_2
invalidate io.mem.s1_data.mask
invalidate io.mem.s1_data.data
connect io.mem.s2_kill, UInt<1>(0h0)
node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8)
node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10)
node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13)
node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15)
node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12)
node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17)
node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21)
node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23)
node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25)
node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28)
node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30)
node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32)
node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12)
node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38)
node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000)))
node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40)
node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43)
node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45)
node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48)
node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50)
node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000))
node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53)
node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000)))
node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55)
node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000))
node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58)
node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60)
node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000))
node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63)
node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65)
node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68)
node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000)))
node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70)
node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000))
node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73)
node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000)))
node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75)
node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000))
node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78)
node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000)))
node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80)
node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83)
node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000)))
node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85)
node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42)
node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47)
node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52)
node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57)
node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62)
node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67)
node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72)
node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77)
node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82)
node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87)
node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98)
node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100)
node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102)
node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105)
node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000)))
node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107)
node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000))
node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110)
node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000)))
node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112)
node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115)
node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000)))
node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117)
node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120)
node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000)))
node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122)
node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125)
node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000)))
node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127)
node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109)
node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114)
node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119)
node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124)
node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129)
node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000))
node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135)
node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000)))
node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137)
node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000))
node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140)
node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000)))
node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142)
node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139)
node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144)
node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147)
node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149)
node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151)
node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0))
node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000))
node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154)
node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000)))
node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156)
node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0)))
node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158)
node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0))
node _pmaHomogeneous_T = eq(count, UInt<1>(0h1))
node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0))
node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2))
node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1)
node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3))
node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3)
node _pmpHomogeneous_T = shl(r_pte.ppn, 12)
wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0)
connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0)
connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0)
connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0)
connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0)
node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T)
node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4)
node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6)
node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2)
node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3))
node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4)
node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5)
node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30)
node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0))
node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9)
node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3))
node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11)
node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12)
node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21)
node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0))
node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16)
node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3))
node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18)
node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19)
node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12)
node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0))
node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8)
node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24)
node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26)
node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28)
node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0)
node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T)
node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2)
node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3)
node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T)
node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2)
node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3)
node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1)
node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3)
node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1)
node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3)
node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5)
node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask)
node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1)
node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3)
node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask)
node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5)
node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper)
node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper)
node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33)
node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34)
node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35)
node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36)
node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8)
node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12)
node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14)
node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39)
node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3))
node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41)
node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42)
node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30)
node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0))
node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46)
node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3))
node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48)
node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49)
node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21)
node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0))
node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53)
node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3))
node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55)
node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56)
node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12)
node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0))
node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45)
node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61)
node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63)
node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65)
node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0)
node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5)
node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7)
node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8)
node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5)
node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7)
node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8)
node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6)
node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8)
node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7)
node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9)
node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11)
node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1)
node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7)
node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9)
node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1)
node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11)
node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1)
node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1)
node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70)
node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71)
node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72)
node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73)
node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16)
node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20)
node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22)
node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76)
node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3))
node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78)
node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79)
node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30)
node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0))
node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83)
node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3))
node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85)
node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86)
node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21)
node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0))
node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90)
node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3))
node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92)
node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93)
node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12)
node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0))
node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82)
node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98)
node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100)
node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102)
node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0)
node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10)
node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12)
node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13)
node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10)
node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12)
node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13)
node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11)
node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13)
node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13)
node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15)
node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17)
node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2)
node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13)
node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15)
node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2)
node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17)
node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2)
node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2)
node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107)
node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108)
node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109)
node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110)
node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24)
node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28)
node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30)
node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113)
node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3))
node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115)
node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116)
node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30)
node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0))
node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120)
node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3))
node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122)
node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123)
node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21)
node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0))
node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127)
node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3))
node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129)
node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130)
node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12)
node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0))
node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119)
node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135)
node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137)
node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139)
node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0)
node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15)
node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17)
node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18)
node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15)
node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17)
node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18)
node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16)
node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18)
node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19)
node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21)
node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23)
node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3)
node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19)
node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21)
node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3)
node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23)
node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3)
node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3)
node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144)
node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145)
node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146)
node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147)
node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32)
node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36)
node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38)
node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150)
node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3))
node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152)
node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153)
node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30)
node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0))
node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157)
node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3))
node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159)
node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160)
node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21)
node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0))
node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164)
node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3))
node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166)
node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167)
node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12)
node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0))
node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156)
node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172)
node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174)
node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176)
node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0)
node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20)
node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22)
node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23)
node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20)
node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22)
node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23)
node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21)
node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23)
node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25)
node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27)
node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29)
node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4)
node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25)
node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27)
node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4)
node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29)
node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4)
node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4)
node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181)
node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182)
node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183)
node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184)
node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40)
node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44)
node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46)
node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187)
node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3))
node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189)
node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190)
node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30)
node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0))
node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194)
node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3))
node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196)
node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197)
node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21)
node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0))
node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201)
node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3))
node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203)
node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204)
node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12)
node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0))
node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193)
node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209)
node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211)
node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213)
node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0)
node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25)
node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27)
node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28)
node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25)
node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27)
node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28)
node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26)
node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28)
node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31)
node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33)
node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35)
node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5)
node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31)
node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33)
node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5)
node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35)
node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5)
node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5)
node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218)
node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219)
node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220)
node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221)
node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48)
node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52)
node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54)
node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224)
node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3))
node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226)
node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227)
node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30)
node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0))
node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231)
node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3))
node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233)
node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234)
node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21)
node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0))
node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238)
node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3))
node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240)
node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241)
node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12)
node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0))
node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230)
node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246)
node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248)
node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250)
node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0)
node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30)
node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32)
node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33)
node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30)
node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32)
node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33)
node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31)
node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33)
node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37)
node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39)
node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41)
node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6)
node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37)
node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39)
node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6)
node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41)
node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6)
node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6)
node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255)
node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256)
node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257)
node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258)
node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1)
node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29)
node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20)
node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11)
node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56)
node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60)
node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62)
node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261)
node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3))
node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263)
node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264)
node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30)
node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0))
node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268)
node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3))
node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270)
node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271)
node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21)
node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0))
node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275)
node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3))
node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277)
node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278)
node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12)
node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0))
node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267)
node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283)
node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3))
node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285)
node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287)
node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0)
node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35)
node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37)
node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38)
node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0))
node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35)
node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3))
node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37)
node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38)
node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0))
node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1))
node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000))
node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2))
node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36)
node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3))
node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38)
node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2)
node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43)
node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45)
node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47)
node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7)
node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2)
node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43)
node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3))
node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45)
node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7)
node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47)
node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7)
node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7)
node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292)
node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293)
node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294)
node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295)
node homogeneous = and(pmaHomogeneous, pmpHomogeneous)
connect io.requestor[0].resp.valid, resp_valid[0]
connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[0].resp.bits.ae_final, resp_ae_final
connect io.requestor[0].resp.bits.pf, resp_pf
connect io.requestor[0].resp.bits.gf, resp_gf
connect io.requestor[0].resp.bits.hr, resp_hr
connect io.requestor[0].resp.bits.hw, resp_hw
connect io.requestor[0].resp.bits.hx, resp_hx
connect io.requestor[0].resp.bits.pte, r_pte
connect io.requestor[0].resp.bits.level, max_count
node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T
node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T
connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1)
node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3)
node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6)
node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9)
node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7)
node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12)
node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14
node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T
connect io.requestor[0].ptbr, io.dpath.ptbr
connect io.requestor[0].hgatp, io.dpath.hgatp
connect io.requestor[0].vsatp, io.dpath.vsatp
connect io.requestor[0].customCSRs, io.dpath.customCSRs
connect io.requestor[0].status, io.dpath.status
connect io.requestor[0].hstatus, io.dpath.hstatus
connect io.requestor[0].gstatus, io.dpath.gstatus
connect io.requestor[0].pmp, io.dpath.pmp
connect io.requestor[1].resp.valid, resp_valid[1]
connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw
connect io.requestor[1].resp.bits.ae_final, resp_ae_final
connect io.requestor[1].resp.bits.pf, resp_pf
connect io.requestor[1].resp.bits.gf, resp_gf
connect io.requestor[1].resp.bits.hr, resp_hr
connect io.requestor[1].resp.bits.hw, resp_hw
connect io.requestor[1].resp.bits.hx, resp_hx
connect io.requestor[1].resp.bits.pte, r_pte
connect io.requestor[1].resp.bits.level, max_count
node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0))
connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T
node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0))
connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T
connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa
node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0))
node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1)
node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2))
node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3)
node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18)
node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6)
node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9)
node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9)
node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0))
node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0)
node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1))
node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7)
node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12)
node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff)
connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14
node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0))
connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T
connect io.requestor[1].ptbr, io.dpath.ptbr
connect io.requestor[1].hgatp, io.dpath.hgatp
connect io.requestor[1].vsatp, io.dpath.vsatp
connect io.requestor[1].customCSRs, io.dpath.customCSRs
connect io.requestor[1].status, io.dpath.status
connect io.requestor[1].hstatus, io.dpath.hstatus
connect io.requestor[1].gstatus, io.dpath.gstatus
connect io.requestor[1].pmp, io.dpath.pmp
wire next_state : UInt
connect next_state, state
inst state_barrier of OptimizationBarrier_UInt_7
connect state_barrier.clock, clock
connect state_barrier.reset, reset
connect state_barrier.io.x, next_state
connect state, state_barrier.io.y
wire do_switch : UInt<1>
connect do_switch, UInt<1>(0h0)
node _T_128 = eq(UInt<3>(0h0), state)
when _T_128 :
node _T_129 = and(arb.io.out.ready, arb.io.out.valid)
when _T_129 :
node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1)
node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0))
node satp_initial_count = tail(_satp_initial_count_T_2, 1)
node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1)
node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0))
node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1)
node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1)
node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0))
node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1)
node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr)
connect r_req, arb.io.out.bits.bits
connect r_req_dest, arb.io.chosen
node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0))
connect next_state, _next_state_T
connect stage2, arb.io.out.bits.bits.stage2
node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0))
node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T)
connect stage2_final, _stage2_final_T_1
node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count)
connect count, _count_T_3
node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0))
connect aux_count, _aux_count_T
connect aux_pte.ppn, aux_ppn
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect resp_ae_ptw, UInt<1>(0h0)
connect resp_ae_final, UInt<1>(0h0)
connect resp_pf, UInt<1>(0h0)
node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1)
node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0))
node resp_gf_count = tail(_resp_gf_count_T_2, 1)
node resp_gf_idxs_0 = shr(aux_ppn, 29)
wire _resp_gf_WIRE : UInt<15>[1]
connect _resp_gf_WIRE[0], resp_gf_idxs_0
node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0))
node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0))
node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2)
connect resp_gf, _resp_gf_T_2
connect resp_hr, UInt<1>(0h1)
connect resp_hw, UInt<1>(0h1)
connect resp_hx, UInt<1>(0h1)
connect resp_fragmented_superpage, UInt<1>(0h0)
connect r_hgatp, io.dpath.hgatp
node _T_130 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0))
node _T_131 = or(_T_130, arb.io.out.bits.bits.stage2)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
else :
node _T_135 = eq(UInt<3>(0h1), state)
when _T_135 :
node _T_136 = eq(count, r_hgatp_initial_count)
node _T_137 = and(stage2, _T_136)
when _T_137 :
node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2))
node _gpa_pgoff_T_1 = shl(r_req.addr, 3)
node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0))
connect gpa_pgoff, _gpa_pgoff_T_2
when stage2_pte_cache_hit :
node _aux_count_T_1 = add(aux_count, UInt<1>(0h1))
node _aux_count_T_2 = tail(_aux_count_T_1, 1)
connect aux_count, _aux_count_T_2
connect aux_pte.ppn, stage2_pte_cache_data
connect aux_pte.reserved_for_future, UInt<1>(0h0)
connect pte_hit, UInt<1>(0h1)
else :
when pte_cache_hit :
node _count_T_4 = add(count, UInt<1>(0h1))
node _count_T_5 = tail(_count_T_4, 1)
connect count, _count_T_5
connect pte_hit, UInt<1>(0h1)
else :
node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1))
connect next_state, _next_state_T_1
when resp_gf :
connect next_state, UInt<3>(0h0)
node _T_138 = or(r_req_dest, UInt<1>(0h0))
node _T_139 = bits(_T_138, 0, 0)
connect resp_valid[_T_139], UInt<1>(0h1)
else :
node _T_140 = eq(UInt<3>(0h2), state)
when _T_140 :
node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4))
connect next_state, _next_state_T_2
else :
node _T_141 = eq(UInt<3>(0h4), state)
when _T_141 :
connect next_state, UInt<3>(0h5)
node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2))
connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T
when io.mem.s2_xcpt.ae.ld :
connect resp_ae_ptw, UInt<1>(0h1)
connect next_state, UInt<3>(0h0)
node _T_142 = or(r_req_dest, UInt<1>(0h0))
node _T_143 = bits(_T_142, 0, 0)
connect resp_valid[_T_143], UInt<1>(0h1)
else :
node _T_144 = eq(UInt<3>(0h7), state)
when _T_144 :
connect next_state, UInt<3>(0h0)
node _T_145 = or(r_req_dest, UInt<1>(0h0))
node _T_146 = bits(_T_145, 0, 0)
connect resp_valid[_T_146], UInt<1>(0h1)
node _T_147 = eq(homogeneous, UInt<1>(0h0))
when _T_147 :
connect count, UInt<2>(0h2)
connect resp_fragmented_superpage, UInt<1>(0h1)
when do_both_stages :
connect resp_fragmented_superpage, UInt<1>(0h1)
node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1))
node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000))
node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2))
node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2)
node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3))
node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4)
node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18)
node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0)
node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1)
node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0)
node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3)
node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1))
node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0)
node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2))
node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1)
node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3))
node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3)
node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask)
wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect merged_pte, aux_pte
connect merged_pte.ppn, _merged_pte_T
node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T)
node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0))
node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2)
node _r_pte_T_4 = eq(state, UInt<3>(0h1))
node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit)
node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_1 = tail(_r_pte_count_T, 1)
node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0))
node r_pte_count = tail(_r_pte_count_T_2, 1)
node r_pte_idxs_0 = shr(stage2_pte_cache_data, 27)
wire r_pte_lsbs : UInt<2>
connect r_pte_lsbs, r_pte_idxs_0
wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte, l2_pte
node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs)
connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1
node _r_pte_T_6 = eq(state, UInt<3>(0h1))
node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit)
wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_1, l2_pte
connect r_pte_pte_1.ppn, pte_cache_data
node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1)
node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0))
node r_pte_count_1 = tail(_r_pte_count_T_5, 1)
node r_pte_idxs_0_1 = shr(pte.ppn, 27)
wire r_pte_lsbs_1 : UInt<2>
connect r_pte_lsbs_1, r_pte_idxs_0_1
wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_2, r_pte
node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2)
node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1)
connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3
node _r_pte_T_8 = eq(traverse, UInt<1>(0h0))
node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1)
node _r_pte_T_10 = and(_r_pte_T_9, stage2)
node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte)
node _r_pte_T_12 = eq(state, UInt<3>(0h7))
node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0))
node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13)
node _r_pte_T_15 = neq(count, UInt<2>(0h2))
node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15)
node _r_pte_T_17 = shr(r_pte.ppn, 18)
node _r_pte_T_18 = bits(r_req.addr, 17, 0)
node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18)
node _r_pte_T_20 = shr(r_pte.ppn, 9)
node _r_pte_T_21 = bits(r_req.addr, 8, 0)
node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21)
node _r_pte_truncIdx_T = or(count, UInt<1>(0h0))
node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0)
node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1))
node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19)
wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_3, r_pte
connect r_pte_pte_3.ppn, _r_pte_T_24
node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid)
node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3))
node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1)
node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0))
node r_pte_count_2 = tail(_r_pte_count_T_8, 1)
node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27)
wire r_pte_lsbs_2 : UInt<2>
connect r_pte_lsbs_2, r_pte_idxs_0_2
wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_4, r_pte
node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2)
node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2)
connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5
wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect r_pte_pte_5, r_pte
connect r_pte_pte_5.ppn, satp.ppn
node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5)
node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte)
node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27)
node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28)
node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29)
node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30)
node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31)
node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32)
inst r_pte_barrier of OptimizationBarrier_PTE_7
connect r_pte_barrier.clock, clock
connect r_pte_barrier.reset, reset
connect r_pte_barrier.io.x.v, _r_pte_T_33.v
connect r_pte_barrier.io.x.r, _r_pte_T_33.r
connect r_pte_barrier.io.x.w, _r_pte_T_33.w
connect r_pte_barrier.io.x.x, _r_pte_T_33.x
connect r_pte_barrier.io.x.u, _r_pte_T_33.u
connect r_pte_barrier.io.x.g, _r_pte_T_33.g
connect r_pte_barrier.io.x.a, _r_pte_T_33.a
connect r_pte_barrier.io.x.d, _r_pte_T_33.d
connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software
connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn
connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future
connect r_pte, r_pte_barrier.io.y
node _T_148 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_149 = and(UInt<1>(0h0), _T_148)
node _T_150 = eq(resp_gf, UInt<1>(0h0))
node _T_151 = and(_T_149, _T_150)
when _T_151 :
node _T_152 = eq(state, UInt<3>(0h1))
node _T_153 = eq(state, UInt<3>(0h2))
node _T_154 = or(_T_152, _T_153)
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_T_154, UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2
assert(clock, _T_154, UInt<1>(0h1), "") : assert_2
connect next_state, UInt<3>(0h0)
node _T_158 = or(r_req_dest, UInt<1>(0h0))
node _T_159 = bits(_T_158, 0, 0)
connect resp_valid[_T_159], UInt<1>(0h1)
connect count, UInt<2>(0h2)
when mem_resp_valid :
node _T_160 = eq(state, UInt<3>(0h5))
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3
assert(clock, _T_160, UInt<1>(0h1), "") : assert_3
connect next_state, UInt<3>(0h1)
when traverse :
node _T_164 = eq(stage2, UInt<1>(0h0))
node _T_165 = and(do_both_stages, _T_164)
when _T_165 :
connect do_switch, UInt<1>(0h1)
node _count_T_6 = add(count, UInt<1>(0h1))
node _count_T_7 = tail(_count_T_6, 1)
connect count, _count_T_7
else :
node _gf_T = eq(stage2_final, UInt<1>(0h0))
node _gf_T_1 = and(stage2, _gf_T)
node _gf_T_2 = eq(pte.w, UInt<1>(0h0))
node _gf_T_3 = and(pte.x, _gf_T_2)
node _gf_T_4 = or(pte.r, _gf_T_3)
node _gf_T_5 = and(pte.v, _gf_T_4)
node _gf_T_6 = and(_gf_T_5, pte.a)
node _gf_T_7 = and(_gf_T_6, pte.r)
node _gf_T_8 = and(_gf_T_7, pte.u)
node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0))
node _gf_T_10 = and(_gf_T_1, _gf_T_9)
node _gf_T_11 = eq(pte.w, UInt<1>(0h0))
node _gf_T_12 = and(pte.x, _gf_T_11)
node _gf_T_13 = or(pte.r, _gf_T_12)
node _gf_T_14 = and(pte.v, _gf_T_13)
node _gf_T_15 = and(_gf_T_14, pte.a)
node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _gf_T_17 = and(_gf_T_15, _gf_T_16)
node _gf_T_18 = and(_gf_T_17, invalid_gpa)
node gf = or(_gf_T_10, _gf_T_18)
node ae = and(pte.v, invalid_paddr)
node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0))
node pf = and(pte.v, _pf_T)
node _success_T = eq(ae, UInt<1>(0h0))
node _success_T_1 = and(pte.v, _success_T)
node _success_T_2 = eq(pf, UInt<1>(0h0))
node _success_T_3 = and(_success_T_1, _success_T_2)
node _success_T_4 = eq(gf, UInt<1>(0h0))
node success = and(_success_T_3, _success_T_4)
node _T_166 = eq(stage2_final, UInt<1>(0h0))
node _T_167 = and(do_both_stages, _T_166)
node _T_168 = and(_T_167, success)
when _T_168 :
when stage2 :
connect stage2, UInt<1>(0h0)
connect count, aux_count
else :
connect stage2_final, UInt<1>(0h1)
connect do_switch, UInt<1>(0h1)
else :
node _l2_refill_T = eq(count, UInt<2>(0h2))
node _l2_refill_T_1 = and(success, _l2_refill_T)
node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0))
node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2)
node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0))
node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0))
node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5)
node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2))
node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7)
node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9)
node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10)
node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11)
node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a)
node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w)
node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d)
node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u)
node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0))
node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17)
node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18)
node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19)
node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a)
node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x)
node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u)
node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23)
node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24)
node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25)
node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26)
connect l2_refill, _l2_refill_T_27
connect count, max_count
node _T_169 = eq(count, UInt<2>(0h2))
node _T_170 = eq(do_both_stages, UInt<1>(0h0))
node _T_171 = eq(aux_count, UInt<2>(0h2))
node _T_172 = or(_T_170, _T_171)
node _T_173 = and(_T_169, _T_172)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = and(UInt<1>(0h0), _T_174)
when _T_175 :
connect next_state, UInt<3>(0h7)
else :
connect next_state, UInt<3>(0h0)
node _T_176 = or(r_req_dest, UInt<1>(0h0))
node _T_177 = bits(_T_176, 0, 0)
connect resp_valid[_T_177], UInt<1>(0h1)
node _resp_ae_ptw_T = lt(count, UInt<2>(0h2))
node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T)
node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0))
node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2)
node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4)
node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0))
node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6)
node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0))
node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8)
node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0))
node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10)
node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0))
node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12)
node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14)
node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15)
connect resp_ae_ptw, _resp_ae_ptw_T_16
node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0))
node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T)
node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1)
node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2)
node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a)
node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4)
connect resp_ae_final, _resp_ae_final_T_5
node _resp_pf_T = eq(stage2, UInt<1>(0h0))
node _resp_pf_T_1 = and(pf, _resp_pf_T)
connect resp_pf, _resp_pf_T_1
node _resp_gf_T_3 = and(pf, stage2)
node _resp_gf_T_4 = or(gf, _resp_gf_T_3)
connect resp_gf, _resp_gf_T_4
node _resp_hr_T = eq(stage2, UInt<1>(0h0))
node _resp_hr_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hr_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2)
node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4)
node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5)
node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6)
node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a)
node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r)
node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u)
node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10)
node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11)
connect resp_hr, _resp_hr_T_12
node _resp_hw_T = eq(stage2, UInt<1>(0h0))
node _resp_hw_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hw_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2)
node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4)
node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5)
node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6)
node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a)
node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w)
node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d)
node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u)
node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11)
node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12)
connect resp_hw, _resp_hw_T_13
node _resp_hx_T = eq(stage2, UInt<1>(0h0))
node _resp_hx_T_1 = eq(pf, UInt<1>(0h0))
node _resp_hx_T_2 = eq(gf, UInt<1>(0h0))
node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2)
node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0))
node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4)
node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5)
node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6)
node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a)
node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x)
node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u)
node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10)
node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11)
connect resp_hx, _resp_hx_T_12
when io.mem.s2_nack :
node _T_178 = eq(state, UInt<3>(0h4))
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4
assert(clock, _T_178, UInt<1>(0h1), "") : assert_4
connect next_state, UInt<3>(0h1)
when do_switch :
node _aux_count_T_3 = add(count, UInt<1>(0h1))
node _aux_count_T_4 = tail(_aux_count_T_3, 1)
node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count)
connect aux_count, _aux_count_T_5
connect count, r_hgatp_initial_count
node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18)
node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0)
node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1)
node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9)
node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0)
node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3)
node _aux_pte_T = eq(count, UInt<1>(0h1))
node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0)
node _aux_pte_T_2 = eq(count, UInt<2>(0h2))
node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1)
node _aux_pte_T_4 = eq(count, UInt<2>(0h3))
node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3)
wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}
connect aux_pte_pte, pte
connect aux_pte_pte.ppn, _aux_pte_T_5
node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte)
connect aux_pte, _aux_pte_T_6
connect stage2, UInt<1>(0h1)
node _leaf_T = eq(traverse, UInt<1>(0h0))
node _leaf_T_1 = and(mem_resp_valid, _leaf_T)
node _leaf_T_2 = eq(count, UInt<1>(0h0))
node leaf = and(_leaf_T_1, _leaf_T_2)
node _T_182 = and(leaf, pte.v)
node _T_183 = eq(invalid_paddr, UInt<1>(0h0))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(invalid_gpa, UInt<1>(0h0))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = and(leaf, pte.v)
node _T_190 = and(_T_189, invalid_paddr)
node _T_191 = and(leaf, pte.v)
node _T_192 = and(_T_191, invalid_gpa)
node _T_193 = and(leaf, pte.v)
node _T_194 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_195 = and(_T_193, _T_194)
node _T_196 = bits(mem_resp_data, 0, 0)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = and(leaf, _T_197)
node _T_199 = eq(pte.v, UInt<1>(0h0))
node _T_200 = and(leaf, _T_199)
node _T_201 = bits(mem_resp_data, 0, 0)
node _T_202 = and(_T_200, _T_201)
node _leaf_T_3 = eq(traverse, UInt<1>(0h0))
node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3)
node _leaf_T_5 = eq(count, UInt<1>(0h1))
node leaf_1 = and(_leaf_T_4, _leaf_T_5)
node _T_203 = and(leaf_1, pte.v)
node _T_204 = eq(invalid_paddr, UInt<1>(0h0))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(invalid_gpa, UInt<1>(0h0))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_209 = and(_T_207, _T_208)
node _T_210 = and(leaf_1, pte.v)
node _T_211 = and(_T_210, invalid_paddr)
node _T_212 = and(leaf_1, pte.v)
node _T_213 = and(_T_212, invalid_gpa)
node _T_214 = and(leaf_1, pte.v)
node _T_215 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_216 = and(_T_214, _T_215)
node _T_217 = bits(mem_resp_data, 0, 0)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = and(leaf_1, _T_218)
node _T_220 = eq(pte.v, UInt<1>(0h0))
node _T_221 = and(leaf_1, _T_220)
node _T_222 = bits(mem_resp_data, 0, 0)
node _T_223 = and(_T_221, _T_222)
node _leaf_T_6 = eq(traverse, UInt<1>(0h0))
node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6)
node _leaf_T_8 = eq(count, UInt<2>(0h2))
node leaf_2 = and(_leaf_T_7, _leaf_T_8)
node _T_224 = and(leaf_2, pte.v)
node _T_225 = eq(invalid_paddr, UInt<1>(0h0))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(invalid_gpa, UInt<1>(0h0))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_230 = and(_T_228, _T_229)
node _T_231 = and(leaf_2, pte.v)
node _T_232 = and(_T_231, invalid_paddr)
node _T_233 = and(leaf_2, pte.v)
node _T_234 = and(_T_233, invalid_gpa)
node _T_235 = and(leaf_2, pte.v)
node _T_236 = neq(pte.reserved_for_future, UInt<1>(0h0))
node _T_237 = and(_T_235, _T_236)
node _T_238 = bits(mem_resp_data, 0, 0)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = and(leaf_2, _T_239)
node _T_241 = eq(count, UInt<2>(0h2))
node _T_242 = and(mem_resp_valid, _T_241)
node _T_243 = eq(pte.r, UInt<1>(0h0))
node _T_244 = and(pte.v, _T_243)
node _T_245 = eq(pte.w, UInt<1>(0h0))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(pte.x, UInt<1>(0h0))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(pte.d, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(pte.a, UInt<1>(0h0))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(pte.u, UInt<1>(0h0))
node _T_254 = and(_T_252, _T_253)
node _T_255 = eq(pte.reserved_for_future, UInt<1>(0h0))
node _T_256 = and(_T_254, _T_255)
node _T_257 = and(_T_242, _T_256)
node _T_258 = eq(state, UInt<3>(0h4))
node _T_259 = and(_T_258, io.mem.s2_xcpt.ae.ld) | module PTW_7( // @[PTW.scala:219:7]
input clock, // @[PTW.scala:219:7]
input reset, // @[PTW.scala:219:7]
output io_requestor_0_req_ready, // @[PTW.scala:220:14]
input io_requestor_0_req_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_0_resp_valid, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14]
output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_0_status_debug, // @[PTW.scala:220:14]
output io_requestor_0_status_cease, // @[PTW.scala:220:14]
output io_requestor_0_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14]
output io_requestor_0_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14]
output io_requestor_0_status_v, // @[PTW.scala:220:14]
output io_requestor_0_status_sd, // @[PTW.scala:220:14]
output io_requestor_0_status_mpv, // @[PTW.scala:220:14]
output io_requestor_0_status_gva, // @[PTW.scala:220:14]
output io_requestor_0_status_tsr, // @[PTW.scala:220:14]
output io_requestor_0_status_tw, // @[PTW.scala:220:14]
output io_requestor_0_status_tvm, // @[PTW.scala:220:14]
output io_requestor_0_status_mxr, // @[PTW.scala:220:14]
output io_requestor_0_status_sum, // @[PTW.scala:220:14]
output io_requestor_0_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14]
output io_requestor_0_status_spp, // @[PTW.scala:220:14]
output io_requestor_0_status_mpie, // @[PTW.scala:220:14]
output io_requestor_0_status_spie, // @[PTW.scala:220:14]
output io_requestor_0_status_mie, // @[PTW.scala:220:14]
output io_requestor_0_status_sie, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14]
output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14]
output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_requestor_1_req_ready, // @[PTW.scala:220:14]
input io_requestor_1_req_valid, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_valid, // @[PTW.scala:220:14]
input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14]
input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14]
output io_requestor_1_resp_valid, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14]
output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14]
output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14]
output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14]
output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14]
output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14]
output io_requestor_1_status_debug, // @[PTW.scala:220:14]
output io_requestor_1_status_cease, // @[PTW.scala:220:14]
output io_requestor_1_status_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14]
output io_requestor_1_status_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14]
output io_requestor_1_status_v, // @[PTW.scala:220:14]
output io_requestor_1_status_sd, // @[PTW.scala:220:14]
output io_requestor_1_status_mpv, // @[PTW.scala:220:14]
output io_requestor_1_status_gva, // @[PTW.scala:220:14]
output io_requestor_1_status_tsr, // @[PTW.scala:220:14]
output io_requestor_1_status_tw, // @[PTW.scala:220:14]
output io_requestor_1_status_tvm, // @[PTW.scala:220:14]
output io_requestor_1_status_mxr, // @[PTW.scala:220:14]
output io_requestor_1_status_sum, // @[PTW.scala:220:14]
output io_requestor_1_status_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14]
output io_requestor_1_status_spp, // @[PTW.scala:220:14]
output io_requestor_1_status_mpie, // @[PTW.scala:220:14]
output io_requestor_1_status_spie, // @[PTW.scala:220:14]
output io_requestor_1_status_mie, // @[PTW.scala:220:14]
output io_requestor_1_status_sie, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14]
output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_v, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sd, // @[PTW.scala:220:14]
output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14]
output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14]
output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14]
output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14]
output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14]
output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14]
output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
input io_mem_req_ready, // @[PTW.scala:220:14]
output io_mem_req_valid, // @[PTW.scala:220:14]
output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14]
output io_mem_req_bits_dv, // @[PTW.scala:220:14]
output io_mem_s1_kill, // @[PTW.scala:220:14]
input io_mem_s2_nack, // @[PTW.scala:220:14]
input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14]
input io_mem_s2_uncached, // @[PTW.scala:220:14]
input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14]
input io_mem_resp_valid, // @[PTW.scala:220:14]
input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14]
input [6:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14]
input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14]
input io_mem_resp_bits_signed, // @[PTW.scala:220:14]
input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14]
input io_mem_resp_bits_dv, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14]
input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14]
input io_mem_resp_bits_replay, // @[PTW.scala:220:14]
input io_mem_resp_bits_has_data, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14]
input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14]
input io_mem_replay_next, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14]
input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14]
input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14]
input io_mem_ordered, // @[PTW.scala:220:14]
input io_mem_store_pending, // @[PTW.scala:220:14]
input io_mem_perf_acquire, // @[PTW.scala:220:14]
input io_mem_perf_release, // @[PTW.scala:220:14]
input io_mem_perf_grant, // @[PTW.scala:220:14]
input io_mem_perf_tlbMiss, // @[PTW.scala:220:14]
input io_mem_perf_blocked, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14]
input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14]
input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14]
input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14]
input io_dpath_sfence_valid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14]
input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14]
input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14]
input io_dpath_status_debug, // @[PTW.scala:220:14]
input io_dpath_status_cease, // @[PTW.scala:220:14]
input io_dpath_status_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14]
input io_dpath_status_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14]
input io_dpath_status_v, // @[PTW.scala:220:14]
input io_dpath_status_sd, // @[PTW.scala:220:14]
input io_dpath_status_mpv, // @[PTW.scala:220:14]
input io_dpath_status_gva, // @[PTW.scala:220:14]
input io_dpath_status_tsr, // @[PTW.scala:220:14]
input io_dpath_status_tw, // @[PTW.scala:220:14]
input io_dpath_status_tvm, // @[PTW.scala:220:14]
input io_dpath_status_mxr, // @[PTW.scala:220:14]
input io_dpath_status_sum, // @[PTW.scala:220:14]
input io_dpath_status_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14]
input io_dpath_status_spp, // @[PTW.scala:220:14]
input io_dpath_status_mpie, // @[PTW.scala:220:14]
input io_dpath_status_spie, // @[PTW.scala:220:14]
input io_dpath_status_mie, // @[PTW.scala:220:14]
input io_dpath_status_sie, // @[PTW.scala:220:14]
input io_dpath_hstatus_spvp, // @[PTW.scala:220:14]
input io_dpath_hstatus_spv, // @[PTW.scala:220:14]
input io_dpath_hstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_debug, // @[PTW.scala:220:14]
input io_dpath_gstatus_cease, // @[PTW.scala:220:14]
input io_dpath_gstatus_wfi, // @[PTW.scala:220:14]
input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14]
input io_dpath_gstatus_dv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14]
input io_dpath_gstatus_v, // @[PTW.scala:220:14]
input io_dpath_gstatus_sd, // @[PTW.scala:220:14]
input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpv, // @[PTW.scala:220:14]
input io_dpath_gstatus_gva, // @[PTW.scala:220:14]
input io_dpath_gstatus_mbe, // @[PTW.scala:220:14]
input io_dpath_gstatus_sbe, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14]
input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14]
input io_dpath_gstatus_tsr, // @[PTW.scala:220:14]
input io_dpath_gstatus_tw, // @[PTW.scala:220:14]
input io_dpath_gstatus_tvm, // @[PTW.scala:220:14]
input io_dpath_gstatus_mxr, // @[PTW.scala:220:14]
input io_dpath_gstatus_sum, // @[PTW.scala:220:14]
input io_dpath_gstatus_mprv, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14]
input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14]
input io_dpath_gstatus_spp, // @[PTW.scala:220:14]
input io_dpath_gstatus_mpie, // @[PTW.scala:220:14]
input io_dpath_gstatus_ube, // @[PTW.scala:220:14]
input io_dpath_gstatus_spie, // @[PTW.scala:220:14]
input io_dpath_gstatus_upie, // @[PTW.scala:220:14]
input io_dpath_gstatus_mie, // @[PTW.scala:220:14]
input io_dpath_gstatus_hie, // @[PTW.scala:220:14]
input io_dpath_gstatus_sie, // @[PTW.scala:220:14]
input io_dpath_gstatus_uie, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14]
input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14]
input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14]
input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14]
input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14]
output io_dpath_perf_pte_miss, // @[PTW.scala:220:14]
output io_dpath_perf_pte_hit, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14]
input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14]
input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14]
output io_dpath_clock_enabled // @[PTW.scala:220:14]
);
wire tmp_r; // @[PTW.scala:304:37]
wire tmp_w; // @[PTW.scala:304:37]
wire tmp_x; // @[PTW.scala:304:37]
wire tmp_u; // @[PTW.scala:304:37]
wire tmp_g; // @[PTW.scala:304:37]
wire tmp_a; // @[PTW.scala:304:37]
wire tmp_d; // @[PTW.scala:304:37]
wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37]
wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37]
wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25]
wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25]
wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_d; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_a; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_g; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_u; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_x; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_w; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_r; // @[package.scala:267:25]
wire _r_pte_barrier_io_y_v; // @[package.scala:267:25]
wire [2:0] _state_barrier_io_y; // @[package.scala:267:25]
wire _arb_io_out_valid; // @[PTW.scala:236:19]
wire _arb_io_out_bits_valid; // @[PTW.scala:236:19]
wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19]
wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19]
wire _arb_io_chosen; // @[PTW.scala:236:19]
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_valid_0 = io_requestor_1_req_bits_valid; // @[PTW.scala:219:7]
wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7]
wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7]
wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7]
wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7]
wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7]
wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7]
wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7]
wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7]
wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7]
wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7]
wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7]
wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7]
wire io_dpath_status_sd_0 = io_dpath_status_sd; // @[PTW.scala:219:7]
wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7]
wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7]
wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7]
wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7]
wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7]
wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7]
wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7]
wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7]
wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7]
wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7]
wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7]
wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7]
wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7]
wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7]
wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7]
wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7]
wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7]
wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_0 = io_dpath_gstatus_sd; // @[PTW.scala:219:7]
wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7]
wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7]
wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7]
wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7]
wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7]
wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7]
wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7]
wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7]
wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7]
wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7]
wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7]
wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35]
wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35]
wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27]
wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27]
wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20]
wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24]
wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43]
wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13]
wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17]
wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62]
wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17]
wire l2_pte_d = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_a = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_g = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_u = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_x = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_w = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_r = 1'h0; // @[PTW.scala:403:113]
wire l2_pte_v = 1'h0; // @[PTW.scala:403:113]
wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40]
wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32]
wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40]
wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81]
wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53]
wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71]
wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16]
wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29]
wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25]
wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58]
wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26]
wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26]
wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26]
wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7]
wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17]
wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7]
wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27]
wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18]
wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7]
wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113]
wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26]
wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19]
wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7]
wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7]
wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27]
wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43]
wire [1:0] io_requestor_0_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_xs = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7]
wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42]
wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58]
wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44]
wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27]
wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13]
wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62]
wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113]
wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40]
wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45]
wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61]
wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46]
wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62]
wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46]
wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62]
wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27]
wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27]
wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28]
wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44]
wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40]
wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27]
wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26]
wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26]
wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28]
wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44]
wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27]
wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7]
wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40]
wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7]
wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7]
wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7]
wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7]
wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7]
wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33]
wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16]
wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33]
wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7]
wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16]
wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60]
wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28]
wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56]
wire _r_pte_T = 1'h1; // @[PTW.scala:670:19]
wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30]
wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58]
wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42]
wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58]
wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13]
wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45]
wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61]
wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46]
wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62]
wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46]
wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62]
wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28]
wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44]
wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44]
wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28]
wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44]
wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73]
wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58]
wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7]
wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7]
wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7]
wire [6:0] io_mem_req_bits_tag = 7'h0; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7]
wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7]
wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113]
wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26]
wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26]
wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48]
wire [39:0] tag_1 = 40'h8000000000; // @[PTW.scala:363:18]
wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23]
wire [38:0] _tag_T = 39'h0; // @[package.scala:138:15]
wire [1:0] max_count; // @[PTW.scala:289:25]
wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58]
wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45]
wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39]
wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40]
wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51]
wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7]
wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17]
wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7]
wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17]
wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sd_0 = io_dpath_status_sd_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7]
wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sd_0 = io_dpath_gstatus_sd_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7]
wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7]
wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57]
wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7]
wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7]
wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39]
wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7]
wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7]
wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7]
wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7]
wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7]
wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7]
wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7]
wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7]
wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7]
wire io_mem_req_valid_0; // @[PTW.scala:219:7]
wire io_mem_s1_kill_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7]
wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7]
wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7]
reg [2:0] state; // @[PTW.scala:233:22]
wire l2_refill_wire; // @[PTW.scala:234:28]
wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30]
wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46]
wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}]
reg resp_valid_0; // @[PTW.scala:242:27]
assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27]
reg resp_valid_1; // @[PTW.scala:242:27]
assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27]
wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24]
wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}]
wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}]
wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}]
wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61]
wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61]
assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39]
assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39]
reg invalidated; // @[PTW.scala:251:24]
reg [1:0] count; // @[PTW.scala:259:18]
wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21]
reg resp_ae_ptw; // @[PTW.scala:260:24]
assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24]
reg resp_ae_final; // @[PTW.scala:261:26]
assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26]
reg resp_pf; // @[PTW.scala:262:20]
assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20]
reg resp_gf; // @[PTW.scala:263:20]
assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20]
reg resp_hr; // @[PTW.scala:264:20]
assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20]
reg resp_hw; // @[PTW.scala:265:20]
assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20]
reg resp_hx; // @[PTW.scala:266:20]
assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20]
reg resp_fragmented_superpage; // @[PTW.scala:267:38]
reg [26:0] r_req_addr; // @[PTW.scala:270:18]
reg r_req_need_gpa; // @[PTW.scala:270:18]
assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18]
reg r_req_vstage1; // @[PTW.scala:270:18]
reg r_req_stage2; // @[PTW.scala:270:18]
reg r_req_dest; // @[PTW.scala:272:23]
reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18]
wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26]
wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26]
reg [43:0] r_pte_ppn; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18]
reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18]
wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26]
wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26]
reg r_pte_d; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26]
reg r_pte_a; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26]
reg r_pte_g; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26]
reg r_pte_u; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26]
reg r_pte_x; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26]
reg r_pte_w; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26]
reg r_pte_r; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26]
reg r_pte_v; // @[PTW.scala:275:18]
assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18]
wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26]
wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26]
reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20]
reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20]
reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20]
reg [1:0] aux_count; // @[PTW.scala:278:22]
wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21]
reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20]
wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26]
reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20]
reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20]
wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26]
reg aux_pte_d; // @[PTW.scala:280:20]
wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26]
reg aux_pte_a; // @[PTW.scala:280:20]
wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26]
reg aux_pte_g; // @[PTW.scala:280:20]
wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26]
reg aux_pte_u; // @[PTW.scala:280:20]
wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26]
reg aux_pte_x; // @[PTW.scala:280:20]
wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26]
reg aux_pte_w; // @[PTW.scala:280:20]
wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26]
reg aux_pte_r; // @[PTW.scala:280:20]
wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26]
reg aux_pte_v; // @[PTW.scala:280:20]
wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26]
reg [11:0] gpa_pgoff; // @[PTW.scala:281:22]
reg stage2; // @[PTW.scala:282:19]
reg stage2_final; // @[PTW.scala:283:25]
wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26]
wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38]
wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25]
assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25]
assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25]
wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31]
wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}]
wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12]
reg mem_resp_valid; // @[PTW.scala:292:31]
reg [63:0] mem_resp_data; // @[PTW.scala:293:30]
wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37]
wire [9:0] _tmp_T_10; // @[PTW.scala:304:37]
wire [43:0] _tmp_T_9; // @[PTW.scala:304:37]
wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26]
wire [1:0] _tmp_T_8; // @[PTW.scala:304:37]
wire _tmp_T_7; // @[PTW.scala:304:37]
wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_6; // @[PTW.scala:304:37]
wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_5; // @[PTW.scala:304:37]
wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_4; // @[PTW.scala:304:37]
wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_3; // @[PTW.scala:304:37]
wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_2; // @[PTW.scala:304:37]
wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26]
wire _tmp_T_1; // @[PTW.scala:304:37]
wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26]
wire _tmp_T; // @[PTW.scala:304:37]
wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26]
wire [43:0] tmp_ppn; // @[PTW.scala:304:37]
wire tmp_v; // @[PTW.scala:304:37]
assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37]
assign tmp_v = _tmp_T; // @[PTW.scala:304:37]
assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37]
assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37]
assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37]
assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37]
assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37]
assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37]
assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37]
assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37]
assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37]
assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37]
assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37]
assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37]
assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37]
assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37]
assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37]
assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37]
assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37]
assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37]
assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37]
assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37]
wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26]
wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26]
wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26]
wire [43:0] pte_ppn; // @[PTW.scala:305:26]
wire pte_v; // @[PTW.scala:305:26]
wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26]
wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38]
wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}]
wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54]
wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99]
wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}]
assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}]
assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}]
wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}]
wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58]
wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25]
wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26]
wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}]
wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}]
wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}]
wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}]
wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}]
wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}]
wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33]
wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}]
wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51]
wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}]
wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73]
wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}]
wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}]
wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12]
wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}]
wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}]
wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40]
wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}]
wire _T_46 = count == 2'h1; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T = _T_46; // @[package.scala:39:86]
wire _pmaHomogeneous_T; // @[package.scala:39:86]
assign _pmaHomogeneous_T = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_23; // @[package.scala:39:86]
assign _pmpHomogeneous_T_23 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_60; // @[package.scala:39:86]
assign _pmpHomogeneous_T_60 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_5 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_97; // @[package.scala:39:86]
assign _pmpHomogeneous_T_97 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_10 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_134; // @[package.scala:39:86]
assign _pmpHomogeneous_T_134 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_15 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_171; // @[package.scala:39:86]
assign _pmpHomogeneous_T_171 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_20 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_208; // @[package.scala:39:86]
assign _pmpHomogeneous_T_208 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_25 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_245; // @[package.scala:39:86]
assign _pmpHomogeneous_T_245 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_30 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_T_282; // @[package.scala:39:86]
assign _pmpHomogeneous_T_282 = _T_46; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_35 = _T_46; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T = _T_46; // @[package.scala:39:86]
wire _aux_pte_T; // @[package.scala:39:86]
assign _aux_pte_T = _T_46; // @[package.scala:39:86]
wire _leaf_T_5; // @[PTW.scala:751:53]
assign _leaf_T_5 = _T_46; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}]
wire _T_241 = count == 2'h2; // @[package.scala:39:86]
wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86]
assign _pte_addr_vpn_idx_T_2 = _T_241; // @[package.scala:39:86]
wire _pmaHomogeneous_T_2; // @[package.scala:39:86]
assign _pmaHomogeneous_T_2 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_25; // @[package.scala:39:86]
assign _pmpHomogeneous_T_25 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_2 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_62; // @[package.scala:39:86]
assign _pmpHomogeneous_T_62 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_7 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_99; // @[package.scala:39:86]
assign _pmpHomogeneous_T_99 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_12 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_136; // @[package.scala:39:86]
assign _pmpHomogeneous_T_136 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_17 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_173; // @[package.scala:39:86]
assign _pmpHomogeneous_T_173 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_22 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_210; // @[package.scala:39:86]
assign _pmpHomogeneous_T_210 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_27 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_247; // @[package.scala:39:86]
assign _pmpHomogeneous_T_247 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_32 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86]
assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_T_284; // @[package.scala:39:86]
assign _pmpHomogeneous_T_284 = _T_241; // @[package.scala:39:86]
wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86]
assign _pmpHomogeneous_pgMask_T_37 = _T_241; // @[package.scala:39:86]
wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86]
assign _merged_pte_stage1_ppn_T_2 = _T_241; // @[package.scala:39:86]
wire _l2_refill_T; // @[PTW.scala:713:39]
assign _l2_refill_T = _T_241; // @[package.scala:39:86]
wire _aux_pte_T_2; // @[package.scala:39:86]
assign _aux_pte_T_2 = _T_241; // @[package.scala:39:86]
wire _leaf_T_8; // @[PTW.scala:751:53]
assign _leaf_T_8 = _T_241; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}]
wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86]
wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}]
wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76]
wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36]
wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}]
wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}]
wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23]
reg [6:0] state_reg; // @[Replacement.scala:168:70]
reg [7:0] valid; // @[PTW.scala:352:24]
reg [31:0] tags_0; // @[PTW.scala:353:19]
reg [31:0] tags_1; // @[PTW.scala:353:19]
reg [31:0] tags_2; // @[PTW.scala:353:19]
reg [31:0] tags_3; // @[PTW.scala:353:19]
reg [31:0] tags_4; // @[PTW.scala:353:19]
reg [31:0] tags_5; // @[PTW.scala:353:19]
reg [31:0] tags_6; // @[PTW.scala:353:19]
reg [31:0] tags_7; // @[PTW.scala:353:19]
reg [19:0] data_0; // @[PTW.scala:355:19]
reg [19:0] data_1; // @[PTW.scala:355:19]
reg [19:0] data_2; // @[PTW.scala:355:19]
reg [19:0] data_3; // @[PTW.scala:355:19]
reg [19:0] data_4; // @[PTW.scala:355:19]
reg [19:0] data_5; // @[PTW.scala:355:19]
reg [19:0] data_6; // @[PTW.scala:355:19]
reg [19:0] data_7; // @[PTW.scala:355:19]
wire _can_hit_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :358:18]
wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65]
wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}]
wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}]
wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15]
wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27]
wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27]
wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27]
wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27]
wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27]
wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27]
wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27]
wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27]
wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20]
wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}]
wire _r_T = &valid; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13]
wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13]
wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13]
wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57]
wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45]
wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45]
wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45]
wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45]
wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45]
wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45]
wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45]
wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45]
wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13]
wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13]
wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13]
wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13]
wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13]
wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire _T_152 = state == 3'h1; // @[PTW.scala:233:22, :377:24]
wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46]
assign _io_dpath_perf_pte_hit_T = _T_152; // @[PTW.scala:377:24, :394:46]
wire _io_mem_req_valid_T; // @[PTW.scala:515:29]
assign _io_mem_req_valid_T = _T_152; // @[PTW.scala:377:24, :515:29]
wire _r_pte_T_4; // @[PTW.scala:672:15]
assign _r_pte_T_4 = _T_152; // @[PTW.scala:377:24, :672:15]
wire _r_pte_T_6; // @[PTW.scala:674:15]
assign _r_pte_T_6 = _T_152; // @[PTW.scala:377:24, :674:15]
wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18]
wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18]
wire [3:0] _T_30 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_1 = _T_30[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_1 = _T_30[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13]
wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13]
wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13]
wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13]
wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13]
wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13]
wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16]
wire _leaf_T_2 = ~(|count); // @[PTW.scala:259:18, :324:40, :382:47, :751:53]
wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36]
reg [6:0] state_reg_1; // @[Replacement.scala:168:70]
reg [7:0] valid_1; // @[PTW.scala:352:24]
reg [19:0] data_1_0; // @[PTW.scala:355:19]
reg [19:0] data_1_1; // @[PTW.scala:355:19]
reg [19:0] data_1_2; // @[PTW.scala:355:19]
reg [19:0] data_1_3; // @[PTW.scala:355:19]
reg [19:0] data_1_4; // @[PTW.scala:355:19]
reg [19:0] data_1_5; // @[PTW.scala:355:19]
reg [19:0] data_1_6; // @[PTW.scala:355:19]
reg [19:0] data_1_7; // @[PTW.scala:355:19]
wire _can_hit_T_3 = ~(|count); // @[PTW.scala:259:18, :324:40, :357:21]
wire _can_hit_T_4 = ~(aux_count[1]); // @[PTW.scala:278:22, :357:60]
wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}]
wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}]
wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}]
wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107]
wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}]
wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33]
wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}]
wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44]
wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}]
wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25]
wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38]
wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13]
wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38]
wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13]
wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13]
wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12]
wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38]
wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13]
wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13]
wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38]
wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12]
wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57]
wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45]
wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45]
wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45]
wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45]
wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45]
wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45]
wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45]
wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45]
wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45]
wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45]
wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45]
wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45]
wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45]
wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45]
wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70]
wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13]
wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35]
wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35]
wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13]
wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13]
wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13]
wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13]
wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13]
wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13]
wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13]
wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13]
wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13]
wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13]
wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12]
wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13]
wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13]
wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38]
wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16]
wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12]
wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16]
wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16]
wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16]
reg pte_hit; // @[PTW.scala:392:24]
wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}]
assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}]
assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57]
reg l2_refill; // @[PTW.scala:398:26]
assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26]
wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65]
wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}]
wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}]
wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48]
assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}]
assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39]
assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24]
wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43]
assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}]
assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40]
wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38]
wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}]
assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}]
assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51]
wire [55:0] _GEN = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96]
wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_7 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
assign _pmaPgLevelHomogeneous_T_37 = _GEN; // @[PTW.scala:544:96]
wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80]
assign _pmpHomogeneous_T = _GEN; // @[PTW.scala:544:96, :548:80]
wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65]
wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}]
wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65]
wire [55:0] _GEN_0 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_43 = _GEN_0; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_110 = _GEN_0; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_48 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_98 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_115 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_147 = _GEN_1; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_154 = _GEN_1; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_68 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_120 = _GEN_2; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_135 = _GEN_2; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96]
wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96]
wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_83 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_125 = _GEN_3; // @[Parameters.scala:137:31]
wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31]
assign _pmaPgLevelHomogeneous_T_140 = _GEN_3; // @[Parameters.scala:137:31]
wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65]
wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65]
wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65]
wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66]
wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66]
wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}]
wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}]
wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46]
wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}]
wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66]
wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}]
wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}]
wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86]
wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_4 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_2 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_9 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_16 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_4; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76]
wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}]
wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21]
wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_5 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T = _GEN_5; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_5; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62]
wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_6 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_39 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_46 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_53 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76]
wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_7; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_7; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_8 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_76 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_83 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_90 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_8; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76]
wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_9; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_9; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_10 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_113 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_120 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_127 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_10; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76]
wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_11; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_11; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_12 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_150 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_157 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_164 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_12; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76]
wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_13; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_13; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_14 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_187 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_194 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_201 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_14; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76]
wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_15; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_15; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_16 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_224 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_231 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_238 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76]
wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_17; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_17; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10]
wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86]
wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}]
wire [31:0] _GEN_18 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7]
wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_261 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_268 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36]
assign _pmpHomogeneous_T_275 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36]
assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36]
assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_18; // @[PMP.scala:60:36]
wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80]
wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80]
wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}]
wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}]
wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80]
wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}]
wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}]
wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86]
wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76]
wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7]
wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}]
wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80]
wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}]
wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}]
wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}]
wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86]
wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}]
wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76]
wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30]
assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_19; // @[PMP.scala:110:30]
wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30]
assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_19; // @[PMP.scala:110:30, :111:30]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}]
wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76]
wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}]
wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21]
wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62]
wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}]
wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}]
wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}]
wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10]
wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76]
assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58]
assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _T_171 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60]
wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60]
wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60]
assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60]
wire _gpa_pgoff_T; // @[PTW.scala:615:36]
assign _gpa_pgoff_T = _T_171; // @[PTW.scala:566:60, :615:36]
wire _l2_refill_T_7; // @[PTW.scala:715:40]
assign _l2_refill_T_7 = _T_171; // @[PTW.scala:566:60, :715:40]
wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49]
wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79]
wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49]
wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79]
wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58]
wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15]
wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32]
wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}]
wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}]
wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}]
wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76]
wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}]
assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10]
assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45]
assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45]
wire [2:0] next_state; // @[PTW.scala:579:31]
wire do_switch; // @[PTW.scala:581:30]
wire _T_129 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire _GEN_20 = ~(|state) & _T_129; // @[Decoupled.scala:51:35]
wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38]
wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26]
wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58]
wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40]
wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40]
wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67]
wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}]
wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32]
wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32]
wire [2:0] _GEN_21 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24]
wire [2:0] _count_T_4; // @[PTW.scala:624:24]
assign _count_T_4 = _GEN_21; // @[PTW.scala:624:24]
wire [2:0] _count_T_6; // @[PTW.scala:696:22]
assign _count_T_6 = _GEN_21; // @[PTW.scala:624:24, :696:22]
wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38]
assign _aux_count_T_3 = _GEN_21; // @[PTW.scala:624:24, :741:38]
wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24]
wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26]
wire _T_140 = state == 3'h2; // @[PTW.scala:233:22, :583:18]
wire _T_141 = state == 3'h4; // @[PTW.scala:233:22, :583:18]
wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39]
wire _GEN_22 = _T_152 | _T_140; // @[PTW.scala:377:24, :393:26, :583:18]
assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_22) & _T_141 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}]
wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45]
wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86]
wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}]
wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86]
wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}]
wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64]
wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}]
wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64]
wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62]
wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125]
wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}]
wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}]
wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86]
wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}]
wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76]
wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26]
wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32]
wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26]
wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30]
wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30]
assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}]
assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}]
wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26]
assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73]
wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58]
wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27]
assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27]
wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19]
wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26]
assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}]
assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19]
wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29]
wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}]
wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}]
wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26]
wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15]
wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43]
wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}]
wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65]
wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}]
wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}]
wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49]
wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}]
wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}]
wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86]
wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}]
wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76]
wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26]
wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26]
wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26]
wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26]
wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35]
wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35]
wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35]
wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35]
wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26]
wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8]
wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26]
wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8]
wire [43:0] _r_pte_T_31_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_30_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26]
wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_d = ~_r_pte_T_7 & _r_pte_T_30_d; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_a = ~_r_pte_T_7 & _r_pte_T_30_a; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_g = ~_r_pte_T_7 & _r_pte_T_30_g; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_u = ~_r_pte_T_7 & _r_pte_T_30_u; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_x = ~_r_pte_T_7 & _r_pte_T_30_x; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_w = ~_r_pte_T_7 & _r_pte_T_30_w; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_r = ~_r_pte_T_7 & _r_pte_T_30_r; // @[PTW.scala:674:{8,25}, :676:8]
wire _r_pte_T_31_v = ~_r_pte_T_7 & _r_pte_T_30_v; // @[PTW.scala:674:{8,25}, :676:8]
wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8]
wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8]
wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8]
wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8]
wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8]
wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8]
wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8]
wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8]
wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22]
wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27]
wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}]
wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44]
wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}]
wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26]
wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26]
wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26]
wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97]
wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}]
wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}]
wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}]
wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22]
wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49]
wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}]
wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30]
wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}]
wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37]
wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}]
wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44]
wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}]
wire _T_168 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}]
assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_168 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21]
wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}]
wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61]
wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}]
wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12]
wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30]
wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}]
wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}]
wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26]
wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26]
wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26]
wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41]
wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}]
wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59]
wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44]
wire _GEN_23 = traverse | _T_168; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19]
wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36]
wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}]
wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26]
wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26]
wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26]
wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}]
wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26]
wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}]
wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26]
wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}]
wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26]
wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}]
wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26]
wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}]
wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26]
wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}]
wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}]
wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29]
wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26]
wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}]
wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30]
wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}]
wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20]
wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32]
wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39]
wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}]
wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26]
wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26]
wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}]
wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}]
wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20]
wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32]
wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39]
wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}]
wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26]
wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26]
wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26]
wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}]
wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}]
wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20]
wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32]
wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39]
wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}]
wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26]
wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26]
wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26]
wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26]
wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26]
wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26]
wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26]
wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}]
wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_197 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_197( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_18 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_28
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_18( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_28 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_Registered :
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut.sync, nodeIn
extmodule plusarg_reader_68 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_69 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module IntSyncCrossingSource_n1x1_Registered( // @[Crossing.scala:48:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:48:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:48:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:48:9]
assign nodeOut_sync_0 = nodeIn_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:48:9]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:48:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_7 :
input clock : Clock
input reset : Reset
output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[3], flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, brinfo : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}
connect io.req.ready, UInt<1>(0h0)
connect io.iresp.valid, UInt<1>(0h0)
invalidate io.iresp.bits.fflags.bits.flags
invalidate io.iresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.iresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.iresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.iresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.iresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.iresp.bits.fflags.bits.uop.fp_single
invalidate io.iresp.bits.fflags.bits.uop.fp_val
invalidate io.iresp.bits.fflags.bits.uop.frs3_en
invalidate io.iresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.iresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.iresp.bits.fflags.bits.uop.dst_rtype
invalidate io.iresp.bits.fflags.bits.uop.ldst_val
invalidate io.iresp.bits.fflags.bits.uop.lrs3
invalidate io.iresp.bits.fflags.bits.uop.lrs2
invalidate io.iresp.bits.fflags.bits.uop.lrs1
invalidate io.iresp.bits.fflags.bits.uop.ldst
invalidate io.iresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.iresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.iresp.bits.fflags.bits.uop.is_unique
invalidate io.iresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.iresp.bits.fflags.bits.uop.uses_stq
invalidate io.iresp.bits.fflags.bits.uop.uses_ldq
invalidate io.iresp.bits.fflags.bits.uop.is_amo
invalidate io.iresp.bits.fflags.bits.uop.is_fencei
invalidate io.iresp.bits.fflags.bits.uop.is_fence
invalidate io.iresp.bits.fflags.bits.uop.mem_signed
invalidate io.iresp.bits.fflags.bits.uop.mem_size
invalidate io.iresp.bits.fflags.bits.uop.mem_cmd
invalidate io.iresp.bits.fflags.bits.uop.bypassable
invalidate io.iresp.bits.fflags.bits.uop.exc_cause
invalidate io.iresp.bits.fflags.bits.uop.exception
invalidate io.iresp.bits.fflags.bits.uop.stale_pdst
invalidate io.iresp.bits.fflags.bits.uop.ppred_busy
invalidate io.iresp.bits.fflags.bits.uop.prs3_busy
invalidate io.iresp.bits.fflags.bits.uop.prs2_busy
invalidate io.iresp.bits.fflags.bits.uop.prs1_busy
invalidate io.iresp.bits.fflags.bits.uop.ppred
invalidate io.iresp.bits.fflags.bits.uop.prs3
invalidate io.iresp.bits.fflags.bits.uop.prs2
invalidate io.iresp.bits.fflags.bits.uop.prs1
invalidate io.iresp.bits.fflags.bits.uop.pdst
invalidate io.iresp.bits.fflags.bits.uop.rxq_idx
invalidate io.iresp.bits.fflags.bits.uop.stq_idx
invalidate io.iresp.bits.fflags.bits.uop.ldq_idx
invalidate io.iresp.bits.fflags.bits.uop.rob_idx
invalidate io.iresp.bits.fflags.bits.uop.csr_addr
invalidate io.iresp.bits.fflags.bits.uop.imm_packed
invalidate io.iresp.bits.fflags.bits.uop.taken
invalidate io.iresp.bits.fflags.bits.uop.pc_lob
invalidate io.iresp.bits.fflags.bits.uop.edge_inst
invalidate io.iresp.bits.fflags.bits.uop.ftq_idx
invalidate io.iresp.bits.fflags.bits.uop.br_tag
invalidate io.iresp.bits.fflags.bits.uop.br_mask
invalidate io.iresp.bits.fflags.bits.uop.is_sfb
invalidate io.iresp.bits.fflags.bits.uop.is_jal
invalidate io.iresp.bits.fflags.bits.uop.is_jalr
invalidate io.iresp.bits.fflags.bits.uop.is_br
invalidate io.iresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.iresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.iresp.bits.fflags.bits.uop.iw_state
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.iresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.iresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.iresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.iresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.iresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.iresp.bits.fflags.bits.uop.fu_code
invalidate io.iresp.bits.fflags.bits.uop.iq_type
invalidate io.iresp.bits.fflags.bits.uop.debug_pc
invalidate io.iresp.bits.fflags.bits.uop.is_rvc
invalidate io.iresp.bits.fflags.bits.uop.debug_inst
invalidate io.iresp.bits.fflags.bits.uop.inst
invalidate io.iresp.bits.fflags.bits.uop.uopc
invalidate io.iresp.bits.fflags.valid
invalidate io.iresp.bits.predicated
invalidate io.iresp.bits.data
invalidate io.iresp.bits.uop.debug_tsrc
invalidate io.iresp.bits.uop.debug_fsrc
invalidate io.iresp.bits.uop.bp_xcpt_if
invalidate io.iresp.bits.uop.bp_debug_if
invalidate io.iresp.bits.uop.xcpt_ma_if
invalidate io.iresp.bits.uop.xcpt_ae_if
invalidate io.iresp.bits.uop.xcpt_pf_if
invalidate io.iresp.bits.uop.fp_single
invalidate io.iresp.bits.uop.fp_val
invalidate io.iresp.bits.uop.frs3_en
invalidate io.iresp.bits.uop.lrs2_rtype
invalidate io.iresp.bits.uop.lrs1_rtype
invalidate io.iresp.bits.uop.dst_rtype
invalidate io.iresp.bits.uop.ldst_val
invalidate io.iresp.bits.uop.lrs3
invalidate io.iresp.bits.uop.lrs2
invalidate io.iresp.bits.uop.lrs1
invalidate io.iresp.bits.uop.ldst
invalidate io.iresp.bits.uop.ldst_is_rs1
invalidate io.iresp.bits.uop.flush_on_commit
invalidate io.iresp.bits.uop.is_unique
invalidate io.iresp.bits.uop.is_sys_pc2epc
invalidate io.iresp.bits.uop.uses_stq
invalidate io.iresp.bits.uop.uses_ldq
invalidate io.iresp.bits.uop.is_amo
invalidate io.iresp.bits.uop.is_fencei
invalidate io.iresp.bits.uop.is_fence
invalidate io.iresp.bits.uop.mem_signed
invalidate io.iresp.bits.uop.mem_size
invalidate io.iresp.bits.uop.mem_cmd
invalidate io.iresp.bits.uop.bypassable
invalidate io.iresp.bits.uop.exc_cause
invalidate io.iresp.bits.uop.exception
invalidate io.iresp.bits.uop.stale_pdst
invalidate io.iresp.bits.uop.ppred_busy
invalidate io.iresp.bits.uop.prs3_busy
invalidate io.iresp.bits.uop.prs2_busy
invalidate io.iresp.bits.uop.prs1_busy
invalidate io.iresp.bits.uop.ppred
invalidate io.iresp.bits.uop.prs3
invalidate io.iresp.bits.uop.prs2
invalidate io.iresp.bits.uop.prs1
invalidate io.iresp.bits.uop.pdst
invalidate io.iresp.bits.uop.rxq_idx
invalidate io.iresp.bits.uop.stq_idx
invalidate io.iresp.bits.uop.ldq_idx
invalidate io.iresp.bits.uop.rob_idx
invalidate io.iresp.bits.uop.csr_addr
invalidate io.iresp.bits.uop.imm_packed
invalidate io.iresp.bits.uop.taken
invalidate io.iresp.bits.uop.pc_lob
invalidate io.iresp.bits.uop.edge_inst
invalidate io.iresp.bits.uop.ftq_idx
invalidate io.iresp.bits.uop.br_tag
invalidate io.iresp.bits.uop.br_mask
invalidate io.iresp.bits.uop.is_sfb
invalidate io.iresp.bits.uop.is_jal
invalidate io.iresp.bits.uop.is_jalr
invalidate io.iresp.bits.uop.is_br
invalidate io.iresp.bits.uop.iw_p2_poisoned
invalidate io.iresp.bits.uop.iw_p1_poisoned
invalidate io.iresp.bits.uop.iw_state
invalidate io.iresp.bits.uop.ctrl.is_std
invalidate io.iresp.bits.uop.ctrl.is_sta
invalidate io.iresp.bits.uop.ctrl.is_load
invalidate io.iresp.bits.uop.ctrl.csr_cmd
invalidate io.iresp.bits.uop.ctrl.fcn_dw
invalidate io.iresp.bits.uop.ctrl.op_fcn
invalidate io.iresp.bits.uop.ctrl.imm_sel
invalidate io.iresp.bits.uop.ctrl.op2_sel
invalidate io.iresp.bits.uop.ctrl.op1_sel
invalidate io.iresp.bits.uop.ctrl.br_type
invalidate io.iresp.bits.uop.fu_code
invalidate io.iresp.bits.uop.iq_type
invalidate io.iresp.bits.uop.debug_pc
invalidate io.iresp.bits.uop.is_rvc
invalidate io.iresp.bits.uop.debug_inst
invalidate io.iresp.bits.uop.inst
invalidate io.iresp.bits.uop.uopc
connect io.iresp.bits.fflags.valid, UInt<1>(0h0)
connect io.iresp.bits.predicated, UInt<1>(0h0)
node _T = asUInt(reset)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
node _T_2 = eq(io.iresp.ready, UInt<1>(0h0))
when _T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:147 assert(io.iresp.ready)\n") : printf
assert(clock, io.iresp.ready, UInt<1>(0h1), "") : assert
wire div_busy : UInt<1>
connect div_busy, UInt<1>(0h0)
wire ifpu_busy : UInt<1>
connect ifpu_busy, UInt<1>(0h0)
node _io_fu_types_T = mux(UInt<1>(0h1), UInt<10>(0h1), UInt<1>(0h0))
node _io_fu_types_T_1 = mux(UInt<1>(0h1), UInt<10>(0h8), UInt<1>(0h0))
node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1)
node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0))
node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h0))
node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0))
node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5)
node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0))
node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7)
node _io_fu_types_T_9 = mux(UInt<1>(0h0), UInt<10>(0h2), UInt<1>(0h0))
node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9)
node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0))
node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0))
node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0))
node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13)
node _io_fu_types_T_15 = mux(UInt<1>(0h0), UInt<10>(0h4), UInt<1>(0h0))
node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15)
connect io.fu_types, _io_fu_types_T_16
inst ALUUnit of ALUUnit_5
connect ALUUnit.clock, clock
connect ALUUnit.reset, reset
node _T_3 = eq(io.req.bits.uop.fu_code, UInt<10>(0h1))
node _T_4 = eq(io.req.bits.uop.fu_code, UInt<10>(0h2))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(io.req.bits.uop.fu_code, UInt<10>(0h20))
node _T_7 = neq(io.req.bits.uop.uopc, UInt<7>(0h6c))
node _T_8 = and(_T_6, _T_7)
node _T_9 = or(_T_5, _T_8)
node _T_10 = and(io.req.valid, _T_9)
connect ALUUnit.io.req.valid, _T_10
connect ALUUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect ALUUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect ALUUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect ALUUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect ALUUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect ALUUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect ALUUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect ALUUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect ALUUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect ALUUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect ALUUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect ALUUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect ALUUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect ALUUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect ALUUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect ALUUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect ALUUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect ALUUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect ALUUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect ALUUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect ALUUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect ALUUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect ALUUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect ALUUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect ALUUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect ALUUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect ALUUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect ALUUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect ALUUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect ALUUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect ALUUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect ALUUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect ALUUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect ALUUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect ALUUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect ALUUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect ALUUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect ALUUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect ALUUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect ALUUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect ALUUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect ALUUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect ALUUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect ALUUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect ALUUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect ALUUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect ALUUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect ALUUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect ALUUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect ALUUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect ALUUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect ALUUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect ALUUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect ALUUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect ALUUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect ALUUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect ALUUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect ALUUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect ALUUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect ALUUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect ALUUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect ALUUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect ALUUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect ALUUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect ALUUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect ALUUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect ALUUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect ALUUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect ALUUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect ALUUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect ALUUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect ALUUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect ALUUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect ALUUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect ALUUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect ALUUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect ALUUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect ALUUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect ALUUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect ALUUnit.io.req.bits.kill, io.req.bits.kill
connect ALUUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect ALUUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
invalidate ALUUnit.io.req.bits.rs3_data
connect ALUUnit.io.req.bits.pred_data, io.req.bits.pred_data
invalidate ALUUnit.io.resp.ready
connect ALUUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect ALUUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect ALUUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect ALUUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect ALUUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect ALUUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect ALUUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect ALUUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect ALUUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect ALUUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect ALUUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect ALUUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect ALUUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect ALUUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect ALUUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect ALUUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect ALUUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect ALUUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect ALUUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect ALUUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect ALUUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect ALUUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect ALUUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect ALUUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect ALUUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect ALUUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect ALUUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect ALUUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect ALUUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect ALUUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect ALUUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect ALUUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect ALUUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect ALUUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect ALUUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect ALUUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect ALUUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect ALUUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect ALUUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect ALUUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect ALUUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect ALUUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect ALUUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect ALUUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect ALUUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect ALUUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect ALUUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect ALUUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect ALUUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect ALUUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect ALUUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect ALUUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect ALUUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect ALUUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect ALUUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect ALUUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect ALUUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect ALUUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect ALUUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect ALUUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect ALUUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect ALUUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect ALUUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect ALUUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect ALUUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect ALUUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect ALUUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect ALUUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect ALUUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect ALUUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect ALUUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect ALUUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect ALUUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect ALUUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect ALUUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect ALUUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect ALUUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect ALUUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect ALUUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect ALUUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect ALUUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect ALUUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect io.bypass, ALUUnit.io.bypass
connect io.brinfo, ALUUnit.io.brinfo
inst PipelinedMulUnit of PipelinedMulUnit_1
connect PipelinedMulUnit.clock, clock
connect PipelinedMulUnit.reset, reset
invalidate PipelinedMulUnit.io.brupdate.b2.target_offset
invalidate PipelinedMulUnit.io.brupdate.b2.jalr_target
invalidate PipelinedMulUnit.io.brupdate.b2.pc_sel
invalidate PipelinedMulUnit.io.brupdate.b2.cfi_type
invalidate PipelinedMulUnit.io.brupdate.b2.taken
invalidate PipelinedMulUnit.io.brupdate.b2.mispredict
invalidate PipelinedMulUnit.io.brupdate.b2.valid
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_tsrc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_fsrc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.bp_debug_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.brupdate.b2.uop.fp_single
invalidate PipelinedMulUnit.io.brupdate.b2.uop.fp_val
invalidate PipelinedMulUnit.io.brupdate.b2.uop.frs3_en
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.brupdate.b2.uop.dst_rtype
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst_val
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs3
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs2
invalidate PipelinedMulUnit.io.brupdate.b2.uop.lrs1
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.brupdate.b2.uop.flush_on_commit
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_unique
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.uses_stq
invalidate PipelinedMulUnit.io.brupdate.b2.uop.uses_ldq
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_amo
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_fencei
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_fence
invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_signed
invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_size
invalidate PipelinedMulUnit.io.brupdate.b2.uop.mem_cmd
invalidate PipelinedMulUnit.io.brupdate.b2.uop.bypassable
invalidate PipelinedMulUnit.io.brupdate.b2.uop.exc_cause
invalidate PipelinedMulUnit.io.brupdate.b2.uop.exception
invalidate PipelinedMulUnit.io.brupdate.b2.uop.stale_pdst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ppred_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs3_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs2_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs1_busy
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ppred
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs3
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs2
invalidate PipelinedMulUnit.io.brupdate.b2.uop.prs1
invalidate PipelinedMulUnit.io.brupdate.b2.uop.pdst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.rxq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.stq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ldq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.rob_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.csr_addr
invalidate PipelinedMulUnit.io.brupdate.b2.uop.imm_packed
invalidate PipelinedMulUnit.io.brupdate.b2.uop.taken
invalidate PipelinedMulUnit.io.brupdate.b2.uop.pc_lob
invalidate PipelinedMulUnit.io.brupdate.b2.uop.edge_inst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ftq_idx
invalidate PipelinedMulUnit.io.brupdate.b2.uop.br_tag
invalidate PipelinedMulUnit.io.brupdate.b2.uop.br_mask
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_sfb
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_jal
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_jalr
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_br
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iw_state
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.brupdate.b2.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.brupdate.b2.uop.fu_code
invalidate PipelinedMulUnit.io.brupdate.b2.uop.iq_type
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_pc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.is_rvc
invalidate PipelinedMulUnit.io.brupdate.b2.uop.debug_inst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.inst
invalidate PipelinedMulUnit.io.brupdate.b2.uop.uopc
invalidate PipelinedMulUnit.io.brupdate.b1.mispredict_mask
invalidate PipelinedMulUnit.io.brupdate.b1.resolve_mask
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.hg
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.hv
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.asid
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.addr
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.rs2
invalidate PipelinedMulUnit.io.resp.bits.sfence.bits.rs1
invalidate PipelinedMulUnit.io.resp.bits.sfence.valid
invalidate PipelinedMulUnit.io.resp.bits.mxcpt.bits
invalidate PipelinedMulUnit.io.resp.bits.mxcpt.valid
invalidate PipelinedMulUnit.io.resp.bits.addr
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.flags
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fp_single
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fp_val
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.frs3_en
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.dst_rtype
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst_val
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs3
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs2
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.lrs1
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_unique
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uses_stq
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uses_ldq
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_amo
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_fencei
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_fence
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_signed
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_size
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.mem_cmd
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.bypassable
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.exc_cause
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.exception
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.stale_pdst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ppred_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs3_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs2_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs1_busy
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ppred
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs3
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs2
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.prs1
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.pdst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.rxq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.stq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ldq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.rob_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.csr_addr
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.imm_packed
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.taken
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.pc_lob
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.edge_inst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ftq_idx
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.br_tag
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.br_mask
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_sfb
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_jal
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_jalr
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_br
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iw_state
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.fu_code
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.iq_type
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_pc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.is_rvc
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.debug_inst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.inst
invalidate PipelinedMulUnit.io.resp.bits.fflags.bits.uop.uopc
invalidate PipelinedMulUnit.io.resp.bits.fflags.valid
invalidate PipelinedMulUnit.io.resp.bits.data
invalidate PipelinedMulUnit.io.resp.bits.predicated
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_tsrc
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_fsrc
invalidate PipelinedMulUnit.io.resp.bits.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.resp.bits.uop.bp_debug_if
invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.resp.bits.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.resp.bits.uop.fp_single
invalidate PipelinedMulUnit.io.resp.bits.uop.fp_val
invalidate PipelinedMulUnit.io.resp.bits.uop.frs3_en
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.resp.bits.uop.dst_rtype
invalidate PipelinedMulUnit.io.resp.bits.uop.ldst_val
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs3
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs2
invalidate PipelinedMulUnit.io.resp.bits.uop.lrs1
invalidate PipelinedMulUnit.io.resp.bits.uop.ldst
invalidate PipelinedMulUnit.io.resp.bits.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.resp.bits.uop.flush_on_commit
invalidate PipelinedMulUnit.io.resp.bits.uop.is_unique
invalidate PipelinedMulUnit.io.resp.bits.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.resp.bits.uop.uses_stq
invalidate PipelinedMulUnit.io.resp.bits.uop.uses_ldq
invalidate PipelinedMulUnit.io.resp.bits.uop.is_amo
invalidate PipelinedMulUnit.io.resp.bits.uop.is_fencei
invalidate PipelinedMulUnit.io.resp.bits.uop.is_fence
invalidate PipelinedMulUnit.io.resp.bits.uop.mem_signed
invalidate PipelinedMulUnit.io.resp.bits.uop.mem_size
invalidate PipelinedMulUnit.io.resp.bits.uop.mem_cmd
invalidate PipelinedMulUnit.io.resp.bits.uop.bypassable
invalidate PipelinedMulUnit.io.resp.bits.uop.exc_cause
invalidate PipelinedMulUnit.io.resp.bits.uop.exception
invalidate PipelinedMulUnit.io.resp.bits.uop.stale_pdst
invalidate PipelinedMulUnit.io.resp.bits.uop.ppred_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.prs3_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.prs2_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.prs1_busy
invalidate PipelinedMulUnit.io.resp.bits.uop.ppred
invalidate PipelinedMulUnit.io.resp.bits.uop.prs3
invalidate PipelinedMulUnit.io.resp.bits.uop.prs2
invalidate PipelinedMulUnit.io.resp.bits.uop.prs1
invalidate PipelinedMulUnit.io.resp.bits.uop.pdst
invalidate PipelinedMulUnit.io.resp.bits.uop.rxq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.stq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.ldq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.rob_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.csr_addr
invalidate PipelinedMulUnit.io.resp.bits.uop.imm_packed
invalidate PipelinedMulUnit.io.resp.bits.uop.taken
invalidate PipelinedMulUnit.io.resp.bits.uop.pc_lob
invalidate PipelinedMulUnit.io.resp.bits.uop.edge_inst
invalidate PipelinedMulUnit.io.resp.bits.uop.ftq_idx
invalidate PipelinedMulUnit.io.resp.bits.uop.br_tag
invalidate PipelinedMulUnit.io.resp.bits.uop.br_mask
invalidate PipelinedMulUnit.io.resp.bits.uop.is_sfb
invalidate PipelinedMulUnit.io.resp.bits.uop.is_jal
invalidate PipelinedMulUnit.io.resp.bits.uop.is_jalr
invalidate PipelinedMulUnit.io.resp.bits.uop.is_br
invalidate PipelinedMulUnit.io.resp.bits.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.resp.bits.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.resp.bits.uop.iw_state
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.resp.bits.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.resp.bits.uop.fu_code
invalidate PipelinedMulUnit.io.resp.bits.uop.iq_type
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_pc
invalidate PipelinedMulUnit.io.resp.bits.uop.is_rvc
invalidate PipelinedMulUnit.io.resp.bits.uop.debug_inst
invalidate PipelinedMulUnit.io.resp.bits.uop.inst
invalidate PipelinedMulUnit.io.resp.bits.uop.uopc
invalidate PipelinedMulUnit.io.resp.valid
invalidate PipelinedMulUnit.io.resp.ready
invalidate PipelinedMulUnit.io.req.bits.kill
invalidate PipelinedMulUnit.io.req.bits.pred_data
invalidate PipelinedMulUnit.io.req.bits.rs3_data
invalidate PipelinedMulUnit.io.req.bits.rs2_data
invalidate PipelinedMulUnit.io.req.bits.rs1_data
invalidate PipelinedMulUnit.io.req.bits.uop.debug_tsrc
invalidate PipelinedMulUnit.io.req.bits.uop.debug_fsrc
invalidate PipelinedMulUnit.io.req.bits.uop.bp_xcpt_if
invalidate PipelinedMulUnit.io.req.bits.uop.bp_debug_if
invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_ma_if
invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_ae_if
invalidate PipelinedMulUnit.io.req.bits.uop.xcpt_pf_if
invalidate PipelinedMulUnit.io.req.bits.uop.fp_single
invalidate PipelinedMulUnit.io.req.bits.uop.fp_val
invalidate PipelinedMulUnit.io.req.bits.uop.frs3_en
invalidate PipelinedMulUnit.io.req.bits.uop.lrs2_rtype
invalidate PipelinedMulUnit.io.req.bits.uop.lrs1_rtype
invalidate PipelinedMulUnit.io.req.bits.uop.dst_rtype
invalidate PipelinedMulUnit.io.req.bits.uop.ldst_val
invalidate PipelinedMulUnit.io.req.bits.uop.lrs3
invalidate PipelinedMulUnit.io.req.bits.uop.lrs2
invalidate PipelinedMulUnit.io.req.bits.uop.lrs1
invalidate PipelinedMulUnit.io.req.bits.uop.ldst
invalidate PipelinedMulUnit.io.req.bits.uop.ldst_is_rs1
invalidate PipelinedMulUnit.io.req.bits.uop.flush_on_commit
invalidate PipelinedMulUnit.io.req.bits.uop.is_unique
invalidate PipelinedMulUnit.io.req.bits.uop.is_sys_pc2epc
invalidate PipelinedMulUnit.io.req.bits.uop.uses_stq
invalidate PipelinedMulUnit.io.req.bits.uop.uses_ldq
invalidate PipelinedMulUnit.io.req.bits.uop.is_amo
invalidate PipelinedMulUnit.io.req.bits.uop.is_fencei
invalidate PipelinedMulUnit.io.req.bits.uop.is_fence
invalidate PipelinedMulUnit.io.req.bits.uop.mem_signed
invalidate PipelinedMulUnit.io.req.bits.uop.mem_size
invalidate PipelinedMulUnit.io.req.bits.uop.mem_cmd
invalidate PipelinedMulUnit.io.req.bits.uop.bypassable
invalidate PipelinedMulUnit.io.req.bits.uop.exc_cause
invalidate PipelinedMulUnit.io.req.bits.uop.exception
invalidate PipelinedMulUnit.io.req.bits.uop.stale_pdst
invalidate PipelinedMulUnit.io.req.bits.uop.ppred_busy
invalidate PipelinedMulUnit.io.req.bits.uop.prs3_busy
invalidate PipelinedMulUnit.io.req.bits.uop.prs2_busy
invalidate PipelinedMulUnit.io.req.bits.uop.prs1_busy
invalidate PipelinedMulUnit.io.req.bits.uop.ppred
invalidate PipelinedMulUnit.io.req.bits.uop.prs3
invalidate PipelinedMulUnit.io.req.bits.uop.prs2
invalidate PipelinedMulUnit.io.req.bits.uop.prs1
invalidate PipelinedMulUnit.io.req.bits.uop.pdst
invalidate PipelinedMulUnit.io.req.bits.uop.rxq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.stq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.ldq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.rob_idx
invalidate PipelinedMulUnit.io.req.bits.uop.csr_addr
invalidate PipelinedMulUnit.io.req.bits.uop.imm_packed
invalidate PipelinedMulUnit.io.req.bits.uop.taken
invalidate PipelinedMulUnit.io.req.bits.uop.pc_lob
invalidate PipelinedMulUnit.io.req.bits.uop.edge_inst
invalidate PipelinedMulUnit.io.req.bits.uop.ftq_idx
invalidate PipelinedMulUnit.io.req.bits.uop.br_tag
invalidate PipelinedMulUnit.io.req.bits.uop.br_mask
invalidate PipelinedMulUnit.io.req.bits.uop.is_sfb
invalidate PipelinedMulUnit.io.req.bits.uop.is_jal
invalidate PipelinedMulUnit.io.req.bits.uop.is_jalr
invalidate PipelinedMulUnit.io.req.bits.uop.is_br
invalidate PipelinedMulUnit.io.req.bits.uop.iw_p2_poisoned
invalidate PipelinedMulUnit.io.req.bits.uop.iw_p1_poisoned
invalidate PipelinedMulUnit.io.req.bits.uop.iw_state
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_std
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_sta
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.is_load
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.csr_cmd
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.fcn_dw
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op_fcn
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.imm_sel
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op2_sel
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.op1_sel
invalidate PipelinedMulUnit.io.req.bits.uop.ctrl.br_type
invalidate PipelinedMulUnit.io.req.bits.uop.fu_code
invalidate PipelinedMulUnit.io.req.bits.uop.iq_type
invalidate PipelinedMulUnit.io.req.bits.uop.debug_pc
invalidate PipelinedMulUnit.io.req.bits.uop.is_rvc
invalidate PipelinedMulUnit.io.req.bits.uop.debug_inst
invalidate PipelinedMulUnit.io.req.bits.uop.inst
invalidate PipelinedMulUnit.io.req.bits.uop.uopc
invalidate PipelinedMulUnit.io.req.valid
invalidate PipelinedMulUnit.io.req.ready
node _T_11 = and(io.req.bits.uop.fu_code, UInt<10>(0h8))
node _T_12 = neq(_T_11, UInt<1>(0h0))
node _T_13 = and(io.req.valid, _T_12)
connect PipelinedMulUnit.io.req.valid, _T_13
connect PipelinedMulUnit.io.req.bits.uop.debug_tsrc, io.req.bits.uop.debug_tsrc
connect PipelinedMulUnit.io.req.bits.uop.debug_fsrc, io.req.bits.uop.debug_fsrc
connect PipelinedMulUnit.io.req.bits.uop.bp_xcpt_if, io.req.bits.uop.bp_xcpt_if
connect PipelinedMulUnit.io.req.bits.uop.bp_debug_if, io.req.bits.uop.bp_debug_if
connect PipelinedMulUnit.io.req.bits.uop.xcpt_ma_if, io.req.bits.uop.xcpt_ma_if
connect PipelinedMulUnit.io.req.bits.uop.xcpt_ae_if, io.req.bits.uop.xcpt_ae_if
connect PipelinedMulUnit.io.req.bits.uop.xcpt_pf_if, io.req.bits.uop.xcpt_pf_if
connect PipelinedMulUnit.io.req.bits.uop.fp_single, io.req.bits.uop.fp_single
connect PipelinedMulUnit.io.req.bits.uop.fp_val, io.req.bits.uop.fp_val
connect PipelinedMulUnit.io.req.bits.uop.frs3_en, io.req.bits.uop.frs3_en
connect PipelinedMulUnit.io.req.bits.uop.lrs2_rtype, io.req.bits.uop.lrs2_rtype
connect PipelinedMulUnit.io.req.bits.uop.lrs1_rtype, io.req.bits.uop.lrs1_rtype
connect PipelinedMulUnit.io.req.bits.uop.dst_rtype, io.req.bits.uop.dst_rtype
connect PipelinedMulUnit.io.req.bits.uop.ldst_val, io.req.bits.uop.ldst_val
connect PipelinedMulUnit.io.req.bits.uop.lrs3, io.req.bits.uop.lrs3
connect PipelinedMulUnit.io.req.bits.uop.lrs2, io.req.bits.uop.lrs2
connect PipelinedMulUnit.io.req.bits.uop.lrs1, io.req.bits.uop.lrs1
connect PipelinedMulUnit.io.req.bits.uop.ldst, io.req.bits.uop.ldst
connect PipelinedMulUnit.io.req.bits.uop.ldst_is_rs1, io.req.bits.uop.ldst_is_rs1
connect PipelinedMulUnit.io.req.bits.uop.flush_on_commit, io.req.bits.uop.flush_on_commit
connect PipelinedMulUnit.io.req.bits.uop.is_unique, io.req.bits.uop.is_unique
connect PipelinedMulUnit.io.req.bits.uop.is_sys_pc2epc, io.req.bits.uop.is_sys_pc2epc
connect PipelinedMulUnit.io.req.bits.uop.uses_stq, io.req.bits.uop.uses_stq
connect PipelinedMulUnit.io.req.bits.uop.uses_ldq, io.req.bits.uop.uses_ldq
connect PipelinedMulUnit.io.req.bits.uop.is_amo, io.req.bits.uop.is_amo
connect PipelinedMulUnit.io.req.bits.uop.is_fencei, io.req.bits.uop.is_fencei
connect PipelinedMulUnit.io.req.bits.uop.is_fence, io.req.bits.uop.is_fence
connect PipelinedMulUnit.io.req.bits.uop.mem_signed, io.req.bits.uop.mem_signed
connect PipelinedMulUnit.io.req.bits.uop.mem_size, io.req.bits.uop.mem_size
connect PipelinedMulUnit.io.req.bits.uop.mem_cmd, io.req.bits.uop.mem_cmd
connect PipelinedMulUnit.io.req.bits.uop.bypassable, io.req.bits.uop.bypassable
connect PipelinedMulUnit.io.req.bits.uop.exc_cause, io.req.bits.uop.exc_cause
connect PipelinedMulUnit.io.req.bits.uop.exception, io.req.bits.uop.exception
connect PipelinedMulUnit.io.req.bits.uop.stale_pdst, io.req.bits.uop.stale_pdst
connect PipelinedMulUnit.io.req.bits.uop.ppred_busy, io.req.bits.uop.ppred_busy
connect PipelinedMulUnit.io.req.bits.uop.prs3_busy, io.req.bits.uop.prs3_busy
connect PipelinedMulUnit.io.req.bits.uop.prs2_busy, io.req.bits.uop.prs2_busy
connect PipelinedMulUnit.io.req.bits.uop.prs1_busy, io.req.bits.uop.prs1_busy
connect PipelinedMulUnit.io.req.bits.uop.ppred, io.req.bits.uop.ppred
connect PipelinedMulUnit.io.req.bits.uop.prs3, io.req.bits.uop.prs3
connect PipelinedMulUnit.io.req.bits.uop.prs2, io.req.bits.uop.prs2
connect PipelinedMulUnit.io.req.bits.uop.prs1, io.req.bits.uop.prs1
connect PipelinedMulUnit.io.req.bits.uop.pdst, io.req.bits.uop.pdst
connect PipelinedMulUnit.io.req.bits.uop.rxq_idx, io.req.bits.uop.rxq_idx
connect PipelinedMulUnit.io.req.bits.uop.stq_idx, io.req.bits.uop.stq_idx
connect PipelinedMulUnit.io.req.bits.uop.ldq_idx, io.req.bits.uop.ldq_idx
connect PipelinedMulUnit.io.req.bits.uop.rob_idx, io.req.bits.uop.rob_idx
connect PipelinedMulUnit.io.req.bits.uop.csr_addr, io.req.bits.uop.csr_addr
connect PipelinedMulUnit.io.req.bits.uop.imm_packed, io.req.bits.uop.imm_packed
connect PipelinedMulUnit.io.req.bits.uop.taken, io.req.bits.uop.taken
connect PipelinedMulUnit.io.req.bits.uop.pc_lob, io.req.bits.uop.pc_lob
connect PipelinedMulUnit.io.req.bits.uop.edge_inst, io.req.bits.uop.edge_inst
connect PipelinedMulUnit.io.req.bits.uop.ftq_idx, io.req.bits.uop.ftq_idx
connect PipelinedMulUnit.io.req.bits.uop.br_tag, io.req.bits.uop.br_tag
connect PipelinedMulUnit.io.req.bits.uop.br_mask, io.req.bits.uop.br_mask
connect PipelinedMulUnit.io.req.bits.uop.is_sfb, io.req.bits.uop.is_sfb
connect PipelinedMulUnit.io.req.bits.uop.is_jal, io.req.bits.uop.is_jal
connect PipelinedMulUnit.io.req.bits.uop.is_jalr, io.req.bits.uop.is_jalr
connect PipelinedMulUnit.io.req.bits.uop.is_br, io.req.bits.uop.is_br
connect PipelinedMulUnit.io.req.bits.uop.iw_p2_poisoned, io.req.bits.uop.iw_p2_poisoned
connect PipelinedMulUnit.io.req.bits.uop.iw_p1_poisoned, io.req.bits.uop.iw_p1_poisoned
connect PipelinedMulUnit.io.req.bits.uop.iw_state, io.req.bits.uop.iw_state
connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_std, io.req.bits.uop.ctrl.is_std
connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_sta, io.req.bits.uop.ctrl.is_sta
connect PipelinedMulUnit.io.req.bits.uop.ctrl.is_load, io.req.bits.uop.ctrl.is_load
connect PipelinedMulUnit.io.req.bits.uop.ctrl.csr_cmd, io.req.bits.uop.ctrl.csr_cmd
connect PipelinedMulUnit.io.req.bits.uop.ctrl.fcn_dw, io.req.bits.uop.ctrl.fcn_dw
connect PipelinedMulUnit.io.req.bits.uop.ctrl.op_fcn, io.req.bits.uop.ctrl.op_fcn
connect PipelinedMulUnit.io.req.bits.uop.ctrl.imm_sel, io.req.bits.uop.ctrl.imm_sel
connect PipelinedMulUnit.io.req.bits.uop.ctrl.op2_sel, io.req.bits.uop.ctrl.op2_sel
connect PipelinedMulUnit.io.req.bits.uop.ctrl.op1_sel, io.req.bits.uop.ctrl.op1_sel
connect PipelinedMulUnit.io.req.bits.uop.ctrl.br_type, io.req.bits.uop.ctrl.br_type
connect PipelinedMulUnit.io.req.bits.uop.fu_code, io.req.bits.uop.fu_code
connect PipelinedMulUnit.io.req.bits.uop.iq_type, io.req.bits.uop.iq_type
connect PipelinedMulUnit.io.req.bits.uop.debug_pc, io.req.bits.uop.debug_pc
connect PipelinedMulUnit.io.req.bits.uop.is_rvc, io.req.bits.uop.is_rvc
connect PipelinedMulUnit.io.req.bits.uop.debug_inst, io.req.bits.uop.debug_inst
connect PipelinedMulUnit.io.req.bits.uop.inst, io.req.bits.uop.inst
connect PipelinedMulUnit.io.req.bits.uop.uopc, io.req.bits.uop.uopc
connect PipelinedMulUnit.io.req.bits.rs1_data, io.req.bits.rs1_data
connect PipelinedMulUnit.io.req.bits.rs2_data, io.req.bits.rs2_data
connect PipelinedMulUnit.io.req.bits.kill, io.req.bits.kill
connect PipelinedMulUnit.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect PipelinedMulUnit.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect PipelinedMulUnit.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect PipelinedMulUnit.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect PipelinedMulUnit.io.brupdate.b2.taken, io.brupdate.b2.taken
connect PipelinedMulUnit.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect PipelinedMulUnit.io.brupdate.b2.valid, io.brupdate.b2.valid
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect PipelinedMulUnit.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect PipelinedMulUnit.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect PipelinedMulUnit.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect PipelinedMulUnit.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect PipelinedMulUnit.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect PipelinedMulUnit.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect PipelinedMulUnit.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect PipelinedMulUnit.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect PipelinedMulUnit.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect PipelinedMulUnit.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect PipelinedMulUnit.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect PipelinedMulUnit.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect PipelinedMulUnit.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect PipelinedMulUnit.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect PipelinedMulUnit.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect PipelinedMulUnit.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect PipelinedMulUnit.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect PipelinedMulUnit.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect PipelinedMulUnit.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect PipelinedMulUnit.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect PipelinedMulUnit.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect PipelinedMulUnit.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect PipelinedMulUnit.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect PipelinedMulUnit.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect PipelinedMulUnit.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect PipelinedMulUnit.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect PipelinedMulUnit.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect PipelinedMulUnit.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect PipelinedMulUnit.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect PipelinedMulUnit.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect PipelinedMulUnit.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect PipelinedMulUnit.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect PipelinedMulUnit.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect PipelinedMulUnit.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect PipelinedMulUnit.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect PipelinedMulUnit.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect PipelinedMulUnit.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect PipelinedMulUnit.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect PipelinedMulUnit.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect PipelinedMulUnit.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect PipelinedMulUnit.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect PipelinedMulUnit.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect PipelinedMulUnit.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect PipelinedMulUnit.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect PipelinedMulUnit.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect PipelinedMulUnit.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect PipelinedMulUnit.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect PipelinedMulUnit.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect PipelinedMulUnit.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect PipelinedMulUnit.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect PipelinedMulUnit.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect PipelinedMulUnit.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect PipelinedMulUnit.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect PipelinedMulUnit.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect PipelinedMulUnit.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect PipelinedMulUnit.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
wire div_resp_val : UInt<1>
connect div_resp_val, UInt<1>(0h0)
node _io_iresp_valid_T = or(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid)
connect io.iresp.valid, _io_iresp_valid_T
node _io_iresp_bits_uop_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.uop, PipelinedMulUnit.io.resp.bits.uop)
connect io.iresp.bits.uop, _io_iresp_bits_uop_T
node _io_iresp_bits_data_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.data, PipelinedMulUnit.io.resp.bits.data)
connect io.iresp.bits.data, _io_iresp_bits_data_T
node _io_iresp_bits_predicated_T = mux(ALUUnit.io.resp.valid, ALUUnit.io.resp.bits.predicated, PipelinedMulUnit.io.resp.bits.predicated)
connect io.iresp.bits.predicated, _io_iresp_bits_predicated_T
node _io_iresp_bits_uop_csr_addr_sign_T = bits(ALUUnit.io.resp.bits.uop.imm_packed, 19, 19)
node io_iresp_bits_uop_csr_addr_sign = asSInt(_io_iresp_bits_uop_csr_addr_sign_T)
node _io_iresp_bits_uop_csr_addr_i30_20_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i30_20_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 8)
node _io_iresp_bits_uop_csr_addr_i30_20_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i30_20_T_1)
node io_iresp_bits_uop_csr_addr_i30_20 = mux(_io_iresp_bits_uop_csr_addr_i30_20_T, _io_iresp_bits_uop_csr_addr_i30_20_T_2, io_iresp_bits_uop_csr_addr_sign)
node _io_iresp_bits_uop_csr_addr_i19_12_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i19_12_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4))
node _io_iresp_bits_uop_csr_addr_i19_12_T_2 = or(_io_iresp_bits_uop_csr_addr_i19_12_T, _io_iresp_bits_uop_csr_addr_i19_12_T_1)
node _io_iresp_bits_uop_csr_addr_i19_12_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 7, 0)
node _io_iresp_bits_uop_csr_addr_i19_12_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i19_12_T_3)
node io_iresp_bits_uop_csr_addr_i19_12 = mux(_io_iresp_bits_uop_csr_addr_i19_12_T_2, _io_iresp_bits_uop_csr_addr_i19_12_T_4, io_iresp_bits_uop_csr_addr_sign)
node _io_iresp_bits_uop_csr_addr_i11_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i11_T_1 = eq(UInt<3>(0h0), UInt<3>(0h4))
node _io_iresp_bits_uop_csr_addr_i11_T_2 = eq(UInt<3>(0h0), UInt<3>(0h2))
node _io_iresp_bits_uop_csr_addr_i11_T_3 = or(_io_iresp_bits_uop_csr_addr_i11_T_1, _io_iresp_bits_uop_csr_addr_i11_T_2)
node _io_iresp_bits_uop_csr_addr_i11_T_4 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8)
node _io_iresp_bits_uop_csr_addr_i11_T_5 = asSInt(_io_iresp_bits_uop_csr_addr_i11_T_4)
node _io_iresp_bits_uop_csr_addr_i11_T_6 = mux(_io_iresp_bits_uop_csr_addr_i11_T_3, _io_iresp_bits_uop_csr_addr_i11_T_5, io_iresp_bits_uop_csr_addr_sign)
node io_iresp_bits_uop_csr_addr_i11 = mux(_io_iresp_bits_uop_csr_addr_i11_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i11_T_6)
node _io_iresp_bits_uop_csr_addr_i10_5_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i10_5_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 18, 14)
node _io_iresp_bits_uop_csr_addr_i10_5_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i10_5_T_1)
node io_iresp_bits_uop_csr_addr_i10_5 = mux(_io_iresp_bits_uop_csr_addr_i10_5_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i10_5_T_2)
node _io_iresp_bits_uop_csr_addr_i4_1_T = eq(UInt<3>(0h0), UInt<3>(0h3))
node _io_iresp_bits_uop_csr_addr_i4_1_T_1 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 13, 9)
node _io_iresp_bits_uop_csr_addr_i4_1_T_2 = asSInt(_io_iresp_bits_uop_csr_addr_i4_1_T_1)
node io_iresp_bits_uop_csr_addr_i4_1 = mux(_io_iresp_bits_uop_csr_addr_i4_1_T, asSInt(UInt<1>(0h0)), _io_iresp_bits_uop_csr_addr_i4_1_T_2)
node _io_iresp_bits_uop_csr_addr_i0_T = eq(UInt<3>(0h0), UInt<3>(0h1))
node _io_iresp_bits_uop_csr_addr_i0_T_1 = eq(UInt<3>(0h0), UInt<3>(0h0))
node _io_iresp_bits_uop_csr_addr_i0_T_2 = or(_io_iresp_bits_uop_csr_addr_i0_T, _io_iresp_bits_uop_csr_addr_i0_T_1)
node _io_iresp_bits_uop_csr_addr_i0_T_3 = bits(ALUUnit.io.resp.bits.uop.imm_packed, 8, 8)
node _io_iresp_bits_uop_csr_addr_i0_T_4 = asSInt(_io_iresp_bits_uop_csr_addr_i0_T_3)
node io_iresp_bits_uop_csr_addr_i0 = mux(_io_iresp_bits_uop_csr_addr_i0_T_2, _io_iresp_bits_uop_csr_addr_i0_T_4, asSInt(UInt<1>(0h0)))
node io_iresp_bits_uop_csr_addr_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i0)
node io_iresp_bits_uop_csr_addr_lo_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i4_1)
node io_iresp_bits_uop_csr_addr_lo_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_i10_5)
node io_iresp_bits_uop_csr_addr_lo_hi = cat(io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo)
node io_iresp_bits_uop_csr_addr_lo = cat(io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo)
node io_iresp_bits_uop_csr_addr_hi_lo_lo = asUInt(io_iresp_bits_uop_csr_addr_i11)
node io_iresp_bits_uop_csr_addr_hi_lo_hi = asUInt(io_iresp_bits_uop_csr_addr_i19_12)
node io_iresp_bits_uop_csr_addr_hi_lo = cat(io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo)
node io_iresp_bits_uop_csr_addr_hi_hi_lo = asUInt(io_iresp_bits_uop_csr_addr_i30_20)
node io_iresp_bits_uop_csr_addr_hi_hi_hi = asUInt(io_iresp_bits_uop_csr_addr_sign)
node io_iresp_bits_uop_csr_addr_hi_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo)
node io_iresp_bits_uop_csr_addr_hi = cat(io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo)
node _io_iresp_bits_uop_csr_addr_T = cat(io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo)
node _io_iresp_bits_uop_csr_addr_T_1 = asSInt(_io_iresp_bits_uop_csr_addr_T)
node _io_iresp_bits_uop_csr_addr_T_2 = asUInt(_io_iresp_bits_uop_csr_addr_T_1)
connect io.iresp.bits.uop.csr_addr, _io_iresp_bits_uop_csr_addr_T_2
connect io.iresp.bits.uop.ctrl.csr_cmd, ALUUnit.io.resp.bits.uop.ctrl.csr_cmd
node _T_14 = add(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid)
node _T_15 = bits(_T_14, 1, 0)
node _T_16 = leq(_T_15, UInt<1>(0h1))
node _T_17 = eq(div_resp_val, UInt<1>(0h0))
node _T_18 = and(_T_16, _T_17)
node _T_19 = add(ALUUnit.io.resp.valid, PipelinedMulUnit.io.resp.valid)
node _T_20 = bits(_T_19, 1, 0)
node _T_21 = leq(_T_20, UInt<2>(0h2))
node _T_22 = and(_T_21, div_resp_val)
node _T_23 = or(_T_18, _T_22)
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 | module ALUExeUnit_7( // @[execution-unit.scala:204:7]
input clock, // @[execution-unit.scala:204:7]
input reset, // @[execution-unit.scala:204:7]
input io_req_valid, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [15:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_req_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14]
input io_req_bits_kill, // @[execution-unit.scala:104:14]
output io_iresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_iresp_bits_data, // @[execution-unit.scala:104:14]
output io_bypass_0_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_0_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_0_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_0_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_0_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_bypass_0_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_0_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_0_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_0_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_0_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_0_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_0_bits_data, // @[execution-unit.scala:104:14]
output io_bypass_1_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_1_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_1_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_1_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_1_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_1_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_bypass_1_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_1_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_1_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_1_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_1_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_1_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_1_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_1_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_1_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_1_bits_data, // @[execution-unit.scala:104:14]
output io_bypass_2_valid, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_2_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_bypass_2_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_bypass_2_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_bypass_2_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_2_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_bypass_2_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_bypass_2_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_bypass_2_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_bypass_2_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_bypass_2_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_bypass_2_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_bypass_2_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_bypass_2_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_bypass_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_bypass_2_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_bypass_2_bits_data, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_valid, // @[execution-unit.scala:104:14]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14]
input io_brupdate_b2_taken, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_brinfo_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_brinfo_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_brinfo_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_brinfo_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_iw_state, // @[execution-unit.scala:104:14]
output io_brinfo_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_brinfo_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_br, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_jal, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_sfb, // @[execution-unit.scala:104:14]
output [15:0] io_brinfo_uop_br_mask, // @[execution-unit.scala:104:14]
output [3:0] io_brinfo_uop_br_tag, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_brinfo_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_brinfo_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_brinfo_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_brinfo_uop_csr_addr, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_rob_idx, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_pdst, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_prs1, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_prs2, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_prs3, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_ppred, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [6:0] io_brinfo_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_brinfo_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_brinfo_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_brinfo_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_mem_size, // @[execution-unit.scala:104:14]
output io_brinfo_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_fence, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_amo, // @[execution-unit.scala:104:14]
output io_brinfo_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_brinfo_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_brinfo_uop_is_unique, // @[execution-unit.scala:104:14]
output io_brinfo_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_brinfo_uop_lrs3, // @[execution-unit.scala:104:14]
output io_brinfo_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_brinfo_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_brinfo_uop_fp_val, // @[execution-unit.scala:104:14]
output io_brinfo_uop_fp_single, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_brinfo_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output io_brinfo_valid, // @[execution-unit.scala:104:14]
output io_brinfo_mispredict, // @[execution-unit.scala:104:14]
output io_brinfo_taken, // @[execution-unit.scala:104:14]
output [2:0] io_brinfo_cfi_type, // @[execution-unit.scala:104:14]
output [1:0] io_brinfo_pc_sel, // @[execution-unit.scala:104:14]
output [20:0] io_brinfo_target_offset, // @[execution-unit.scala:104:14]
input io_status_debug, // @[execution-unit.scala:104:14]
input io_status_cease, // @[execution-unit.scala:104:14]
input io_status_wfi, // @[execution-unit.scala:104:14]
input [1:0] io_status_dprv, // @[execution-unit.scala:104:14]
input io_status_dv, // @[execution-unit.scala:104:14]
input [1:0] io_status_prv, // @[execution-unit.scala:104:14]
input io_status_v, // @[execution-unit.scala:104:14]
input io_status_sd, // @[execution-unit.scala:104:14]
input io_status_mpv, // @[execution-unit.scala:104:14]
input io_status_gva, // @[execution-unit.scala:104:14]
input io_status_tsr, // @[execution-unit.scala:104:14]
input io_status_tw, // @[execution-unit.scala:104:14]
input io_status_tvm, // @[execution-unit.scala:104:14]
input io_status_mxr, // @[execution-unit.scala:104:14]
input io_status_sum, // @[execution-unit.scala:104:14]
input io_status_mprv, // @[execution-unit.scala:104:14]
input [1:0] io_status_fs, // @[execution-unit.scala:104:14]
input [1:0] io_status_mpp, // @[execution-unit.scala:104:14]
input io_status_spp, // @[execution-unit.scala:104:14]
input io_status_mpie, // @[execution-unit.scala:104:14]
input io_status_spie, // @[execution-unit.scala:104:14]
input io_status_mie, // @[execution-unit.scala:104:14]
input io_status_sie // @[execution-unit.scala:104:14]
);
wire _PipelinedMulUnit_io_resp_valid; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:326:18]
wire [31:0] _PipelinedMulUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:326:18]
wire [31:0] _PipelinedMulUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:326:18]
wire [39:0] _PipelinedMulUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:326:18]
wire [9:0] _PipelinedMulUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:326:18]
wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:326:18]
wire [2:0] _PipelinedMulUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:326:18]
wire [15:0] _PipelinedMulUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:326:18]
wire [3:0] _PipelinedMulUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:326:18]
wire [19:0] _PipelinedMulUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:326:18]
wire [11:0] _PipelinedMulUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:326:18]
wire [6:0] _PipelinedMulUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:326:18]
wire [63:0] _PipelinedMulUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:326:18]
wire [4:0] _PipelinedMulUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:326:18]
wire [5:0] _PipelinedMulUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:326:18]
wire _PipelinedMulUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:326:18]
wire [1:0] _PipelinedMulUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:326:18]
wire [63:0] _PipelinedMulUnit_io_resp_bits_data; // @[execution-unit.scala:326:18]
wire _ALUUnit_io_resp_valid; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_uopc; // @[execution-unit.scala:271:17]
wire [31:0] _ALUUnit_io_resp_bits_uop_inst; // @[execution-unit.scala:271:17]
wire [31:0] _ALUUnit_io_resp_bits_uop_debug_inst; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_rvc; // @[execution-unit.scala:271:17]
wire [39:0] _ALUUnit_io_resp_bits_uop_debug_pc; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_iq_type; // @[execution-unit.scala:271:17]
wire [9:0] _ALUUnit_io_resp_bits_uop_fu_code; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_ctrl_br_type; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:271:17]
wire [2:0] _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_load; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ctrl_is_std; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_iw_state; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_br; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_jalr; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_jal; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_sfb; // @[execution-unit.scala:271:17]
wire [15:0] _ALUUnit_io_resp_bits_uop_br_mask; // @[execution-unit.scala:271:17]
wire [3:0] _ALUUnit_io_resp_bits_uop_br_tag; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ftq_idx; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_edge_inst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_pc_lob; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_taken; // @[execution-unit.scala:271:17]
wire [19:0] _ALUUnit_io_resp_bits_uop_imm_packed; // @[execution-unit.scala:271:17]
wire [11:0] _ALUUnit_io_resp_bits_uop_csr_addr; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_rob_idx; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ldq_idx; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_stq_idx; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_rxq_idx; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_pdst; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_prs1; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_prs2; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_prs3; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_ppred; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs1_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs2_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_prs3_busy; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ppred_busy; // @[execution-unit.scala:271:17]
wire [6:0] _ALUUnit_io_resp_bits_uop_stale_pdst; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_exception; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_resp_bits_uop_exc_cause; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bypassable; // @[execution-unit.scala:271:17]
wire [4:0] _ALUUnit_io_resp_bits_uop_mem_cmd; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_mem_size; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_mem_signed; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_fence; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_fencei; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_amo; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_uses_ldq; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_uses_stq; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_is_unique; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_flush_on_commit; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_ldst; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs1; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs2; // @[execution-unit.scala:271:17]
wire [5:0] _ALUUnit_io_resp_bits_uop_lrs3; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_ldst_val; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_dst_rtype; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_lrs1_rtype; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_lrs2_rtype; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_frs3_en; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_fp_val; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_fp_single; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bp_debug_if; // @[execution-unit.scala:271:17]
wire _ALUUnit_io_resp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_debug_fsrc; // @[execution-unit.scala:271:17]
wire [1:0] _ALUUnit_io_resp_bits_uop_debug_tsrc; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_resp_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_0_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_1_bits_data; // @[execution-unit.scala:271:17]
wire [63:0] _ALUUnit_io_bypass_2_bits_data; // @[execution-unit.scala:271:17]
wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7]
wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7]
wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7]
wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7]
wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7]
wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7]
wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7]
wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7]
wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7]
wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7]
wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7]
wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7]
wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7]
wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7]
wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7]
wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7]
wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7]
wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7]
wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7]
wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7]
wire io_req_ready = 1'h0; // @[execution-unit.scala:204:7]
wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7]
wire div_busy = 1'h0; // @[execution-unit.scala:253:27]
wire ifpu_busy = 1'h0; // @[execution-unit.scala:254:27]
wire _io_fu_types_T_4 = 1'h0; // @[execution-unit.scala:262:32]
wire _io_fu_types_T_12 = 1'h0; // @[execution-unit.scala:265:33]
wire div_resp_val = 1'h0; // @[execution-unit.scala:364:30]
wire _io_iresp_bits_predicated_T = 1'h0; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_csr_addr_i30_20_T = 1'h0; // @[util.scala:274:27]
wire _io_iresp_bits_uop_csr_addr_i19_12_T = 1'h0; // @[util.scala:275:27]
wire _io_iresp_bits_uop_csr_addr_i19_12_T_1 = 1'h0; // @[util.scala:275:44]
wire _io_iresp_bits_uop_csr_addr_i19_12_T_2 = 1'h0; // @[util.scala:275:36]
wire _io_iresp_bits_uop_csr_addr_i11_T = 1'h0; // @[util.scala:276:27]
wire _io_iresp_bits_uop_csr_addr_i11_T_1 = 1'h0; // @[util.scala:277:27]
wire _io_iresp_bits_uop_csr_addr_i11_T_2 = 1'h0; // @[util.scala:277:44]
wire _io_iresp_bits_uop_csr_addr_i11_T_3 = 1'h0; // @[util.scala:277:36]
wire _io_iresp_bits_uop_csr_addr_i10_5_T = 1'h0; // @[util.scala:278:27]
wire _io_iresp_bits_uop_csr_addr_i4_1_T = 1'h0; // @[util.scala:279:27]
wire _io_iresp_bits_uop_csr_addr_i0_T = 1'h0; // @[util.scala:280:27]
wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:204:7]
wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_fu_types = 10'h9; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_2 = 10'h9; // @[execution-unit.scala:260:45]
wire [9:0] _io_fu_types_T_6 = 10'h9; // @[execution-unit.scala:261:45]
wire [9:0] _io_fu_types_T_8 = 10'h9; // @[execution-unit.scala:262:58]
wire [9:0] _io_fu_types_T_10 = 10'h9; // @[execution-unit.scala:263:45]
wire [9:0] _io_fu_types_T_14 = 10'h9; // @[execution-unit.scala:264:49]
wire [9:0] _io_fu_types_T_16 = 10'h9; // @[execution-unit.scala:265:60]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:204:7]
wire io_iresp_ready = 1'h1; // @[execution-unit.scala:204:7]
wire _io_fu_types_T_3 = 1'h1; // @[execution-unit.scala:262:22]
wire _io_fu_types_T_11 = 1'h1; // @[execution-unit.scala:265:22]
wire _io_iresp_bits_uop_csr_addr_i0_T_1 = 1'h1; // @[util.scala:280:44]
wire _io_iresp_bits_uop_csr_addr_i0_T_2 = 1'h1; // @[util.scala:280:36]
wire [6:0] io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:204:7]
wire [39:0] io_brinfo_jalr_target = 40'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_5 = 10'h0; // @[execution-unit.scala:262:21]
wire [9:0] _io_fu_types_T_7 = 10'h0; // @[execution-unit.scala:263:21]
wire [9:0] _io_fu_types_T_9 = 10'h0; // @[execution-unit.scala:264:21]
wire [9:0] _io_fu_types_T_13 = 10'h0; // @[execution-unit.scala:265:21]
wire [9:0] _io_fu_types_T_15 = 10'h0; // @[execution-unit.scala:266:21]
wire [3:0] io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ppred = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:204:7]
wire [15:0] io_iresp_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:204:7]
wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_1 = 10'h8; // @[execution-unit.scala:261:21]
wire [9:0] _io_fu_types_T = 10'h1; // @[execution-unit.scala:260:21]
wire _io_iresp_valid_T; // @[execution-unit.scala:409:71]
wire [6:0] _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70]
wire [31:0] _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
wire [39:0] _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
wire [9:0] _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
wire [15:0] _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
wire [3:0] _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70]
wire [19:0] _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
wire [6:0] _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
wire [4:0] _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
wire [5:0] _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
wire [1:0] _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
wire [3:0] io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_iresp_bits_data_0; // @[execution-unit.scala:204:7]
wire io_iresp_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_0_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_0_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_0_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_0_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_0_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_0_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_0_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_0_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_0_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_0_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_0_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_0_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_0_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_0_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_1_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_1_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_1_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_1_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_1_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_1_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_1_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_1_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_1_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_1_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_1_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_1_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_1_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_1_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_1_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_bypass_2_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_bypass_2_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_bypass_2_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_bypass_2_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_bypass_2_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_bypass_2_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_bypass_2_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_bypass_2_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_bypass_2_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_bypass_2_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_bypass_2_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_bypass_2_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_bypass_2_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_bypass_2_bits_data_0; // @[execution-unit.scala:204:7]
wire io_bypass_2_valid_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_brinfo_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_brinfo_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_brinfo_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_brinfo_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [15:0] io_brinfo_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [3:0] io_brinfo_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_brinfo_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_brinfo_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [6:0] io_brinfo_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_brinfo_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_brinfo_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_brinfo_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_brinfo_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire io_brinfo_valid_0; // @[execution-unit.scala:204:7]
wire io_brinfo_mispredict_0; // @[execution-unit.scala:204:7]
wire io_brinfo_taken_0; // @[execution-unit.scala:204:7]
wire [2:0] io_brinfo_cfi_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_brinfo_pc_sel_0; // @[execution-unit.scala:204:7]
wire [20:0] io_brinfo_target_offset_0; // @[execution-unit.scala:204:7]
assign io_bypass_0_bits_data_0 = {1'h0, _ALUUnit_io_bypass_0_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
assign io_bypass_1_bits_data_0 = {1'h0, _ALUUnit_io_bypass_1_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
assign io_bypass_2_bits_data_0 = {1'h0, _ALUUnit_io_bypass_2_bits_data}; // @[execution-unit.scala:204:7, :271:17, :293:15]
assign _io_iresp_valid_T = _ALUUnit_io_resp_valid | _PipelinedMulUnit_io_resp_valid; // @[execution-unit.scala:271:17, :326:18, :409:71]
assign io_iresp_valid_0 = _io_iresp_valid_T; // @[execution-unit.scala:204:7, :409:71]
assign _io_iresp_bits_uop_T_uopc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uopc : _PipelinedMulUnit_io_resp_bits_uop_uopc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_inst : _PipelinedMulUnit_io_resp_bits_uop_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_inst : _PipelinedMulUnit_io_resp_bits_uop_debug_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_rvc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_rvc : _PipelinedMulUnit_io_resp_bits_uop_is_rvc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_pc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_pc : _PipelinedMulUnit_io_resp_bits_uop_debug_pc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iq_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iq_type : _PipelinedMulUnit_io_resp_bits_uop_iq_type; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_fu_code = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fu_code : _PipelinedMulUnit_io_resp_bits_uop_fu_code; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_br_type = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_br_type : _PipelinedMulUnit_io_resp_bits_uop_ctrl_br_type; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_op1_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op1_sel : _PipelinedMulUnit_io_resp_bits_uop_ctrl_op1_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_op2_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op2_sel : _PipelinedMulUnit_io_resp_bits_uop_ctrl_op2_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_imm_sel = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_imm_sel : _PipelinedMulUnit_io_resp_bits_uop_ctrl_imm_sel; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_op_fcn = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_op_fcn : _PipelinedMulUnit_io_resp_bits_uop_ctrl_op_fcn; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_fcn_dw = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_fcn_dw : _PipelinedMulUnit_io_resp_bits_uop_ctrl_fcn_dw; // @[Mux.scala:50:70]
wire [2:0] _io_iresp_bits_uop_T_ctrl_csr_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_csr_cmd : _PipelinedMulUnit_io_resp_bits_uop_ctrl_csr_cmd; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_is_load = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_load : _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_load; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_is_sta = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_sta : _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_sta; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ctrl_is_std = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ctrl_is_std : _PipelinedMulUnit_io_resp_bits_uop_ctrl_is_std; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iw_state = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_state : _PipelinedMulUnit_io_resp_bits_uop_iw_state; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iw_p1_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p1_poisoned : _PipelinedMulUnit_io_resp_bits_uop_iw_p1_poisoned; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_iw_p2_poisoned = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_iw_p2_poisoned : _PipelinedMulUnit_io_resp_bits_uop_iw_p2_poisoned; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_br = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_br : _PipelinedMulUnit_io_resp_bits_uop_is_br; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_jalr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jalr : _PipelinedMulUnit_io_resp_bits_uop_is_jalr; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_jal = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_jal : _PipelinedMulUnit_io_resp_bits_uop_is_jal; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_sfb = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sfb : _PipelinedMulUnit_io_resp_bits_uop_is_sfb; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_br_mask = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_mask : _PipelinedMulUnit_io_resp_bits_uop_br_mask; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_br_tag = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_br_tag : _PipelinedMulUnit_io_resp_bits_uop_br_tag; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ftq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ftq_idx : _PipelinedMulUnit_io_resp_bits_uop_ftq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_edge_inst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_edge_inst : _PipelinedMulUnit_io_resp_bits_uop_edge_inst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_pc_lob = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pc_lob : _PipelinedMulUnit_io_resp_bits_uop_pc_lob; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_taken = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_taken : _PipelinedMulUnit_io_resp_bits_uop_taken; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_imm_packed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_imm_packed : _PipelinedMulUnit_io_resp_bits_uop_imm_packed; // @[Mux.scala:50:70]
wire [11:0] _io_iresp_bits_uop_T_csr_addr = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_csr_addr : _PipelinedMulUnit_io_resp_bits_uop_csr_addr; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_rob_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rob_idx : _PipelinedMulUnit_io_resp_bits_uop_rob_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldq_idx : _PipelinedMulUnit_io_resp_bits_uop_ldq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_stq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stq_idx : _PipelinedMulUnit_io_resp_bits_uop_stq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_rxq_idx = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_rxq_idx : _PipelinedMulUnit_io_resp_bits_uop_rxq_idx; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_pdst : _PipelinedMulUnit_io_resp_bits_uop_pdst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1 : _PipelinedMulUnit_io_resp_bits_uop_prs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2 : _PipelinedMulUnit_io_resp_bits_uop_prs2; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3 : _PipelinedMulUnit_io_resp_bits_uop_prs3; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ppred = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred : _PipelinedMulUnit_io_resp_bits_uop_ppred; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs1_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs1_busy : _PipelinedMulUnit_io_resp_bits_uop_prs1_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs2_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs2_busy : _PipelinedMulUnit_io_resp_bits_uop_prs2_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_prs3_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_prs3_busy : _PipelinedMulUnit_io_resp_bits_uop_prs3_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ppred_busy = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ppred_busy : _PipelinedMulUnit_io_resp_bits_uop_ppred_busy; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_stale_pdst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_stale_pdst : _PipelinedMulUnit_io_resp_bits_uop_stale_pdst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_exception = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exception : _PipelinedMulUnit_io_resp_bits_uop_exception; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_exc_cause = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_exc_cause : _PipelinedMulUnit_io_resp_bits_uop_exc_cause; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_bypassable = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bypassable : _PipelinedMulUnit_io_resp_bits_uop_bypassable; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_mem_cmd = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_cmd : _PipelinedMulUnit_io_resp_bits_uop_mem_cmd; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_mem_size = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_size : _PipelinedMulUnit_io_resp_bits_uop_mem_size; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_mem_signed = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_mem_signed : _PipelinedMulUnit_io_resp_bits_uop_mem_signed; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_fence = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fence : _PipelinedMulUnit_io_resp_bits_uop_is_fence; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_fencei = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_fencei : _PipelinedMulUnit_io_resp_bits_uop_is_fencei; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_amo = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_amo : _PipelinedMulUnit_io_resp_bits_uop_is_amo; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_uses_ldq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_ldq : _PipelinedMulUnit_io_resp_bits_uop_uses_ldq; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_uses_stq = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_uses_stq : _PipelinedMulUnit_io_resp_bits_uop_uses_stq; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_sys_pc2epc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_sys_pc2epc : _PipelinedMulUnit_io_resp_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_is_unique = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_is_unique : _PipelinedMulUnit_io_resp_bits_uop_is_unique; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_flush_on_commit = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_flush_on_commit : _PipelinedMulUnit_io_resp_bits_uop_flush_on_commit; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldst_is_rs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_is_rs1 : _PipelinedMulUnit_io_resp_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldst = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst : _PipelinedMulUnit_io_resp_bits_uop_ldst; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs1 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1 : _PipelinedMulUnit_io_resp_bits_uop_lrs1; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs2 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2 : _PipelinedMulUnit_io_resp_bits_uop_lrs2; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs3 = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs3 : _PipelinedMulUnit_io_resp_bits_uop_lrs3; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_ldst_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_ldst_val : _PipelinedMulUnit_io_resp_bits_uop_ldst_val; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_dst_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_dst_rtype : _PipelinedMulUnit_io_resp_bits_uop_dst_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs1_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs1_rtype : _PipelinedMulUnit_io_resp_bits_uop_lrs1_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_lrs2_rtype = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_lrs2_rtype : _PipelinedMulUnit_io_resp_bits_uop_lrs2_rtype; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_frs3_en = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_frs3_en : _PipelinedMulUnit_io_resp_bits_uop_frs3_en; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_fp_val = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_val : _PipelinedMulUnit_io_resp_bits_uop_fp_val; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_fp_single = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_fp_single : _PipelinedMulUnit_io_resp_bits_uop_fp_single; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_xcpt_pf_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_pf_if : _PipelinedMulUnit_io_resp_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_xcpt_ae_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ae_if : _PipelinedMulUnit_io_resp_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_xcpt_ma_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_xcpt_ma_if : _PipelinedMulUnit_io_resp_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_bp_debug_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_debug_if : _PipelinedMulUnit_io_resp_bits_uop_bp_debug_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_bp_xcpt_if = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_bp_xcpt_if : _PipelinedMulUnit_io_resp_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_fsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_fsrc : _PipelinedMulUnit_io_resp_bits_uop_debug_fsrc; // @[Mux.scala:50:70]
assign _io_iresp_bits_uop_T_debug_tsrc = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_uop_debug_tsrc : _PipelinedMulUnit_io_resp_bits_uop_debug_tsrc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uopc_0 = _io_iresp_bits_uop_T_uopc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_inst_0 = _io_iresp_bits_uop_T_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_inst_0 = _io_iresp_bits_uop_T_debug_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_rvc_0 = _io_iresp_bits_uop_T_is_rvc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_pc_0 = _io_iresp_bits_uop_T_debug_pc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iq_type_0 = _io_iresp_bits_uop_T_iq_type; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fu_code_0 = _io_iresp_bits_uop_T_fu_code; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_br_type_0 = _io_iresp_bits_uop_T_ctrl_br_type; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op1_sel_0 = _io_iresp_bits_uop_T_ctrl_op1_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op2_sel_0 = _io_iresp_bits_uop_T_ctrl_op2_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_imm_sel_0 = _io_iresp_bits_uop_T_ctrl_imm_sel; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_op_fcn_0 = _io_iresp_bits_uop_T_ctrl_op_fcn; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_fcn_dw_0 = _io_iresp_bits_uop_T_ctrl_fcn_dw; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_load_0 = _io_iresp_bits_uop_T_ctrl_is_load; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_sta_0 = _io_iresp_bits_uop_T_ctrl_is_sta; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ctrl_is_std_0 = _io_iresp_bits_uop_T_ctrl_is_std; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_state_0 = _io_iresp_bits_uop_T_iw_state; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_p1_poisoned_0 = _io_iresp_bits_uop_T_iw_p1_poisoned; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_iw_p2_poisoned_0 = _io_iresp_bits_uop_T_iw_p2_poisoned; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_br_0 = _io_iresp_bits_uop_T_is_br; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_jalr_0 = _io_iresp_bits_uop_T_is_jalr; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_jal_0 = _io_iresp_bits_uop_T_is_jal; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_sfb_0 = _io_iresp_bits_uop_T_is_sfb; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_br_mask_0 = _io_iresp_bits_uop_T_br_mask; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_br_tag_0 = _io_iresp_bits_uop_T_br_tag; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ftq_idx_0 = _io_iresp_bits_uop_T_ftq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_edge_inst_0 = _io_iresp_bits_uop_T_edge_inst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_pc_lob_0 = _io_iresp_bits_uop_T_pc_lob; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_taken_0 = _io_iresp_bits_uop_T_taken; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_imm_packed_0 = _io_iresp_bits_uop_T_imm_packed; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_rob_idx_0 = _io_iresp_bits_uop_T_rob_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldq_idx_0 = _io_iresp_bits_uop_T_ldq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_stq_idx_0 = _io_iresp_bits_uop_T_stq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_rxq_idx_0 = _io_iresp_bits_uop_T_rxq_idx; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_pdst_0 = _io_iresp_bits_uop_T_pdst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs1_0 = _io_iresp_bits_uop_T_prs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs2_0 = _io_iresp_bits_uop_T_prs2; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs3_0 = _io_iresp_bits_uop_T_prs3; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ppred_0 = _io_iresp_bits_uop_T_ppred; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs1_busy_0 = _io_iresp_bits_uop_T_prs1_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs2_busy_0 = _io_iresp_bits_uop_T_prs2_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_prs3_busy_0 = _io_iresp_bits_uop_T_prs3_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ppred_busy_0 = _io_iresp_bits_uop_T_ppred_busy; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_stale_pdst_0 = _io_iresp_bits_uop_T_stale_pdst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_exception_0 = _io_iresp_bits_uop_T_exception; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_exc_cause_0 = _io_iresp_bits_uop_T_exc_cause; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bypassable_0 = _io_iresp_bits_uop_T_bypassable; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_cmd_0 = _io_iresp_bits_uop_T_mem_cmd; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_size_0 = _io_iresp_bits_uop_T_mem_size; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_mem_signed_0 = _io_iresp_bits_uop_T_mem_signed; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_fence_0 = _io_iresp_bits_uop_T_is_fence; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_fencei_0 = _io_iresp_bits_uop_T_is_fencei; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_amo_0 = _io_iresp_bits_uop_T_is_amo; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uses_ldq_0 = _io_iresp_bits_uop_T_uses_ldq; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_uses_stq_0 = _io_iresp_bits_uop_T_uses_stq; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_sys_pc2epc_0 = _io_iresp_bits_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_is_unique_0 = _io_iresp_bits_uop_T_is_unique; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_flush_on_commit_0 = _io_iresp_bits_uop_T_flush_on_commit; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_is_rs1_0 = _io_iresp_bits_uop_T_ldst_is_rs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_0 = _io_iresp_bits_uop_T_ldst; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs1_0 = _io_iresp_bits_uop_T_lrs1; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs2_0 = _io_iresp_bits_uop_T_lrs2; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs3_0 = _io_iresp_bits_uop_T_lrs3; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_ldst_val_0 = _io_iresp_bits_uop_T_ldst_val; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_dst_rtype_0 = _io_iresp_bits_uop_T_dst_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs1_rtype_0 = _io_iresp_bits_uop_T_lrs1_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_lrs2_rtype_0 = _io_iresp_bits_uop_T_lrs2_rtype; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_frs3_en_0 = _io_iresp_bits_uop_T_frs3_en; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fp_val_0 = _io_iresp_bits_uop_T_fp_val; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_fp_single_0 = _io_iresp_bits_uop_T_fp_single; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_pf_if_0 = _io_iresp_bits_uop_T_xcpt_pf_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_ae_if_0 = _io_iresp_bits_uop_T_xcpt_ae_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_xcpt_ma_if_0 = _io_iresp_bits_uop_T_xcpt_ma_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bp_debug_if_0 = _io_iresp_bits_uop_T_bp_debug_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_bp_xcpt_if_0 = _io_iresp_bits_uop_T_bp_xcpt_if; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_fsrc_0 = _io_iresp_bits_uop_T_debug_fsrc; // @[Mux.scala:50:70]
assign io_iresp_bits_uop_debug_tsrc_0 = _io_iresp_bits_uop_T_debug_tsrc; // @[Mux.scala:50:70]
wire [63:0] _io_iresp_bits_data_T = _ALUUnit_io_resp_valid ? _ALUUnit_io_resp_bits_data : _PipelinedMulUnit_io_resp_bits_data; // @[Mux.scala:50:70]
assign io_iresp_bits_data_0 = {1'h0, _io_iresp_bits_data_T}; // @[Mux.scala:50:70]
wire _io_iresp_bits_uop_csr_addr_sign_T = _ALUUnit_io_resp_bits_uop_imm_packed[19]; // @[util.scala:273:18]
wire io_iresp_bits_uop_csr_addr_sign = _io_iresp_bits_uop_csr_addr_sign_T; // @[util.scala:273:{18,37}]
wire _io_iresp_bits_uop_csr_addr_i11_T_6 = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :277:21]
wire io_iresp_bits_uop_csr_addr_hi_hi_hi = io_iresp_bits_uop_csr_addr_sign; // @[util.scala:273:37, :282:15]
wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:8]; // @[util.scala:274:39]
wire [10:0] _io_iresp_bits_uop_csr_addr_i30_20_T_2 = _io_iresp_bits_uop_csr_addr_i30_20_T_1; // @[util.scala:274:{39,46}]
wire [10:0] io_iresp_bits_uop_csr_addr_i30_20 = {11{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :274:21]
wire [10:0] io_iresp_bits_uop_csr_addr_hi_hi_lo = io_iresp_bits_uop_csr_addr_i30_20; // @[util.scala:274:21, :282:15]
wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[7:0]; // @[util.scala:275:56]
wire [7:0] _io_iresp_bits_uop_csr_addr_i19_12_T_4 = _io_iresp_bits_uop_csr_addr_i19_12_T_3; // @[util.scala:275:{56,62}]
wire [7:0] io_iresp_bits_uop_csr_addr_i19_12 = {8{io_iresp_bits_uop_csr_addr_sign}}; // @[util.scala:273:37, :275:21]
wire [7:0] io_iresp_bits_uop_csr_addr_hi_lo_hi = io_iresp_bits_uop_csr_addr_i19_12; // @[util.scala:275:21, :282:15]
wire _io_iresp_bits_uop_csr_addr_i11_T_4 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56]
wire _io_iresp_bits_uop_csr_addr_i0_T_3 = _ALUUnit_io_resp_bits_uop_imm_packed[8]; // @[util.scala:277:56, :280:56]
wire _io_iresp_bits_uop_csr_addr_i11_T_5 = _io_iresp_bits_uop_csr_addr_i11_T_4; // @[util.scala:277:{56,60}]
wire io_iresp_bits_uop_csr_addr_i11 = _io_iresp_bits_uop_csr_addr_i11_T_6; // @[util.scala:276:21, :277:21]
wire io_iresp_bits_uop_csr_addr_hi_lo_lo = io_iresp_bits_uop_csr_addr_i11; // @[util.scala:276:21, :282:15]
wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[18:14]; // @[util.scala:278:44]
wire [4:0] _io_iresp_bits_uop_csr_addr_i10_5_T_2 = _io_iresp_bits_uop_csr_addr_i10_5_T_1; // @[util.scala:278:{44,52}]
wire [4:0] io_iresp_bits_uop_csr_addr_i10_5 = _io_iresp_bits_uop_csr_addr_i10_5_T_2; // @[util.scala:278:{21,52}]
wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_hi = io_iresp_bits_uop_csr_addr_i10_5; // @[util.scala:278:21, :282:15]
wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_1 = _ALUUnit_io_resp_bits_uop_imm_packed[13:9]; // @[util.scala:279:44]
wire [4:0] _io_iresp_bits_uop_csr_addr_i4_1_T_2 = _io_iresp_bits_uop_csr_addr_i4_1_T_1; // @[util.scala:279:{44,51}]
wire [4:0] io_iresp_bits_uop_csr_addr_i4_1 = _io_iresp_bits_uop_csr_addr_i4_1_T_2; // @[util.scala:279:{21,51}]
wire [4:0] io_iresp_bits_uop_csr_addr_lo_hi_lo = io_iresp_bits_uop_csr_addr_i4_1; // @[util.scala:279:21, :282:15]
wire _io_iresp_bits_uop_csr_addr_i0_T_4 = _io_iresp_bits_uop_csr_addr_i0_T_3; // @[util.scala:280:{56,60}]
wire io_iresp_bits_uop_csr_addr_i0 = _io_iresp_bits_uop_csr_addr_i0_T_4; // @[util.scala:280:{21,60}]
wire io_iresp_bits_uop_csr_addr_lo_lo = io_iresp_bits_uop_csr_addr_i0; // @[util.scala:280:21, :282:15]
wire [9:0] io_iresp_bits_uop_csr_addr_lo_hi = {io_iresp_bits_uop_csr_addr_lo_hi_hi, io_iresp_bits_uop_csr_addr_lo_hi_lo}; // @[util.scala:282:15]
wire [10:0] io_iresp_bits_uop_csr_addr_lo = {io_iresp_bits_uop_csr_addr_lo_hi, io_iresp_bits_uop_csr_addr_lo_lo}; // @[util.scala:282:15]
wire [8:0] io_iresp_bits_uop_csr_addr_hi_lo = {io_iresp_bits_uop_csr_addr_hi_lo_hi, io_iresp_bits_uop_csr_addr_hi_lo_lo}; // @[util.scala:282:15]
wire [11:0] io_iresp_bits_uop_csr_addr_hi_hi = {io_iresp_bits_uop_csr_addr_hi_hi_hi, io_iresp_bits_uop_csr_addr_hi_hi_lo}; // @[util.scala:282:15]
wire [20:0] io_iresp_bits_uop_csr_addr_hi = {io_iresp_bits_uop_csr_addr_hi_hi, io_iresp_bits_uop_csr_addr_hi_lo}; // @[util.scala:282:15]
wire [31:0] _io_iresp_bits_uop_csr_addr_T = {io_iresp_bits_uop_csr_addr_hi, io_iresp_bits_uop_csr_addr_lo}; // @[util.scala:282:15]
wire [31:0] _io_iresp_bits_uop_csr_addr_T_1 = _io_iresp_bits_uop_csr_addr_T; // @[util.scala:282:{15,60}]
wire [31:0] _io_iresp_bits_uop_csr_addr_T_2 = _io_iresp_bits_uop_csr_addr_T_1; // @[util.scala:282:60]
assign io_iresp_bits_uop_csr_addr_0 = _io_iresp_bits_uop_csr_addr_T_2[11:0]; // @[execution-unit.scala:204:7, :420:{34,83}] |
Generate the Verilog code corresponding to this FIRRTL code module PE_57 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_57( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_21 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_21( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire notNaN_isSpecialInfOut = io_infiniteExc_0 | io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, io_infiniteExc_0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<6>(0h20))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<6>(0h21))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<6>(0h22))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<6>(0h23))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 5, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 6)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<6>(0h3f))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 5, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 6)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<6>(0h3f))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<6>(0h20))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<6>(0h21))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<6>(0h22))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<6>(0h23))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_64 = shr(io.in.a.bits.source, 6)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<6>(0h3f))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_77 = shr(io.in.a.bits.source, 6)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<6>(0h3f))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<6>(0h20))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<6>(0h21))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<6>(0h22))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<6>(0h23))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 5, 0)
node _T_164 = shr(io.in.a.bits.source, 6)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<6>(0h3f))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 5, 0)
node _T_170 = shr(io.in.a.bits.source, 6)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<6>(0h3f))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_177 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_178 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_179 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = or(_T_197, _T_202)
node _T_204 = and(_T_192, _T_203)
node _T_205 = or(UInt<1>(0h0), _T_204)
node _T_206 = and(_T_191, _T_205)
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_206, UInt<1>(0h1), "") : assert_2
node _T_210 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<6>(0h20))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<6>(0h21))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<6>(0h22))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_229 = shr(io.in.a.bits.source, 2)
node _T_230 = eq(_T_229, UInt<6>(0h23))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 5, 0)
node _T_235 = shr(io.in.a.bits.source, 6)
node _T_236 = eq(_T_235, UInt<1>(0h1))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_16, UInt<6>(0h3f))
node _T_240 = and(_T_238, _T_239)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 5, 0)
node _T_241 = shr(io.in.a.bits.source, 6)
node _T_242 = eq(_T_241, UInt<1>(0h0))
node _T_243 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_244 = and(_T_242, _T_243)
node _T_245 = leq(uncommonBits_17, UInt<6>(0h3f))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_248 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_249 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_210
connect _WIRE[1], _T_216
connect _WIRE[2], _T_222
connect _WIRE[3], _T_228
connect _WIRE[4], _T_234
connect _WIRE[5], _T_240
connect _WIRE[6], _T_246
connect _WIRE[7], _T_247
connect _WIRE[8], _T_248
connect _WIRE[9], _T_249
connect _WIRE[10], _T_250
node _T_251 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_252 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_254 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_258 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_259 = mux(_WIRE[7], _T_251, UInt<1>(0h0))
node _T_260 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_261 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = or(_T_252, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
node _T_267 = or(_T_266, _T_257)
node _T_268 = or(_T_267, _T_258)
node _T_269 = or(_T_268, _T_259)
node _T_270 = or(_T_269, _T_260)
node _T_271 = or(_T_270, _T_261)
node _T_272 = or(_T_271, _T_262)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_272
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<13>(0h1000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<13>(0h1000)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = or(_T_281, _T_286)
node _T_288 = and(_T_276, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = and(_WIRE_1, _T_289)
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_290, UInt<1>(0h1), "") : assert_3
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(source_ok, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_297 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_297, UInt<1>(0h1), "") : assert_5
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(is_aligned, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_304 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_T_304, UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_304, UInt<1>(0h1), "") : assert_7
node _T_308 = not(io.in.a.bits.mask)
node _T_309 = eq(_T_308, UInt<1>(0h0))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_309, UInt<1>(0h1), "") : assert_8
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_313, UInt<1>(0h1), "") : assert_9
node _T_317 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<6>(0h20))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<6>(0h21))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_334 = shr(io.in.a.bits.source, 2)
node _T_335 = eq(_T_334, UInt<6>(0h22))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_340 = shr(io.in.a.bits.source, 2)
node _T_341 = eq(_T_340, UInt<6>(0h23))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_345 = and(_T_343, _T_344)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 5, 0)
node _T_346 = shr(io.in.a.bits.source, 6)
node _T_347 = eq(_T_346, UInt<1>(0h1))
node _T_348 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_349 = and(_T_347, _T_348)
node _T_350 = leq(uncommonBits_22, UInt<6>(0h3f))
node _T_351 = and(_T_349, _T_350)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 5, 0)
node _T_352 = shr(io.in.a.bits.source, 6)
node _T_353 = eq(_T_352, UInt<1>(0h0))
node _T_354 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_355 = and(_T_353, _T_354)
node _T_356 = leq(uncommonBits_23, UInt<6>(0h3f))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_359 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_360 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_361 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_362 = or(_T_321, _T_327)
node _T_363 = or(_T_362, _T_333)
node _T_364 = or(_T_363, _T_339)
node _T_365 = or(_T_364, _T_345)
node _T_366 = or(_T_365, _T_351)
node _T_367 = or(_T_366, _T_357)
node _T_368 = or(_T_367, _T_358)
node _T_369 = or(_T_368, _T_359)
node _T_370 = or(_T_369, _T_360)
node _T_371 = or(_T_370, _T_361)
node _T_372 = and(_T_320, _T_371)
node _T_373 = or(UInt<1>(0h0), _T_372)
node _T_374 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_375 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_376 = cvt(_T_375)
node _T_377 = and(_T_376, asSInt(UInt<13>(0h1000)))
node _T_378 = asSInt(_T_377)
node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0)))
node _T_380 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_381 = cvt(_T_380)
node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000)))
node _T_383 = asSInt(_T_382)
node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0)))
node _T_385 = or(_T_379, _T_384)
node _T_386 = and(_T_374, _T_385)
node _T_387 = or(UInt<1>(0h0), _T_386)
node _T_388 = and(_T_373, _T_387)
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(_T_388, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_388, UInt<1>(0h1), "") : assert_10
node _T_392 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<6>(0h20))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<6>(0h21))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_405 = shr(io.in.a.bits.source, 2)
node _T_406 = eq(_T_405, UInt<6>(0h22))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_410 = and(_T_408, _T_409)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_411 = shr(io.in.a.bits.source, 2)
node _T_412 = eq(_T_411, UInt<6>(0h23))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 5, 0)
node _T_417 = shr(io.in.a.bits.source, 6)
node _T_418 = eq(_T_417, UInt<1>(0h1))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_28, UInt<6>(0h3f))
node _T_422 = and(_T_420, _T_421)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 5, 0)
node _T_423 = shr(io.in.a.bits.source, 6)
node _T_424 = eq(_T_423, UInt<1>(0h0))
node _T_425 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_426 = and(_T_424, _T_425)
node _T_427 = leq(uncommonBits_29, UInt<6>(0h3f))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_430 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_431 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_432 = eq(io.in.a.bits.source, UInt<9>(0h100))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_392
connect _WIRE_2[1], _T_398
connect _WIRE_2[2], _T_404
connect _WIRE_2[3], _T_410
connect _WIRE_2[4], _T_416
connect _WIRE_2[5], _T_422
connect _WIRE_2[6], _T_428
connect _WIRE_2[7], _T_429
connect _WIRE_2[8], _T_430
connect _WIRE_2[9], _T_431
connect _WIRE_2[10], _T_432
node _T_433 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_434 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_435 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_436 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_437 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_438 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_439 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_440 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_441 = mux(_WIRE_2[7], _T_433, UInt<1>(0h0))
node _T_442 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_443 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_444 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_445 = or(_T_434, _T_435)
node _T_446 = or(_T_445, _T_436)
node _T_447 = or(_T_446, _T_437)
node _T_448 = or(_T_447, _T_438)
node _T_449 = or(_T_448, _T_439)
node _T_450 = or(_T_449, _T_440)
node _T_451 = or(_T_450, _T_441)
node _T_452 = or(_T_451, _T_442)
node _T_453 = or(_T_452, _T_443)
node _T_454 = or(_T_453, _T_444)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_454
node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_457 = and(_T_455, _T_456)
node _T_458 = or(UInt<1>(0h0), _T_457)
node _T_459 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<13>(0h1000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<13>(0h1000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = or(_T_463, _T_468)
node _T_470 = and(_T_458, _T_469)
node _T_471 = or(UInt<1>(0h0), _T_470)
node _T_472 = and(_WIRE_3, _T_471)
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_472, UInt<1>(0h1), "") : assert_11
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(source_ok, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_479 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_479, UInt<1>(0h1), "") : assert_13
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(is_aligned, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_486 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_486, UInt<1>(0h1), "") : assert_15
node _T_490 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_490, UInt<1>(0h1), "") : assert_16
node _T_494 = not(io.in.a.bits.mask)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_495, UInt<1>(0h1), "") : assert_17
node _T_499 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_499, UInt<1>(0h1), "") : assert_18
node _T_503 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_503 :
node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_505 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_506 = and(_T_504, _T_505)
node _T_507 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_508 = shr(io.in.a.bits.source, 2)
node _T_509 = eq(_T_508, UInt<6>(0h20))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_514 = shr(io.in.a.bits.source, 2)
node _T_515 = eq(_T_514, UInt<6>(0h21))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_519 = and(_T_517, _T_518)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_520 = shr(io.in.a.bits.source, 2)
node _T_521 = eq(_T_520, UInt<6>(0h22))
node _T_522 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_523 = and(_T_521, _T_522)
node _T_524 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_525 = and(_T_523, _T_524)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_526 = shr(io.in.a.bits.source, 2)
node _T_527 = eq(_T_526, UInt<6>(0h23))
node _T_528 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_529 = and(_T_527, _T_528)
node _T_530 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_531 = and(_T_529, _T_530)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 5, 0)
node _T_532 = shr(io.in.a.bits.source, 6)
node _T_533 = eq(_T_532, UInt<1>(0h1))
node _T_534 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_535 = and(_T_533, _T_534)
node _T_536 = leq(uncommonBits_34, UInt<6>(0h3f))
node _T_537 = and(_T_535, _T_536)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 5, 0)
node _T_538 = shr(io.in.a.bits.source, 6)
node _T_539 = eq(_T_538, UInt<1>(0h0))
node _T_540 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_541 = and(_T_539, _T_540)
node _T_542 = leq(uncommonBits_35, UInt<6>(0h3f))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_545 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_546 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_547 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_548 = or(_T_507, _T_513)
node _T_549 = or(_T_548, _T_519)
node _T_550 = or(_T_549, _T_525)
node _T_551 = or(_T_550, _T_531)
node _T_552 = or(_T_551, _T_537)
node _T_553 = or(_T_552, _T_543)
node _T_554 = or(_T_553, _T_544)
node _T_555 = or(_T_554, _T_545)
node _T_556 = or(_T_555, _T_546)
node _T_557 = or(_T_556, _T_547)
node _T_558 = and(_T_506, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_559, UInt<1>(0h1), "") : assert_19
node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_564 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_565 = and(_T_563, _T_564)
node _T_566 = or(UInt<1>(0h0), _T_565)
node _T_567 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<13>(0h1000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = or(_T_571, _T_576)
node _T_578 = and(_T_566, _T_577)
node _T_579 = or(UInt<1>(0h0), _T_578)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_579, UInt<1>(0h1), "") : assert_20
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(source_ok, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(is_aligned, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_589 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_589, UInt<1>(0h1), "") : assert_23
node _T_593 = eq(io.in.a.bits.mask, mask)
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(_T_593, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_593, UInt<1>(0h1), "") : assert_24
node _T_597 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_597, UInt<1>(0h1), "") : assert_25
node _T_601 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_601 :
node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_606 = shr(io.in.a.bits.source, 2)
node _T_607 = eq(_T_606, UInt<6>(0h20))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_611 = and(_T_609, _T_610)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_612 = shr(io.in.a.bits.source, 2)
node _T_613 = eq(_T_612, UInt<6>(0h21))
node _T_614 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_615 = and(_T_613, _T_614)
node _T_616 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_617 = and(_T_615, _T_616)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_618 = shr(io.in.a.bits.source, 2)
node _T_619 = eq(_T_618, UInt<6>(0h22))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_624 = shr(io.in.a.bits.source, 2)
node _T_625 = eq(_T_624, UInt<6>(0h23))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 5, 0)
node _T_630 = shr(io.in.a.bits.source, 6)
node _T_631 = eq(_T_630, UInt<1>(0h1))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_40, UInt<6>(0h3f))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 5, 0)
node _T_636 = shr(io.in.a.bits.source, 6)
node _T_637 = eq(_T_636, UInt<1>(0h0))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_41, UInt<6>(0h3f))
node _T_641 = and(_T_639, _T_640)
node _T_642 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_643 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_644 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_645 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_646 = or(_T_605, _T_611)
node _T_647 = or(_T_646, _T_617)
node _T_648 = or(_T_647, _T_623)
node _T_649 = or(_T_648, _T_629)
node _T_650 = or(_T_649, _T_635)
node _T_651 = or(_T_650, _T_641)
node _T_652 = or(_T_651, _T_642)
node _T_653 = or(_T_652, _T_643)
node _T_654 = or(_T_653, _T_644)
node _T_655 = or(_T_654, _T_645)
node _T_656 = and(_T_604, _T_655)
node _T_657 = or(UInt<1>(0h0), _T_656)
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_660 = and(_T_658, _T_659)
node _T_661 = or(UInt<1>(0h0), _T_660)
node _T_662 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_663 = cvt(_T_662)
node _T_664 = and(_T_663, asSInt(UInt<13>(0h1000)))
node _T_665 = asSInt(_T_664)
node _T_666 = eq(_T_665, asSInt(UInt<1>(0h0)))
node _T_667 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<13>(0h1000)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = or(_T_666, _T_671)
node _T_673 = and(_T_661, _T_672)
node _T_674 = or(UInt<1>(0h0), _T_673)
node _T_675 = and(_T_657, _T_674)
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(_T_675, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_675, UInt<1>(0h1), "") : assert_26
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(source_ok, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(is_aligned, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_685 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(_T_685, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_685, UInt<1>(0h1), "") : assert_29
node _T_689 = eq(io.in.a.bits.mask, mask)
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_689, UInt<1>(0h1), "") : assert_30
node _T_693 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_693 :
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_696 = and(_T_694, _T_695)
node _T_697 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_698 = shr(io.in.a.bits.source, 2)
node _T_699 = eq(_T_698, UInt<6>(0h20))
node _T_700 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_701 = and(_T_699, _T_700)
node _T_702 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_704 = shr(io.in.a.bits.source, 2)
node _T_705 = eq(_T_704, UInt<6>(0h21))
node _T_706 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_707 = and(_T_705, _T_706)
node _T_708 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_709 = and(_T_707, _T_708)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_710 = shr(io.in.a.bits.source, 2)
node _T_711 = eq(_T_710, UInt<6>(0h22))
node _T_712 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_713 = and(_T_711, _T_712)
node _T_714 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_715 = and(_T_713, _T_714)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_716 = shr(io.in.a.bits.source, 2)
node _T_717 = eq(_T_716, UInt<6>(0h23))
node _T_718 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_719 = and(_T_717, _T_718)
node _T_720 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_721 = and(_T_719, _T_720)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 5, 0)
node _T_722 = shr(io.in.a.bits.source, 6)
node _T_723 = eq(_T_722, UInt<1>(0h1))
node _T_724 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_725 = and(_T_723, _T_724)
node _T_726 = leq(uncommonBits_46, UInt<6>(0h3f))
node _T_727 = and(_T_725, _T_726)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 5, 0)
node _T_728 = shr(io.in.a.bits.source, 6)
node _T_729 = eq(_T_728, UInt<1>(0h0))
node _T_730 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_731 = and(_T_729, _T_730)
node _T_732 = leq(uncommonBits_47, UInt<6>(0h3f))
node _T_733 = and(_T_731, _T_732)
node _T_734 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_735 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_736 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_737 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_738 = or(_T_697, _T_703)
node _T_739 = or(_T_738, _T_709)
node _T_740 = or(_T_739, _T_715)
node _T_741 = or(_T_740, _T_721)
node _T_742 = or(_T_741, _T_727)
node _T_743 = or(_T_742, _T_733)
node _T_744 = or(_T_743, _T_734)
node _T_745 = or(_T_744, _T_735)
node _T_746 = or(_T_745, _T_736)
node _T_747 = or(_T_746, _T_737)
node _T_748 = and(_T_696, _T_747)
node _T_749 = or(UInt<1>(0h0), _T_748)
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_752 = and(_T_750, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<13>(0h1000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = or(_T_758, _T_763)
node _T_765 = and(_T_753, _T_764)
node _T_766 = or(UInt<1>(0h0), _T_765)
node _T_767 = and(_T_749, _T_766)
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_767, UInt<1>(0h1), "") : assert_31
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(source_ok, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(is_aligned, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_777 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_777, UInt<1>(0h1), "") : assert_34
node _T_781 = not(mask)
node _T_782 = and(io.in.a.bits.mask, _T_781)
node _T_783 = eq(_T_782, UInt<1>(0h0))
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(_T_783, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_783, UInt<1>(0h1), "") : assert_35
node _T_787 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_787 :
node _T_788 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_789 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_790 = and(_T_788, _T_789)
node _T_791 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_792 = shr(io.in.a.bits.source, 2)
node _T_793 = eq(_T_792, UInt<6>(0h20))
node _T_794 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_795 = and(_T_793, _T_794)
node _T_796 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_797 = and(_T_795, _T_796)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_798 = shr(io.in.a.bits.source, 2)
node _T_799 = eq(_T_798, UInt<6>(0h21))
node _T_800 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_801 = and(_T_799, _T_800)
node _T_802 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_803 = and(_T_801, _T_802)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_804 = shr(io.in.a.bits.source, 2)
node _T_805 = eq(_T_804, UInt<6>(0h22))
node _T_806 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_807 = and(_T_805, _T_806)
node _T_808 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_809 = and(_T_807, _T_808)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_810 = shr(io.in.a.bits.source, 2)
node _T_811 = eq(_T_810, UInt<6>(0h23))
node _T_812 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_813 = and(_T_811, _T_812)
node _T_814 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_815 = and(_T_813, _T_814)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 5, 0)
node _T_816 = shr(io.in.a.bits.source, 6)
node _T_817 = eq(_T_816, UInt<1>(0h1))
node _T_818 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_819 = and(_T_817, _T_818)
node _T_820 = leq(uncommonBits_52, UInt<6>(0h3f))
node _T_821 = and(_T_819, _T_820)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 5, 0)
node _T_822 = shr(io.in.a.bits.source, 6)
node _T_823 = eq(_T_822, UInt<1>(0h0))
node _T_824 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_825 = and(_T_823, _T_824)
node _T_826 = leq(uncommonBits_53, UInt<6>(0h3f))
node _T_827 = and(_T_825, _T_826)
node _T_828 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_829 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_830 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_831 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_832 = or(_T_791, _T_797)
node _T_833 = or(_T_832, _T_803)
node _T_834 = or(_T_833, _T_809)
node _T_835 = or(_T_834, _T_815)
node _T_836 = or(_T_835, _T_821)
node _T_837 = or(_T_836, _T_827)
node _T_838 = or(_T_837, _T_828)
node _T_839 = or(_T_838, _T_829)
node _T_840 = or(_T_839, _T_830)
node _T_841 = or(_T_840, _T_831)
node _T_842 = and(_T_790, _T_841)
node _T_843 = or(UInt<1>(0h0), _T_842)
node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_845 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_846 = cvt(_T_845)
node _T_847 = and(_T_846, asSInt(UInt<13>(0h1000)))
node _T_848 = asSInt(_T_847)
node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0)))
node _T_850 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_851 = cvt(_T_850)
node _T_852 = and(_T_851, asSInt(UInt<13>(0h1000)))
node _T_853 = asSInt(_T_852)
node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0)))
node _T_855 = or(_T_849, _T_854)
node _T_856 = and(_T_844, _T_855)
node _T_857 = or(UInt<1>(0h0), _T_856)
node _T_858 = and(_T_843, _T_857)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_858, UInt<1>(0h1), "") : assert_36
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(source_ok, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(is_aligned, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_868, UInt<1>(0h1), "") : assert_39
node _T_872 = eq(io.in.a.bits.mask, mask)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_872, UInt<1>(0h1), "") : assert_40
node _T_876 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_876 :
node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_879 = and(_T_877, _T_878)
node _T_880 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_881 = shr(io.in.a.bits.source, 2)
node _T_882 = eq(_T_881, UInt<6>(0h20))
node _T_883 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_884 = and(_T_882, _T_883)
node _T_885 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_886 = and(_T_884, _T_885)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_887 = shr(io.in.a.bits.source, 2)
node _T_888 = eq(_T_887, UInt<6>(0h21))
node _T_889 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_890 = and(_T_888, _T_889)
node _T_891 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_892 = and(_T_890, _T_891)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_893 = shr(io.in.a.bits.source, 2)
node _T_894 = eq(_T_893, UInt<6>(0h22))
node _T_895 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_896 = and(_T_894, _T_895)
node _T_897 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_898 = and(_T_896, _T_897)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_899 = shr(io.in.a.bits.source, 2)
node _T_900 = eq(_T_899, UInt<6>(0h23))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_904 = and(_T_902, _T_903)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 5, 0)
node _T_905 = shr(io.in.a.bits.source, 6)
node _T_906 = eq(_T_905, UInt<1>(0h1))
node _T_907 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_908 = and(_T_906, _T_907)
node _T_909 = leq(uncommonBits_58, UInt<6>(0h3f))
node _T_910 = and(_T_908, _T_909)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 5, 0)
node _T_911 = shr(io.in.a.bits.source, 6)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_914 = and(_T_912, _T_913)
node _T_915 = leq(uncommonBits_59, UInt<6>(0h3f))
node _T_916 = and(_T_914, _T_915)
node _T_917 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_918 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_919 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_920 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_921 = or(_T_880, _T_886)
node _T_922 = or(_T_921, _T_892)
node _T_923 = or(_T_922, _T_898)
node _T_924 = or(_T_923, _T_904)
node _T_925 = or(_T_924, _T_910)
node _T_926 = or(_T_925, _T_916)
node _T_927 = or(_T_926, _T_917)
node _T_928 = or(_T_927, _T_918)
node _T_929 = or(_T_928, _T_919)
node _T_930 = or(_T_929, _T_920)
node _T_931 = and(_T_879, _T_930)
node _T_932 = or(UInt<1>(0h0), _T_931)
node _T_933 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_934 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<13>(0h1000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = or(_T_938, _T_943)
node _T_945 = and(_T_933, _T_944)
node _T_946 = or(UInt<1>(0h0), _T_945)
node _T_947 = and(_T_932, _T_946)
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_947, UInt<1>(0h1), "") : assert_41
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(source_ok, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(is_aligned, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_957 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_957, UInt<1>(0h1), "") : assert_44
node _T_961 = eq(io.in.a.bits.mask, mask)
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_T_961, UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_961, UInt<1>(0h1), "") : assert_45
node _T_965 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_965 :
node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_968 = and(_T_966, _T_967)
node _T_969 = eq(io.in.a.bits.source, UInt<8>(0h90))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_970 = shr(io.in.a.bits.source, 2)
node _T_971 = eq(_T_970, UInt<6>(0h20))
node _T_972 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_973 = and(_T_971, _T_972)
node _T_974 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_975 = and(_T_973, _T_974)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_976 = shr(io.in.a.bits.source, 2)
node _T_977 = eq(_T_976, UInt<6>(0h21))
node _T_978 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_979 = and(_T_977, _T_978)
node _T_980 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_981 = and(_T_979, _T_980)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_982 = shr(io.in.a.bits.source, 2)
node _T_983 = eq(_T_982, UInt<6>(0h22))
node _T_984 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_985 = and(_T_983, _T_984)
node _T_986 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_987 = and(_T_985, _T_986)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_988 = shr(io.in.a.bits.source, 2)
node _T_989 = eq(_T_988, UInt<6>(0h23))
node _T_990 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_991 = and(_T_989, _T_990)
node _T_992 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_993 = and(_T_991, _T_992)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 5, 0)
node _T_994 = shr(io.in.a.bits.source, 6)
node _T_995 = eq(_T_994, UInt<1>(0h1))
node _T_996 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_997 = and(_T_995, _T_996)
node _T_998 = leq(uncommonBits_64, UInt<6>(0h3f))
node _T_999 = and(_T_997, _T_998)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 5, 0)
node _T_1000 = shr(io.in.a.bits.source, 6)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
node _T_1002 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1003 = and(_T_1001, _T_1002)
node _T_1004 = leq(uncommonBits_65, UInt<6>(0h3f))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = eq(io.in.a.bits.source, UInt<8>(0ha0))
node _T_1007 = eq(io.in.a.bits.source, UInt<8>(0ha1))
node _T_1008 = eq(io.in.a.bits.source, UInt<8>(0ha2))
node _T_1009 = eq(io.in.a.bits.source, UInt<9>(0h100))
node _T_1010 = or(_T_969, _T_975)
node _T_1011 = or(_T_1010, _T_981)
node _T_1012 = or(_T_1011, _T_987)
node _T_1013 = or(_T_1012, _T_993)
node _T_1014 = or(_T_1013, _T_999)
node _T_1015 = or(_T_1014, _T_1005)
node _T_1016 = or(_T_1015, _T_1006)
node _T_1017 = or(_T_1016, _T_1007)
node _T_1018 = or(_T_1017, _T_1008)
node _T_1019 = or(_T_1018, _T_1009)
node _T_1020 = and(_T_968, _T_1019)
node _T_1021 = or(UInt<1>(0h0), _T_1020)
node _T_1022 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1023 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1024 = cvt(_T_1023)
node _T_1025 = and(_T_1024, asSInt(UInt<13>(0h1000)))
node _T_1026 = asSInt(_T_1025)
node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0)))
node _T_1028 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1029 = cvt(_T_1028)
node _T_1030 = and(_T_1029, asSInt(UInt<13>(0h1000)))
node _T_1031 = asSInt(_T_1030)
node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0)))
node _T_1033 = or(_T_1027, _T_1032)
node _T_1034 = and(_T_1022, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_1034)
node _T_1036 = and(_T_1021, _T_1035)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_46
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(source_ok, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(is_aligned, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1046 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_49
node _T_1050 = eq(io.in.a.bits.mask, mask)
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_50
node _T_1054 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1058 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<8>(0h90))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<6>(0h20))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<6>(0h21))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<6>(0h22))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<6>(0h23))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 5, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 6)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<6>(0h3f))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 5, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 6)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<6>(0h3f))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0ha0))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<8>(0ha1))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<8>(0ha2))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<9>(0h100))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1062 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1062 :
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(source_ok_1, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1066 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_54
node _T_1070 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_55
node _T_1074 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_56
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_57
node _T_1082 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1082 :
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(source_ok_1, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(sink_ok, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1089 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_T_1089, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1089, UInt<1>(0h1), "") : assert_60
node _T_1093 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_61
node _T_1097 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_62
node _T_1101 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_63
node _T_1105 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1106 = or(UInt<1>(0h0), _T_1105)
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_64
node _T_1110 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1110 :
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(source_ok_1, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(sink_ok, UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1117 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_67
node _T_1121 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_68
node _T_1125 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_69
node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1130 = or(_T_1129, io.in.d.bits.corrupt)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_70
node _T_1134 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1135 = or(UInt<1>(0h0), _T_1134)
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_71
node _T_1139 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(source_ok_1, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1143 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_73
node _T_1147 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_74
node _T_1151 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1152 = or(UInt<1>(0h0), _T_1151)
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_75
node _T_1156 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1156 :
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(source_ok_1, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1160 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_77
node _T_1164 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1165 = or(_T_1164, io.in.d.bits.corrupt)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_78
node _T_1169 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1170 = or(UInt<1>(0h0), _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_79
node _T_1174 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1174 :
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(source_ok_1, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1178 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_81
node _T_1182 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_82
node _T_1186 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1187 = or(UInt<1>(0h0), _T_1186)
node _T_1188 = asUInt(reset)
node _T_1189 = eq(_T_1188, UInt<1>(0h0))
when _T_1189 :
node _T_1190 = eq(_T_1187, UInt<1>(0h0))
when _T_1190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1187, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<9>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<9>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1191 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<9>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1195 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1199 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1203 = eq(a_first, UInt<1>(0h0))
node _T_1204 = and(io.in.a.valid, _T_1203)
when _T_1204 :
node _T_1205 = eq(io.in.a.bits.opcode, opcode)
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_87
node _T_1209 = eq(io.in.a.bits.param, param)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_88
node _T_1213 = eq(io.in.a.bits.size, size)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_89
node _T_1217 = eq(io.in.a.bits.source, source)
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_90
node _T_1221 = eq(io.in.a.bits.address, address)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_91
node _T_1225 = and(io.in.a.ready, io.in.a.valid)
node _T_1226 = and(_T_1225, a_first)
when _T_1226 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1227 = eq(d_first, UInt<1>(0h0))
node _T_1228 = and(io.in.d.valid, _T_1227)
when _T_1228 :
node _T_1229 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_92
node _T_1233 = eq(io.in.d.bits.param, param_1)
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_93
node _T_1237 = eq(io.in.d.bits.size, size_1)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_94
node _T_1241 = eq(io.in.d.bits.source, source_1)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_95
node _T_1245 = eq(io.in.d.bits.sink, sink)
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_96
node _T_1249 = eq(io.in.d.bits.denied, denied)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_97
node _T_1253 = and(io.in.d.ready, io.in.d.valid)
node _T_1254 = and(_T_1253, d_first)
when _T_1254 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes : UInt<1028>, clock, reset, UInt<1028>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<257>
connect a_set, UInt<257>(0h0)
wire a_set_wo_ready : UInt<257>
connect a_set_wo_ready, UInt<257>(0h0)
wire a_opcodes_set : UInt<1028>
connect a_opcodes_set, UInt<1028>(0h0)
wire a_sizes_set : UInt<1028>
connect a_sizes_set, UInt<1028>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1255 = and(io.in.a.valid, a_first_1)
node _T_1256 = and(_T_1255, UInt<1>(0h1))
when _T_1256 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1257 = and(io.in.a.ready, io.in.a.valid)
node _T_1258 = and(_T_1257, a_first_1)
node _T_1259 = and(_T_1258, UInt<1>(0h1))
when _T_1259 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1260 = dshr(inflight, io.in.a.bits.source)
node _T_1261 = bits(_T_1260, 0, 0)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<257>
connect d_clr, UInt<257>(0h0)
wire d_clr_wo_ready : UInt<257>
connect d_clr_wo_ready, UInt<257>(0h0)
wire d_opcodes_clr : UInt<1028>
connect d_opcodes_clr, UInt<1028>(0h0)
wire d_sizes_clr : UInt<1028>
connect d_sizes_clr, UInt<1028>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1266 = and(io.in.d.valid, d_first_1)
node _T_1267 = and(_T_1266, UInt<1>(0h1))
node _T_1268 = eq(d_release_ack, UInt<1>(0h0))
node _T_1269 = and(_T_1267, _T_1268)
when _T_1269 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1270 = and(io.in.d.ready, io.in.d.valid)
node _T_1271 = and(_T_1270, d_first_1)
node _T_1272 = and(_T_1271, UInt<1>(0h1))
node _T_1273 = eq(d_release_ack, UInt<1>(0h0))
node _T_1274 = and(_T_1272, _T_1273)
when _T_1274 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1275 = and(io.in.d.valid, d_first_1)
node _T_1276 = and(_T_1275, UInt<1>(0h1))
node _T_1277 = eq(d_release_ack, UInt<1>(0h0))
node _T_1278 = and(_T_1276, _T_1277)
when _T_1278 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1279 = dshr(inflight, io.in.d.bits.source)
node _T_1280 = bits(_T_1279, 0, 0)
node _T_1281 = or(_T_1280, same_cycle_resp)
node _T_1282 = asUInt(reset)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = eq(_T_1281, UInt<1>(0h0))
when _T_1284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1281, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1285 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1286 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1287 = or(_T_1285, _T_1286)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_100
node _T_1291 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_101
else :
node _T_1295 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1296 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1297 = or(_T_1295, _T_1296)
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_102
node _T_1301 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_103
node _T_1305 = and(io.in.d.valid, d_first_1)
node _T_1306 = and(_T_1305, a_first_1)
node _T_1307 = and(_T_1306, io.in.a.valid)
node _T_1308 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1309 = and(_T_1307, _T_1308)
node _T_1310 = eq(d_release_ack, UInt<1>(0h0))
node _T_1311 = and(_T_1309, _T_1310)
when _T_1311 :
node _T_1312 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1313 = or(_T_1312, io.in.a.ready)
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(_T_1313, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1313, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_10
node _T_1317 = orr(inflight)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
node _T_1319 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1320 = or(_T_1318, _T_1319)
node _T_1321 = lt(watchdog, plusarg_reader.out)
node _T_1322 = or(_T_1320, _T_1321)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1326 = and(io.in.a.ready, io.in.a.valid)
node _T_1327 = and(io.in.d.ready, io.in.d.valid)
node _T_1328 = or(_T_1326, _T_1327)
when _T_1328 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<257>, clock, reset, UInt<257>(0h0)
regreset inflight_opcodes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
regreset inflight_sizes_1 : UInt<1028>, clock, reset, UInt<1028>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<9>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<257>
connect c_set, UInt<257>(0h0)
wire c_set_wo_ready : UInt<257>
connect c_set_wo_ready, UInt<257>(0h0)
wire c_opcodes_set : UInt<1028>
connect c_opcodes_set, UInt<1028>(0h0)
wire c_sizes_set : UInt<1028>
connect c_sizes_set, UInt<1028>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<9>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1329 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<9>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1330 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1331 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1332 = and(_T_1330, _T_1331)
node _T_1333 = and(_T_1329, _T_1332)
when _T_1333 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<9>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1334 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1335 = and(_T_1334, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<9>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1336 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1337 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = and(_T_1335, _T_1338)
when _T_1339 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<9>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1340 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1341 = bits(_T_1340, 0, 0)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
node _T_1343 = asUInt(reset)
node _T_1344 = eq(_T_1343, UInt<1>(0h0))
when _T_1344 :
node _T_1345 = eq(_T_1342, UInt<1>(0h0))
when _T_1345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1342, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<257>
connect d_clr_1, UInt<257>(0h0)
wire d_clr_wo_ready_1 : UInt<257>
connect d_clr_wo_ready_1, UInt<257>(0h0)
wire d_opcodes_clr_1 : UInt<1028>
connect d_opcodes_clr_1, UInt<1028>(0h0)
wire d_sizes_clr_1 : UInt<1028>
connect d_sizes_clr_1, UInt<1028>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1346 = and(io.in.d.valid, d_first_2)
node _T_1347 = and(_T_1346, UInt<1>(0h1))
node _T_1348 = and(_T_1347, d_release_ack_1)
when _T_1348 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1349 = and(io.in.d.ready, io.in.d.valid)
node _T_1350 = and(_T_1349, d_first_2)
node _T_1351 = and(_T_1350, UInt<1>(0h1))
node _T_1352 = and(_T_1351, d_release_ack_1)
when _T_1352 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1353 = and(io.in.d.valid, d_first_2)
node _T_1354 = and(_T_1353, UInt<1>(0h1))
node _T_1355 = and(_T_1354, d_release_ack_1)
when _T_1355 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1356 = dshr(inflight_1, io.in.d.bits.source)
node _T_1357 = bits(_T_1356, 0, 0)
node _T_1358 = or(_T_1357, same_cycle_resp_1)
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<9>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1362 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_108
else :
node _T_1366 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_109
node _T_1370 = and(io.in.d.valid, d_first_2)
node _T_1371 = and(_T_1370, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<9>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1372 = and(_T_1371, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<9>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1373 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1374 = and(_T_1372, _T_1373)
node _T_1375 = and(_T_1374, d_release_ack_1)
node _T_1376 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1377 = and(_T_1375, _T_1376)
when _T_1377 :
node _T_1378 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<9>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1379 = or(_T_1378, _WIRE_27.ready)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_11
node _T_1383 = orr(inflight_1)
node _T_1384 = eq(_T_1383, UInt<1>(0h0))
node _T_1385 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1386 = or(_T_1384, _T_1385)
node _T_1387 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1388 = or(_T_1386, _T_1387)
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<9>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1392 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1393 = and(io.in.d.ready, io.in.d.valid)
node _T_1394 = or(_T_1392, _T_1393)
when _T_1394 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_5( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [8:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [8:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_source = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_source = 9'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [4098:0] _c_opcodes_set_T_1 = 4099'h0; // @[Monitor.scala:767:54]
wire [4098:0] _c_sizes_set_T_1 = 4099'h0; // @[Monitor.scala:768:52]
wire [11:0] _c_opcodes_set_T = 12'h0; // @[Monitor.scala:767:79]
wire [11:0] _c_sizes_set_T = 12'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [511:0] _c_set_wo_ready_T = 512'h1; // @[OneHot.scala:58:35]
wire [511:0] _c_set_T = 512'h1; // @[OneHot.scala:58:35]
wire [1027:0] c_opcodes_set = 1028'h0; // @[Monitor.scala:740:34]
wire [1027:0] c_sizes_set = 1028'h0; // @[Monitor.scala:741:34]
wire [256:0] c_set = 257'h0; // @[Monitor.scala:738:34]
wire [256:0] c_set_wo_ready = 257'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [8:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [8:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_1 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_7 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_13 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_19 = io_in_a_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_25 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_31 = io_in_a_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_4 = _uncommonBits_T_4[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_5 = _uncommonBits_T_5[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_10 = _uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_11 = _uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_16 = _uncommonBits_T_16[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_17 = _uncommonBits_T_17[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_22 = _uncommonBits_T_22[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_23 = _uncommonBits_T_23[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_28 = _uncommonBits_T_28[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_29 = _uncommonBits_T_29[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_34 = _uncommonBits_T_34[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_35 = _uncommonBits_T_35[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_40 = _uncommonBits_T_40[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_41 = _uncommonBits_T_41[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_46 = _uncommonBits_T_46[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_47 = _uncommonBits_T_47[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_52 = _uncommonBits_T_52[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_53 = _uncommonBits_T_53[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_58 = _uncommonBits_T_58[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_59 = _uncommonBits_T_59[5:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_64 = _uncommonBits_T_64[5:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] uncommonBits_65 = _uncommonBits_T_65[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 9'h90; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [6:0] _source_ok_T_51 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_57 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_63 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_T_69 = io_in_d_bits_source_0[8:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 7'h20; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 7'h21; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 7'h22; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 7'h23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[5:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_75 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_81 = io_in_d_bits_source_0[8:6]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [5:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[5:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 9'hA0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 9'hA1; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 9'hA2; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 9'h100; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1326 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1326; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1326; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [8:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1394 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1394; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1394; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1394; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [8:0] source_1; // @[Monitor.scala:541:22]
reg [256:0] inflight; // @[Monitor.scala:614:27]
reg [1027:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1027:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [256:0] a_set; // @[Monitor.scala:626:34]
wire [256:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [1027:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1027:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [11:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [11:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [11:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [11:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [11:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [11:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [11:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [11:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [11:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [1027:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [1027:0] _a_opcode_lookup_T_6 = {1024'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [1027:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [1027:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1027:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [1027:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1027:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [511:0] _GEN_2 = 512'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [511:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1259 = _T_1326 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1259 ? _a_set_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1259 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1259 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [11:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [11:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [11:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [4098:0] _a_opcodes_set_T_1 = {4095'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1259 ? _a_opcodes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4098:0] _a_sizes_set_T_1 = {4095'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1259 ? _a_sizes_set_T_1[1027:0] : 1028'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [256:0] d_clr; // @[Monitor.scala:664:34]
wire [256:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [1027:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1027:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1305 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [511:0] _GEN_5 = 512'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [511:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1305 & ~d_release_ack ? _d_clr_wo_ready_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1274 = _T_1394 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1274 ? _d_clr_T[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_5 = 4111'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1274 ? _d_opcodes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [4110:0] _d_sizes_clr_T_5 = 4111'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1274 ? _d_sizes_clr_T_5[1027:0] : 1028'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [256:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [256:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [256:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [1027:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [1027:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [1027:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1027:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1027:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1027:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [256:0] inflight_1; // @[Monitor.scala:726:35]
wire [256:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [1027:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [1027:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1027:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1027:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [1027:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [1027:0] _c_opcode_lookup_T_6 = {1024'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [1027:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[1027:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1027:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1027:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [1027:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1027:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [256:0] d_clr_1; // @[Monitor.scala:774:34]
wire [256:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [1027:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1027:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1370 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1370 & d_release_ack_1 ? _d_clr_wo_ready_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire _T_1352 = _T_1394 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1352 ? _d_clr_T_1[256:0] : 257'h0; // @[OneHot.scala:58:35]
wire [4110:0] _d_opcodes_clr_T_11 = 4111'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1352 ? _d_opcodes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [4110:0] _d_sizes_clr_T_11 = 4111'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1352 ? _d_sizes_clr_T_11[1027:0] : 1028'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 9'h0; // @[Monitor.scala:36:7, :795:113]
wire [256:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [256:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [1027:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [1027:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1027:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1027:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLAToBeat_SerialRAM_a64d64s8k8z8c :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, beat : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}}
inst q of Queue1_TLBundleA_a64d64s8k8z8c
connect q.clock, clock
connect q.reset, reset
connect q.io.enq, io.protocol
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0))
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0))
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data)
node body = cat(body_hi, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.beat.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.beat.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_beat_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_beat_bits_head_T_1 = and(head, _io_beat_bits_head_T)
connect io.beat.bits.head, _io_beat_bits_head_T_1
node _io_beat_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_beat_bits_tail_T_1 = or(is_body, _io_beat_bits_tail_T)
node _io_beat_bits_tail_T_2 = and(tail, _io_beat_bits_tail_T_1)
connect io.beat.bits.tail, _io_beat_bits_tail_T_2
node _io_beat_bits_payload_T = mux(is_body, body, const)
connect io.beat.bits.payload, _io_beat_bits_payload_T
node _T = and(io.beat.ready, io.beat.valid)
node _T_1 = and(_T, io.beat.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.beat.ready, io.beat.valid)
node _T_3 = and(_T_2, io.beat.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0))
node _has_body_T = not(q.io.deq.bits.mask)
node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0))
node _has_body_T_2 = or(has_body_opdata, _has_body_T_1)
connect has_body, _has_body_T_2 | module TLAToBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:108:7]
input clock, // @[TLChannelCompactor.scala:108:7]
input reset, // @[TLChannelCompactor.scala:108:7]
output io_protocol_ready, // @[TLChannelCompactor.scala:40:14]
input io_protocol_valid, // @[TLChannelCompactor.scala:40:14]
input [2:0] io_protocol_bits_opcode, // @[TLChannelCompactor.scala:40:14]
input [2:0] io_protocol_bits_param, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_size, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_source, // @[TLChannelCompactor.scala:40:14]
input [63:0] io_protocol_bits_address, // @[TLChannelCompactor.scala:40:14]
input [7:0] io_protocol_bits_mask, // @[TLChannelCompactor.scala:40:14]
input [63:0] io_protocol_bits_data, // @[TLChannelCompactor.scala:40:14]
input io_protocol_bits_corrupt, // @[TLChannelCompactor.scala:40:14]
input io_beat_ready, // @[TLChannelCompactor.scala:40:14]
output io_beat_valid, // @[TLChannelCompactor.scala:40:14]
output [85:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_head, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_tail // @[TLChannelCompactor.scala:40:14]
);
wire _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TLChannelCompactor.scala:47:17]
wire [2:0] _q_io_deq_bits_param; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_source; // @[TLChannelCompactor.scala:47:17]
wire [63:0] _q_io_deq_bits_address; // @[TLChannelCompactor.scala:47:17]
wire [7:0] _q_io_deq_bits_mask; // @[TLChannelCompactor.scala:47:17]
wire [63:0] _q_io_deq_bits_data; // @[TLChannelCompactor.scala:47:17]
wire _q_io_deq_bits_corrupt; // @[TLChannelCompactor.scala:47:17]
wire io_protocol_valid_0 = io_protocol_valid; // @[TLChannelCompactor.scala:108:7]
wire [2:0] io_protocol_bits_opcode_0 = io_protocol_bits_opcode; // @[TLChannelCompactor.scala:108:7]
wire [2:0] io_protocol_bits_param_0 = io_protocol_bits_param; // @[TLChannelCompactor.scala:108:7]
wire [7:0] io_protocol_bits_size_0 = io_protocol_bits_size; // @[TLChannelCompactor.scala:108:7]
wire [7:0] io_protocol_bits_source_0 = io_protocol_bits_source; // @[TLChannelCompactor.scala:108:7]
wire [63:0] io_protocol_bits_address_0 = io_protocol_bits_address; // @[TLChannelCompactor.scala:108:7]
wire [7:0] io_protocol_bits_mask_0 = io_protocol_bits_mask; // @[TLChannelCompactor.scala:108:7]
wire [63:0] io_protocol_bits_data_0 = io_protocol_bits_data; // @[TLChannelCompactor.scala:108:7]
wire io_protocol_bits_corrupt_0 = io_protocol_bits_corrupt; // @[TLChannelCompactor.scala:108:7]
wire io_beat_ready_0 = io_beat_ready; // @[TLChannelCompactor.scala:108:7]
wire [85:0] _io_beat_bits_payload_T; // @[TLChannelCompactor.scala:66:33]
wire _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35]
wire _io_beat_bits_tail_T_2; // @[TLChannelCompactor.scala:65:35]
wire io_protocol_ready_0; // @[TLChannelCompactor.scala:108:7]
wire [85:0] io_beat_bits_payload_0; // @[TLChannelCompactor.scala:108:7]
wire io_beat_bits_head_0; // @[TLChannelCompactor.scala:108:7]
wire io_beat_bits_tail_0; // @[TLChannelCompactor.scala:108:7]
wire io_beat_valid_0; // @[TLChannelCompactor.scala:108:7]
wire _has_body_T_2; // @[TLChannelCompactor.scala:109:45]
wire has_body; // @[TLChannelCompactor.scala:51:22]
wire _q_io_deq_ready_T_2; // @[TLChannelCompactor.scala:62:35]
wire _GEN = _q_io_deq_ready_T_2 & _q_io_deq_valid; // @[Decoupled.scala:51:35]
wire _head_T; // @[Decoupled.scala:51:35]
assign _head_T = _GEN; // @[Decoupled.scala:51:35]
wire _tail_T; // @[Decoupled.scala:51:35]
assign _tail_T = _GEN; // @[Decoupled.scala:51:35]
wire [266:0] _GEN_0 = 267'hFFF << _q_io_deq_bits_size; // @[TLChannelCompactor.scala:47:17]
wire [266:0] _head_beats1_decode_T; // @[package.scala:243:71]
assign _head_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [266:0] _tail_beats1_decode_T; // @[package.scala:243:71]
assign _tail_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [11:0] _head_beats1_decode_T_1 = _head_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _head_beats1_decode_T_2 = ~_head_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] head_beats1_decode = _head_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _head_beats1_opdata_T = _q_io_deq_bits_opcode[2]; // @[TLChannelCompactor.scala:47:17]
wire _tail_beats1_opdata_T = _q_io_deq_bits_opcode[2]; // @[TLChannelCompactor.scala:47:17]
wire _has_body_opdata_T = _q_io_deq_bits_opcode[2]; // @[TLChannelCompactor.scala:47:17]
wire head_beats1_opdata = ~_head_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] head_beats1 = head_beats1_opdata ? head_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire [9:0] _head_counter1_T = {1'h0, head_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] head_counter1 = _head_counter1_T[8:0]; // @[Edges.scala:230:28]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _head_last_T = head_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _head_last_T_1 = head_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire head_last = _head_last_T | _head_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire head_done = head_last & _head_T; // @[Decoupled.scala:51:35]
wire [8:0] _head_count_T = ~head_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] head_count = head_beats1 & _head_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _head_counter_T = head ? head_beats1 : head_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _tail_beats1_decode_T_1 = _tail_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _tail_beats1_decode_T_2 = ~_tail_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] tail_beats1_decode = _tail_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire tail_beats1_opdata = ~_tail_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] tail_beats1 = tail_beats1_opdata ? tail_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
wire [9:0] _tail_counter1_T = {1'h0, tail_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] tail_counter1 = _tail_counter1_T[8:0]; // @[Edges.scala:230:28]
wire tail_first = tail_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _tail_last_T = tail_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _tail_last_T_1 = tail_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire tail = _tail_last_T | _tail_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire tail_done = tail & _tail_T; // @[Decoupled.scala:51:35]
wire [8:0] _tail_count_T = ~tail_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] tail_count = tail_beats1 & _tail_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _tail_counter_T = tail_first ? tail_beats1 : tail_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [71:0] body_hi = {_q_io_deq_bits_mask, _q_io_deq_bits_data}; // @[TLChannelCompactor.scala:47:17, :57:18]
wire [72:0] body = {body_hi, _q_io_deq_bits_corrupt}; // @[TLChannelCompactor.scala:47:17, :57:18]
wire [71:0] const_lo = {_q_io_deq_bits_source, _q_io_deq_bits_address}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [5:0] const_hi_hi = {_q_io_deq_bits_opcode, _q_io_deq_bits_param}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [13:0] const_hi = {const_hi_hi, _q_io_deq_bits_size}; // @[TLChannelCompactor.scala:47:17, :58:18]
wire [85:0] const_0 = {const_hi, const_lo}; // @[TLChannelCompactor.scala:58:18]
reg is_body; // @[TLChannelCompactor.scala:60:24]
wire _q_io_deq_ready_T = ~has_body; // @[TLChannelCompactor.scala:51:22, :62:50]
wire _q_io_deq_ready_T_1 = is_body | _q_io_deq_ready_T; // @[TLChannelCompactor.scala:60:24, :62:{47,50}]
assign _q_io_deq_ready_T_2 = io_beat_ready_0 & _q_io_deq_ready_T_1; // @[TLChannelCompactor.scala:62:{35,47}, :108:7]
wire _io_beat_bits_head_T = ~is_body; // @[TLChannelCompactor.scala:60:24, :64:38]
assign _io_beat_bits_head_T_1 = head & _io_beat_bits_head_T; // @[TLChannelCompactor.scala:64:{35,38}]
assign io_beat_bits_head_0 = _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35, :108:7]
wire _io_beat_bits_tail_T = ~has_body; // @[TLChannelCompactor.scala:51:22, :62:50, :65:50]
wire _io_beat_bits_tail_T_1 = is_body | _io_beat_bits_tail_T; // @[TLChannelCompactor.scala:60:24, :65:{47,50}]
assign _io_beat_bits_tail_T_2 = tail & _io_beat_bits_tail_T_1; // @[TLChannelCompactor.scala:65:{35,47}]
assign io_beat_bits_tail_0 = _io_beat_bits_tail_T_2; // @[TLChannelCompactor.scala:65:35, :108:7]
assign _io_beat_bits_payload_T = is_body ? {13'h0, body} : const_0; // @[TLChannelCompactor.scala:57:18, :58:18, :60:24, :66:33]
assign io_beat_bits_payload_0 = _io_beat_bits_payload_T; // @[TLChannelCompactor.scala:66:33, :108:7]
wire has_body_opdata = ~_has_body_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] _has_body_T = ~_q_io_deq_bits_mask; // @[TLChannelCompactor.scala:47:17, :109:49]
wire _has_body_T_1 = |_has_body_T; // @[TLChannelCompactor.scala:109:{49,69}]
assign _has_body_T_2 = has_body_opdata | _has_body_T_1; // @[TLChannelCompactor.scala:109:{45,69}]
assign has_body = _has_body_T_2; // @[TLChannelCompactor.scala:51:22, :109:45]
wire _T_2 = io_beat_ready_0 & io_beat_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:108:7]
if (reset) begin // @[TLChannelCompactor.scala:108:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24]
end
else begin // @[TLChannelCompactor.scala:108:7]
if (_head_T) // @[Decoupled.scala:51:35]
head_counter <= _head_counter_T; // @[Edges.scala:229:27, :236:21]
if (_tail_T) // @[Decoupled.scala:51:35]
tail_counter <= _tail_counter_T; // @[Edges.scala:229:27, :236:21]
is_body <= ~(_T_2 & io_beat_bits_tail_0) & (_T_2 & io_beat_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge)
Queue1_TLBundleA_a64d64s8k8z8c q ( // @[TLChannelCompactor.scala:47:17]
.clock (clock),
.reset (reset),
.io_enq_ready (io_protocol_ready_0),
.io_enq_valid (io_protocol_valid_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_opcode (io_protocol_bits_opcode_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_param (io_protocol_bits_param_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_size (io_protocol_bits_size_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_source (io_protocol_bits_source_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_address (io_protocol_bits_address_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_mask (io_protocol_bits_mask_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_data (io_protocol_bits_data_0), // @[TLChannelCompactor.scala:108:7]
.io_enq_bits_corrupt (io_protocol_bits_corrupt_0), // @[TLChannelCompactor.scala:108:7]
.io_deq_ready (_q_io_deq_ready_T_2), // @[TLChannelCompactor.scala:62:35]
.io_deq_valid (_q_io_deq_valid),
.io_deq_bits_opcode (_q_io_deq_bits_opcode),
.io_deq_bits_param (_q_io_deq_bits_param),
.io_deq_bits_size (_q_io_deq_bits_size),
.io_deq_bits_source (_q_io_deq_bits_source),
.io_deq_bits_address (_q_io_deq_bits_address),
.io_deq_bits_mask (_q_io_deq_bits_mask),
.io_deq_bits_data (_q_io_deq_bits_data),
.io_deq_bits_corrupt (_q_io_deq_bits_corrupt)
); // @[TLChannelCompactor.scala:47:17]
assign io_beat_valid_0 = _q_io_deq_valid; // @[TLChannelCompactor.scala:47:17, :108:7]
assign io_protocol_ready = io_protocol_ready_0; // @[TLChannelCompactor.scala:108:7]
assign io_beat_valid = io_beat_valid_0; // @[TLChannelCompactor.scala:108:7]
assign io_beat_bits_payload = io_beat_bits_payload_0; // @[TLChannelCompactor.scala:108:7]
assign io_beat_bits_head = io_beat_bits_head_0; // @[TLChannelCompactor.scala:108:7]
assign io_beat_bits_tail = io_beat_bits_tail_0; // @[TLChannelCompactor.scala:108:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_44 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_393
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_394
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_395
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_396
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_44( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_393 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_394 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_395 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_396 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchAllocator :
input clock : Clock
input reset : Reset
output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1]}, credit_alloc : { `2` : { alloc : UInt<1>, tail : UInt<1>}[1], `1` : { alloc : UInt<1>, tail : UInt<1>}[1], `0` : { alloc : UInt<1>, tail : UInt<1>}[10]}, switch_sel : { `2` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}}
inst arbs_0 of SwitchArbiter_1
connect arbs_0.clock, clock
connect arbs_0.reset, reset
inst arbs_1 of SwitchArbiter_2
connect arbs_1.clock, clock
connect arbs_1.reset, reset
inst arbs_2 of SwitchArbiter_3
connect arbs_2.clock, clock
connect arbs_2.reset, reset
connect arbs_0.io.out[0].ready, UInt<1>(0h1)
connect arbs_1.io.out[0].ready, UInt<1>(0h1)
connect arbs_2.io.out[0].ready, UInt<1>(0h1)
wire fires : UInt<1>[3]
node _arbs_0_io_in_0_valid_T = or(io.req.`0`[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_0_valid_T_1 = or(_arbs_0_io_in_0_valid_T, io.req.`0`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_0_valid_T_2 = or(_arbs_0_io_in_0_valid_T_1, io.req.`0`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_0_valid_T_3 = or(_arbs_0_io_in_0_valid_T_2, io.req.`0`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_0_valid_T_4 = or(_arbs_0_io_in_0_valid_T_3, io.req.`0`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_0_valid_T_5 = or(_arbs_0_io_in_0_valid_T_4, io.req.`0`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_0_valid_T_6 = or(_arbs_0_io_in_0_valid_T_5, io.req.`0`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_0_valid_T_7 = or(_arbs_0_io_in_0_valid_T_6, io.req.`0`[0].bits.vc_sel.`0`[8])
node _arbs_0_io_in_0_valid_T_8 = or(_arbs_0_io_in_0_valid_T_7, io.req.`0`[0].bits.vc_sel.`0`[9])
node _arbs_0_io_in_0_valid_T_9 = and(io.req.`0`[0].valid, _arbs_0_io_in_0_valid_T_8)
connect arbs_0.io.in[0].valid, _arbs_0_io_in_0_valid_T_9
connect arbs_0.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_0.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8]
connect arbs_0.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9]
connect arbs_0.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
node _fires_0_T = and(arbs_0.io.in[0].ready, arbs_0.io.in[0].valid)
connect fires[0], _fires_0_T
node _arbs_1_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[0].valid, _arbs_1_io_in_0_valid_T
connect arbs_1.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_1.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8]
connect arbs_1.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9]
connect arbs_1.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
node _fires_1_T = and(arbs_1.io.in[0].ready, arbs_1.io.in[0].valid)
connect fires[1], _fires_1_T
node _arbs_2_io_in_0_valid_T = and(io.req.`0`[0].valid, io.req.`0`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[0].valid, _arbs_2_io_in_0_valid_T
connect arbs_2.io.in[0].bits.tail, io.req.`0`[0].bits.tail
connect arbs_2.io.in[0].bits.vc_sel.`0`[0], io.req.`0`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[0].bits.vc_sel.`0`[1], io.req.`0`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[0].bits.vc_sel.`0`[2], io.req.`0`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[0].bits.vc_sel.`0`[3], io.req.`0`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[0].bits.vc_sel.`0`[4], io.req.`0`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[0].bits.vc_sel.`0`[5], io.req.`0`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[0].bits.vc_sel.`0`[6], io.req.`0`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[0].bits.vc_sel.`0`[7], io.req.`0`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[0].bits.vc_sel.`0`[8], io.req.`0`[0].bits.vc_sel.`0`[8]
connect arbs_2.io.in[0].bits.vc_sel.`0`[9], io.req.`0`[0].bits.vc_sel.`0`[9]
connect arbs_2.io.in[0].bits.vc_sel.`1`[0], io.req.`0`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[0].bits.vc_sel.`2`[0], io.req.`0`[0].bits.vc_sel.`2`[0]
node _fires_2_T = and(arbs_2.io.in[0].ready, arbs_2.io.in[0].valid)
connect fires[2], _fires_2_T
node _io_req_0_0_ready_T = or(fires[0], fires[1])
node _io_req_0_0_ready_T_1 = or(_io_req_0_0_ready_T, fires[2])
connect io.req.`0`[0].ready, _io_req_0_0_ready_T_1
wire fires_1 : UInt<1>[3]
node _arbs_0_io_in_1_valid_T = or(io.req.`1`[0].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_1_valid_T_1 = or(_arbs_0_io_in_1_valid_T, io.req.`1`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_1_valid_T_2 = or(_arbs_0_io_in_1_valid_T_1, io.req.`1`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_1_valid_T_3 = or(_arbs_0_io_in_1_valid_T_2, io.req.`1`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_1_valid_T_4 = or(_arbs_0_io_in_1_valid_T_3, io.req.`1`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_1_valid_T_5 = or(_arbs_0_io_in_1_valid_T_4, io.req.`1`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_1_valid_T_6 = or(_arbs_0_io_in_1_valid_T_5, io.req.`1`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_1_valid_T_7 = or(_arbs_0_io_in_1_valid_T_6, io.req.`1`[0].bits.vc_sel.`0`[8])
node _arbs_0_io_in_1_valid_T_8 = or(_arbs_0_io_in_1_valid_T_7, io.req.`1`[0].bits.vc_sel.`0`[9])
node _arbs_0_io_in_1_valid_T_9 = and(io.req.`1`[0].valid, _arbs_0_io_in_1_valid_T_8)
connect arbs_0.io.in[1].valid, _arbs_0_io_in_1_valid_T_9
connect arbs_0.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_0.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8]
connect arbs_0.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9]
connect arbs_0.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
node _fires_0_T_1 = and(arbs_0.io.in[1].ready, arbs_0.io.in[1].valid)
connect fires_1[0], _fires_0_T_1
node _arbs_1_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[1].valid, _arbs_1_io_in_1_valid_T
connect arbs_1.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_1.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8]
connect arbs_1.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9]
connect arbs_1.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
node _fires_1_T_1 = and(arbs_1.io.in[1].ready, arbs_1.io.in[1].valid)
connect fires_1[1], _fires_1_T_1
node _arbs_2_io_in_1_valid_T = and(io.req.`1`[0].valid, io.req.`1`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[1].valid, _arbs_2_io_in_1_valid_T
connect arbs_2.io.in[1].bits.tail, io.req.`1`[0].bits.tail
connect arbs_2.io.in[1].bits.vc_sel.`0`[0], io.req.`1`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[1].bits.vc_sel.`0`[1], io.req.`1`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[1].bits.vc_sel.`0`[2], io.req.`1`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[1].bits.vc_sel.`0`[3], io.req.`1`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[1].bits.vc_sel.`0`[4], io.req.`1`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[1].bits.vc_sel.`0`[5], io.req.`1`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[1].bits.vc_sel.`0`[6], io.req.`1`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[1].bits.vc_sel.`0`[7], io.req.`1`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[1].bits.vc_sel.`0`[8], io.req.`1`[0].bits.vc_sel.`0`[8]
connect arbs_2.io.in[1].bits.vc_sel.`0`[9], io.req.`1`[0].bits.vc_sel.`0`[9]
connect arbs_2.io.in[1].bits.vc_sel.`1`[0], io.req.`1`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[1].bits.vc_sel.`2`[0], io.req.`1`[0].bits.vc_sel.`2`[0]
node _fires_2_T_1 = and(arbs_2.io.in[1].ready, arbs_2.io.in[1].valid)
connect fires_1[2], _fires_2_T_1
node _io_req_1_0_ready_T = or(fires_1[0], fires_1[1])
node _io_req_1_0_ready_T_1 = or(_io_req_1_0_ready_T, fires_1[2])
connect io.req.`1`[0].ready, _io_req_1_0_ready_T_1
wire fires_2 : UInt<1>[3]
node _arbs_0_io_in_2_valid_T = or(io.req.`2`[0].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_2_valid_T_1 = or(_arbs_0_io_in_2_valid_T, io.req.`2`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_2_valid_T_2 = or(_arbs_0_io_in_2_valid_T_1, io.req.`2`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_2_valid_T_3 = or(_arbs_0_io_in_2_valid_T_2, io.req.`2`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_2_valid_T_4 = or(_arbs_0_io_in_2_valid_T_3, io.req.`2`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_2_valid_T_5 = or(_arbs_0_io_in_2_valid_T_4, io.req.`2`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_2_valid_T_6 = or(_arbs_0_io_in_2_valid_T_5, io.req.`2`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_2_valid_T_7 = or(_arbs_0_io_in_2_valid_T_6, io.req.`2`[0].bits.vc_sel.`0`[8])
node _arbs_0_io_in_2_valid_T_8 = or(_arbs_0_io_in_2_valid_T_7, io.req.`2`[0].bits.vc_sel.`0`[9])
node _arbs_0_io_in_2_valid_T_9 = and(io.req.`2`[0].valid, _arbs_0_io_in_2_valid_T_8)
connect arbs_0.io.in[2].valid, _arbs_0_io_in_2_valid_T_9
connect arbs_0.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_0.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8]
connect arbs_0.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9]
connect arbs_0.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
node _fires_0_T_2 = and(arbs_0.io.in[2].ready, arbs_0.io.in[2].valid)
connect fires_2[0], _fires_0_T_2
node _arbs_1_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[2].valid, _arbs_1_io_in_2_valid_T
connect arbs_1.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_1.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8]
connect arbs_1.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9]
connect arbs_1.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
node _fires_1_T_2 = and(arbs_1.io.in[2].ready, arbs_1.io.in[2].valid)
connect fires_2[1], _fires_1_T_2
node _arbs_2_io_in_2_valid_T = and(io.req.`2`[0].valid, io.req.`2`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[2].valid, _arbs_2_io_in_2_valid_T
connect arbs_2.io.in[2].bits.tail, io.req.`2`[0].bits.tail
connect arbs_2.io.in[2].bits.vc_sel.`0`[0], io.req.`2`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[2].bits.vc_sel.`0`[1], io.req.`2`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[2].bits.vc_sel.`0`[2], io.req.`2`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[2].bits.vc_sel.`0`[3], io.req.`2`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[2].bits.vc_sel.`0`[4], io.req.`2`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[2].bits.vc_sel.`0`[5], io.req.`2`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[2].bits.vc_sel.`0`[6], io.req.`2`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[2].bits.vc_sel.`0`[7], io.req.`2`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[2].bits.vc_sel.`0`[8], io.req.`2`[0].bits.vc_sel.`0`[8]
connect arbs_2.io.in[2].bits.vc_sel.`0`[9], io.req.`2`[0].bits.vc_sel.`0`[9]
connect arbs_2.io.in[2].bits.vc_sel.`1`[0], io.req.`2`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[2].bits.vc_sel.`2`[0], io.req.`2`[0].bits.vc_sel.`2`[0]
node _fires_2_T_2 = and(arbs_2.io.in[2].ready, arbs_2.io.in[2].valid)
connect fires_2[2], _fires_2_T_2
node _io_req_2_0_ready_T = or(fires_2[0], fires_2[1])
node _io_req_2_0_ready_T_1 = or(_io_req_2_0_ready_T, fires_2[2])
connect io.req.`2`[0].ready, _io_req_2_0_ready_T_1
wire fires_3 : UInt<1>[3]
node _arbs_0_io_in_3_valid_T = or(io.req.`3`[0].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[1])
node _arbs_0_io_in_3_valid_T_1 = or(_arbs_0_io_in_3_valid_T, io.req.`3`[0].bits.vc_sel.`0`[2])
node _arbs_0_io_in_3_valid_T_2 = or(_arbs_0_io_in_3_valid_T_1, io.req.`3`[0].bits.vc_sel.`0`[3])
node _arbs_0_io_in_3_valid_T_3 = or(_arbs_0_io_in_3_valid_T_2, io.req.`3`[0].bits.vc_sel.`0`[4])
node _arbs_0_io_in_3_valid_T_4 = or(_arbs_0_io_in_3_valid_T_3, io.req.`3`[0].bits.vc_sel.`0`[5])
node _arbs_0_io_in_3_valid_T_5 = or(_arbs_0_io_in_3_valid_T_4, io.req.`3`[0].bits.vc_sel.`0`[6])
node _arbs_0_io_in_3_valid_T_6 = or(_arbs_0_io_in_3_valid_T_5, io.req.`3`[0].bits.vc_sel.`0`[7])
node _arbs_0_io_in_3_valid_T_7 = or(_arbs_0_io_in_3_valid_T_6, io.req.`3`[0].bits.vc_sel.`0`[8])
node _arbs_0_io_in_3_valid_T_8 = or(_arbs_0_io_in_3_valid_T_7, io.req.`3`[0].bits.vc_sel.`0`[9])
node _arbs_0_io_in_3_valid_T_9 = and(io.req.`3`[0].valid, _arbs_0_io_in_3_valid_T_8)
connect arbs_0.io.in[3].valid, _arbs_0_io_in_3_valid_T_9
connect arbs_0.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_0.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_0.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_0.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_0.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3]
connect arbs_0.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4]
connect arbs_0.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5]
connect arbs_0.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6]
connect arbs_0.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7]
connect arbs_0.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8]
connect arbs_0.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9]
connect arbs_0.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_0.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
node _fires_0_T_3 = and(arbs_0.io.in[3].ready, arbs_0.io.in[3].valid)
connect fires_3[0], _fires_0_T_3
node _arbs_1_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`1`[0])
connect arbs_1.io.in[3].valid, _arbs_1_io_in_3_valid_T
connect arbs_1.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_1.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_1.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_1.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_1.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3]
connect arbs_1.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4]
connect arbs_1.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5]
connect arbs_1.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6]
connect arbs_1.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7]
connect arbs_1.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8]
connect arbs_1.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9]
connect arbs_1.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_1.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
node _fires_1_T_3 = and(arbs_1.io.in[3].ready, arbs_1.io.in[3].valid)
connect fires_3[1], _fires_1_T_3
node _arbs_2_io_in_3_valid_T = and(io.req.`3`[0].valid, io.req.`3`[0].bits.vc_sel.`2`[0])
connect arbs_2.io.in[3].valid, _arbs_2_io_in_3_valid_T
connect arbs_2.io.in[3].bits.tail, io.req.`3`[0].bits.tail
connect arbs_2.io.in[3].bits.vc_sel.`0`[0], io.req.`3`[0].bits.vc_sel.`0`[0]
connect arbs_2.io.in[3].bits.vc_sel.`0`[1], io.req.`3`[0].bits.vc_sel.`0`[1]
connect arbs_2.io.in[3].bits.vc_sel.`0`[2], io.req.`3`[0].bits.vc_sel.`0`[2]
connect arbs_2.io.in[3].bits.vc_sel.`0`[3], io.req.`3`[0].bits.vc_sel.`0`[3]
connect arbs_2.io.in[3].bits.vc_sel.`0`[4], io.req.`3`[0].bits.vc_sel.`0`[4]
connect arbs_2.io.in[3].bits.vc_sel.`0`[5], io.req.`3`[0].bits.vc_sel.`0`[5]
connect arbs_2.io.in[3].bits.vc_sel.`0`[6], io.req.`3`[0].bits.vc_sel.`0`[6]
connect arbs_2.io.in[3].bits.vc_sel.`0`[7], io.req.`3`[0].bits.vc_sel.`0`[7]
connect arbs_2.io.in[3].bits.vc_sel.`0`[8], io.req.`3`[0].bits.vc_sel.`0`[8]
connect arbs_2.io.in[3].bits.vc_sel.`0`[9], io.req.`3`[0].bits.vc_sel.`0`[9]
connect arbs_2.io.in[3].bits.vc_sel.`1`[0], io.req.`3`[0].bits.vc_sel.`1`[0]
connect arbs_2.io.in[3].bits.vc_sel.`2`[0], io.req.`3`[0].bits.vc_sel.`2`[0]
node _fires_2_T_3 = and(arbs_2.io.in[3].ready, arbs_2.io.in[3].valid)
connect fires_3[2], _fires_2_T_3
node _io_req_3_0_ready_T = or(fires_3[0], fires_3[1])
node _io_req_3_0_ready_T_1 = or(_io_req_3_0_ready_T, fires_3[2])
connect io.req.`3`[0].ready, _io_req_3_0_ready_T_1
node _io_switch_sel_0_0_0_0_T = bits(arbs_0.io.chosen_oh[0], 0, 0)
node _io_switch_sel_0_0_0_0_T_1 = and(arbs_0.io.in[0].valid, _io_switch_sel_0_0_0_0_T)
node _io_switch_sel_0_0_0_0_T_2 = and(_io_switch_sel_0_0_0_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`0`[0], _io_switch_sel_0_0_0_0_T_2
node _io_switch_sel_0_0_1_0_T = bits(arbs_0.io.chosen_oh[0], 1, 1)
node _io_switch_sel_0_0_1_0_T_1 = and(arbs_0.io.in[1].valid, _io_switch_sel_0_0_1_0_T)
node _io_switch_sel_0_0_1_0_T_2 = and(_io_switch_sel_0_0_1_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`1`[0], _io_switch_sel_0_0_1_0_T_2
node _io_switch_sel_0_0_2_0_T = bits(arbs_0.io.chosen_oh[0], 2, 2)
node _io_switch_sel_0_0_2_0_T_1 = and(arbs_0.io.in[2].valid, _io_switch_sel_0_0_2_0_T)
node _io_switch_sel_0_0_2_0_T_2 = and(_io_switch_sel_0_0_2_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`2`[0], _io_switch_sel_0_0_2_0_T_2
node _io_switch_sel_0_0_3_0_T = bits(arbs_0.io.chosen_oh[0], 3, 3)
node _io_switch_sel_0_0_3_0_T_1 = and(arbs_0.io.in[3].valid, _io_switch_sel_0_0_3_0_T)
node _io_switch_sel_0_0_3_0_T_2 = and(_io_switch_sel_0_0_3_0_T_1, arbs_0.io.out[0].valid)
connect io.switch_sel.`0`[0].`3`[0], _io_switch_sel_0_0_3_0_T_2
node _io_switch_sel_1_0_0_0_T = bits(arbs_1.io.chosen_oh[0], 0, 0)
node _io_switch_sel_1_0_0_0_T_1 = and(arbs_1.io.in[0].valid, _io_switch_sel_1_0_0_0_T)
node _io_switch_sel_1_0_0_0_T_2 = and(_io_switch_sel_1_0_0_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`0`[0], _io_switch_sel_1_0_0_0_T_2
node _io_switch_sel_1_0_1_0_T = bits(arbs_1.io.chosen_oh[0], 1, 1)
node _io_switch_sel_1_0_1_0_T_1 = and(arbs_1.io.in[1].valid, _io_switch_sel_1_0_1_0_T)
node _io_switch_sel_1_0_1_0_T_2 = and(_io_switch_sel_1_0_1_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`1`[0], _io_switch_sel_1_0_1_0_T_2
node _io_switch_sel_1_0_2_0_T = bits(arbs_1.io.chosen_oh[0], 2, 2)
node _io_switch_sel_1_0_2_0_T_1 = and(arbs_1.io.in[2].valid, _io_switch_sel_1_0_2_0_T)
node _io_switch_sel_1_0_2_0_T_2 = and(_io_switch_sel_1_0_2_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`2`[0], _io_switch_sel_1_0_2_0_T_2
node _io_switch_sel_1_0_3_0_T = bits(arbs_1.io.chosen_oh[0], 3, 3)
node _io_switch_sel_1_0_3_0_T_1 = and(arbs_1.io.in[3].valid, _io_switch_sel_1_0_3_0_T)
node _io_switch_sel_1_0_3_0_T_2 = and(_io_switch_sel_1_0_3_0_T_1, arbs_1.io.out[0].valid)
connect io.switch_sel.`1`[0].`3`[0], _io_switch_sel_1_0_3_0_T_2
node _io_switch_sel_2_0_0_0_T = bits(arbs_2.io.chosen_oh[0], 0, 0)
node _io_switch_sel_2_0_0_0_T_1 = and(arbs_2.io.in[0].valid, _io_switch_sel_2_0_0_0_T)
node _io_switch_sel_2_0_0_0_T_2 = and(_io_switch_sel_2_0_0_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`0`[0], _io_switch_sel_2_0_0_0_T_2
node _io_switch_sel_2_0_1_0_T = bits(arbs_2.io.chosen_oh[0], 1, 1)
node _io_switch_sel_2_0_1_0_T_1 = and(arbs_2.io.in[1].valid, _io_switch_sel_2_0_1_0_T)
node _io_switch_sel_2_0_1_0_T_2 = and(_io_switch_sel_2_0_1_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`1`[0], _io_switch_sel_2_0_1_0_T_2
node _io_switch_sel_2_0_2_0_T = bits(arbs_2.io.chosen_oh[0], 2, 2)
node _io_switch_sel_2_0_2_0_T_1 = and(arbs_2.io.in[2].valid, _io_switch_sel_2_0_2_0_T)
node _io_switch_sel_2_0_2_0_T_2 = and(_io_switch_sel_2_0_2_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`2`[0], _io_switch_sel_2_0_2_0_T_2
node _io_switch_sel_2_0_3_0_T = bits(arbs_2.io.chosen_oh[0], 3, 3)
node _io_switch_sel_2_0_3_0_T_1 = and(arbs_2.io.in[3].valid, _io_switch_sel_2_0_3_0_T)
node _io_switch_sel_2_0_3_0_T_2 = and(_io_switch_sel_2_0_3_0_T_1, arbs_2.io.out[0].valid)
connect io.switch_sel.`2`[0].`3`[0], _io_switch_sel_2_0_3_0_T_2
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h0)
connect io.credit_alloc.`0`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[1].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[2].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[3].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[4].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[5].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[6].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[7].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[8].tail, UInt<1>(0h0)
connect io.credit_alloc.`0`[9].tail, UInt<1>(0h0)
connect io.credit_alloc.`1`[0].tail, UInt<1>(0h0)
connect io.credit_alloc.`2`[0].tail, UInt<1>(0h0)
node _T = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[0])
when _T :
connect io.credit_alloc.`0`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[0].tail, arbs_0.io.out[0].bits.tail
node _T_1 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[1])
when _T_1 :
connect io.credit_alloc.`0`[1].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[1].tail, arbs_0.io.out[0].bits.tail
node _T_2 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[2])
when _T_2 :
connect io.credit_alloc.`0`[2].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[2].tail, arbs_0.io.out[0].bits.tail
node _T_3 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[3])
when _T_3 :
connect io.credit_alloc.`0`[3].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[3].tail, arbs_0.io.out[0].bits.tail
node _T_4 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[4])
when _T_4 :
connect io.credit_alloc.`0`[4].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[4].tail, arbs_0.io.out[0].bits.tail
node _T_5 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[5])
when _T_5 :
connect io.credit_alloc.`0`[5].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[5].tail, arbs_0.io.out[0].bits.tail
node _T_6 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[6])
when _T_6 :
connect io.credit_alloc.`0`[6].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[6].tail, arbs_0.io.out[0].bits.tail
node _T_7 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[7])
when _T_7 :
connect io.credit_alloc.`0`[7].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[7].tail, arbs_0.io.out[0].bits.tail
node _T_8 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[8])
when _T_8 :
connect io.credit_alloc.`0`[8].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[8].tail, arbs_0.io.out[0].bits.tail
node _T_9 = and(arbs_0.io.out[0].valid, arbs_0.io.out[0].bits.vc_sel.`0`[9])
when _T_9 :
connect io.credit_alloc.`0`[9].alloc, UInt<1>(0h1)
connect io.credit_alloc.`0`[9].tail, arbs_0.io.out[0].bits.tail
node _T_10 = and(arbs_1.io.out[0].valid, arbs_1.io.out[0].bits.vc_sel.`1`[0])
when _T_10 :
connect io.credit_alloc.`1`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`1`[0].tail, arbs_1.io.out[0].bits.tail
node _T_11 = and(arbs_2.io.out[0].valid, arbs_2.io.out[0].bits.vc_sel.`2`[0])
when _T_11 :
connect io.credit_alloc.`2`[0].alloc, UInt<1>(0h1)
connect io.credit_alloc.`2`[0].tail, arbs_2.io.out[0].bits.tail | module SwitchAllocator( // @[SwitchAllocator.scala:64:7]
input clock, // @[SwitchAllocator.scala:64:7]
input reset, // @[SwitchAllocator.scala:64:7]
output io_req_3_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14]
input io_req_3_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_2_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14]
input io_req_2_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_1_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14]
input io_req_1_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_req_0_0_ready, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_valid, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_0, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_1, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:74:14]
input io_req_0_0_bits_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_2_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_1_0_tail, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_0_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_1_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_2_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_3_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_4_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_5_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_6_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_7_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_8_alloc, // @[SwitchAllocator.scala:74:14]
output io_credit_alloc_0_9_alloc, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_2_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_1_0_0_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_3_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_2_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_1_0, // @[SwitchAllocator.scala:74:14]
output io_switch_sel_0_0_0_0 // @[SwitchAllocator.scala:74:14]
);
wire _arbs_2_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_2_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_1_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_0_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_1_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_2_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_in_3_ready; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:83:45]
wire _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:83:45]
wire [3:0] _arbs_0_io_chosen_oh_0; // @[SwitchAllocator.scala:83:45]
wire arbs_0_io_in_0_valid = io_req_0_0_valid & (io_req_0_0_bits_vc_sel_0_0 | io_req_0_0_bits_vc_sel_0_1 | io_req_0_0_bits_vc_sel_0_2 | io_req_0_0_bits_vc_sel_0_3 | io_req_0_0_bits_vc_sel_0_4 | io_req_0_0_bits_vc_sel_0_5 | io_req_0_0_bits_vc_sel_0_6 | io_req_0_0_bits_vc_sel_0_7 | io_req_0_0_bits_vc_sel_0_8 | io_req_0_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_0_valid = io_req_0_0_valid & io_req_0_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_1_valid = io_req_1_0_valid & (io_req_1_0_bits_vc_sel_0_0 | io_req_1_0_bits_vc_sel_0_1 | io_req_1_0_bits_vc_sel_0_2 | io_req_1_0_bits_vc_sel_0_3 | io_req_1_0_bits_vc_sel_0_4 | io_req_1_0_bits_vc_sel_0_5 | io_req_1_0_bits_vc_sel_0_6 | io_req_1_0_bits_vc_sel_0_7 | io_req_1_0_bits_vc_sel_0_8 | io_req_1_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_1_valid = io_req_1_0_valid & io_req_1_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_2_valid = io_req_2_0_valid & (io_req_2_0_bits_vc_sel_0_0 | io_req_2_0_bits_vc_sel_0_1 | io_req_2_0_bits_vc_sel_0_2 | io_req_2_0_bits_vc_sel_0_3 | io_req_2_0_bits_vc_sel_0_4 | io_req_2_0_bits_vc_sel_0_5 | io_req_2_0_bits_vc_sel_0_6 | io_req_2_0_bits_vc_sel_0_7 | io_req_2_0_bits_vc_sel_0_8 | io_req_2_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_2_valid = io_req_2_0_valid & io_req_2_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire arbs_0_io_in_3_valid = io_req_3_0_valid & (io_req_3_0_bits_vc_sel_0_0 | io_req_3_0_bits_vc_sel_0_1 | io_req_3_0_bits_vc_sel_0_2 | io_req_3_0_bits_vc_sel_0_3 | io_req_3_0_bits_vc_sel_0_4 | io_req_3_0_bits_vc_sel_0_5 | io_req_3_0_bits_vc_sel_0_6 | io_req_3_0_bits_vc_sel_0_7 | io_req_3_0_bits_vc_sel_0_8 | io_req_3_0_bits_vc_sel_0_9); // @[SwitchAllocator.scala:95:{37,65}]
wire arbs_1_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:95:37]
wire arbs_2_io_in_3_valid = io_req_3_0_valid & io_req_3_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:95:37]
wire io_credit_alloc_1_0_alloc_0 = _arbs_1_io_out_0_valid & _arbs_1_io_out_0_bits_vc_sel_1_0; // @[SwitchAllocator.scala:83:45, :120:33]
wire io_credit_alloc_2_0_alloc_0 = _arbs_2_io_out_0_valid & _arbs_2_io_out_0_bits_vc_sel_2_0; // @[SwitchAllocator.scala:83:45, :120:33]
SwitchArbiter_1 arbs_0 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_0_io_in_0_ready),
.io_in_0_valid (arbs_0_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2),
.io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3),
.io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4),
.io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5),
.io_in_0_bits_vc_sel_0_6 (io_req_0_0_bits_vc_sel_0_6),
.io_in_0_bits_vc_sel_0_7 (io_req_0_0_bits_vc_sel_0_7),
.io_in_0_bits_vc_sel_0_8 (io_req_0_0_bits_vc_sel_0_8),
.io_in_0_bits_vc_sel_0_9 (io_req_0_0_bits_vc_sel_0_9),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_0_io_in_1_ready),
.io_in_1_valid (arbs_0_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_vc_sel_0_8 (io_req_1_0_bits_vc_sel_0_8),
.io_in_1_bits_vc_sel_0_9 (io_req_1_0_bits_vc_sel_0_9),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_0_io_in_2_ready),
.io_in_2_valid (arbs_0_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8),
.io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_0_io_in_3_ready),
.io_in_3_valid (arbs_0_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1),
.io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2),
.io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3),
.io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4),
.io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5),
.io_in_3_bits_vc_sel_0_6 (io_req_3_0_bits_vc_sel_0_6),
.io_in_3_bits_vc_sel_0_7 (io_req_3_0_bits_vc_sel_0_7),
.io_in_3_bits_vc_sel_0_8 (io_req_3_0_bits_vc_sel_0_8),
.io_in_3_bits_vc_sel_0_9 (io_req_3_0_bits_vc_sel_0_9),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_0_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (_arbs_0_io_out_0_bits_vc_sel_0_0),
.io_out_0_bits_vc_sel_0_1 (_arbs_0_io_out_0_bits_vc_sel_0_1),
.io_out_0_bits_vc_sel_0_2 (_arbs_0_io_out_0_bits_vc_sel_0_2),
.io_out_0_bits_vc_sel_0_3 (_arbs_0_io_out_0_bits_vc_sel_0_3),
.io_out_0_bits_vc_sel_0_4 (_arbs_0_io_out_0_bits_vc_sel_0_4),
.io_out_0_bits_vc_sel_0_5 (_arbs_0_io_out_0_bits_vc_sel_0_5),
.io_out_0_bits_vc_sel_0_6 (_arbs_0_io_out_0_bits_vc_sel_0_6),
.io_out_0_bits_vc_sel_0_7 (_arbs_0_io_out_0_bits_vc_sel_0_7),
.io_out_0_bits_vc_sel_0_8 (_arbs_0_io_out_0_bits_vc_sel_0_8),
.io_out_0_bits_vc_sel_0_9 (_arbs_0_io_out_0_bits_vc_sel_0_9),
.io_out_0_bits_tail (/* unused */),
.io_chosen_oh_0 (_arbs_0_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_1 arbs_1 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_1_io_in_0_ready),
.io_in_0_valid (arbs_1_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2),
.io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3),
.io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4),
.io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5),
.io_in_0_bits_vc_sel_0_6 (io_req_0_0_bits_vc_sel_0_6),
.io_in_0_bits_vc_sel_0_7 (io_req_0_0_bits_vc_sel_0_7),
.io_in_0_bits_vc_sel_0_8 (io_req_0_0_bits_vc_sel_0_8),
.io_in_0_bits_vc_sel_0_9 (io_req_0_0_bits_vc_sel_0_9),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_1_io_in_1_ready),
.io_in_1_valid (arbs_1_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_vc_sel_0_8 (io_req_1_0_bits_vc_sel_0_8),
.io_in_1_bits_vc_sel_0_9 (io_req_1_0_bits_vc_sel_0_9),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_1_io_in_2_ready),
.io_in_2_valid (arbs_1_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8),
.io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_1_io_in_3_ready),
.io_in_3_valid (arbs_1_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1),
.io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2),
.io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3),
.io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4),
.io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5),
.io_in_3_bits_vc_sel_0_6 (io_req_3_0_bits_vc_sel_0_6),
.io_in_3_bits_vc_sel_0_7 (io_req_3_0_bits_vc_sel_0_7),
.io_in_3_bits_vc_sel_0_8 (io_req_3_0_bits_vc_sel_0_8),
.io_in_3_bits_vc_sel_0_9 (io_req_3_0_bits_vc_sel_0_9),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_1_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (/* unused */),
.io_out_0_bits_vc_sel_1_0 (_arbs_1_io_out_0_bits_vc_sel_1_0),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_vc_sel_0_2 (/* unused */),
.io_out_0_bits_vc_sel_0_3 (/* unused */),
.io_out_0_bits_vc_sel_0_4 (/* unused */),
.io_out_0_bits_vc_sel_0_5 (/* unused */),
.io_out_0_bits_vc_sel_0_6 (/* unused */),
.io_out_0_bits_vc_sel_0_7 (/* unused */),
.io_out_0_bits_vc_sel_0_8 (/* unused */),
.io_out_0_bits_vc_sel_0_9 (/* unused */),
.io_out_0_bits_tail (_arbs_1_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_1_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
SwitchArbiter_1 arbs_2 ( // @[SwitchAllocator.scala:83:45]
.clock (clock),
.reset (reset),
.io_in_0_ready (_arbs_2_io_in_0_ready),
.io_in_0_valid (arbs_2_io_in_0_valid), // @[SwitchAllocator.scala:95:37]
.io_in_0_bits_vc_sel_2_0 (io_req_0_0_bits_vc_sel_2_0),
.io_in_0_bits_vc_sel_1_0 (io_req_0_0_bits_vc_sel_1_0),
.io_in_0_bits_vc_sel_0_0 (io_req_0_0_bits_vc_sel_0_0),
.io_in_0_bits_vc_sel_0_1 (io_req_0_0_bits_vc_sel_0_1),
.io_in_0_bits_vc_sel_0_2 (io_req_0_0_bits_vc_sel_0_2),
.io_in_0_bits_vc_sel_0_3 (io_req_0_0_bits_vc_sel_0_3),
.io_in_0_bits_vc_sel_0_4 (io_req_0_0_bits_vc_sel_0_4),
.io_in_0_bits_vc_sel_0_5 (io_req_0_0_bits_vc_sel_0_5),
.io_in_0_bits_vc_sel_0_6 (io_req_0_0_bits_vc_sel_0_6),
.io_in_0_bits_vc_sel_0_7 (io_req_0_0_bits_vc_sel_0_7),
.io_in_0_bits_vc_sel_0_8 (io_req_0_0_bits_vc_sel_0_8),
.io_in_0_bits_vc_sel_0_9 (io_req_0_0_bits_vc_sel_0_9),
.io_in_0_bits_tail (io_req_0_0_bits_tail),
.io_in_1_ready (_arbs_2_io_in_1_ready),
.io_in_1_valid (arbs_2_io_in_1_valid), // @[SwitchAllocator.scala:95:37]
.io_in_1_bits_vc_sel_2_0 (io_req_1_0_bits_vc_sel_2_0),
.io_in_1_bits_vc_sel_1_0 (io_req_1_0_bits_vc_sel_1_0),
.io_in_1_bits_vc_sel_0_0 (io_req_1_0_bits_vc_sel_0_0),
.io_in_1_bits_vc_sel_0_1 (io_req_1_0_bits_vc_sel_0_1),
.io_in_1_bits_vc_sel_0_2 (io_req_1_0_bits_vc_sel_0_2),
.io_in_1_bits_vc_sel_0_3 (io_req_1_0_bits_vc_sel_0_3),
.io_in_1_bits_vc_sel_0_4 (io_req_1_0_bits_vc_sel_0_4),
.io_in_1_bits_vc_sel_0_5 (io_req_1_0_bits_vc_sel_0_5),
.io_in_1_bits_vc_sel_0_6 (io_req_1_0_bits_vc_sel_0_6),
.io_in_1_bits_vc_sel_0_7 (io_req_1_0_bits_vc_sel_0_7),
.io_in_1_bits_vc_sel_0_8 (io_req_1_0_bits_vc_sel_0_8),
.io_in_1_bits_vc_sel_0_9 (io_req_1_0_bits_vc_sel_0_9),
.io_in_1_bits_tail (io_req_1_0_bits_tail),
.io_in_2_ready (_arbs_2_io_in_2_ready),
.io_in_2_valid (arbs_2_io_in_2_valid), // @[SwitchAllocator.scala:95:37]
.io_in_2_bits_vc_sel_2_0 (io_req_2_0_bits_vc_sel_2_0),
.io_in_2_bits_vc_sel_1_0 (io_req_2_0_bits_vc_sel_1_0),
.io_in_2_bits_vc_sel_0_0 (io_req_2_0_bits_vc_sel_0_0),
.io_in_2_bits_vc_sel_0_1 (io_req_2_0_bits_vc_sel_0_1),
.io_in_2_bits_vc_sel_0_2 (io_req_2_0_bits_vc_sel_0_2),
.io_in_2_bits_vc_sel_0_3 (io_req_2_0_bits_vc_sel_0_3),
.io_in_2_bits_vc_sel_0_4 (io_req_2_0_bits_vc_sel_0_4),
.io_in_2_bits_vc_sel_0_5 (io_req_2_0_bits_vc_sel_0_5),
.io_in_2_bits_vc_sel_0_6 (io_req_2_0_bits_vc_sel_0_6),
.io_in_2_bits_vc_sel_0_7 (io_req_2_0_bits_vc_sel_0_7),
.io_in_2_bits_vc_sel_0_8 (io_req_2_0_bits_vc_sel_0_8),
.io_in_2_bits_vc_sel_0_9 (io_req_2_0_bits_vc_sel_0_9),
.io_in_2_bits_tail (io_req_2_0_bits_tail),
.io_in_3_ready (_arbs_2_io_in_3_ready),
.io_in_3_valid (arbs_2_io_in_3_valid), // @[SwitchAllocator.scala:95:37]
.io_in_3_bits_vc_sel_2_0 (io_req_3_0_bits_vc_sel_2_0),
.io_in_3_bits_vc_sel_1_0 (io_req_3_0_bits_vc_sel_1_0),
.io_in_3_bits_vc_sel_0_0 (io_req_3_0_bits_vc_sel_0_0),
.io_in_3_bits_vc_sel_0_1 (io_req_3_0_bits_vc_sel_0_1),
.io_in_3_bits_vc_sel_0_2 (io_req_3_0_bits_vc_sel_0_2),
.io_in_3_bits_vc_sel_0_3 (io_req_3_0_bits_vc_sel_0_3),
.io_in_3_bits_vc_sel_0_4 (io_req_3_0_bits_vc_sel_0_4),
.io_in_3_bits_vc_sel_0_5 (io_req_3_0_bits_vc_sel_0_5),
.io_in_3_bits_vc_sel_0_6 (io_req_3_0_bits_vc_sel_0_6),
.io_in_3_bits_vc_sel_0_7 (io_req_3_0_bits_vc_sel_0_7),
.io_in_3_bits_vc_sel_0_8 (io_req_3_0_bits_vc_sel_0_8),
.io_in_3_bits_vc_sel_0_9 (io_req_3_0_bits_vc_sel_0_9),
.io_in_3_bits_tail (io_req_3_0_bits_tail),
.io_out_0_valid (_arbs_2_io_out_0_valid),
.io_out_0_bits_vc_sel_2_0 (_arbs_2_io_out_0_bits_vc_sel_2_0),
.io_out_0_bits_vc_sel_1_0 (/* unused */),
.io_out_0_bits_vc_sel_0_0 (/* unused */),
.io_out_0_bits_vc_sel_0_1 (/* unused */),
.io_out_0_bits_vc_sel_0_2 (/* unused */),
.io_out_0_bits_vc_sel_0_3 (/* unused */),
.io_out_0_bits_vc_sel_0_4 (/* unused */),
.io_out_0_bits_vc_sel_0_5 (/* unused */),
.io_out_0_bits_vc_sel_0_6 (/* unused */),
.io_out_0_bits_vc_sel_0_7 (/* unused */),
.io_out_0_bits_vc_sel_0_8 (/* unused */),
.io_out_0_bits_vc_sel_0_9 (/* unused */),
.io_out_0_bits_tail (_arbs_2_io_out_0_bits_tail),
.io_chosen_oh_0 (_arbs_2_io_chosen_oh_0)
); // @[SwitchAllocator.scala:83:45]
assign io_req_3_0_ready = _arbs_0_io_in_3_ready & arbs_0_io_in_3_valid | _arbs_1_io_in_3_ready & arbs_1_io_in_3_valid | _arbs_2_io_in_3_ready & arbs_2_io_in_3_valid; // @[Decoupled.scala:51:35]
assign io_req_2_0_ready = _arbs_0_io_in_2_ready & arbs_0_io_in_2_valid | _arbs_1_io_in_2_ready & arbs_1_io_in_2_valid | _arbs_2_io_in_2_ready & arbs_2_io_in_2_valid; // @[Decoupled.scala:51:35]
assign io_req_1_0_ready = _arbs_0_io_in_1_ready & arbs_0_io_in_1_valid | _arbs_1_io_in_1_ready & arbs_1_io_in_1_valid | _arbs_2_io_in_1_ready & arbs_2_io_in_1_valid; // @[Decoupled.scala:51:35]
assign io_req_0_0_ready = _arbs_0_io_in_0_ready & arbs_0_io_in_0_valid | _arbs_1_io_in_0_ready & arbs_1_io_in_0_valid | _arbs_2_io_in_0_ready & arbs_2_io_in_0_valid; // @[Decoupled.scala:51:35]
assign io_credit_alloc_2_0_alloc = io_credit_alloc_2_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_2_0_tail = io_credit_alloc_2_0_alloc_0 & _arbs_2_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_1_0_alloc = io_credit_alloc_1_0_alloc_0; // @[SwitchAllocator.scala:64:7, :120:33]
assign io_credit_alloc_1_0_tail = io_credit_alloc_1_0_alloc_0 & _arbs_1_io_out_0_bits_tail; // @[SwitchAllocator.scala:64:7, :83:45, :116:44, :120:{33,67}, :122:21]
assign io_credit_alloc_0_0_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_0; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_1_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_1; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_2_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_2; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_3_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_3; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_4_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_4; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_5_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_5; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_6_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_6; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_7_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_7; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_8_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_8; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_credit_alloc_0_9_alloc = _arbs_0_io_out_0_valid & _arbs_0_io_out_0_bits_vc_sel_0_9; // @[SwitchAllocator.scala:64:7, :83:45, :120:33]
assign io_switch_sel_2_0_3_0 = arbs_2_io_in_3_valid & _arbs_2_io_chosen_oh_0[3] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_2_0 = arbs_2_io_in_2_valid & _arbs_2_io_chosen_oh_0[2] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_1_0 = arbs_2_io_in_1_valid & _arbs_2_io_chosen_oh_0[1] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_2_0_0_0 = arbs_2_io_in_0_valid & _arbs_2_io_chosen_oh_0[0] & _arbs_2_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_3_0 = arbs_1_io_in_3_valid & _arbs_1_io_chosen_oh_0[3] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_2_0 = arbs_1_io_in_2_valid & _arbs_1_io_chosen_oh_0[2] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_1_0 = arbs_1_io_in_1_valid & _arbs_1_io_chosen_oh_0[1] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_1_0_0_0 = arbs_1_io_in_0_valid & _arbs_1_io_chosen_oh_0[0] & _arbs_1_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_3_0 = arbs_0_io_in_3_valid & _arbs_0_io_chosen_oh_0[3] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_2_0 = arbs_0_io_in_2_valid & _arbs_0_io_chosen_oh_0[2] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_1_0 = arbs_0_io_in_1_valid & _arbs_0_io_chosen_oh_0[1] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
assign io_switch_sel_0_0_0_0 = arbs_0_io_in_0_valid & _arbs_0_io_chosen_oh_0[0] & _arbs_0_io_out_0_valid; // @[SwitchAllocator.scala:64:7, :83:45, :95:37, :108:{65,91,97}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_180 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_436
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_180( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_436 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SwitchArbiter_288 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[3], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}}[1], chosen_oh : UInt<3>[1]}
regreset lock_0 : UInt<3>, clock, reset, UInt<3>(0h0)
node unassigned_hi = cat(io.in[2].valid, io.in[1].valid)
node _unassigned_T = cat(unassigned_hi, io.in[0].valid)
node _unassigned_T_1 = not(lock_0)
node unassigned = and(_unassigned_T, _unassigned_T_1)
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire choices : UInt<3>[1]
node _sel_T = not(mask)
node _sel_T_1 = and(unassigned, _sel_T)
node _sel_T_2 = cat(unassigned, _sel_T_1)
node _sel_T_3 = bits(_sel_T_2, 0, 0)
node _sel_T_4 = bits(_sel_T_2, 1, 1)
node _sel_T_5 = bits(_sel_T_2, 2, 2)
node _sel_T_6 = bits(_sel_T_2, 3, 3)
node _sel_T_7 = bits(_sel_T_2, 4, 4)
node _sel_T_8 = bits(_sel_T_2, 5, 5)
node _sel_T_9 = mux(_sel_T_8, UInt<6>(0h20), UInt<6>(0h0))
node _sel_T_10 = mux(_sel_T_7, UInt<6>(0h10), _sel_T_9)
node _sel_T_11 = mux(_sel_T_6, UInt<6>(0h8), _sel_T_10)
node _sel_T_12 = mux(_sel_T_5, UInt<6>(0h4), _sel_T_11)
node _sel_T_13 = mux(_sel_T_4, UInt<6>(0h2), _sel_T_12)
node sel = mux(_sel_T_3, UInt<6>(0h1), _sel_T_13)
node _choices_0_T = shr(sel, 3)
node _choices_0_T_1 = or(sel, _choices_0_T)
connect choices[0], _choices_0_T_1
node _T = not(choices[0])
node _T_1 = and(unassigned, _T)
node _T_2 = bits(_T_1, 0, 0)
node _T_3 = bits(_T_1, 1, 1)
node _T_4 = bits(_T_1, 2, 2)
node _T_5 = mux(_T_4, UInt<3>(0h4), UInt<3>(0h0))
node _T_6 = mux(_T_3, UInt<3>(0h2), _T_5)
node _T_7 = mux(_T_2, UInt<3>(0h1), _T_6)
connect io.in[0].ready, UInt<1>(0h0)
connect io.in[1].ready, UInt<1>(0h0)
connect io.in[2].ready, UInt<1>(0h0)
node in_tails_hi = cat(io.in[2].bits.tail, io.in[1].bits.tail)
node in_tails = cat(in_tails_hi, io.in[0].bits.tail)
node _in_valids_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_1 = and(io.in[0].valid, _in_valids_T)
node _in_valids_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_3 = and(io.in[1].valid, _in_valids_T_2)
node _in_valids_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _in_valids_T_5 = and(io.in[2].valid, _in_valids_T_4)
node in_valids_hi = cat(_in_valids_T_5, _in_valids_T_3)
node in_valids = cat(in_valids_hi, _in_valids_T_1)
node _chosen_T = and(in_valids, lock_0)
node _chosen_T_1 = not(UInt<3>(0h0))
node _chosen_T_2 = and(_chosen_T, _chosen_T_1)
node _chosen_T_3 = orr(_chosen_T_2)
node chosen = mux(_chosen_T_3, lock_0, choices[0])
connect io.chosen_oh[0], chosen
node _io_out_0_valid_T = and(in_valids, chosen)
node _io_out_0_valid_T_1 = orr(_io_out_0_valid_T)
connect io.out[0].valid, _io_out_0_valid_T_1
node _io_out_0_bits_T = bits(chosen, 0, 0)
node _io_out_0_bits_T_1 = bits(chosen, 1, 1)
node _io_out_0_bits_T_2 = bits(chosen, 2, 2)
wire _io_out_0_bits_WIRE : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}, tail : UInt<1>}
node _io_out_0_bits_T_3 = mux(_io_out_0_bits_T, io.in[0].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_4 = mux(_io_out_0_bits_T_1, io.in[1].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_5 = mux(_io_out_0_bits_T_2, io.in[2].bits.tail, UInt<1>(0h0))
node _io_out_0_bits_T_6 = or(_io_out_0_bits_T_3, _io_out_0_bits_T_4)
node _io_out_0_bits_T_7 = or(_io_out_0_bits_T_6, _io_out_0_bits_T_5)
wire _io_out_0_bits_WIRE_1 : UInt<1>
connect _io_out_0_bits_WIRE_1, _io_out_0_bits_T_7
connect _io_out_0_bits_WIRE.tail, _io_out_0_bits_WIRE_1
wire _io_out_0_bits_WIRE_2 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}
wire _io_out_0_bits_WIRE_3 : UInt<1>[10]
node _io_out_0_bits_T_8 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_9 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_10 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[0], UInt<1>(0h0))
node _io_out_0_bits_T_11 = or(_io_out_0_bits_T_8, _io_out_0_bits_T_9)
node _io_out_0_bits_T_12 = or(_io_out_0_bits_T_11, _io_out_0_bits_T_10)
wire _io_out_0_bits_WIRE_4 : UInt<1>
connect _io_out_0_bits_WIRE_4, _io_out_0_bits_T_12
connect _io_out_0_bits_WIRE_3[0], _io_out_0_bits_WIRE_4
node _io_out_0_bits_T_13 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_14 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_15 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[1], UInt<1>(0h0))
node _io_out_0_bits_T_16 = or(_io_out_0_bits_T_13, _io_out_0_bits_T_14)
node _io_out_0_bits_T_17 = or(_io_out_0_bits_T_16, _io_out_0_bits_T_15)
wire _io_out_0_bits_WIRE_5 : UInt<1>
connect _io_out_0_bits_WIRE_5, _io_out_0_bits_T_17
connect _io_out_0_bits_WIRE_3[1], _io_out_0_bits_WIRE_5
node _io_out_0_bits_T_18 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_19 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_20 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[2], UInt<1>(0h0))
node _io_out_0_bits_T_21 = or(_io_out_0_bits_T_18, _io_out_0_bits_T_19)
node _io_out_0_bits_T_22 = or(_io_out_0_bits_T_21, _io_out_0_bits_T_20)
wire _io_out_0_bits_WIRE_6 : UInt<1>
connect _io_out_0_bits_WIRE_6, _io_out_0_bits_T_22
connect _io_out_0_bits_WIRE_3[2], _io_out_0_bits_WIRE_6
node _io_out_0_bits_T_23 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_24 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_25 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[3], UInt<1>(0h0))
node _io_out_0_bits_T_26 = or(_io_out_0_bits_T_23, _io_out_0_bits_T_24)
node _io_out_0_bits_T_27 = or(_io_out_0_bits_T_26, _io_out_0_bits_T_25)
wire _io_out_0_bits_WIRE_7 : UInt<1>
connect _io_out_0_bits_WIRE_7, _io_out_0_bits_T_27
connect _io_out_0_bits_WIRE_3[3], _io_out_0_bits_WIRE_7
node _io_out_0_bits_T_28 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_29 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_30 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[4], UInt<1>(0h0))
node _io_out_0_bits_T_31 = or(_io_out_0_bits_T_28, _io_out_0_bits_T_29)
node _io_out_0_bits_T_32 = or(_io_out_0_bits_T_31, _io_out_0_bits_T_30)
wire _io_out_0_bits_WIRE_8 : UInt<1>
connect _io_out_0_bits_WIRE_8, _io_out_0_bits_T_32
connect _io_out_0_bits_WIRE_3[4], _io_out_0_bits_WIRE_8
node _io_out_0_bits_T_33 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_34 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_35 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[5], UInt<1>(0h0))
node _io_out_0_bits_T_36 = or(_io_out_0_bits_T_33, _io_out_0_bits_T_34)
node _io_out_0_bits_T_37 = or(_io_out_0_bits_T_36, _io_out_0_bits_T_35)
wire _io_out_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_bits_WIRE_9, _io_out_0_bits_T_37
connect _io_out_0_bits_WIRE_3[5], _io_out_0_bits_WIRE_9
node _io_out_0_bits_T_38 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_39 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_40 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[6], UInt<1>(0h0))
node _io_out_0_bits_T_41 = or(_io_out_0_bits_T_38, _io_out_0_bits_T_39)
node _io_out_0_bits_T_42 = or(_io_out_0_bits_T_41, _io_out_0_bits_T_40)
wire _io_out_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_bits_WIRE_10, _io_out_0_bits_T_42
connect _io_out_0_bits_WIRE_3[6], _io_out_0_bits_WIRE_10
node _io_out_0_bits_T_43 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_44 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_45 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[7], UInt<1>(0h0))
node _io_out_0_bits_T_46 = or(_io_out_0_bits_T_43, _io_out_0_bits_T_44)
node _io_out_0_bits_T_47 = or(_io_out_0_bits_T_46, _io_out_0_bits_T_45)
wire _io_out_0_bits_WIRE_11 : UInt<1>
connect _io_out_0_bits_WIRE_11, _io_out_0_bits_T_47
connect _io_out_0_bits_WIRE_3[7], _io_out_0_bits_WIRE_11
node _io_out_0_bits_T_48 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[8], UInt<1>(0h0))
node _io_out_0_bits_T_49 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[8], UInt<1>(0h0))
node _io_out_0_bits_T_50 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[8], UInt<1>(0h0))
node _io_out_0_bits_T_51 = or(_io_out_0_bits_T_48, _io_out_0_bits_T_49)
node _io_out_0_bits_T_52 = or(_io_out_0_bits_T_51, _io_out_0_bits_T_50)
wire _io_out_0_bits_WIRE_12 : UInt<1>
connect _io_out_0_bits_WIRE_12, _io_out_0_bits_T_52
connect _io_out_0_bits_WIRE_3[8], _io_out_0_bits_WIRE_12
node _io_out_0_bits_T_53 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`0`[9], UInt<1>(0h0))
node _io_out_0_bits_T_54 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`0`[9], UInt<1>(0h0))
node _io_out_0_bits_T_55 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`0`[9], UInt<1>(0h0))
node _io_out_0_bits_T_56 = or(_io_out_0_bits_T_53, _io_out_0_bits_T_54)
node _io_out_0_bits_T_57 = or(_io_out_0_bits_T_56, _io_out_0_bits_T_55)
wire _io_out_0_bits_WIRE_13 : UInt<1>
connect _io_out_0_bits_WIRE_13, _io_out_0_bits_T_57
connect _io_out_0_bits_WIRE_3[9], _io_out_0_bits_WIRE_13
connect _io_out_0_bits_WIRE_2.`0`, _io_out_0_bits_WIRE_3
wire _io_out_0_bits_WIRE_14 : UInt<1>[1]
node _io_out_0_bits_T_58 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_59 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_60 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`1`[0], UInt<1>(0h0))
node _io_out_0_bits_T_61 = or(_io_out_0_bits_T_58, _io_out_0_bits_T_59)
node _io_out_0_bits_T_62 = or(_io_out_0_bits_T_61, _io_out_0_bits_T_60)
wire _io_out_0_bits_WIRE_15 : UInt<1>
connect _io_out_0_bits_WIRE_15, _io_out_0_bits_T_62
connect _io_out_0_bits_WIRE_14[0], _io_out_0_bits_WIRE_15
connect _io_out_0_bits_WIRE_2.`1`, _io_out_0_bits_WIRE_14
wire _io_out_0_bits_WIRE_16 : UInt<1>[1]
node _io_out_0_bits_T_63 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_64 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_65 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`2`[0], UInt<1>(0h0))
node _io_out_0_bits_T_66 = or(_io_out_0_bits_T_63, _io_out_0_bits_T_64)
node _io_out_0_bits_T_67 = or(_io_out_0_bits_T_66, _io_out_0_bits_T_65)
wire _io_out_0_bits_WIRE_17 : UInt<1>
connect _io_out_0_bits_WIRE_17, _io_out_0_bits_T_67
connect _io_out_0_bits_WIRE_16[0], _io_out_0_bits_WIRE_17
connect _io_out_0_bits_WIRE_2.`2`, _io_out_0_bits_WIRE_16
wire _io_out_0_bits_WIRE_18 : UInt<1>[1]
node _io_out_0_bits_T_68 = mux(_io_out_0_bits_T, io.in[0].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_69 = mux(_io_out_0_bits_T_1, io.in[1].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_70 = mux(_io_out_0_bits_T_2, io.in[2].bits.vc_sel.`3`[0], UInt<1>(0h0))
node _io_out_0_bits_T_71 = or(_io_out_0_bits_T_68, _io_out_0_bits_T_69)
node _io_out_0_bits_T_72 = or(_io_out_0_bits_T_71, _io_out_0_bits_T_70)
wire _io_out_0_bits_WIRE_19 : UInt<1>
connect _io_out_0_bits_WIRE_19, _io_out_0_bits_T_72
connect _io_out_0_bits_WIRE_18[0], _io_out_0_bits_WIRE_19
connect _io_out_0_bits_WIRE_2.`3`, _io_out_0_bits_WIRE_18
connect _io_out_0_bits_WIRE.vc_sel, _io_out_0_bits_WIRE_2
connect io.out[0].bits, _io_out_0_bits_WIRE
node _T_8 = bits(chosen, 0, 0)
node _T_9 = and(_T_8, io.out[0].ready)
when _T_9 :
connect io.in[0].ready, UInt<1>(0h1)
node _T_10 = bits(chosen, 1, 1)
node _T_11 = and(_T_10, io.out[0].ready)
when _T_11 :
connect io.in[1].ready, UInt<1>(0h1)
node _T_12 = bits(chosen, 2, 2)
node _T_13 = and(_T_12, io.out[0].ready)
when _T_13 :
connect io.in[2].ready, UInt<1>(0h1)
node _T_14 = or(UInt<3>(0h0), chosen)
node _T_15 = and(io.out[0].ready, io.out[0].valid)
when _T_15 :
node _lock_0_T = not(in_tails)
node _lock_0_T_1 = and(chosen, _lock_0_T)
connect lock_0, _lock_0_T_1
node _T_16 = and(io.out[0].ready, io.out[0].valid)
when _T_16 :
node _mask_T = shr(io.chosen_oh[0], 0)
node _mask_T_1 = shr(io.chosen_oh[0], 1)
node _mask_T_2 = shr(io.chosen_oh[0], 2)
node _mask_T_3 = or(_mask_T, _mask_T_1)
node _mask_T_4 = or(_mask_T_3, _mask_T_2)
connect mask, _mask_T_4
else :
node _mask_T_5 = not(mask)
node _mask_T_6 = eq(_mask_T_5, UInt<1>(0h0))
node _mask_T_7 = shl(mask, 1)
node _mask_T_8 = or(_mask_T_7, UInt<1>(0h1))
node _mask_T_9 = mux(_mask_T_6, UInt<1>(0h0), _mask_T_8)
connect mask, _mask_T_9 | module SwitchArbiter_288( // @[SwitchAllocator.scala:17:7]
input clock, // @[SwitchAllocator.scala:17:7]
input reset, // @[SwitchAllocator.scala:17:7]
output io_in_0_ready, // @[SwitchAllocator.scala:18:14]
input io_in_0_valid, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_in_2_ready, // @[SwitchAllocator.scala:18:14]
input io_in_2_valid, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14]
output io_out_0_valid, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_3_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_2_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_1_0, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14]
output io_out_0_bits_tail, // @[SwitchAllocator.scala:18:14]
output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14]
);
reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38]
wire [2:0] unassigned = {io_in_2_valid, 1'h0, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:17:7, :24:38, :25:{23,52,54}]
reg [2:0] mask; // @[SwitchAllocator.scala:27:21]
wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}]
wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71]
wire [2:0] in_valids = {io_in_2_valid, 1'h0, io_in_0_valid}; // @[SwitchAllocator.scala:17:7, :41:24]
wire [2:0] _chosen_T_2 = in_valids & lock_0; // @[SwitchAllocator.scala:24:38, :41:24, :42:33]
wire [2:0] chosen = (|{_chosen_T_2[2], _chosen_T_2[0]}) ? lock_0 : sel[2:0] | sel[5:3]; // @[Mux.scala:50:70]
wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35]
wire [1:0] _GEN = {_io_out_0_valid_T[2], _io_out_0_valid_T[0]}; // @[SwitchAllocator.scala:44:35]
wire [1:0] _GEN_0 = chosen[1:0] | chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}]
always @(posedge clock) begin // @[SwitchAllocator.scala:17:7]
if (reset) begin // @[SwitchAllocator.scala:17:7]
lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38]
mask <= 3'h0; // @[SwitchAllocator.scala:27:21]
end
else begin // @[SwitchAllocator.scala:17:7]
if (|_GEN) // @[SwitchAllocator.scala:44:{35,45}]
lock_0 <= chosen & {~io_in_2_bits_tail, 1'h1, ~io_in_0_bits_tail}; // @[SwitchAllocator.scala:17:7, :24:38, :39:21, :42:21, :53:{25,27}]
mask <= (|_GEN) ? {chosen[2], _GEN_0[1], _GEN_0[0] | chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_332 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_332( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 :
input clock : Clock
input reset : Reset
output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}}
wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate clientNodeOut.d.bits.corrupt
invalidate clientNodeOut.d.bits.data
invalidate clientNodeOut.d.bits.denied
invalidate clientNodeOut.d.bits.sink
invalidate clientNodeOut.d.bits.source
invalidate clientNodeOut.d.bits.size
invalidate clientNodeOut.d.bits.param
invalidate clientNodeOut.d.bits.opcode
invalidate clientNodeOut.d.valid
invalidate clientNodeOut.d.ready
invalidate clientNodeOut.a.bits.corrupt
invalidate clientNodeOut.a.bits.data
invalidate clientNodeOut.a.bits.mask
invalidate clientNodeOut.a.bits.address
invalidate clientNodeOut.a.bits.source
invalidate clientNodeOut.a.bits.size
invalidate clientNodeOut.a.bits.param
invalidate clientNodeOut.a.bits.opcode
invalidate clientNodeOut.a.valid
invalidate clientNodeOut.a.ready
connect auto.client_out, clientNodeOut
wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}}
connect manager_tl.e.bits.sink, UInt<8>(0h0)
connect manager_tl.e.valid, UInt<1>(0h0)
connect manager_tl.e.ready, UInt<1>(0h0)
connect manager_tl.d.bits.corrupt, UInt<1>(0h0)
connect manager_tl.d.bits.data, UInt<64>(0h0)
connect manager_tl.d.bits.denied, UInt<1>(0h0)
connect manager_tl.d.bits.sink, UInt<8>(0h0)
connect manager_tl.d.bits.source, UInt<8>(0h0)
connect manager_tl.d.bits.size, UInt<8>(0h0)
connect manager_tl.d.bits.param, UInt<2>(0h0)
connect manager_tl.d.bits.opcode, UInt<3>(0h0)
connect manager_tl.d.valid, UInt<1>(0h0)
connect manager_tl.d.ready, UInt<1>(0h0)
connect manager_tl.c.bits.corrupt, UInt<1>(0h0)
connect manager_tl.c.bits.data, UInt<64>(0h0)
connect manager_tl.c.bits.address, UInt<64>(0h0)
connect manager_tl.c.bits.source, UInt<8>(0h0)
connect manager_tl.c.bits.size, UInt<8>(0h0)
connect manager_tl.c.bits.param, UInt<3>(0h0)
connect manager_tl.c.bits.opcode, UInt<3>(0h0)
connect manager_tl.c.valid, UInt<1>(0h0)
connect manager_tl.c.ready, UInt<1>(0h0)
connect manager_tl.b.bits.corrupt, UInt<1>(0h0)
connect manager_tl.b.bits.data, UInt<64>(0h0)
connect manager_tl.b.bits.mask, UInt<8>(0h0)
connect manager_tl.b.bits.address, UInt<64>(0h0)
connect manager_tl.b.bits.source, UInt<8>(0h0)
connect manager_tl.b.bits.size, UInt<8>(0h0)
connect manager_tl.b.bits.param, UInt<2>(0h0)
connect manager_tl.b.bits.opcode, UInt<3>(0h0)
connect manager_tl.b.valid, UInt<1>(0h0)
connect manager_tl.b.ready, UInt<1>(0h0)
connect manager_tl.a.bits.corrupt, UInt<1>(0h0)
connect manager_tl.a.bits.data, UInt<64>(0h0)
connect manager_tl.a.bits.mask, UInt<8>(0h0)
connect manager_tl.a.bits.address, UInt<64>(0h0)
connect manager_tl.a.bits.source, UInt<8>(0h0)
connect manager_tl.a.bits.size, UInt<8>(0h0)
connect manager_tl.a.bits.param, UInt<3>(0h0)
connect manager_tl.a.bits.opcode, UInt<3>(0h0)
connect manager_tl.a.valid, UInt<1>(0h0)
connect manager_tl.a.ready, UInt<1>(0h0)
inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c
connect out_channels_1_2.clock, clock
connect out_channels_1_2.reset, reset
wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0)
connect _out_channels_WIRE.bits.data, UInt<64>(0h0)
connect _out_channels_WIRE.bits.mask, UInt<8>(0h0)
connect _out_channels_WIRE.bits.address, UInt<32>(0h0)
connect _out_channels_WIRE.bits.source, UInt<4>(0h0)
connect _out_channels_WIRE.bits.size, UInt<4>(0h0)
connect _out_channels_WIRE.bits.param, UInt<2>(0h0)
connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0)
connect _out_channels_WIRE.valid, UInt<1>(0h0)
connect _out_channels_WIRE.ready, UInt<1>(0h0)
wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect out_channels_3_1.bits, _out_channels_WIRE.bits
connect out_channels_3_1.valid, _out_channels_WIRE.valid
connect out_channels_3_1.ready, _out_channels_WIRE.ready
inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c
connect out_channels_3_2.clock, clock
connect out_channels_3_2.reset, reset
connect io.ser[0].out.valid, UInt<1>(0h0)
connect io.ser[1].out.valid, UInt<1>(0h0)
connect io.ser[2].out.valid, UInt<1>(0h0)
connect io.ser[3].out.valid, UInt<1>(0h0)
connect io.ser[4].out.valid, UInt<1>(0h0)
invalidate io.ser[0].out.bits.flit
invalidate io.ser[1].out.bits.flit
invalidate io.ser[2].out.bits.flit
invalidate io.ser[3].out.bits.flit
invalidate io.ser[4].out.bits.flit
connect out_channels_1_2.io.protocol, clientNodeOut.d
inst ser_1 of GenericSerializer_TLBeatw67_f32
connect ser_1.clock, clock
connect ser_1.reset, reset
connect ser_1.io.in, out_channels_1_2.io.beat
connect io.ser[1].out.bits, ser_1.io.out.bits
connect io.ser[1].out.valid, ser_1.io.out.valid
connect ser_1.io.out.ready, io.ser[1].out.ready
connect out_channels_3_2.io.protocol, out_channels_3_1
inst ser_3 of GenericSerializer_TLBeatw87_f32
connect ser_3.clock, clock
connect ser_3.reset, reset
connect ser_3.io.in, out_channels_3_2.io.beat
connect io.ser[3].out.bits, ser_3.io.out.bits
connect io.ser[3].out.valid, ser_3.io.out.valid
connect ser_3.io.out.ready, io.ser[3].out.ready
node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy)
connect io.debug.ser_busy, _io_debug_ser_busy_T
wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _in_channels_WIRE.bits.sink, UInt<3>(0h0)
connect _in_channels_WIRE.valid, UInt<1>(0h0)
connect _in_channels_WIRE.ready, UInt<1>(0h0)
wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect in_channels_0_1.bits, _in_channels_WIRE.bits
connect in_channels_0_1.valid, _in_channels_WIRE.valid
connect in_channels_0_1.ready, _in_channels_WIRE.ready
inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_0_2.clock, clock
connect in_channels_0_2.reset, reset
inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_1_2.clock, clock
connect in_channels_1_2.reset, reset
wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0)
connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0)
connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0)
connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0)
connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0)
connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0)
connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0)
connect _in_channels_WIRE_1.valid, UInt<1>(0h0)
connect _in_channels_WIRE_1.ready, UInt<1>(0h0)
wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect in_channels_2_1.bits, _in_channels_WIRE_1.bits
connect in_channels_2_1.valid, _in_channels_WIRE_1.valid
connect in_channels_2_1.ready, _in_channels_WIRE_1.ready
inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_2_2.clock, clock
connect in_channels_2_2.reset, reset
inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_3_2.clock, clock
connect in_channels_3_2.reset, reset
inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_4_2.clock, clock
connect in_channels_4_2.reset, reset
connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits
connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid
connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready
inst des_0 of GenericDeserializer_TLBeatw10_f32
connect des_0.clock, clock
connect des_0.reset, reset
connect des_0.io.in, io.ser[0].in
connect in_channels_0_2.io.beat, des_0.io.out
connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt
connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data
connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied
connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink
connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source
connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size
connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param
connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode
connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid
connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready
inst des_1 of GenericDeserializer_TLBeatw67_f32
connect des_1.clock, clock
connect des_1.reset, reset
connect des_1.io.in, io.ser[1].in
connect in_channels_1_2.io.beat, des_1.io.out
connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits
connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid
connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready
inst des_2 of GenericDeserializer_TLBeatw88_f32
connect des_2.clock, clock
connect des_2.reset, reset
connect des_2.io.in, io.ser[2].in
connect in_channels_2_2.io.beat, des_2.io.out
connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt
connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data
connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask
connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address
connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source
connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size
connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param
connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode
connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid
connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready
inst des_3 of GenericDeserializer_TLBeatw87_f32
connect des_3.clock, clock
connect des_3.reset, reset
connect des_3.io.in, io.ser[3].in
connect in_channels_3_2.io.beat, des_3.io.out
connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits
connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid
connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready
inst des_4 of GenericDeserializer_TLBeatw88_f32_1
connect des_4.clock, clock
connect des_4.reset, reset
connect des_4.io.in, io.ser[4].in
connect in_channels_4_2.io.beat, des_4.io.out
node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy)
node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy)
node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy)
node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy)
connect io.debug.des_busy, _io_debug_des_busy_T_3 | module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_1_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_1_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_3_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_3_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_debug_ser_busy, // @[TLSerdes.scala:40:16]
output io_debug_des_busy // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_4_io_busy; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_busy; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28]
wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire [7:0] _in_channels_2_2_io_protocol_bits_size; // @[TLSerdes.scala:80:28]
wire [7:0] _in_channels_2_2_io_protocol_bits_source; // @[TLSerdes.scala:80:28]
wire [63:0] _in_channels_2_2_io_protocol_bits_address; // @[TLSerdes.scala:80:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire [7:0] _in_channels_0_2_io_protocol_bits_sink; // @[TLSerdes.scala:78:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_3_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_3_io_busy; // @[TLSerdes.scala:69:23]
wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23]
wire _ser_1_io_busy; // @[TLSerdes.scala:69:23]
wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50]
wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50]
wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50]
wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50]
wire auto_client_out_a_ready_0 = auto_client_out_a_ready; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_valid_0 = auto_client_out_d_valid; // @[TLSerdes.scala:39:9]
wire [2:0] auto_client_out_d_bits_opcode_0 = auto_client_out_d_bits_opcode; // @[TLSerdes.scala:39:9]
wire [1:0] auto_client_out_d_bits_param_0 = auto_client_out_d_bits_param; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_d_bits_size_0 = auto_client_out_d_bits_size; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_d_bits_source_0 = auto_client_out_d_bits_source; // @[TLSerdes.scala:39:9]
wire [2:0] auto_client_out_d_bits_sink_0 = auto_client_out_d_bits_sink; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_bits_denied_0 = auto_client_out_d_bits_denied; // @[TLSerdes.scala:39:9]
wire [63:0] auto_client_out_d_bits_data_0 = auto_client_out_d_bits_data; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_bits_corrupt_0 = auto_client_out_d_bits_corrupt; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_ready_0 = io_ser_1_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_ready_0 = io_ser_3_out_ready; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9]
wire [1:0] _out_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] out_channels_3_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [7:0] manager_tl_a_bits_size = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_a_bits_source = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_a_bits_mask = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_c_bits_size = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_c_bits_source = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_e_bits_sink = 8'h0; // @[TLSerdes.scala:47:72]
wire [7:0] _out_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] out_channels_3_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [2:0] manager_tl_a_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_a_bits_param = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_c_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_c_bits_param = 3'h0; // @[TLSerdes.scala:47:72]
wire [2:0] _out_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] out_channels_3_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _in_channels_WIRE_bits_sink = 3'h0; // @[Bundles.scala:267:74]
wire [2:0] _in_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _in_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [3:0] _out_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _out_channels_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] out_channels_3_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] out_channels_3_1_bits_source = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _in_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _in_channels_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [63:0] manager_tl_a_bits_address = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_a_bits_data = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_c_bits_address = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_c_bits_data = 64'h0; // @[TLSerdes.scala:47:72]
wire [63:0] _out_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] out_channels_3_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _in_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [31:0] io_ser_0_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_2_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_4_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9]
wire [31:0] _out_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] out_channels_3_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _in_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_2_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire io_ser_4_out_valid = 1'h0; // @[TLSerdes.scala:39:9]
wire manager_tl_a_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_a_valid = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_a_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_b_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_c_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_c_valid = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_c_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_d_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_e_ready = 1'h0; // @[TLSerdes.scala:47:72]
wire manager_tl_e_valid = 1'h0; // @[TLSerdes.scala:47:72]
wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _out_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire out_channels_3_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire out_channels_3_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire in_channels_0_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _in_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74]
wire _in_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74]
wire _in_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire in_channels_2_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire io_ser_0_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire io_ser_2_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire io_ser_4_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire out_channels_3_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50]
wire clientNodeOut_a_ready = auto_client_out_a_ready_0; // @[TLSerdes.scala:39:9]
wire clientNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] clientNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] clientNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] clientNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] clientNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] clientNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] clientNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] clientNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire clientNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire clientNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire clientNodeOut_d_valid = auto_client_out_d_valid_0; // @[TLSerdes.scala:39:9]
wire [2:0] clientNodeOut_d_bits_opcode = auto_client_out_d_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [1:0] clientNodeOut_d_bits_param = auto_client_out_d_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] clientNodeOut_d_bits_size = auto_client_out_d_bits_size_0; // @[TLSerdes.scala:39:9]
wire [3:0] clientNodeOut_d_bits_source = auto_client_out_d_bits_source_0; // @[TLSerdes.scala:39:9]
wire [2:0] clientNodeOut_d_bits_sink = auto_client_out_d_bits_sink_0; // @[TLSerdes.scala:39:9]
wire clientNodeOut_d_bits_denied = auto_client_out_d_bits_denied_0; // @[TLSerdes.scala:39:9]
wire [63:0] clientNodeOut_d_bits_data = auto_client_out_d_bits_data_0; // @[TLSerdes.scala:39:9]
wire clientNodeOut_d_bits_corrupt = auto_client_out_d_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire _io_debug_ser_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_3; // @[package.scala:81:59]
wire [2:0] auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
wire [2:0] auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9]
wire [3:0] auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9]
wire [31:0] auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9]
wire [7:0] auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9]
wire [63:0] auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9]
wire auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
wire auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9]
wire auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
wire [31:0] io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9]
wire io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9]
wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
wire io_debug_ser_busy_0; // @[TLSerdes.scala:39:9]
wire io_debug_des_busy_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_valid_0 = clientNodeOut_a_valid; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_opcode_0 = clientNodeOut_a_bits_opcode; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_param_0 = clientNodeOut_a_bits_param; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_size_0 = clientNodeOut_a_bits_size; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_source_0 = clientNodeOut_a_bits_source; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_address_0 = clientNodeOut_a_bits_address; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_mask_0 = clientNodeOut_a_bits_mask; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_data_0 = clientNodeOut_a_bits_data; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_corrupt_0 = clientNodeOut_a_bits_corrupt; // @[TLSerdes.scala:39:9]
assign auto_client_out_d_ready_0 = clientNodeOut_d_ready; // @[TLSerdes.scala:39:9]
wire [2:0] manager_tl_b_bits_opcode; // @[TLSerdes.scala:47:72]
wire [1:0] manager_tl_b_bits_param; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_b_bits_size; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_b_bits_source; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_b_bits_address; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_b_bits_mask; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_b_bits_data; // @[TLSerdes.scala:47:72]
wire manager_tl_b_bits_corrupt; // @[TLSerdes.scala:47:72]
wire manager_tl_b_valid; // @[TLSerdes.scala:47:72]
wire [2:0] manager_tl_d_bits_opcode; // @[TLSerdes.scala:47:72]
wire [1:0] manager_tl_d_bits_param; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_d_bits_size; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_d_bits_source; // @[TLSerdes.scala:47:72]
wire [7:0] manager_tl_d_bits_sink; // @[TLSerdes.scala:47:72]
wire manager_tl_d_bits_denied; // @[TLSerdes.scala:47:72]
wire [63:0] manager_tl_d_bits_data; // @[TLSerdes.scala:47:72]
wire manager_tl_d_bits_corrupt; // @[TLSerdes.scala:47:72]
wire manager_tl_d_valid; // @[TLSerdes.scala:47:72]
assign _io_debug_ser_busy_T = _ser_1_io_busy | _ser_3_io_busy; // @[TLSerdes.scala:69:23]
assign io_debug_ser_busy_0 = _io_debug_ser_busy_T; // @[TLSerdes.scala:39:9]
wire [2:0] in_channels_0_1_bits_sink; // @[Bundles.scala:267:61]
wire in_channels_0_1_valid; // @[Bundles.scala:267:61]
wire [2:0] in_channels_2_1_bits_opcode; // @[Bundles.scala:265:61]
wire [2:0] in_channels_2_1_bits_param; // @[Bundles.scala:265:61]
wire [3:0] in_channels_2_1_bits_size; // @[Bundles.scala:265:61]
wire [3:0] in_channels_2_1_bits_source; // @[Bundles.scala:265:61]
wire [31:0] in_channels_2_1_bits_address; // @[Bundles.scala:265:61]
wire [63:0] in_channels_2_1_bits_data; // @[Bundles.scala:265:61]
wire in_channels_2_1_bits_corrupt; // @[Bundles.scala:265:61]
wire in_channels_2_1_valid; // @[Bundles.scala:265:61]
assign in_channels_0_1_bits_sink = _in_channels_0_2_io_protocol_bits_sink[2:0]; // @[TLSerdes.scala:78:28, :85:9]
assign in_channels_2_1_bits_size = _in_channels_2_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:80:28, :85:9]
assign in_channels_2_1_bits_source = _in_channels_2_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:80:28, :85:9]
assign in_channels_2_1_bits_address = _in_channels_2_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:80:28, :85:9]
assign clientNodeOut_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:82:28, :85:9]
assign clientNodeOut_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:82:28, :85:9]
assign clientNodeOut_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:82:28, :85:9]
wire _io_debug_des_busy_T; // @[package.scala:81:59]
wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23]
wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23]
assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23]
assign io_debug_des_busy_0 = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9]
TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (clientNodeOut_d_ready),
.io_protocol_valid (clientNodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_protocol_bits_opcode (clientNodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_protocol_bits_param (clientNodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_protocol_bits_size ({4'h0, clientNodeOut_d_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({4'h0, clientNodeOut_d_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_sink ({5'h0, clientNodeOut_d_bits_sink}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_denied (clientNodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_protocol_bits_data (clientNodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_protocol_bits_corrupt (clientNodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_1_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_1_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail)
); // @[TLSerdes.scala:60:50]
TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50]
.clock (clock),
.reset (reset),
.io_beat_ready (_ser_3_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_bits_head (_out_channels_3_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail)
); // @[TLSerdes.scala:62:50]
GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_1_io_in_ready),
.io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50]
.io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50]
.io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50]
.io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50]
.io_out_ready (io_ser_1_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_1_out_valid_0),
.io_out_bits_flit (io_ser_1_out_bits_flit_0),
.io_busy (_ser_1_io_busy)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_3_io_in_ready),
.io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50]
.io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50]
.io_out_ready (io_ser_3_out_ready_0), // @[TLSerdes.scala:39:9]
.io_out_valid (io_ser_3_out_valid_0),
.io_out_bits_flit (io_ser_3_out_bits_flit_0),
.io_busy (_ser_3_io_busy)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_0_1_valid),
.io_protocol_bits_sink (_in_channels_0_2_io_protocol_bits_sink),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (manager_tl_d_valid),
.io_protocol_bits_opcode (manager_tl_d_bits_opcode),
.io_protocol_bits_param (manager_tl_d_bits_param),
.io_protocol_bits_size (manager_tl_d_bits_size),
.io_protocol_bits_source (manager_tl_d_bits_source),
.io_protocol_bits_sink (manager_tl_d_bits_sink),
.io_protocol_bits_denied (manager_tl_d_bits_denied),
.io_protocol_bits_data (manager_tl_d_bits_data),
.io_protocol_bits_corrupt (manager_tl_d_bits_corrupt),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (in_channels_2_1_valid),
.io_protocol_bits_opcode (in_channels_2_1_bits_opcode),
.io_protocol_bits_param (in_channels_2_1_bits_param),
.io_protocol_bits_size (_in_channels_2_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_2_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_2_2_io_protocol_bits_address),
.io_protocol_bits_data (in_channels_2_1_bits_data),
.io_protocol_bits_corrupt (in_channels_2_1_bits_corrupt),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_protocol_valid (manager_tl_b_valid),
.io_protocol_bits_opcode (manager_tl_b_bits_opcode),
.io_protocol_bits_param (manager_tl_b_bits_param),
.io_protocol_bits_size (manager_tl_b_bits_size),
.io_protocol_bits_source (manager_tl_b_bits_source),
.io_protocol_bits_address (manager_tl_b_bits_address),
.io_protocol_bits_mask (manager_tl_b_bits_mask),
.io_protocol_bits_data (manager_tl_b_bits_data),
.io_protocol_bits_corrupt (manager_tl_b_bits_corrupt),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (clientNodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_protocol_valid (clientNodeOut_a_valid),
.io_protocol_bits_opcode (clientNodeOut_a_bits_opcode),
.io_protocol_bits_param (clientNodeOut_a_bits_param),
.io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address),
.io_protocol_bits_mask (clientNodeOut_a_bits_mask),
.io_protocol_bits_data (clientNodeOut_a_bits_data),
.io_protocol_bits_corrupt (clientNodeOut_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_0_in_ready_0),
.io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_payload (_des_0_io_out_bits_payload),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready_0),
.io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (_des_1_io_out_bits_payload),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail),
.io_busy (_io_debug_des_busy_T)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready_0),
.io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (_des_2_io_out_bits_payload),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail),
.io_busy (_des_2_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready_0),
.io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_payload (_des_3_io_out_bits_payload),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail),
.io_busy (_des_3_io_busy)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32_1 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready_0),
.io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9]
.io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9]
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail),
.io_busy (_des_4_io_busy)
); // @[TLSerdes.scala:86:23]
assign auto_client_out_a_valid = auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_opcode = auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_param = auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_size = auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_source = auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_address = auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_mask = auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_data = auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_a_bits_corrupt = auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9]
assign auto_client_out_d_ready = auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_out_valid = io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_1_out_bits_flit = io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_out_valid = io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9]
assign io_ser_3_out_bits_flit = io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9]
assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9]
assign io_debug_ser_busy = io_debug_ser_busy_0; // @[TLSerdes.scala:39:9]
assign io_debug_des_busy = io_debug_des_busy_0; // @[TLSerdes.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BoomProbeUnit_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, rep : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<8>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<8>, voluntary : UInt<1>}}, flip way_en : UInt<8>, flip wb_rdy : UInt<1>, flip mshr_rdy : UInt<1>, mshr_wb_rdy : UInt<1>, flip block_state : { state : UInt<2>}, lsu_release : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, state : { valid : UInt<1>, bits : UInt<40>}}
regreset state : UInt<4>, clock, reset, UInt<4>(0h0)
reg req : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, clock
node req_idx = bits(req.address, 11, 6)
node req_tag = shr(req.address, 12)
reg way_en : UInt, clock
node tag_matches = orr(way_en)
reg old_coh : { state : UInt<2>}, clock
wire miss_coh : { state : UInt<2>}
connect miss_coh.state, UInt<2>(0h0)
node reply_coh = mux(tag_matches, old_coh, miss_coh)
node _r_T = cat(req.param, reply_coh.state)
node _r_T_1 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_2 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_3 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_4 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_5 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_6 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_7 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_8 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_9 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_10 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_11 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_12 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_13 = eq(_r_T_12, _r_T)
node _r_T_14 = mux(_r_T_13, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_15 = mux(_r_T_13, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_16 = mux(_r_T_13, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_17 = eq(_r_T_11, _r_T)
node _r_T_18 = mux(_r_T_17, UInt<1>(0h0), _r_T_14)
node _r_T_19 = mux(_r_T_17, UInt<3>(0h2), _r_T_15)
node _r_T_20 = mux(_r_T_17, UInt<2>(0h0), _r_T_16)
node _r_T_21 = eq(_r_T_10, _r_T)
node _r_T_22 = mux(_r_T_21, UInt<1>(0h0), _r_T_18)
node _r_T_23 = mux(_r_T_21, UInt<3>(0h1), _r_T_19)
node _r_T_24 = mux(_r_T_21, UInt<2>(0h0), _r_T_20)
node _r_T_25 = eq(_r_T_9, _r_T)
node _r_T_26 = mux(_r_T_25, UInt<1>(0h1), _r_T_22)
node _r_T_27 = mux(_r_T_25, UInt<3>(0h1), _r_T_23)
node _r_T_28 = mux(_r_T_25, UInt<2>(0h0), _r_T_24)
node _r_T_29 = eq(_r_T_8, _r_T)
node _r_T_30 = mux(_r_T_29, UInt<1>(0h0), _r_T_26)
node _r_T_31 = mux(_r_T_29, UInt<3>(0h5), _r_T_27)
node _r_T_32 = mux(_r_T_29, UInt<2>(0h0), _r_T_28)
node _r_T_33 = eq(_r_T_7, _r_T)
node _r_T_34 = mux(_r_T_33, UInt<1>(0h0), _r_T_30)
node _r_T_35 = mux(_r_T_33, UInt<3>(0h4), _r_T_31)
node _r_T_36 = mux(_r_T_33, UInt<2>(0h1), _r_T_32)
node _r_T_37 = eq(_r_T_6, _r_T)
node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_34)
node _r_T_39 = mux(_r_T_37, UInt<3>(0h0), _r_T_35)
node _r_T_40 = mux(_r_T_37, UInt<2>(0h1), _r_T_36)
node _r_T_41 = eq(_r_T_5, _r_T)
node _r_T_42 = mux(_r_T_41, UInt<1>(0h1), _r_T_38)
node _r_T_43 = mux(_r_T_41, UInt<3>(0h0), _r_T_39)
node _r_T_44 = mux(_r_T_41, UInt<2>(0h1), _r_T_40)
node _r_T_45 = eq(_r_T_4, _r_T)
node _r_T_46 = mux(_r_T_45, UInt<1>(0h0), _r_T_42)
node _r_T_47 = mux(_r_T_45, UInt<3>(0h5), _r_T_43)
node _r_T_48 = mux(_r_T_45, UInt<2>(0h0), _r_T_44)
node _r_T_49 = eq(_r_T_3, _r_T)
node _r_T_50 = mux(_r_T_49, UInt<1>(0h0), _r_T_46)
node _r_T_51 = mux(_r_T_49, UInt<3>(0h4), _r_T_47)
node _r_T_52 = mux(_r_T_49, UInt<2>(0h1), _r_T_48)
node _r_T_53 = eq(_r_T_2, _r_T)
node _r_T_54 = mux(_r_T_53, UInt<1>(0h0), _r_T_50)
node _r_T_55 = mux(_r_T_53, UInt<3>(0h3), _r_T_51)
node _r_T_56 = mux(_r_T_53, UInt<2>(0h2), _r_T_52)
node _r_T_57 = eq(_r_T_1, _r_T)
node is_dirty = mux(_r_T_57, UInt<1>(0h1), _r_T_54)
node report_param = mux(_r_T_57, UInt<3>(0h3), _r_T_55)
node r_3 = mux(_r_T_57, UInt<2>(0h2), _r_T_56)
wire new_coh : { state : UInt<2>}
connect new_coh.state, r_3
node _io_state_valid_T = neq(state, UInt<4>(0h0))
connect io.state.valid, _io_state_valid_T
connect io.state.bits, req.address
node _io_req_ready_T = eq(state, UInt<4>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_rep_valid_T = eq(state, UInt<4>(0h6))
connect io.rep.valid, _io_rep_valid_T
wire io_rep_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}
connect io_rep_bits_c.opcode, UInt<3>(0h4)
connect io_rep_bits_c.param, report_param
connect io_rep_bits_c.size, req.size
connect io_rep_bits_c.source, req.source
connect io_rep_bits_c.address, req.address
invalidate io_rep_bits_c.data
connect io_rep_bits_c.corrupt, UInt<1>(0h0)
connect io.rep.bits, io_rep_bits_c
node _T = eq(io.rep.valid, UInt<1>(0h0))
node opdata = bits(io.rep.bits.opcode, 0, 0)
node _T_1 = eq(opdata, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: ProbeUnit should not send ProbeAcks with data, WritebackUnit should handle it\n at dcache.scala:185 assert(!io.rep.valid || !edge.hasData(io.rep.bits),\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_meta_read_valid_T = eq(state, UInt<4>(0h1))
connect io.meta_read.valid, _io_meta_read_valid_T
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
node _io_meta_read_bits_way_en_T = not(UInt<8>(0h0))
connect io.meta_read.bits.way_en, _io_meta_read_bits_way_en_T
node _io_meta_write_valid_T = eq(state, UInt<4>(0h9))
connect io.meta_write.valid, _io_meta_write_valid_T
connect io.meta_write.bits.way_en, way_en
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.tag, req_tag
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.data.coh, new_coh
node _io_wb_req_valid_T = eq(state, UInt<4>(0h7))
connect io.wb_req.valid, _io_wb_req_valid_T
connect io.wb_req.bits.source, req.source
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.tag, req_tag
connect io.wb_req.bits.param, report_param
connect io.wb_req.bits.way_en, way_en
connect io.wb_req.bits.voluntary, UInt<1>(0h0)
node _io_mshr_wb_rdy_T = eq(state, UInt<4>(0h6))
node _io_mshr_wb_rdy_T_1 = eq(state, UInt<4>(0h7))
node _io_mshr_wb_rdy_T_2 = eq(state, UInt<4>(0h8))
node _io_mshr_wb_rdy_T_3 = eq(state, UInt<4>(0h9))
node _io_mshr_wb_rdy_T_4 = eq(state, UInt<4>(0ha))
node _io_mshr_wb_rdy_T_5 = or(_io_mshr_wb_rdy_T, _io_mshr_wb_rdy_T_1)
node _io_mshr_wb_rdy_T_6 = or(_io_mshr_wb_rdy_T_5, _io_mshr_wb_rdy_T_2)
node _io_mshr_wb_rdy_T_7 = or(_io_mshr_wb_rdy_T_6, _io_mshr_wb_rdy_T_3)
node _io_mshr_wb_rdy_T_8 = or(_io_mshr_wb_rdy_T_7, _io_mshr_wb_rdy_T_4)
node _io_mshr_wb_rdy_T_9 = eq(_io_mshr_wb_rdy_T_8, UInt<1>(0h0))
connect io.mshr_wb_rdy, _io_mshr_wb_rdy_T_9
node _io_lsu_release_valid_T = eq(state, UInt<4>(0h5))
connect io.lsu_release.valid, _io_lsu_release_valid_T
wire io_lsu_release_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}
connect io_lsu_release_bits_c.opcode, UInt<3>(0h4)
connect io_lsu_release_bits_c.param, report_param
connect io_lsu_release_bits_c.size, req.size
connect io_lsu_release_bits_c.source, req.source
connect io_lsu_release_bits_c.address, req.address
invalidate io_lsu_release_bits_c.data
connect io_lsu_release_bits_c.corrupt, UInt<1>(0h0)
connect io.lsu_release.bits, io_lsu_release_bits_c
node _T_6 = eq(state, UInt<4>(0h0))
when _T_6 :
node _T_7 = and(io.req.ready, io.req.valid)
when _T_7 :
connect state, UInt<4>(0h1)
connect req, io.req.bits
else :
node _T_8 = eq(state, UInt<4>(0h1))
when _T_8 :
node _T_9 = and(io.meta_read.ready, io.meta_read.valid)
when _T_9 :
connect state, UInt<4>(0h2)
else :
node _T_10 = eq(state, UInt<4>(0h2))
when _T_10 :
connect state, UInt<4>(0h3)
else :
node _T_11 = eq(state, UInt<4>(0h3))
when _T_11 :
connect old_coh, io.block_state
connect way_en, io.way_en
node _state_T = and(io.mshr_rdy, io.wb_rdy)
node _state_T_1 = mux(_state_T, UInt<4>(0h4), UInt<4>(0h1))
connect state, _state_T_1
else :
node _T_12 = eq(state, UInt<4>(0h4))
when _T_12 :
node _state_T_2 = and(tag_matches, is_dirty)
node _state_T_3 = mux(_state_T_2, UInt<4>(0h7), UInt<4>(0h5))
connect state, _state_T_3
else :
node _T_13 = eq(state, UInt<4>(0h5))
when _T_13 :
node _T_14 = and(io.lsu_release.ready, io.lsu_release.valid)
when _T_14 :
connect state, UInt<4>(0h6)
else :
node _T_15 = eq(state, UInt<4>(0h6))
when _T_15 :
when io.rep.ready :
node _state_T_4 = mux(tag_matches, UInt<4>(0h9), UInt<4>(0h0))
connect state, _state_T_4
else :
node _T_16 = eq(state, UInt<4>(0h7))
when _T_16 :
node _T_17 = and(io.wb_req.ready, io.wb_req.valid)
when _T_17 :
connect state, UInt<4>(0h8)
else :
node _T_18 = eq(state, UInt<4>(0h8))
when _T_18 :
when io.wb_req.ready :
connect state, UInt<4>(0h9)
else :
node _T_19 = eq(state, UInt<4>(0h9))
when _T_19 :
node _T_20 = and(io.meta_write.ready, io.meta_write.valid)
when _T_20 :
connect state, UInt<4>(0ha)
else :
node _T_21 = eq(state, UInt<4>(0ha))
when _T_21 :
connect state, UInt<4>(0h0) | module BoomProbeUnit_1( // @[dcache.scala:145:7]
input clock, // @[dcache.scala:145:7]
input reset, // @[dcache.scala:145:7]
output io_req_ready, // @[dcache.scala:146:14]
input io_req_valid, // @[dcache.scala:146:14]
input [2:0] io_req_bits_opcode, // @[dcache.scala:146:14]
input [1:0] io_req_bits_param, // @[dcache.scala:146:14]
input [3:0] io_req_bits_size, // @[dcache.scala:146:14]
input [2:0] io_req_bits_source, // @[dcache.scala:146:14]
input [31:0] io_req_bits_address, // @[dcache.scala:146:14]
input [15:0] io_req_bits_mask, // @[dcache.scala:146:14]
input [127:0] io_req_bits_data, // @[dcache.scala:146:14]
input io_req_bits_corrupt, // @[dcache.scala:146:14]
input io_rep_ready, // @[dcache.scala:146:14]
output io_rep_valid, // @[dcache.scala:146:14]
output [2:0] io_rep_bits_param, // @[dcache.scala:146:14]
output [3:0] io_rep_bits_size, // @[dcache.scala:146:14]
output [2:0] io_rep_bits_source, // @[dcache.scala:146:14]
output [31:0] io_rep_bits_address, // @[dcache.scala:146:14]
input io_meta_read_ready, // @[dcache.scala:146:14]
output io_meta_read_valid, // @[dcache.scala:146:14]
output [5:0] io_meta_read_bits_idx, // @[dcache.scala:146:14]
output [19:0] io_meta_read_bits_tag, // @[dcache.scala:146:14]
input io_meta_write_ready, // @[dcache.scala:146:14]
output io_meta_write_valid, // @[dcache.scala:146:14]
output [5:0] io_meta_write_bits_idx, // @[dcache.scala:146:14]
output [7:0] io_meta_write_bits_way_en, // @[dcache.scala:146:14]
output [19:0] io_meta_write_bits_tag, // @[dcache.scala:146:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[dcache.scala:146:14]
output [19:0] io_meta_write_bits_data_tag, // @[dcache.scala:146:14]
input io_wb_req_ready, // @[dcache.scala:146:14]
output io_wb_req_valid, // @[dcache.scala:146:14]
output [19:0] io_wb_req_bits_tag, // @[dcache.scala:146:14]
output [5:0] io_wb_req_bits_idx, // @[dcache.scala:146:14]
output [2:0] io_wb_req_bits_source, // @[dcache.scala:146:14]
output [2:0] io_wb_req_bits_param, // @[dcache.scala:146:14]
output [7:0] io_wb_req_bits_way_en, // @[dcache.scala:146:14]
input [7:0] io_way_en, // @[dcache.scala:146:14]
input io_wb_rdy, // @[dcache.scala:146:14]
input io_mshr_rdy, // @[dcache.scala:146:14]
output io_mshr_wb_rdy, // @[dcache.scala:146:14]
input [1:0] io_block_state_state, // @[dcache.scala:146:14]
input io_lsu_release_ready, // @[dcache.scala:146:14]
output io_lsu_release_valid, // @[dcache.scala:146:14]
output [2:0] io_lsu_release_bits_param, // @[dcache.scala:146:14]
output [3:0] io_lsu_release_bits_size, // @[dcache.scala:146:14]
output [2:0] io_lsu_release_bits_source, // @[dcache.scala:146:14]
output [31:0] io_lsu_release_bits_address, // @[dcache.scala:146:14]
output io_state_valid, // @[dcache.scala:146:14]
output [39:0] io_state_bits // @[dcache.scala:146:14]
);
wire io_req_valid_0 = io_req_valid; // @[dcache.scala:145:7]
wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[dcache.scala:145:7]
wire [1:0] io_req_bits_param_0 = io_req_bits_param; // @[dcache.scala:145:7]
wire [3:0] io_req_bits_size_0 = io_req_bits_size; // @[dcache.scala:145:7]
wire [2:0] io_req_bits_source_0 = io_req_bits_source; // @[dcache.scala:145:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[dcache.scala:145:7]
wire [15:0] io_req_bits_mask_0 = io_req_bits_mask; // @[dcache.scala:145:7]
wire [127:0] io_req_bits_data_0 = io_req_bits_data; // @[dcache.scala:145:7]
wire io_req_bits_corrupt_0 = io_req_bits_corrupt; // @[dcache.scala:145:7]
wire io_rep_ready_0 = io_rep_ready; // @[dcache.scala:145:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[dcache.scala:145:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[dcache.scala:145:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[dcache.scala:145:7]
wire [7:0] io_way_en_0 = io_way_en; // @[dcache.scala:145:7]
wire io_wb_rdy_0 = io_wb_rdy; // @[dcache.scala:145:7]
wire io_mshr_rdy_0 = io_mshr_rdy; // @[dcache.scala:145:7]
wire [1:0] io_block_state_state_0 = io_block_state_state; // @[dcache.scala:145:7]
wire io_lsu_release_ready_0 = io_lsu_release_ready; // @[dcache.scala:145:7]
wire [3:0] _r_T_1 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_2 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_3 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_4 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_5 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_6 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_7 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_8 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_9 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_10 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_11 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_12 = 4'h8; // @[Metadata.scala:133:10]
wire [1:0] miss_coh_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_16 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_20 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_24 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_28 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_32 = 2'h0; // @[Misc.scala:38:63]
wire [7:0] io_meta_read_bits_way_en = 8'hFF; // @[dcache.scala:145:7]
wire [7:0] _io_meta_read_bits_way_en_T = 8'hFF; // @[dcache.scala:191:31]
wire io_rep_bits_corrupt = 1'h0; // @[dcache.scala:145:7]
wire io_wb_req_bits_voluntary = 1'h0; // @[dcache.scala:145:7]
wire io_lsu_release_bits_corrupt = 1'h0; // @[dcache.scala:145:7]
wire _r_T_14 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_18 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_22 = 1'h0; // @[Misc.scala:38:9]
wire io_rep_bits_c_corrupt = 1'h0; // @[Edges.scala:416:17]
wire opdata = 1'h0; // @[Edges.scala:102:36]
wire io_lsu_release_bits_c_corrupt = 1'h0; // @[Edges.scala:416:17]
wire [127:0] io_rep_bits_data = 128'h0; // @[dcache.scala:145:7]
wire [127:0] io_lsu_release_bits_data = 128'h0; // @[dcache.scala:145:7]
wire [127:0] io_rep_bits_c_data = 128'h0; // @[Edges.scala:416:17]
wire [127:0] io_lsu_release_bits_c_data = 128'h0; // @[Edges.scala:416:17]
wire [2:0] io_rep_bits_opcode = 3'h4; // @[dcache.scala:145:7]
wire [2:0] io_lsu_release_bits_opcode = 3'h4; // @[dcache.scala:145:7]
wire _io_req_ready_T; // @[dcache.scala:181:25]
wire [2:0] io_rep_bits_c_opcode = 3'h4; // @[Edges.scala:416:17]
wire [2:0] io_lsu_release_bits_c_opcode = 3'h4; // @[Edges.scala:416:17]
wire _io_rep_valid_T; // @[dcache.scala:182:25]
wire [2:0] io_rep_bits_c_param; // @[Edges.scala:416:17]
wire [3:0] io_rep_bits_c_size; // @[Edges.scala:416:17]
wire [2:0] io_rep_bits_c_source; // @[Edges.scala:416:17]
wire [31:0] io_rep_bits_c_address; // @[Edges.scala:416:17]
wire _io_meta_read_valid_T; // @[dcache.scala:188:31]
wire [5:0] req_idx; // @[dcache.scala:168:28]
wire [19:0] req_tag; // @[dcache.scala:169:29]
wire _io_meta_write_valid_T; // @[dcache.scala:193:32]
wire [1:0] new_coh_state; // @[Metadata.scala:160:20]
wire _io_wb_req_valid_T; // @[dcache.scala:200:28]
wire [2:0] report_param; // @[Misc.scala:38:36]
wire _io_mshr_wb_rdy_T_9; // @[dcache.scala:209:21]
wire _io_lsu_release_valid_T; // @[dcache.scala:211:33]
wire [2:0] io_lsu_release_bits_c_param; // @[Edges.scala:416:17]
wire [3:0] io_lsu_release_bits_c_size; // @[Edges.scala:416:17]
wire [2:0] io_lsu_release_bits_c_source; // @[Edges.scala:416:17]
wire [31:0] io_lsu_release_bits_c_address; // @[Edges.scala:416:17]
wire _io_state_valid_T; // @[dcache.scala:178:27]
wire io_req_ready_0; // @[dcache.scala:145:7]
wire [2:0] io_rep_bits_param_0; // @[dcache.scala:145:7]
wire [3:0] io_rep_bits_size_0; // @[dcache.scala:145:7]
wire [2:0] io_rep_bits_source_0; // @[dcache.scala:145:7]
wire [31:0] io_rep_bits_address_0; // @[dcache.scala:145:7]
wire io_rep_valid_0; // @[dcache.scala:145:7]
wire [5:0] io_meta_read_bits_idx_0; // @[dcache.scala:145:7]
wire [19:0] io_meta_read_bits_tag_0; // @[dcache.scala:145:7]
wire io_meta_read_valid_0; // @[dcache.scala:145:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[dcache.scala:145:7]
wire [19:0] io_meta_write_bits_data_tag_0; // @[dcache.scala:145:7]
wire [5:0] io_meta_write_bits_idx_0; // @[dcache.scala:145:7]
wire [7:0] io_meta_write_bits_way_en_0; // @[dcache.scala:145:7]
wire [19:0] io_meta_write_bits_tag_0; // @[dcache.scala:145:7]
wire io_meta_write_valid_0; // @[dcache.scala:145:7]
wire [19:0] io_wb_req_bits_tag_0; // @[dcache.scala:145:7]
wire [5:0] io_wb_req_bits_idx_0; // @[dcache.scala:145:7]
wire [2:0] io_wb_req_bits_source_0; // @[dcache.scala:145:7]
wire [2:0] io_wb_req_bits_param_0; // @[dcache.scala:145:7]
wire [7:0] io_wb_req_bits_way_en_0; // @[dcache.scala:145:7]
wire io_wb_req_valid_0; // @[dcache.scala:145:7]
wire [2:0] io_lsu_release_bits_param_0; // @[dcache.scala:145:7]
wire [3:0] io_lsu_release_bits_size_0; // @[dcache.scala:145:7]
wire [2:0] io_lsu_release_bits_source_0; // @[dcache.scala:145:7]
wire [31:0] io_lsu_release_bits_address_0; // @[dcache.scala:145:7]
wire io_lsu_release_valid_0; // @[dcache.scala:145:7]
wire io_state_valid_0; // @[dcache.scala:145:7]
wire [39:0] io_state_bits_0; // @[dcache.scala:145:7]
wire io_mshr_wb_rdy_0; // @[dcache.scala:145:7]
reg [3:0] state; // @[dcache.scala:165:22]
reg [2:0] req_opcode; // @[dcache.scala:167:16]
reg [1:0] req_param; // @[dcache.scala:167:16]
reg [3:0] req_size; // @[dcache.scala:167:16]
assign io_rep_bits_c_size = req_size; // @[Edges.scala:416:17]
assign io_lsu_release_bits_c_size = req_size; // @[Edges.scala:416:17]
reg [2:0] req_source; // @[dcache.scala:167:16]
assign io_wb_req_bits_source_0 = req_source; // @[dcache.scala:145:7, :167:16]
assign io_rep_bits_c_source = req_source; // @[Edges.scala:416:17]
assign io_lsu_release_bits_c_source = req_source; // @[Edges.scala:416:17]
reg [31:0] req_address; // @[dcache.scala:167:16]
assign io_rep_bits_c_address = req_address; // @[Edges.scala:416:17]
assign io_lsu_release_bits_c_address = req_address; // @[Edges.scala:416:17]
reg [15:0] req_mask; // @[dcache.scala:167:16]
reg [127:0] req_data; // @[dcache.scala:167:16]
reg req_corrupt; // @[dcache.scala:167:16]
assign req_idx = req_address[11:6]; // @[dcache.scala:167:16, :168:28]
assign io_meta_read_bits_idx_0 = req_idx; // @[dcache.scala:145:7, :168:28]
assign io_meta_write_bits_idx_0 = req_idx; // @[dcache.scala:145:7, :168:28]
assign io_wb_req_bits_idx_0 = req_idx; // @[dcache.scala:145:7, :168:28]
assign req_tag = req_address[31:12]; // @[dcache.scala:167:16, :169:29]
assign io_meta_read_bits_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29]
assign io_meta_write_bits_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29]
assign io_meta_write_bits_data_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29]
assign io_wb_req_bits_tag_0 = req_tag; // @[dcache.scala:145:7, :169:29]
reg [7:0] way_en; // @[dcache.scala:171:19]
assign io_meta_write_bits_way_en_0 = way_en; // @[dcache.scala:145:7, :171:19]
assign io_wb_req_bits_way_en_0 = way_en; // @[dcache.scala:145:7, :171:19]
wire tag_matches = |way_en; // @[dcache.scala:171:19, :172:28]
reg [1:0] old_coh_state; // @[dcache.scala:173:20]
wire [1:0] reply_coh_state = tag_matches ? old_coh_state : 2'h0; // @[dcache.scala:172:28, :173:20, :175:22]
wire [3:0] _r_T = {req_param, reply_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_13 = _r_T == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_15 = _r_T_13 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_17 = _r_T == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_19 = _r_T_17 ? 3'h2 : _r_T_15; // @[Misc.scala:38:36, :56:20]
wire _r_T_21 = _r_T == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_23 = _r_T_21 ? 3'h1 : _r_T_19; // @[Misc.scala:38:36, :56:20]
wire _r_T_25 = _r_T == 4'hB; // @[Misc.scala:56:20]
wire _r_T_26 = _r_T_25; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_27 = _r_T_25 ? 3'h1 : _r_T_23; // @[Misc.scala:38:36, :56:20]
wire _r_T_29 = _r_T == 4'h4; // @[Misc.scala:56:20]
wire _r_T_30 = ~_r_T_29 & _r_T_26; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_31 = _r_T_29 ? 3'h5 : _r_T_27; // @[Misc.scala:38:36, :56:20]
wire _r_T_33 = _r_T == 4'h5; // @[Misc.scala:56:20]
wire _r_T_34 = ~_r_T_33 & _r_T_30; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_35 = _r_T_33 ? 3'h4 : _r_T_31; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_36 = {1'h0, _r_T_33}; // @[Misc.scala:38:63, :56:20]
wire _r_T_37 = _r_T == 4'h6; // @[Misc.scala:56:20]
wire _r_T_38 = ~_r_T_37 & _r_T_34; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_39 = _r_T_37 ? 3'h0 : _r_T_35; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_40 = _r_T_37 ? 2'h1 : _r_T_36; // @[Misc.scala:38:63, :56:20]
wire _r_T_41 = _r_T == 4'h7; // @[Misc.scala:56:20]
wire _r_T_42 = _r_T_41 | _r_T_38; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_43 = _r_T_41 ? 3'h0 : _r_T_39; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_44 = _r_T_41 ? 2'h1 : _r_T_40; // @[Misc.scala:38:63, :56:20]
wire _r_T_45 = _r_T == 4'h0; // @[Misc.scala:56:20]
wire _r_T_46 = ~_r_T_45 & _r_T_42; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_47 = _r_T_45 ? 3'h5 : _r_T_43; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_48 = _r_T_45 ? 2'h0 : _r_T_44; // @[Misc.scala:38:63, :56:20]
wire _r_T_49 = _r_T == 4'h1; // @[Misc.scala:56:20]
wire _r_T_50 = ~_r_T_49 & _r_T_46; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_51 = _r_T_49 ? 3'h4 : _r_T_47; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_52 = _r_T_49 ? 2'h1 : _r_T_48; // @[Misc.scala:38:63, :56:20]
wire _r_T_53 = _r_T == 4'h2; // @[Misc.scala:56:20]
wire _r_T_54 = ~_r_T_53 & _r_T_50; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_55 = _r_T_53 ? 3'h3 : _r_T_51; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_56 = _r_T_53 ? 2'h2 : _r_T_52; // @[Misc.scala:38:63, :56:20]
wire _r_T_57 = _r_T == 4'h3; // @[Misc.scala:56:20]
wire is_dirty = _r_T_57 | _r_T_54; // @[Misc.scala:38:9, :56:20]
assign report_param = _r_T_57 ? 3'h3 : _r_T_55; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = report_param; // @[Misc.scala:38:36]
assign io_rep_bits_c_param = report_param; // @[Misc.scala:38:36]
assign io_lsu_release_bits_c_param = report_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_57 ? 2'h2 : _r_T_56; // @[Misc.scala:38:63, :56:20]
assign new_coh_state = r_3; // @[Misc.scala:38:63]
assign io_meta_write_bits_data_coh_state_0 = new_coh_state; // @[Metadata.scala:160:20]
assign _io_state_valid_T = |state; // @[dcache.scala:165:22, :178:27]
assign io_state_valid_0 = _io_state_valid_T; // @[dcache.scala:145:7, :178:27]
assign io_state_bits_0 = {8'h0, req_address}; // @[dcache.scala:145:7, :167:16, :172:28, :179:18]
assign _io_req_ready_T = ~(|state); // @[dcache.scala:165:22, :178:27, :181:25]
assign io_req_ready_0 = _io_req_ready_T; // @[dcache.scala:145:7, :181:25]
wire _T_15 = state == 4'h6; // @[dcache.scala:165:22, :182:25]
assign _io_rep_valid_T = _T_15; // @[dcache.scala:182:25]
wire _io_mshr_wb_rdy_T; // @[package.scala:16:47]
assign _io_mshr_wb_rdy_T = _T_15; // @[package.scala:16:47]
assign io_rep_valid_0 = _io_rep_valid_T; // @[dcache.scala:145:7, :182:25]
assign io_rep_bits_param_0 = io_rep_bits_c_param; // @[Edges.scala:416:17]
assign io_rep_bits_size_0 = io_rep_bits_c_size; // @[Edges.scala:416:17]
assign io_rep_bits_source_0 = io_rep_bits_c_source; // @[Edges.scala:416:17]
assign io_rep_bits_address_0 = io_rep_bits_c_address; // @[Edges.scala:416:17]
assign _io_meta_read_valid_T = state == 4'h1; // @[dcache.scala:165:22, :188:31]
assign io_meta_read_valid_0 = _io_meta_read_valid_T; // @[dcache.scala:145:7, :188:31]
wire _T_19 = state == 4'h9; // @[dcache.scala:165:22, :193:32]
assign _io_meta_write_valid_T = _T_19; // @[dcache.scala:193:32]
wire _io_mshr_wb_rdy_T_3; // @[package.scala:16:47]
assign _io_mshr_wb_rdy_T_3 = _T_19; // @[package.scala:16:47]
assign io_meta_write_valid_0 = _io_meta_write_valid_T; // @[dcache.scala:145:7, :193:32]
wire _T_16 = state == 4'h7; // @[dcache.scala:165:22, :200:28]
assign _io_wb_req_valid_T = _T_16; // @[dcache.scala:200:28]
wire _io_mshr_wb_rdy_T_1; // @[package.scala:16:47]
assign _io_mshr_wb_rdy_T_1 = _T_16; // @[package.scala:16:47]
assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[dcache.scala:145:7, :200:28]
wire _io_mshr_wb_rdy_T_2 = state == 4'h8; // @[package.scala:16:47]
wire _io_mshr_wb_rdy_T_4 = state == 4'hA; // @[package.scala:16:47]
wire _io_mshr_wb_rdy_T_5 = _io_mshr_wb_rdy_T | _io_mshr_wb_rdy_T_1; // @[package.scala:16:47, :81:59]
wire _io_mshr_wb_rdy_T_6 = _io_mshr_wb_rdy_T_5 | _io_mshr_wb_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_mshr_wb_rdy_T_7 = _io_mshr_wb_rdy_T_6 | _io_mshr_wb_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_mshr_wb_rdy_T_8 = _io_mshr_wb_rdy_T_7 | _io_mshr_wb_rdy_T_4; // @[package.scala:16:47, :81:59]
assign _io_mshr_wb_rdy_T_9 = ~_io_mshr_wb_rdy_T_8; // @[package.scala:81:59]
assign io_mshr_wb_rdy_0 = _io_mshr_wb_rdy_T_9; // @[dcache.scala:145:7, :209:21]
assign _io_lsu_release_valid_T = state == 4'h5; // @[dcache.scala:165:22, :211:33]
assign io_lsu_release_valid_0 = _io_lsu_release_valid_T; // @[dcache.scala:145:7, :211:33]
assign io_lsu_release_bits_param_0 = io_lsu_release_bits_c_param; // @[Edges.scala:416:17]
assign io_lsu_release_bits_size_0 = io_lsu_release_bits_c_size; // @[Edges.scala:416:17]
assign io_lsu_release_bits_source_0 = io_lsu_release_bits_c_source; // @[Edges.scala:416:17]
assign io_lsu_release_bits_address_0 = io_lsu_release_bits_c_address; // @[Edges.scala:416:17]
wire _state_T = io_mshr_rdy_0 & io_wb_rdy_0; // @[dcache.scala:145:7, :231:30]
wire [3:0] _state_T_1 = _state_T ? 4'h4 : 4'h1; // @[dcache.scala:231:{17,30}]
wire _state_T_2 = tag_matches & is_dirty; // @[Misc.scala:38:9]
wire [3:0] _state_T_3 = {2'h1, _state_T_2, 1'h1}; // @[dcache.scala:233:{17,30}]
wire [3:0] _state_T_4 = tag_matches ? 4'h9 : 4'h0; // @[dcache.scala:172:28, :240:19]
wire [15:0][3:0] _GEN = {{state}, {state}, {state}, {state}, {state}, {4'h0}, {io_meta_write_ready_0 & io_meta_write_valid_0 ? 4'hA : state}, {io_wb_req_ready_0 ? 4'h9 : state}, {io_wb_req_ready_0 & io_wb_req_valid_0 ? 4'h8 : state}, {io_rep_ready_0 ? _state_T_4 : state}, {io_lsu_release_ready_0 & io_lsu_release_valid_0 ? 4'h6 : state}, {_state_T_3}, {_state_T_1}, {4'h3}, {io_meta_read_ready_0 & io_meta_read_valid_0 ? 4'h2 : state}, {state}}; // @[Decoupled.scala:51:35]
wire _T_7 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[dcache.scala:145:7]
if (reset) // @[dcache.scala:145:7]
state <= 4'h0; // @[dcache.scala:165:22]
else if (|state) // @[dcache.scala:165:22, :178:27]
state <= _GEN[state]; // @[package.scala:16:47]
else if (_T_7) // @[Decoupled.scala:51:35]
state <= 4'h1; // @[dcache.scala:165:22]
if (~(|state) & _T_7) begin // @[Decoupled.scala:51:35]
req_opcode <= io_req_bits_opcode_0; // @[dcache.scala:145:7, :167:16]
req_param <= io_req_bits_param_0; // @[dcache.scala:145:7, :167:16]
req_size <= io_req_bits_size_0; // @[dcache.scala:145:7, :167:16]
req_source <= io_req_bits_source_0; // @[dcache.scala:145:7, :167:16]
req_address <= io_req_bits_address_0; // @[dcache.scala:145:7, :167:16]
req_mask <= io_req_bits_mask_0; // @[dcache.scala:145:7, :167:16]
req_data <= io_req_bits_data_0; // @[dcache.scala:145:7, :167:16]
req_corrupt <= io_req_bits_corrupt_0; // @[dcache.scala:145:7, :167:16]
end
if (~(|state) | _io_meta_read_valid_T | state == 4'h2 | state != 4'h3) begin // @[dcache.scala:165:22, :173:20, :178:27, :181:25, :188:31, :215:30, :220:39, :224:{22,39}, :227:{22,38}]
end
else begin // @[dcache.scala:173:20, :215:30, :220:39, :224:39, :227:38]
way_en <= io_way_en_0; // @[dcache.scala:145:7, :171:19]
old_coh_state <= io_block_state_state_0; // @[dcache.scala:145:7, :173:20]
end
always @(posedge)
assign io_req_ready = io_req_ready_0; // @[dcache.scala:145:7]
assign io_rep_valid = io_rep_valid_0; // @[dcache.scala:145:7]
assign io_rep_bits_param = io_rep_bits_param_0; // @[dcache.scala:145:7]
assign io_rep_bits_size = io_rep_bits_size_0; // @[dcache.scala:145:7]
assign io_rep_bits_source = io_rep_bits_source_0; // @[dcache.scala:145:7]
assign io_rep_bits_address = io_rep_bits_address_0; // @[dcache.scala:145:7]
assign io_meta_read_valid = io_meta_read_valid_0; // @[dcache.scala:145:7]
assign io_meta_read_bits_idx = io_meta_read_bits_idx_0; // @[dcache.scala:145:7]
assign io_meta_read_bits_tag = io_meta_read_bits_tag_0; // @[dcache.scala:145:7]
assign io_meta_write_valid = io_meta_write_valid_0; // @[dcache.scala:145:7]
assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[dcache.scala:145:7]
assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[dcache.scala:145:7]
assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[dcache.scala:145:7]
assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[dcache.scala:145:7]
assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[dcache.scala:145:7]
assign io_wb_req_valid = io_wb_req_valid_0; // @[dcache.scala:145:7]
assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[dcache.scala:145:7]
assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[dcache.scala:145:7]
assign io_wb_req_bits_source = io_wb_req_bits_source_0; // @[dcache.scala:145:7]
assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[dcache.scala:145:7]
assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[dcache.scala:145:7]
assign io_mshr_wb_rdy = io_mshr_wb_rdy_0; // @[dcache.scala:145:7]
assign io_lsu_release_valid = io_lsu_release_valid_0; // @[dcache.scala:145:7]
assign io_lsu_release_bits_param = io_lsu_release_bits_param_0; // @[dcache.scala:145:7]
assign io_lsu_release_bits_size = io_lsu_release_bits_size_0; // @[dcache.scala:145:7]
assign io_lsu_release_bits_source = io_lsu_release_bits_source_0; // @[dcache.scala:145:7]
assign io_lsu_release_bits_address = io_lsu_release_bits_address_0; // @[dcache.scala:145:7]
assign io_state_valid = io_state_valid_0; // @[dcache.scala:145:7]
assign io_state_bits = io_state_bits_0; // @[dcache.scala:145:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_22 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_210
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_212
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_22( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_210 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_211 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_212 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_21 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<1>, egress_node : UInt<4>, egress_node_id : UInt<1>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<4>, vc_free : UInt<4>}}
wire _in_flight_WIRE : UInt<1>[4]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
regreset in_flight : UInt<1>[4], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_89 = and(_T_87, _T_88)
node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_105 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_112 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_119 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_126 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_133 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_134 = and(_T_132, _T_133)
node _T_135 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_140 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_141 = and(_T_139, _T_140)
node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_147 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_154 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_161 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_164 = and(_T_162, _T_163)
node _T_165 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_168 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_173 = and(_T_171, _T_172)
node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_175 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_178 = and(_T_176, _T_177)
node _T_179 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_180 = and(_T_178, _T_179)
node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_182 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_185 = and(_T_183, _T_184)
node _T_186 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_187 = and(_T_185, _T_186)
node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_189 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_192 = and(_T_190, _T_191)
node _T_193 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_194 = and(_T_192, _T_193)
node _T_195 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_196 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_199 = and(_T_197, _T_198)
node _T_200 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_201 = and(_T_199, _T_200)
node _T_202 = or(_T_12, _T_19)
node _T_203 = or(_T_202, _T_26)
node _T_204 = or(_T_203, _T_33)
node _T_205 = or(_T_204, _T_40)
node _T_206 = or(_T_205, _T_47)
node _T_207 = or(_T_206, _T_54)
node _T_208 = or(_T_207, _T_61)
node _T_209 = or(_T_208, _T_68)
node _T_210 = or(_T_209, _T_75)
node _T_211 = or(_T_210, _T_82)
node _T_212 = or(_T_211, _T_89)
node _T_213 = or(_T_212, _T_96)
node _T_214 = or(_T_213, _T_103)
node _T_215 = or(_T_214, _T_110)
node _T_216 = or(_T_215, _T_117)
node _T_217 = or(_T_216, _T_124)
node _T_218 = or(_T_217, _T_131)
node _T_219 = or(_T_218, _T_138)
node _T_220 = or(_T_219, _T_145)
node _T_221 = or(_T_220, _T_152)
node _T_222 = or(_T_221, _T_159)
node _T_223 = or(_T_222, _T_166)
node _T_224 = or(_T_223, _T_173)
node _T_225 = or(_T_224, _T_180)
node _T_226 = or(_T_225, _T_187)
node _T_227 = or(_T_226, _T_194)
node _T_228 = or(_T_227, _T_201)
node _T_229 = or(_T_5, _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_229, UInt<1>(0h1), "") : assert_1
node _T_233 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_235 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_236 = and(_T_234, _T_235)
node _T_237 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_242 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_243 = and(_T_241, _T_242)
node _T_244 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_249 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_254 = and(_T_252, _T_253)
node _T_255 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_261 = and(_T_259, _T_260)
node _T_262 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_268 = and(_T_266, _T_267)
node _T_269 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_284 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_287 = and(_T_285, _T_286)
node _T_288 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_289 = and(_T_287, _T_288)
node _T_290 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_291 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_294 = and(_T_292, _T_293)
node _T_295 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_296 = and(_T_294, _T_295)
node _T_297 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_298 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_301 = and(_T_299, _T_300)
node _T_302 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_303 = and(_T_301, _T_302)
node _T_304 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_305 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_310 = and(_T_308, _T_309)
node _T_311 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_312 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_313 = and(_T_311, _T_312)
node _T_314 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_315 = and(_T_313, _T_314)
node _T_316 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_317 = and(_T_315, _T_316)
node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_319 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_322 = and(_T_320, _T_321)
node _T_323 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_326 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_329 = and(_T_327, _T_328)
node _T_330 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_333 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_340 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_341 = and(_T_339, _T_340)
node _T_342 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_347 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_354 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_355 = and(_T_353, _T_354)
node _T_356 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_361 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_368 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_369 = and(_T_367, _T_368)
node _T_370 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_375 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_376 = and(_T_374, _T_375)
node _T_377 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_382 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_389 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_390 = and(_T_388, _T_389)
node _T_391 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_396 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_397 = and(_T_395, _T_396)
node _T_398 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_399 = and(_T_397, _T_398)
node _T_400 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_401 = and(_T_399, _T_400)
node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_403 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_404 = and(_T_402, _T_403)
node _T_405 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_406 = and(_T_404, _T_405)
node _T_407 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_408 = and(_T_406, _T_407)
node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_410 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_411 = and(_T_409, _T_410)
node _T_412 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_413 = and(_T_411, _T_412)
node _T_414 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_415 = and(_T_413, _T_414)
node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_417 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_418 = and(_T_416, _T_417)
node _T_419 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_420 = and(_T_418, _T_419)
node _T_421 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_424 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_425 = and(_T_423, _T_424)
node _T_426 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_427 = and(_T_425, _T_426)
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_432 = and(_T_430, _T_431)
node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_446 = and(_T_444, _T_445)
node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_448 = and(_T_446, _T_447)
node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_452 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_453 = and(_T_451, _T_452)
node _T_454 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_455 = and(_T_453, _T_454)
node _T_456 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_457 = and(_T_455, _T_456)
node _T_458 = or(_T_240, _T_247)
node _T_459 = or(_T_458, _T_254)
node _T_460 = or(_T_459, _T_261)
node _T_461 = or(_T_460, _T_268)
node _T_462 = or(_T_461, _T_275)
node _T_463 = or(_T_462, _T_282)
node _T_464 = or(_T_463, _T_289)
node _T_465 = or(_T_464, _T_296)
node _T_466 = or(_T_465, _T_303)
node _T_467 = or(_T_466, _T_310)
node _T_468 = or(_T_467, _T_317)
node _T_469 = or(_T_468, _T_324)
node _T_470 = or(_T_469, _T_331)
node _T_471 = or(_T_470, _T_338)
node _T_472 = or(_T_471, _T_345)
node _T_473 = or(_T_472, _T_352)
node _T_474 = or(_T_473, _T_359)
node _T_475 = or(_T_474, _T_366)
node _T_476 = or(_T_475, _T_373)
node _T_477 = or(_T_476, _T_380)
node _T_478 = or(_T_477, _T_387)
node _T_479 = or(_T_478, _T_394)
node _T_480 = or(_T_479, _T_401)
node _T_481 = or(_T_480, _T_408)
node _T_482 = or(_T_481, _T_415)
node _T_483 = or(_T_482, _T_422)
node _T_484 = or(_T_483, _T_429)
node _T_485 = or(_T_484, _T_436)
node _T_486 = or(_T_485, _T_443)
node _T_487 = or(_T_486, _T_450)
node _T_488 = or(_T_487, _T_457)
node _T_489 = or(_T_233, _T_488)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_489, UInt<1>(0h1), "") : assert_2
node _T_493 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_494 = or(_T_493, UInt<1>(0h0))
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_494, UInt<1>(0h1), "") : assert_3
node _T_498 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_499 = or(_T_498, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_499, UInt<1>(0h1), "") : assert_4 | module NoCMonitor_21( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h2; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_241 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_241( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_14 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = or(_T_667, _T_672)
node _T_699 = or(_T_698, _T_677)
node _T_700 = or(_T_699, _T_682)
node _T_701 = or(_T_700, _T_687)
node _T_702 = or(_T_701, _T_692)
node _T_703 = or(_T_702, _T_697)
node _T_704 = and(_T_662, _T_703)
node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = and(_T_705, _T_710)
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_714 = and(_T_712, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = or(_T_720, _T_725)
node _T_727 = and(_T_715, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_704)
node _T_729 = or(_T_728, _T_711)
node _T_730 = or(_T_729, _T_727)
node _T_731 = and(_T_658, _T_730)
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_731, UInt<1>(0h1), "") : assert_36
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(is_aligned, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_741, UInt<1>(0h1), "") : assert_39
node _T_745 = eq(io.in.a.bits.mask, mask)
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_745, UInt<1>(0h1), "") : assert_40
node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_749 :
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_754 = and(_T_752, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_758 = and(_T_756, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = or(_T_764, _T_769)
node _T_796 = or(_T_795, _T_774)
node _T_797 = or(_T_796, _T_779)
node _T_798 = or(_T_797, _T_784)
node _T_799 = or(_T_798, _T_789)
node _T_800 = or(_T_799, _T_794)
node _T_801 = and(_T_759, _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_811 = and(_T_809, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = or(_T_817, _T_822)
node _T_824 = and(_T_812, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_801)
node _T_826 = or(_T_825, _T_808)
node _T_827 = or(_T_826, _T_824)
node _T_828 = and(_T_755, _T_827)
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_828, UInt<1>(0h1), "") : assert_41
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(is_aligned, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_838, UInt<1>(0h1), "") : assert_44
node _T_842 = eq(io.in.a.bits.mask, mask)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_842, UInt<1>(0h1), "") : assert_45
node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_846 :
node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_851 = and(_T_849, _T_850)
node _T_852 = or(UInt<1>(0h0), _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = and(_T_856, _T_861)
node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = or(_T_868, _T_873)
node _T_900 = or(_T_899, _T_878)
node _T_901 = or(_T_900, _T_883)
node _T_902 = or(_T_901, _T_888)
node _T_903 = or(_T_902, _T_893)
node _T_904 = or(_T_903, _T_898)
node _T_905 = and(_T_863, _T_904)
node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_908 = and(_T_906, _T_907)
node _T_909 = or(UInt<1>(0h0), _T_908)
node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_911 = cvt(_T_910)
node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000)))
node _T_913 = asSInt(_T_912)
node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0)))
node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = or(_T_914, _T_919)
node _T_921 = and(_T_909, _T_920)
node _T_922 = or(UInt<1>(0h0), _T_862)
node _T_923 = or(_T_922, _T_905)
node _T_924 = or(_T_923, _T_921)
node _T_925 = and(_T_852, _T_924)
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_925, UInt<1>(0h1), "") : assert_46
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(is_aligned, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_935, UInt<1>(0h1), "") : assert_49
node _T_939 = eq(io.in.a.bits.mask, mask)
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_939, UInt<1>(0h1), "") : assert_50
node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_943, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_947, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_951 :
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_955, UInt<1>(0h1), "") : assert_54
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_959, UInt<1>(0h1), "") : assert_55
node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_963, UInt<1>(0h1), "") : assert_56
node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_967, UInt<1>(0h1), "") : assert_57
node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_971 :
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(sink_ok, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_978, UInt<1>(0h1), "") : assert_60
node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_982, UInt<1>(0h1), "") : assert_61
node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_986, UInt<1>(0h1), "") : assert_62
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_990, UInt<1>(0h1), "") : assert_63
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = or(UInt<1>(0h1), _T_994)
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_995, UInt<1>(0h1), "") : assert_64
node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_999 :
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(sink_ok, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67
node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68
node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = or(_T_1018, io.in.d.bits.corrupt)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70
node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1024 = or(UInt<1>(0h1), _T_1023)
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71
node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73
node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74
node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1041 = or(UInt<1>(0h1), _T_1040)
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75
node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1045 :
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79
node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1092 = eq(a_first, UInt<1>(0h0))
node _T_1093 = and(io.in.a.valid, _T_1092)
when _T_1093 :
node _T_1094 = eq(io.in.a.bits.opcode, opcode)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87
node _T_1098 = eq(io.in.a.bits.param, param)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88
node _T_1102 = eq(io.in.a.bits.size, size)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89
node _T_1106 = eq(io.in.a.bits.source, source)
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90
node _T_1110 = eq(io.in.a.bits.address, address)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91
node _T_1114 = and(io.in.a.ready, io.in.a.valid)
node _T_1115 = and(_T_1114, a_first)
when _T_1115 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1116 = eq(d_first, UInt<1>(0h0))
node _T_1117 = and(io.in.d.valid, _T_1116)
when _T_1117 :
node _T_1118 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92
node _T_1122 = eq(io.in.d.bits.param, param_1)
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93
node _T_1126 = eq(io.in.d.bits.size, size_1)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94
node _T_1130 = eq(io.in.d.bits.source, source_1)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95
node _T_1134 = eq(io.in.d.bits.sink, sink)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96
node _T_1138 = eq(io.in.d.bits.denied, denied)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97
node _T_1142 = and(io.in.d.ready, io.in.d.valid)
node _T_1143 = and(_T_1142, d_first)
when _T_1143 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1144 = and(io.in.a.valid, a_first_1)
node _T_1145 = and(_T_1144, UInt<1>(0h1))
when _T_1145 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1146 = and(io.in.a.ready, io.in.a.valid)
node _T_1147 = and(_T_1146, a_first_1)
node _T_1148 = and(_T_1147, UInt<1>(0h1))
when _T_1148 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1149 = dshr(inflight, io.in.a.bits.source)
node _T_1150 = bits(_T_1149, 0, 0)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1155 = and(io.in.d.valid, d_first_1)
node _T_1156 = and(_T_1155, UInt<1>(0h1))
node _T_1157 = eq(d_release_ack, UInt<1>(0h0))
node _T_1158 = and(_T_1156, _T_1157)
when _T_1158 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1159 = and(io.in.d.ready, io.in.d.valid)
node _T_1160 = and(_T_1159, d_first_1)
node _T_1161 = and(_T_1160, UInt<1>(0h1))
node _T_1162 = eq(d_release_ack, UInt<1>(0h0))
node _T_1163 = and(_T_1161, _T_1162)
when _T_1163 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1164 = and(io.in.d.valid, d_first_1)
node _T_1165 = and(_T_1164, UInt<1>(0h1))
node _T_1166 = eq(d_release_ack, UInt<1>(0h0))
node _T_1167 = and(_T_1165, _T_1166)
when _T_1167 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1168 = dshr(inflight, io.in.d.bits.source)
node _T_1169 = bits(_T_1168, 0, 0)
node _T_1170 = or(_T_1169, same_cycle_resp)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100
node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101
else :
node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1186 = or(_T_1184, _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102
node _T_1190 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103
node _T_1194 = and(io.in.d.valid, d_first_1)
node _T_1195 = and(_T_1194, a_first_1)
node _T_1196 = and(_T_1195, io.in.a.valid)
node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1198 = and(_T_1196, _T_1197)
node _T_1199 = eq(d_release_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1202 = or(_T_1201, io.in.a.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104
node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1207 = orr(a_set_wo_ready)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
node _T_1209 = or(_T_1206, _T_1208)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_28
node _T_1213 = orr(inflight)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1216 = or(_T_1214, _T_1215)
node _T_1217 = lt(watchdog, plusarg_reader.out)
node _T_1218 = or(_T_1216, _T_1217)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1222 = and(io.in.a.ready, io.in.a.valid)
node _T_1223 = and(io.in.d.ready, io.in.d.valid)
node _T_1224 = or(_T_1222, _T_1223)
when _T_1224 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1225 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = and(_T_1225, _T_1228)
when _T_1229 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1231 = and(_T_1230, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1234 = and(_T_1232, _T_1233)
node _T_1235 = and(_T_1231, _T_1234)
when _T_1235 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1237 = bits(_T_1236, 0, 0)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1242 = and(io.in.d.valid, d_first_2)
node _T_1243 = and(_T_1242, UInt<1>(0h1))
node _T_1244 = and(_T_1243, d_release_ack_1)
when _T_1244 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1245 = and(io.in.d.ready, io.in.d.valid)
node _T_1246 = and(_T_1245, d_first_2)
node _T_1247 = and(_T_1246, UInt<1>(0h1))
node _T_1248 = and(_T_1247, d_release_ack_1)
when _T_1248 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1249 = and(io.in.d.valid, d_first_2)
node _T_1250 = and(_T_1249, UInt<1>(0h1))
node _T_1251 = and(_T_1250, d_release_ack_1)
when _T_1251 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1252 = dshr(inflight_1, io.in.d.bits.source)
node _T_1253 = bits(_T_1252, 0, 0)
node _T_1254 = or(_T_1253, same_cycle_resp_1)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109
else :
node _T_1262 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110
node _T_1266 = and(io.in.d.valid, d_first_2)
node _T_1267 = and(_T_1266, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1268 = and(_T_1267, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1270 = and(_T_1268, _T_1269)
node _T_1271 = and(_T_1270, d_release_ack_1)
node _T_1272 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1275 = or(_T_1274, _WIRE_23.ready)
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(_T_1275, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111
node _T_1279 = orr(c_set_wo_ready)
when _T_1279 :
node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_29
node _T_1284 = orr(inflight_1)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1287 = or(_T_1285, _T_1286)
node _T_1288 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1294 = and(io.in.d.ready, io.in.d.valid)
node _T_1295 = or(_T_1293, _T_1294)
when _T_1295 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_30 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_31 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_14( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1295 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1295; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1295; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1295; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_1295 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_1295 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module FDivSqrtUnit_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<65>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip fcsr_rm : UInt<3>}
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.sfence.bits.hg
invalidate io.resp.bits.sfence.bits.hv
invalidate io.resp.bits.sfence.bits.asid
invalidate io.resp.bits.sfence.bits.addr
invalidate io.resp.bits.sfence.bits.rs2
invalidate io.resp.bits.sfence.bits.rs1
invalidate io.resp.bits.sfence.valid
invalidate io.resp.bits.mxcpt.bits
invalidate io.resp.bits.mxcpt.valid
invalidate io.resp.bits.addr
invalidate io.resp.bits.fflags.bits.flags
invalidate io.resp.bits.fflags.bits.uop.debug_tsrc
invalidate io.resp.bits.fflags.bits.uop.debug_fsrc
invalidate io.resp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.resp.bits.fflags.bits.uop.bp_debug_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.resp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.resp.bits.fflags.bits.uop.fp_single
invalidate io.resp.bits.fflags.bits.uop.fp_val
invalidate io.resp.bits.fflags.bits.uop.frs3_en
invalidate io.resp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.resp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.resp.bits.fflags.bits.uop.dst_rtype
invalidate io.resp.bits.fflags.bits.uop.ldst_val
invalidate io.resp.bits.fflags.bits.uop.lrs3
invalidate io.resp.bits.fflags.bits.uop.lrs2
invalidate io.resp.bits.fflags.bits.uop.lrs1
invalidate io.resp.bits.fflags.bits.uop.ldst
invalidate io.resp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.resp.bits.fflags.bits.uop.flush_on_commit
invalidate io.resp.bits.fflags.bits.uop.is_unique
invalidate io.resp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.fflags.bits.uop.uses_stq
invalidate io.resp.bits.fflags.bits.uop.uses_ldq
invalidate io.resp.bits.fflags.bits.uop.is_amo
invalidate io.resp.bits.fflags.bits.uop.is_fencei
invalidate io.resp.bits.fflags.bits.uop.is_fence
invalidate io.resp.bits.fflags.bits.uop.mem_signed
invalidate io.resp.bits.fflags.bits.uop.mem_size
invalidate io.resp.bits.fflags.bits.uop.mem_cmd
invalidate io.resp.bits.fflags.bits.uop.bypassable
invalidate io.resp.bits.fflags.bits.uop.exc_cause
invalidate io.resp.bits.fflags.bits.uop.exception
invalidate io.resp.bits.fflags.bits.uop.stale_pdst
invalidate io.resp.bits.fflags.bits.uop.ppred_busy
invalidate io.resp.bits.fflags.bits.uop.prs3_busy
invalidate io.resp.bits.fflags.bits.uop.prs2_busy
invalidate io.resp.bits.fflags.bits.uop.prs1_busy
invalidate io.resp.bits.fflags.bits.uop.ppred
invalidate io.resp.bits.fflags.bits.uop.prs3
invalidate io.resp.bits.fflags.bits.uop.prs2
invalidate io.resp.bits.fflags.bits.uop.prs1
invalidate io.resp.bits.fflags.bits.uop.pdst
invalidate io.resp.bits.fflags.bits.uop.rxq_idx
invalidate io.resp.bits.fflags.bits.uop.stq_idx
invalidate io.resp.bits.fflags.bits.uop.ldq_idx
invalidate io.resp.bits.fflags.bits.uop.rob_idx
invalidate io.resp.bits.fflags.bits.uop.csr_addr
invalidate io.resp.bits.fflags.bits.uop.imm_packed
invalidate io.resp.bits.fflags.bits.uop.taken
invalidate io.resp.bits.fflags.bits.uop.pc_lob
invalidate io.resp.bits.fflags.bits.uop.edge_inst
invalidate io.resp.bits.fflags.bits.uop.ftq_idx
invalidate io.resp.bits.fflags.bits.uop.br_tag
invalidate io.resp.bits.fflags.bits.uop.br_mask
invalidate io.resp.bits.fflags.bits.uop.is_sfb
invalidate io.resp.bits.fflags.bits.uop.is_jal
invalidate io.resp.bits.fflags.bits.uop.is_jalr
invalidate io.resp.bits.fflags.bits.uop.is_br
invalidate io.resp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.fflags.bits.uop.iw_state
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.resp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.resp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.resp.bits.fflags.bits.uop.fu_code
invalidate io.resp.bits.fflags.bits.uop.iq_type
invalidate io.resp.bits.fflags.bits.uop.debug_pc
invalidate io.resp.bits.fflags.bits.uop.is_rvc
invalidate io.resp.bits.fflags.bits.uop.debug_inst
invalidate io.resp.bits.fflags.bits.uop.inst
invalidate io.resp.bits.fflags.bits.uop.uopc
invalidate io.resp.bits.fflags.valid
invalidate io.resp.bits.data
invalidate io.resp.bits.predicated
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
regreset r_buffer_val : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_buffer_req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}, clock
reg r_buffer_fin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
inst fdiv_decoder of UOPCodeFDivDecoder_1
connect fdiv_decoder.clock, clock
connect fdiv_decoder.reset, reset
connect fdiv_decoder.io.uopc, io.req.bits.uop.uopc
node _r_buffer_val_T = and(io.brupdate.b1.mispredict_mask, r_buffer_req.uop.br_mask)
node _r_buffer_val_T_1 = neq(_r_buffer_val_T, UInt<1>(0h0))
node _r_buffer_val_T_2 = eq(_r_buffer_val_T_1, UInt<1>(0h0))
node _r_buffer_val_T_3 = eq(io.req.bits.kill, UInt<1>(0h0))
node _r_buffer_val_T_4 = and(_r_buffer_val_T_2, _r_buffer_val_T_3)
node _r_buffer_val_T_5 = and(_r_buffer_val_T_4, r_buffer_val)
connect r_buffer_val, _r_buffer_val_T_5
node _r_buffer_req_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_buffer_req_uop_br_mask_T_1 = and(r_buffer_req.uop.br_mask, _r_buffer_req_uop_br_mask_T)
connect r_buffer_req.uop.br_mask, _r_buffer_req_uop_br_mask_T_1
node _io_req_ready_T = eq(r_buffer_val, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T
node _in1_upconvert_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31)
node _in1_upconvert_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52)
node _in1_upconvert_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0)
node in1_upconvert_prev_unswizzled_hi = cat(_in1_upconvert_prev_unswizzled_T, _in1_upconvert_prev_unswizzled_T_1)
node in1_upconvert_floats_0 = cat(in1_upconvert_prev_unswizzled_hi, _in1_upconvert_prev_unswizzled_T_2)
node _in1_upconvert_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60)
node in1_upconvert_prev_isbox = andr(_in1_upconvert_prev_isbox_T)
node in1_upconvert_oks_0 = and(in1_upconvert_prev_isbox, UInt<1>(0h1))
node in1_upconvert_sign = bits(io.req.bits.rs1_data, 64, 64)
node in1_upconvert_fractIn = bits(io.req.bits.rs1_data, 51, 0)
node in1_upconvert_expIn = bits(io.req.bits.rs1_data, 63, 52)
node _in1_upconvert_fractOut_T = shl(in1_upconvert_fractIn, 24)
node in1_upconvert_fractOut = shr(_in1_upconvert_fractOut_T, 53)
node in1_upconvert_expOut_expCode = bits(in1_upconvert_expIn, 11, 9)
node _in1_upconvert_expOut_commonCase_T = add(in1_upconvert_expIn, UInt<9>(0h100))
node _in1_upconvert_expOut_commonCase_T_1 = tail(_in1_upconvert_expOut_commonCase_T, 1)
node _in1_upconvert_expOut_commonCase_T_2 = sub(_in1_upconvert_expOut_commonCase_T_1, UInt<12>(0h800))
node in1_upconvert_expOut_commonCase = tail(_in1_upconvert_expOut_commonCase_T_2, 1)
node _in1_upconvert_expOut_T = eq(in1_upconvert_expOut_expCode, UInt<1>(0h0))
node _in1_upconvert_expOut_T_1 = geq(in1_upconvert_expOut_expCode, UInt<3>(0h6))
node _in1_upconvert_expOut_T_2 = or(_in1_upconvert_expOut_T, _in1_upconvert_expOut_T_1)
node _in1_upconvert_expOut_T_3 = bits(in1_upconvert_expOut_commonCase, 5, 0)
node _in1_upconvert_expOut_T_4 = cat(in1_upconvert_expOut_expCode, _in1_upconvert_expOut_T_3)
node _in1_upconvert_expOut_T_5 = bits(in1_upconvert_expOut_commonCase, 8, 0)
node in1_upconvert_expOut = mux(_in1_upconvert_expOut_T_2, _in1_upconvert_expOut_T_4, _in1_upconvert_expOut_T_5)
node in1_upconvert_hi = cat(in1_upconvert_sign, in1_upconvert_expOut)
node in1_upconvert_floats_1 = cat(in1_upconvert_hi, in1_upconvert_fractOut)
node _in1_upconvert_T = mux(in1_upconvert_oks_0, UInt<1>(0h0), UInt<33>(0he0400000))
node _in1_upconvert_T_1 = or(in1_upconvert_floats_0, _in1_upconvert_T)
inst in1_upconvert_s2d of RecFNToRecFN_9
connect in1_upconvert_s2d.io.in, _in1_upconvert_T_1
connect in1_upconvert_s2d.io.roundingMode, UInt<1>(0h0)
invalidate in1_upconvert_s2d.io.detectTininess
node _in2_upconvert_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31)
node _in2_upconvert_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52)
node _in2_upconvert_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0)
node in2_upconvert_prev_unswizzled_hi = cat(_in2_upconvert_prev_unswizzled_T, _in2_upconvert_prev_unswizzled_T_1)
node in2_upconvert_floats_0 = cat(in2_upconvert_prev_unswizzled_hi, _in2_upconvert_prev_unswizzled_T_2)
node _in2_upconvert_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60)
node in2_upconvert_prev_isbox = andr(_in2_upconvert_prev_isbox_T)
node in2_upconvert_oks_0 = and(in2_upconvert_prev_isbox, UInt<1>(0h1))
node in2_upconvert_sign = bits(io.req.bits.rs2_data, 64, 64)
node in2_upconvert_fractIn = bits(io.req.bits.rs2_data, 51, 0)
node in2_upconvert_expIn = bits(io.req.bits.rs2_data, 63, 52)
node _in2_upconvert_fractOut_T = shl(in2_upconvert_fractIn, 24)
node in2_upconvert_fractOut = shr(_in2_upconvert_fractOut_T, 53)
node in2_upconvert_expOut_expCode = bits(in2_upconvert_expIn, 11, 9)
node _in2_upconvert_expOut_commonCase_T = add(in2_upconvert_expIn, UInt<9>(0h100))
node _in2_upconvert_expOut_commonCase_T_1 = tail(_in2_upconvert_expOut_commonCase_T, 1)
node _in2_upconvert_expOut_commonCase_T_2 = sub(_in2_upconvert_expOut_commonCase_T_1, UInt<12>(0h800))
node in2_upconvert_expOut_commonCase = tail(_in2_upconvert_expOut_commonCase_T_2, 1)
node _in2_upconvert_expOut_T = eq(in2_upconvert_expOut_expCode, UInt<1>(0h0))
node _in2_upconvert_expOut_T_1 = geq(in2_upconvert_expOut_expCode, UInt<3>(0h6))
node _in2_upconvert_expOut_T_2 = or(_in2_upconvert_expOut_T, _in2_upconvert_expOut_T_1)
node _in2_upconvert_expOut_T_3 = bits(in2_upconvert_expOut_commonCase, 5, 0)
node _in2_upconvert_expOut_T_4 = cat(in2_upconvert_expOut_expCode, _in2_upconvert_expOut_T_3)
node _in2_upconvert_expOut_T_5 = bits(in2_upconvert_expOut_commonCase, 8, 0)
node in2_upconvert_expOut = mux(_in2_upconvert_expOut_T_2, _in2_upconvert_expOut_T_4, _in2_upconvert_expOut_T_5)
node in2_upconvert_hi = cat(in2_upconvert_sign, in2_upconvert_expOut)
node in2_upconvert_floats_1 = cat(in2_upconvert_hi, in2_upconvert_fractOut)
node _in2_upconvert_T = mux(in2_upconvert_oks_0, UInt<1>(0h0), UInt<33>(0he0400000))
node _in2_upconvert_T_1 = or(in2_upconvert_floats_0, _in2_upconvert_T)
inst in2_upconvert_s2d of RecFNToRecFN_10
connect in2_upconvert_s2d.io.in, _in2_upconvert_T_1
connect in2_upconvert_s2d.io.roundingMode, UInt<1>(0h0)
invalidate in2_upconvert_s2d.io.detectTininess
node _T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask)
node _T_1 = neq(_T, UInt<1>(0h0))
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = and(io.req.valid, _T_2)
node _T_4 = eq(io.req.bits.kill, UInt<1>(0h0))
node _T_5 = and(_T_3, _T_4)
when _T_5 :
connect r_buffer_val, UInt<1>(0h1)
connect r_buffer_req, io.req.bits
node _r_buffer_req_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _r_buffer_req_uop_br_mask_T_3 = and(io.req.bits.uop.br_mask, _r_buffer_req_uop_br_mask_T_2)
connect r_buffer_req.uop.br_mask, _r_buffer_req_uop_br_mask_T_3
connect r_buffer_fin.vec, fdiv_decoder.io.sigs.vec
connect r_buffer_fin.wflags, fdiv_decoder.io.sigs.wflags
connect r_buffer_fin.sqrt, fdiv_decoder.io.sigs.sqrt
connect r_buffer_fin.div, fdiv_decoder.io.sigs.div
connect r_buffer_fin.fma, fdiv_decoder.io.sigs.fma
connect r_buffer_fin.fastpipe, fdiv_decoder.io.sigs.fastpipe
connect r_buffer_fin.toint, fdiv_decoder.io.sigs.toint
connect r_buffer_fin.fromint, fdiv_decoder.io.sigs.fromint
connect r_buffer_fin.typeTagOut, fdiv_decoder.io.sigs.typeTagOut
connect r_buffer_fin.typeTagIn, fdiv_decoder.io.sigs.typeTagIn
connect r_buffer_fin.swap23, fdiv_decoder.io.sigs.swap23
connect r_buffer_fin.swap12, fdiv_decoder.io.sigs.swap12
connect r_buffer_fin.ren3, fdiv_decoder.io.sigs.ren3
connect r_buffer_fin.ren2, fdiv_decoder.io.sigs.ren2
connect r_buffer_fin.ren1, fdiv_decoder.io.sigs.ren1
connect r_buffer_fin.wen, fdiv_decoder.io.sigs.wen
connect r_buffer_fin.ldst, fdiv_decoder.io.sigs.ldst
node _r_buffer_fin_rm_T = bits(io.req.bits.uop.imm_packed, 2, 0)
node _r_buffer_fin_rm_T_1 = eq(_r_buffer_fin_rm_T, UInt<3>(0h7))
node _r_buffer_fin_rm_T_2 = bits(io.req.bits.uop.imm_packed, 2, 0)
node _r_buffer_fin_rm_T_3 = mux(_r_buffer_fin_rm_T_1, io.fcsr_rm, _r_buffer_fin_rm_T_2)
connect r_buffer_fin.rm, _r_buffer_fin_rm_T_3
connect r_buffer_fin.typ, UInt<1>(0h0)
node _r_buffer_fin_in1_prev_unswizzled_T = bits(io.req.bits.rs1_data, 31, 31)
node _r_buffer_fin_in1_prev_unswizzled_T_1 = bits(io.req.bits.rs1_data, 52, 52)
node _r_buffer_fin_in1_prev_unswizzled_T_2 = bits(io.req.bits.rs1_data, 30, 0)
node r_buffer_fin_in1_prev_unswizzled_hi = cat(_r_buffer_fin_in1_prev_unswizzled_T, _r_buffer_fin_in1_prev_unswizzled_T_1)
node r_buffer_fin_in1_prev_unswizzled = cat(r_buffer_fin_in1_prev_unswizzled_hi, _r_buffer_fin_in1_prev_unswizzled_T_2)
node r_buffer_fin_in1_prev_prev_sign = bits(r_buffer_fin_in1_prev_unswizzled, 32, 32)
node r_buffer_fin_in1_prev_prev_fractIn = bits(r_buffer_fin_in1_prev_unswizzled, 22, 0)
node r_buffer_fin_in1_prev_prev_expIn = bits(r_buffer_fin_in1_prev_unswizzled, 31, 23)
node _r_buffer_fin_in1_prev_prev_fractOut_T = shl(r_buffer_fin_in1_prev_prev_fractIn, 53)
node r_buffer_fin_in1_prev_prev_fractOut = shr(_r_buffer_fin_in1_prev_prev_fractOut_T, 24)
node r_buffer_fin_in1_prev_prev_expOut_expCode = bits(r_buffer_fin_in1_prev_prev_expIn, 8, 6)
node _r_buffer_fin_in1_prev_prev_expOut_commonCase_T = add(r_buffer_fin_in1_prev_prev_expIn, UInt<12>(0h800))
node _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1 = tail(_r_buffer_fin_in1_prev_prev_expOut_commonCase_T, 1)
node _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2 = sub(_r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100))
node r_buffer_fin_in1_prev_prev_expOut_commonCase = tail(_r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2, 1)
node _r_buffer_fin_in1_prev_prev_expOut_T = eq(r_buffer_fin_in1_prev_prev_expOut_expCode, UInt<1>(0h0))
node _r_buffer_fin_in1_prev_prev_expOut_T_1 = geq(r_buffer_fin_in1_prev_prev_expOut_expCode, UInt<3>(0h6))
node _r_buffer_fin_in1_prev_prev_expOut_T_2 = or(_r_buffer_fin_in1_prev_prev_expOut_T, _r_buffer_fin_in1_prev_prev_expOut_T_1)
node _r_buffer_fin_in1_prev_prev_expOut_T_3 = bits(r_buffer_fin_in1_prev_prev_expOut_commonCase, 8, 0)
node _r_buffer_fin_in1_prev_prev_expOut_T_4 = cat(r_buffer_fin_in1_prev_prev_expOut_expCode, _r_buffer_fin_in1_prev_prev_expOut_T_3)
node _r_buffer_fin_in1_prev_prev_expOut_T_5 = bits(r_buffer_fin_in1_prev_prev_expOut_commonCase, 11, 0)
node r_buffer_fin_in1_prev_prev_expOut = mux(_r_buffer_fin_in1_prev_prev_expOut_T_2, _r_buffer_fin_in1_prev_prev_expOut_T_4, _r_buffer_fin_in1_prev_prev_expOut_T_5)
node r_buffer_fin_in1_prev_prev_hi = cat(r_buffer_fin_in1_prev_prev_sign, r_buffer_fin_in1_prev_prev_expOut)
node r_buffer_fin_in1_floats_0 = cat(r_buffer_fin_in1_prev_prev_hi, r_buffer_fin_in1_prev_prev_fractOut)
node _r_buffer_fin_in1_prev_isbox_T = bits(io.req.bits.rs1_data, 64, 60)
node r_buffer_fin_in1_prev_isbox = andr(_r_buffer_fin_in1_prev_isbox_T)
node r_buffer_fin_in1_oks_0 = and(r_buffer_fin_in1_prev_isbox, UInt<1>(0h1))
node _r_buffer_fin_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000))
node _r_buffer_fin_in1_T_1 = or(io.req.bits.rs1_data, _r_buffer_fin_in1_T)
connect r_buffer_fin.in1, _r_buffer_fin_in1_T_1
node _r_buffer_fin_in2_prev_unswizzled_T = bits(io.req.bits.rs2_data, 31, 31)
node _r_buffer_fin_in2_prev_unswizzled_T_1 = bits(io.req.bits.rs2_data, 52, 52)
node _r_buffer_fin_in2_prev_unswizzled_T_2 = bits(io.req.bits.rs2_data, 30, 0)
node r_buffer_fin_in2_prev_unswizzled_hi = cat(_r_buffer_fin_in2_prev_unswizzled_T, _r_buffer_fin_in2_prev_unswizzled_T_1)
node r_buffer_fin_in2_prev_unswizzled = cat(r_buffer_fin_in2_prev_unswizzled_hi, _r_buffer_fin_in2_prev_unswizzled_T_2)
node r_buffer_fin_in2_prev_prev_sign = bits(r_buffer_fin_in2_prev_unswizzled, 32, 32)
node r_buffer_fin_in2_prev_prev_fractIn = bits(r_buffer_fin_in2_prev_unswizzled, 22, 0)
node r_buffer_fin_in2_prev_prev_expIn = bits(r_buffer_fin_in2_prev_unswizzled, 31, 23)
node _r_buffer_fin_in2_prev_prev_fractOut_T = shl(r_buffer_fin_in2_prev_prev_fractIn, 53)
node r_buffer_fin_in2_prev_prev_fractOut = shr(_r_buffer_fin_in2_prev_prev_fractOut_T, 24)
node r_buffer_fin_in2_prev_prev_expOut_expCode = bits(r_buffer_fin_in2_prev_prev_expIn, 8, 6)
node _r_buffer_fin_in2_prev_prev_expOut_commonCase_T = add(r_buffer_fin_in2_prev_prev_expIn, UInt<12>(0h800))
node _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1 = tail(_r_buffer_fin_in2_prev_prev_expOut_commonCase_T, 1)
node _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2 = sub(_r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100))
node r_buffer_fin_in2_prev_prev_expOut_commonCase = tail(_r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2, 1)
node _r_buffer_fin_in2_prev_prev_expOut_T = eq(r_buffer_fin_in2_prev_prev_expOut_expCode, UInt<1>(0h0))
node _r_buffer_fin_in2_prev_prev_expOut_T_1 = geq(r_buffer_fin_in2_prev_prev_expOut_expCode, UInt<3>(0h6))
node _r_buffer_fin_in2_prev_prev_expOut_T_2 = or(_r_buffer_fin_in2_prev_prev_expOut_T, _r_buffer_fin_in2_prev_prev_expOut_T_1)
node _r_buffer_fin_in2_prev_prev_expOut_T_3 = bits(r_buffer_fin_in2_prev_prev_expOut_commonCase, 8, 0)
node _r_buffer_fin_in2_prev_prev_expOut_T_4 = cat(r_buffer_fin_in2_prev_prev_expOut_expCode, _r_buffer_fin_in2_prev_prev_expOut_T_3)
node _r_buffer_fin_in2_prev_prev_expOut_T_5 = bits(r_buffer_fin_in2_prev_prev_expOut_commonCase, 11, 0)
node r_buffer_fin_in2_prev_prev_expOut = mux(_r_buffer_fin_in2_prev_prev_expOut_T_2, _r_buffer_fin_in2_prev_prev_expOut_T_4, _r_buffer_fin_in2_prev_prev_expOut_T_5)
node r_buffer_fin_in2_prev_prev_hi = cat(r_buffer_fin_in2_prev_prev_sign, r_buffer_fin_in2_prev_prev_expOut)
node r_buffer_fin_in2_floats_0 = cat(r_buffer_fin_in2_prev_prev_hi, r_buffer_fin_in2_prev_prev_fractOut)
node _r_buffer_fin_in2_prev_isbox_T = bits(io.req.bits.rs2_data, 64, 60)
node r_buffer_fin_in2_prev_isbox = andr(_r_buffer_fin_in2_prev_isbox_T)
node r_buffer_fin_in2_oks_0 = and(r_buffer_fin_in2_prev_isbox, UInt<1>(0h1))
node _r_buffer_fin_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000))
node _r_buffer_fin_in2_T_1 = or(io.req.bits.rs2_data, _r_buffer_fin_in2_T)
connect r_buffer_fin.in2, _r_buffer_fin_in2_T_1
node _T_6 = eq(fdiv_decoder.io.sigs.typeTagIn, UInt<1>(0h0))
when _T_6 :
connect r_buffer_fin.in1, in1_upconvert_s2d.io.out
connect r_buffer_fin.in2, in2_upconvert_s2d.io.out
node _T_7 = and(r_buffer_val, io.req.valid)
node _T_8 = eq(_T_7, UInt<1>(0h0))
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed: [fdiv] a request is incoming while the buffer is already full.\n at fdiv.scala:138 assert (!(r_buffer_val && io.req.valid), \"[fdiv] a request is incoming while the buffer is already full.\")\n") : printf
assert(clock, _T_8, UInt<1>(0h1), "") : assert
inst divsqrt of DivSqrtRecF64_1
connect divsqrt.clock, clock
connect divsqrt.reset, reset
regreset r_divsqrt_val : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_divsqrt_killed : UInt<1>, clock
reg r_divsqrt_fin : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
reg r_divsqrt_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
wire output_buffer_available : UInt<1>
node _may_fire_input_T = or(r_buffer_fin.div, r_buffer_fin.sqrt)
node _may_fire_input_T_1 = and(r_buffer_val, _may_fire_input_T)
node _may_fire_input_T_2 = eq(r_divsqrt_val, UInt<1>(0h0))
node _may_fire_input_T_3 = and(_may_fire_input_T_1, _may_fire_input_T_2)
node may_fire_input = and(_may_fire_input_T_3, output_buffer_available)
node divsqrt_ready = mux(divsqrt.io.sqrtOp, divsqrt.io.inReady_sqrt, divsqrt.io.inReady_div)
connect divsqrt.io.inValid, may_fire_input
connect divsqrt.io.sqrtOp, r_buffer_fin.sqrt
connect divsqrt.io.a, r_buffer_fin.in1
node _divsqrt_io_b_T = mux(divsqrt.io.sqrtOp, r_buffer_fin.in1, r_buffer_fin.in2)
connect divsqrt.io.b, _divsqrt_io_b_T
connect divsqrt.io.roundingMode, r_buffer_fin.rm
invalidate divsqrt.io.detectTininess
node _r_divsqrt_killed_T = and(io.brupdate.b1.mispredict_mask, r_divsqrt_uop.br_mask)
node _r_divsqrt_killed_T_1 = neq(_r_divsqrt_killed_T, UInt<1>(0h0))
node _r_divsqrt_killed_T_2 = or(r_divsqrt_killed, _r_divsqrt_killed_T_1)
node _r_divsqrt_killed_T_3 = or(_r_divsqrt_killed_T_2, io.req.bits.kill)
connect r_divsqrt_killed, _r_divsqrt_killed_T_3
node _r_divsqrt_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_divsqrt_uop_br_mask_T_1 = and(r_divsqrt_uop.br_mask, _r_divsqrt_uop_br_mask_T)
connect r_divsqrt_uop.br_mask, _r_divsqrt_uop_br_mask_T_1
node _T_12 = and(may_fire_input, divsqrt_ready)
when _T_12 :
connect r_buffer_val, UInt<1>(0h0)
connect r_divsqrt_val, UInt<1>(0h1)
connect r_divsqrt_fin, r_buffer_fin
connect r_divsqrt_uop, r_buffer_req.uop
node _r_divsqrt_killed_T_4 = and(io.brupdate.b1.mispredict_mask, r_buffer_req.uop.br_mask)
node _r_divsqrt_killed_T_5 = neq(_r_divsqrt_killed_T_4, UInt<1>(0h0))
node _r_divsqrt_killed_T_6 = or(_r_divsqrt_killed_T_5, io.req.bits.kill)
connect r_divsqrt_killed, _r_divsqrt_killed_T_6
node _r_divsqrt_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _r_divsqrt_uop_br_mask_T_3 = and(r_buffer_req.uop.br_mask, _r_divsqrt_uop_br_mask_T_2)
connect r_divsqrt_uop.br_mask, _r_divsqrt_uop_br_mask_T_3
regreset r_out_val : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock
reg r_out_flags_double : UInt, clock
reg r_out_wdata_double : UInt, clock
node _output_buffer_available_T = eq(r_out_val, UInt<1>(0h0))
connect output_buffer_available, _output_buffer_available_T
node _r_out_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _r_out_uop_br_mask_T_1 = and(r_out_uop.br_mask, _r_out_uop_br_mask_T)
connect r_out_uop.br_mask, _r_out_uop_br_mask_T_1
node _T_13 = and(io.brupdate.b1.mispredict_mask, r_out_uop.br_mask)
node _T_14 = neq(_T_13, UInt<1>(0h0))
node _T_15 = or(io.resp.ready, _T_14)
node _T_16 = or(_T_15, io.req.bits.kill)
when _T_16 :
connect r_out_val, UInt<1>(0h0)
node _T_17 = or(divsqrt.io.outValid_div, divsqrt.io.outValid_sqrt)
when _T_17 :
connect r_divsqrt_val, UInt<1>(0h0)
node _r_out_val_T = eq(r_divsqrt_killed, UInt<1>(0h0))
node _r_out_val_T_1 = and(io.brupdate.b1.mispredict_mask, r_divsqrt_uop.br_mask)
node _r_out_val_T_2 = neq(_r_out_val_T_1, UInt<1>(0h0))
node _r_out_val_T_3 = eq(_r_out_val_T_2, UInt<1>(0h0))
node _r_out_val_T_4 = and(_r_out_val_T, _r_out_val_T_3)
node _r_out_val_T_5 = eq(io.req.bits.kill, UInt<1>(0h0))
node _r_out_val_T_6 = and(_r_out_val_T_4, _r_out_val_T_5)
connect r_out_val, _r_out_val_T_6
connect r_out_uop, r_divsqrt_uop
node _r_out_uop_br_mask_T_2 = not(io.brupdate.b1.resolve_mask)
node _r_out_uop_br_mask_T_3 = and(r_divsqrt_uop.br_mask, _r_out_uop_br_mask_T_2)
connect r_out_uop.br_mask, _r_out_uop_br_mask_T_3
node _r_out_wdata_double_maskedNaN_T = not(UInt<65>(0h1010000000000000))
node r_out_wdata_double_maskedNaN = and(divsqrt.io.out, _r_out_wdata_double_maskedNaN_T)
node _r_out_wdata_double_T = bits(divsqrt.io.out, 63, 61)
node _r_out_wdata_double_T_1 = andr(_r_out_wdata_double_T)
node _r_out_wdata_double_T_2 = mux(_r_out_wdata_double_T_1, r_out_wdata_double_maskedNaN, divsqrt.io.out)
connect r_out_wdata_double, _r_out_wdata_double_T_2
connect r_out_flags_double, divsqrt.io.exceptionFlags
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(r_divsqrt_val, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed: [fdiv] a response is being generated for no request.\n at fdiv.scala:205 assert (r_divsqrt_val, \"[fdiv] a response is being generated for no request.\")\n") : printf_1
assert(clock, r_divsqrt_val, UInt<1>(0h1), "") : assert_1
node _T_21 = or(divsqrt.io.outValid_div, divsqrt.io.outValid_sqrt)
node _T_22 = and(r_out_val, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: [fdiv] Buffered output being overwritten by another output from the fdiv/fsqrt unit.\n at fdiv.scala:208 assert (!(r_out_val && (divsqrt.io.outValid_div || divsqrt.io.outValid_sqrt)),\n") : printf_2
assert(clock, _T_23, UInt<1>(0h1), "") : assert_2
inst downvert_d2s of RecFNToRecFN_11
connect downvert_d2s.io.in, r_out_wdata_double
connect downvert_d2s.io.roundingMode, r_divsqrt_fin.rm
invalidate downvert_d2s.io.detectTininess
node _out_flags_T = eq(r_divsqrt_fin.typeTagIn, UInt<1>(0h0))
node _out_flags_T_1 = mux(_out_flags_T, downvert_d2s.io.exceptionFlags, UInt<1>(0h0))
node out_flags = or(r_out_flags_double, _out_flags_T_1)
node _io_resp_valid_T = and(io.brupdate.b1.mispredict_mask, r_out_uop.br_mask)
node _io_resp_valid_T_1 = neq(_io_resp_valid_T, UInt<1>(0h0))
node _io_resp_valid_T_2 = eq(_io_resp_valid_T_1, UInt<1>(0h0))
node _io_resp_valid_T_3 = and(r_out_val, _io_resp_valid_T_2)
connect io.resp.valid, _io_resp_valid_T_3
connect io.resp.bits.uop, r_out_uop
node _io_resp_bits_data_T = eq(r_divsqrt_fin.typeTagIn, UInt<1>(0h0))
node _io_resp_bits_data_opts_bigger_swizzledNaN_T = andr(UInt<20>(0hfffff))
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_1 = bits(downvert_d2s.io.out, 31, 31)
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_2 = bits(downvert_d2s.io.out, 32, 32)
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_3 = bits(downvert_d2s.io.out, 30, 0)
node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_2)
node io_resp_bits_data_opts_bigger_swizzledNaN_lo = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi, _io_resp_bits_data_opts_bigger_swizzledNaN_T_3)
node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_1)
node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T)
node io_resp_bits_data_opts_bigger_swizzledNaN_hi = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo)
node io_resp_bits_data_opts_bigger_swizzledNaN = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi, io_resp_bits_data_opts_bigger_swizzledNaN_lo)
node _io_resp_bits_data_opts_bigger_T = andr(UInt<3>(0h7))
node io_resp_bits_data_opts_bigger = mux(_io_resp_bits_data_opts_bigger_T, io_resp_bits_data_opts_bigger_swizzledNaN, UInt<65>(0h1ffffffffffffffff))
node io_resp_bits_data_opts_0 = or(io_resp_bits_data_opts_bigger, UInt<1>(0h0))
node _io_resp_bits_data_T_1 = eq(UInt<1>(0h0), UInt<1>(0h1))
node _io_resp_bits_data_T_2 = mux(_io_resp_bits_data_T_1, downvert_d2s.io.out, io_resp_bits_data_opts_0)
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff))
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_5 = bits(r_out_wdata_double, 31, 31)
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_6 = bits(r_out_wdata_double, 32, 32)
node _io_resp_bits_data_opts_bigger_swizzledNaN_T_7 = bits(r_out_wdata_double, 30, 0)
node io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _io_resp_bits_data_opts_bigger_swizzledNaN_T_6)
node io_resp_bits_data_opts_bigger_swizzledNaN_lo_1 = cat(io_resp_bits_data_opts_bigger_swizzledNaN_lo_hi_1, _io_resp_bits_data_opts_bigger_swizzledNaN_T_7)
node io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _io_resp_bits_data_opts_bigger_swizzledNaN_T_5)
node io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _io_resp_bits_data_opts_bigger_swizzledNaN_T_4)
node io_resp_bits_data_opts_bigger_swizzledNaN_hi_1 = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1, io_resp_bits_data_opts_bigger_swizzledNaN_hi_lo_1)
node io_resp_bits_data_opts_bigger_swizzledNaN_1 = cat(io_resp_bits_data_opts_bigger_swizzledNaN_hi_1, io_resp_bits_data_opts_bigger_swizzledNaN_lo_1)
node _io_resp_bits_data_opts_bigger_T_1 = andr(UInt<3>(0h7))
node io_resp_bits_data_opts_bigger_1 = mux(_io_resp_bits_data_opts_bigger_T_1, io_resp_bits_data_opts_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff))
node io_resp_bits_data_opts_0_1 = or(io_resp_bits_data_opts_bigger_1, UInt<1>(0h0))
node _io_resp_bits_data_T_3 = eq(UInt<1>(0h1), UInt<1>(0h1))
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, r_out_wdata_double, io_resp_bits_data_opts_0_1)
node _io_resp_bits_data_T_5 = mux(_io_resp_bits_data_T, _io_resp_bits_data_T_2, _io_resp_bits_data_T_4)
connect io.resp.bits.data, _io_resp_bits_data_T_5
connect io.resp.bits.fflags.valid, io.resp.valid
connect io.resp.bits.fflags.bits.uop, r_out_uop
node _io_resp_bits_fflags_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_resp_bits_fflags_bits_uop_br_mask_T_1 = and(r_out_uop.br_mask, _io_resp_bits_fflags_bits_uop_br_mask_T)
connect io.resp.bits.fflags.bits.uop.br_mask, _io_resp_bits_fflags_bits_uop_br_mask_T_1
connect io.resp.bits.fflags.bits.flags, out_flags | module FDivSqrtUnit_1( // @[fdiv.scala:84:7]
input clock, // @[fdiv.scala:84:7]
input reset, // @[fdiv.scala:84:7]
output io_req_ready, // @[functional-unit.scala:168:14]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
input io_resp_ready, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14]
input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14]
);
wire io_resp_valid_0; // @[fdiv.scala:84:7]
wire [32:0] _downvert_d2s_io_out; // @[fdiv.scala:211:28]
wire [4:0] _downvert_d2s_io_exceptionFlags; // @[fdiv.scala:211:28]
wire _divsqrt_io_inReady_div; // @[fdiv.scala:143:23]
wire _divsqrt_io_inReady_sqrt; // @[fdiv.scala:143:23]
wire _divsqrt_io_outValid_div; // @[fdiv.scala:143:23]
wire _divsqrt_io_outValid_sqrt; // @[fdiv.scala:143:23]
wire [64:0] _divsqrt_io_out; // @[fdiv.scala:143:23]
wire [4:0] _divsqrt_io_exceptionFlags; // @[fdiv.scala:143:23]
wire [64:0] _in2_upconvert_s2d_io_out; // @[fdiv.scala:112:21]
wire [64:0] _in1_upconvert_s2d_io_out; // @[fdiv.scala:112:21]
wire _fdiv_decoder_io_sigs_ldst; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_wen; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_ren1; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_ren2; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_ren3; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_swap12; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_swap23; // @[fdiv.scala:101:28]
wire [1:0] _fdiv_decoder_io_sigs_typeTagIn; // @[fdiv.scala:101:28]
wire [1:0] _fdiv_decoder_io_sigs_typeTagOut; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_fromint; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_toint; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_fastpipe; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_fma; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_div; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_sqrt; // @[fdiv.scala:101:28]
wire _fdiv_decoder_io_sigs_wflags; // @[fdiv.scala:101:28]
wire io_req_valid_0 = io_req_valid; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[fdiv.scala:84:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[fdiv.scala:84:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[fdiv.scala:84:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[fdiv.scala:84:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[fdiv.scala:84:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[fdiv.scala:84:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[fdiv.scala:84:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[fdiv.scala:84:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[fdiv.scala:84:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[fdiv.scala:84:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[fdiv.scala:84:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[fdiv.scala:84:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[fdiv.scala:84:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[fdiv.scala:84:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[fdiv.scala:84:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[fdiv.scala:84:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[fdiv.scala:84:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[fdiv.scala:84:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[fdiv.scala:84:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[fdiv.scala:84:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[fdiv.scala:84:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[fdiv.scala:84:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[fdiv.scala:84:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[fdiv.scala:84:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[fdiv.scala:84:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[fdiv.scala:84:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[fdiv.scala:84:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[fdiv.scala:84:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[fdiv.scala:84:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[fdiv.scala:84:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[fdiv.scala:84:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[fdiv.scala:84:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[fdiv.scala:84:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[fdiv.scala:84:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[fdiv.scala:84:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[fdiv.scala:84:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[fdiv.scala:84:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[fdiv.scala:84:7]
wire io_resp_ready_0 = io_resp_ready; // @[fdiv.scala:84:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[fdiv.scala:84:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[fdiv.scala:84:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[fdiv.scala:84:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[fdiv.scala:84:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[fdiv.scala:84:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[fdiv.scala:84:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[fdiv.scala:84:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[fdiv.scala:84:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[fdiv.scala:84:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[fdiv.scala:84:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[fdiv.scala:84:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[fdiv.scala:84:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[fdiv.scala:84:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[fdiv.scala:84:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[fdiv.scala:84:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[fdiv.scala:84:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[fdiv.scala:84:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[fdiv.scala:84:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[fdiv.scala:84:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[fdiv.scala:84:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[fdiv.scala:84:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[fdiv.scala:84:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[fdiv.scala:84:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[fdiv.scala:84:7]
wire io_req_bits_pred_data = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_predicated = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[fdiv.scala:84:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[fdiv.scala:84:7]
wire _io_resp_bits_data_T_1 = 1'h0; // @[package.scala:39:86]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[fdiv.scala:84:7]
wire [64:0] _r_buffer_fin_in1_T = 65'h0; // @[FPU.scala:372:31]
wire [64:0] _r_buffer_fin_in2_T = 65'h0; // @[FPU.scala:372:31]
wire [39:0] io_resp_bits_addr = 40'h0; // @[fdiv.scala:84:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[fdiv.scala:84:7]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[fdiv.scala:84:7]
wire _io_resp_bits_data_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42]
wire _io_resp_bits_data_opts_bigger_T = 1'h1; // @[FPU.scala:249:56]
wire _io_resp_bits_data_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42]
wire _io_resp_bits_data_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56]
wire _io_resp_bits_data_T_3 = 1'h1; // @[package.scala:39:86]
wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26]
wire [4:0] io_resp_bits_data_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26]
wire [64:0] _r_out_wdata_double_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27]
wire _io_req_ready_T; // @[fdiv.scala:109:19]
wire [64:0] _r_buffer_fin_in1_T_1 = io_req_bits_rs1_data_0; // @[FPU.scala:372:26]
wire [64:0] _r_buffer_fin_in2_T_1 = io_req_bits_rs2_data_0; // @[FPU.scala:372:26]
wire _io_resp_valid_T_3; // @[fdiv.scala:218:30]
wire io_resp_bits_fflags_valid_0 = io_resp_valid_0; // @[fdiv.scala:84:7]
wire [64:0] _io_resp_bits_data_T_5; // @[fdiv.scala:221:8]
wire [15:0] _io_resp_bits_fflags_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [4:0] out_flags; // @[fdiv.scala:216:38]
wire io_req_ready_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_rvc_0; // @[fdiv.scala:84:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[fdiv.scala:84:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_br_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_jalr_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_jal_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_sfb_0; // @[fdiv.scala:84:7]
wire [15:0] io_resp_bits_uop_br_mask_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_uop_br_tag_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_edge_inst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_taken_0; // @[fdiv.scala:84:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[fdiv.scala:84:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_rob_idx_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_stq_idx_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_ppred_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_prs1_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_prs2_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_prs3_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ppred_busy_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_exception_0; // @[fdiv.scala:84:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_bypassable_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_mem_signed_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_fence_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_fencei_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_amo_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_uses_ldq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_uses_stq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_is_unique_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_ldst_val_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_frs3_en_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_fp_val_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_fp_single_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst_0; // @[fdiv.scala:84:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_rvc_0; // @[fdiv.scala:84:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0; // @[fdiv.scala:84:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0; // @[fdiv.scala:84:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_br_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_jalr_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_jal_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_sfb_0; // @[fdiv.scala:84:7]
wire [15:0] io_resp_bits_fflags_bits_uop_br_mask_0; // @[fdiv.scala:84:7]
wire [3:0] io_resp_bits_fflags_bits_uop_br_tag_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_edge_inst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_taken_0; // @[fdiv.scala:84:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0; // @[fdiv.scala:84:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_pdst_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs1_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs2_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs3_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ppred_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy_0; // @[fdiv.scala:84:7]
wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_exception_0; // @[fdiv.scala:84:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_bypassable_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_mem_signed_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_fence_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_fencei_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_amo_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_uses_stq_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_is_unique_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0; // @[fdiv.scala:84:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_ldst_val_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_frs3_en_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_fp_val_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_fp_single_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if_0; // @[fdiv.scala:84:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0; // @[fdiv.scala:84:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0; // @[fdiv.scala:84:7]
wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[fdiv.scala:84:7]
wire [64:0] io_resp_bits_data_0; // @[fdiv.scala:84:7]
reg r_buffer_val; // @[fdiv.scala:97:29]
reg [6:0] r_buffer_req_uop_uopc; // @[fdiv.scala:98:25]
reg [31:0] r_buffer_req_uop_inst; // @[fdiv.scala:98:25]
reg [31:0] r_buffer_req_uop_debug_inst; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_rvc; // @[fdiv.scala:98:25]
reg [39:0] r_buffer_req_uop_debug_pc; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_iq_type; // @[fdiv.scala:98:25]
reg [9:0] r_buffer_req_uop_fu_code; // @[fdiv.scala:98:25]
reg [3:0] r_buffer_req_uop_ctrl_br_type; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_ctrl_op1_sel; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ctrl_op2_sel; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ctrl_imm_sel; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_ctrl_op_fcn; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_fcn_dw; // @[fdiv.scala:98:25]
reg [2:0] r_buffer_req_uop_ctrl_csr_cmd; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_is_load; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_is_sta; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ctrl_is_std; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_iw_state; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_iw_p1_poisoned; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_iw_p2_poisoned; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_br; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_jalr; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_jal; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_sfb; // @[fdiv.scala:98:25]
reg [15:0] r_buffer_req_uop_br_mask; // @[fdiv.scala:98:25]
reg [3:0] r_buffer_req_uop_br_tag; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_ftq_idx; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_edge_inst; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_pc_lob; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_taken; // @[fdiv.scala:98:25]
reg [19:0] r_buffer_req_uop_imm_packed; // @[fdiv.scala:98:25]
reg [11:0] r_buffer_req_uop_csr_addr; // @[fdiv.scala:98:25]
reg [6:0] r_buffer_req_uop_rob_idx; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_ldq_idx; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_stq_idx; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_rxq_idx; // @[fdiv.scala:98:25]
reg [6:0] r_buffer_req_uop_pdst; // @[fdiv.scala:98:25]
reg [6:0] r_buffer_req_uop_prs1; // @[fdiv.scala:98:25]
reg [6:0] r_buffer_req_uop_prs2; // @[fdiv.scala:98:25]
reg [6:0] r_buffer_req_uop_prs3; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_ppred; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_prs1_busy; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_prs2_busy; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_prs3_busy; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ppred_busy; // @[fdiv.scala:98:25]
reg [6:0] r_buffer_req_uop_stale_pdst; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_exception; // @[fdiv.scala:98:25]
reg [63:0] r_buffer_req_uop_exc_cause; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_bypassable; // @[fdiv.scala:98:25]
reg [4:0] r_buffer_req_uop_mem_cmd; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_mem_size; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_mem_signed; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_fence; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_fencei; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_amo; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_uses_ldq; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_uses_stq; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_sys_pc2epc; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_is_unique; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_flush_on_commit; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ldst_is_rs1; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_ldst; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_lrs1; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_lrs2; // @[fdiv.scala:98:25]
reg [5:0] r_buffer_req_uop_lrs3; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_ldst_val; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_dst_rtype; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_lrs1_rtype; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_lrs2_rtype; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_frs3_en; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_fp_val; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_fp_single; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_xcpt_pf_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_xcpt_ae_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_xcpt_ma_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_bp_debug_if; // @[fdiv.scala:98:25]
reg r_buffer_req_uop_bp_xcpt_if; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_debug_fsrc; // @[fdiv.scala:98:25]
reg [1:0] r_buffer_req_uop_debug_tsrc; // @[fdiv.scala:98:25]
reg [64:0] r_buffer_req_rs1_data; // @[fdiv.scala:98:25]
reg [64:0] r_buffer_req_rs2_data; // @[fdiv.scala:98:25]
reg r_buffer_req_kill; // @[fdiv.scala:98:25]
reg r_buffer_fin_ldst; // @[fdiv.scala:99:25]
reg r_buffer_fin_wen; // @[fdiv.scala:99:25]
reg r_buffer_fin_ren1; // @[fdiv.scala:99:25]
reg r_buffer_fin_ren2; // @[fdiv.scala:99:25]
reg r_buffer_fin_ren3; // @[fdiv.scala:99:25]
reg r_buffer_fin_swap12; // @[fdiv.scala:99:25]
reg r_buffer_fin_swap23; // @[fdiv.scala:99:25]
reg [1:0] r_buffer_fin_typeTagIn; // @[fdiv.scala:99:25]
reg [1:0] r_buffer_fin_typeTagOut; // @[fdiv.scala:99:25]
reg r_buffer_fin_fromint; // @[fdiv.scala:99:25]
reg r_buffer_fin_toint; // @[fdiv.scala:99:25]
reg r_buffer_fin_fastpipe; // @[fdiv.scala:99:25]
reg r_buffer_fin_fma; // @[fdiv.scala:99:25]
reg r_buffer_fin_div; // @[fdiv.scala:99:25]
reg r_buffer_fin_sqrt; // @[fdiv.scala:99:25]
reg r_buffer_fin_wflags; // @[fdiv.scala:99:25]
reg [2:0] r_buffer_fin_rm; // @[fdiv.scala:99:25]
reg [64:0] r_buffer_fin_in1; // @[fdiv.scala:99:25]
reg [64:0] r_buffer_fin_in2; // @[fdiv.scala:99:25]
wire [15:0] _GEN = io_brupdate_b1_mispredict_mask_0 & r_buffer_req_uop_br_mask; // @[util.scala:118:51]
wire [15:0] _r_buffer_val_T; // @[util.scala:118:51]
assign _r_buffer_val_T = _GEN; // @[util.scala:118:51]
wire [15:0] _r_divsqrt_killed_T_4; // @[util.scala:118:51]
assign _r_divsqrt_killed_T_4 = _GEN; // @[util.scala:118:51]
wire _r_buffer_val_T_1 = |_r_buffer_val_T; // @[util.scala:118:{51,59}]
wire _r_buffer_val_T_2 = ~_r_buffer_val_T_1; // @[util.scala:118:59]
wire _r_buffer_val_T_3 = ~io_req_bits_kill_0; // @[fdiv.scala:84:7, :105:71]
wire _r_buffer_val_T_4 = _r_buffer_val_T_2 & _r_buffer_val_T_3; // @[fdiv.scala:105:{19,68,71}]
wire _r_buffer_val_T_5 = _r_buffer_val_T_4 & r_buffer_val; // @[fdiv.scala:97:29, :105:{68,89}]
wire [15:0] _r_buffer_req_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_buffer_req_uop_br_mask_T_1 = r_buffer_req_uop_br_mask & _r_buffer_req_uop_br_mask_T; // @[util.scala:85:{25,27}]
assign _io_req_ready_T = ~r_buffer_val; // @[fdiv.scala:97:29, :109:19]
assign io_req_ready_0 = _io_req_ready_T; // @[fdiv.scala:84:7, :109:19]
wire _in1_upconvert_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _r_buffer_fin_in1_prev_unswizzled_T = io_req_bits_rs1_data_0[31]; // @[FPU.scala:357:14]
wire _in1_upconvert_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire _r_buffer_fin_in1_prev_unswizzled_T_1 = io_req_bits_rs1_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _in1_upconvert_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _r_buffer_fin_in1_prev_unswizzled_T_2 = io_req_bits_rs1_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] in1_upconvert_prev_unswizzled_hi = {_in1_upconvert_prev_unswizzled_T, _in1_upconvert_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] in1_upconvert_floats_0 = {in1_upconvert_prev_unswizzled_hi, _in1_upconvert_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _in1_upconvert_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _r_buffer_fin_in1_prev_isbox_T = io_req_bits_rs1_data_0[64:60]; // @[FPU.scala:332:49]
wire in1_upconvert_prev_isbox = &_in1_upconvert_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire in1_upconvert_oks_0 = in1_upconvert_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire in1_upconvert_sign = io_req_bits_rs1_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] in1_upconvert_fractIn = io_req_bits_rs1_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] in1_upconvert_expIn = io_req_bits_rs1_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _in1_upconvert_fractOut_T = {in1_upconvert_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] in1_upconvert_fractOut = _in1_upconvert_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] in1_upconvert_expOut_expCode = in1_upconvert_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _in1_upconvert_expOut_commonCase_T = {1'h0, in1_upconvert_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _in1_upconvert_expOut_commonCase_T_1 = _in1_upconvert_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _in1_upconvert_expOut_commonCase_T_2 = {1'h0, _in1_upconvert_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] in1_upconvert_expOut_commonCase = _in1_upconvert_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _in1_upconvert_expOut_T = in1_upconvert_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _in1_upconvert_expOut_T_1 = in1_upconvert_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _in1_upconvert_expOut_T_2 = _in1_upconvert_expOut_T | _in1_upconvert_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _in1_upconvert_expOut_T_3 = in1_upconvert_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _in1_upconvert_expOut_T_4 = {in1_upconvert_expOut_expCode, _in1_upconvert_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _in1_upconvert_expOut_T_5 = in1_upconvert_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] in1_upconvert_expOut = _in1_upconvert_expOut_T_2 ? _in1_upconvert_expOut_T_4 : _in1_upconvert_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] in1_upconvert_hi = {in1_upconvert_sign, in1_upconvert_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] in1_upconvert_floats_1 = {in1_upconvert_hi, in1_upconvert_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _in1_upconvert_T = in1_upconvert_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _in1_upconvert_T_1 = in1_upconvert_floats_0 | _in1_upconvert_T; // @[FPU.scala:356:31, :372:{26,31}]
wire _in2_upconvert_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _r_buffer_fin_in2_prev_unswizzled_T = io_req_bits_rs2_data_0[31]; // @[FPU.scala:357:14]
wire _in2_upconvert_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire _r_buffer_fin_in2_prev_unswizzled_T_1 = io_req_bits_rs2_data_0[52]; // @[FPU.scala:358:14]
wire [30:0] _in2_upconvert_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [30:0] _r_buffer_fin_in2_prev_unswizzled_T_2 = io_req_bits_rs2_data_0[30:0]; // @[FPU.scala:359:14]
wire [1:0] in2_upconvert_prev_unswizzled_hi = {_in2_upconvert_prev_unswizzled_T, _in2_upconvert_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] in2_upconvert_floats_0 = {in2_upconvert_prev_unswizzled_hi, _in2_upconvert_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire [4:0] _in2_upconvert_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire [4:0] _r_buffer_fin_in2_prev_isbox_T = io_req_bits_rs2_data_0[64:60]; // @[FPU.scala:332:49]
wire in2_upconvert_prev_isbox = &_in2_upconvert_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire in2_upconvert_oks_0 = in2_upconvert_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire in2_upconvert_sign = io_req_bits_rs2_data_0[64]; // @[FPU.scala:274:17]
wire [51:0] in2_upconvert_fractIn = io_req_bits_rs2_data_0[51:0]; // @[FPU.scala:275:20]
wire [11:0] in2_upconvert_expIn = io_req_bits_rs2_data_0[63:52]; // @[FPU.scala:276:18]
wire [75:0] _in2_upconvert_fractOut_T = {in2_upconvert_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] in2_upconvert_fractOut = _in2_upconvert_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] in2_upconvert_expOut_expCode = in2_upconvert_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _in2_upconvert_expOut_commonCase_T = {1'h0, in2_upconvert_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _in2_upconvert_expOut_commonCase_T_1 = _in2_upconvert_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _in2_upconvert_expOut_commonCase_T_2 = {1'h0, _in2_upconvert_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] in2_upconvert_expOut_commonCase = _in2_upconvert_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _in2_upconvert_expOut_T = in2_upconvert_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _in2_upconvert_expOut_T_1 = in2_upconvert_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _in2_upconvert_expOut_T_2 = _in2_upconvert_expOut_T | _in2_upconvert_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _in2_upconvert_expOut_T_3 = in2_upconvert_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _in2_upconvert_expOut_T_4 = {in2_upconvert_expOut_expCode, _in2_upconvert_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _in2_upconvert_expOut_T_5 = in2_upconvert_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] in2_upconvert_expOut = _in2_upconvert_expOut_T_2 ? _in2_upconvert_expOut_T_4 : _in2_upconvert_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] in2_upconvert_hi = {in2_upconvert_sign, in2_upconvert_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] in2_upconvert_floats_1 = {in2_upconvert_hi, in2_upconvert_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [32:0] _in2_upconvert_T = in2_upconvert_oks_0 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31]
wire [32:0] _in2_upconvert_T_1 = in2_upconvert_floats_0 | _in2_upconvert_T; // @[FPU.scala:356:31, :372:{26,31}]
wire [15:0] _r_buffer_req_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_buffer_req_uop_br_mask_T_3 = io_req_bits_uop_br_mask_0 & _r_buffer_req_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
wire [2:0] _r_buffer_fin_rm_T = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58]
wire [2:0] _r_buffer_fin_rm_T_2 = io_req_bits_uop_imm_packed_0[2:0]; // @[util.scala:289:58]
wire _r_buffer_fin_rm_T_1 = &_r_buffer_fin_rm_T; // @[util.scala:289:58]
wire [2:0] _r_buffer_fin_rm_T_3 = _r_buffer_fin_rm_T_1 ? io_fcsr_rm_0 : _r_buffer_fin_rm_T_2; // @[util.scala:289:58]
wire [1:0] r_buffer_fin_in1_prev_unswizzled_hi = {_r_buffer_fin_in1_prev_unswizzled_T, _r_buffer_fin_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] r_buffer_fin_in1_prev_unswizzled = {r_buffer_fin_in1_prev_unswizzled_hi, _r_buffer_fin_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire r_buffer_fin_in1_prev_prev_sign = r_buffer_fin_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] r_buffer_fin_in1_prev_prev_fractIn = r_buffer_fin_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] r_buffer_fin_in1_prev_prev_expIn = r_buffer_fin_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _r_buffer_fin_in1_prev_prev_fractOut_T = {r_buffer_fin_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] r_buffer_fin_in1_prev_prev_fractOut = _r_buffer_fin_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] r_buffer_fin_in1_prev_prev_expOut_expCode = r_buffer_fin_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T = {4'h0, r_buffer_fin_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1 = _r_buffer_fin_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] r_buffer_fin_in1_prev_prev_expOut_commonCase = _r_buffer_fin_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_T_5 = r_buffer_fin_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _r_buffer_fin_in1_prev_prev_expOut_T = r_buffer_fin_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _r_buffer_fin_in1_prev_prev_expOut_T_1 = r_buffer_fin_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _r_buffer_fin_in1_prev_prev_expOut_T_2 = _r_buffer_fin_in1_prev_prev_expOut_T | _r_buffer_fin_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _r_buffer_fin_in1_prev_prev_expOut_T_3 = r_buffer_fin_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _r_buffer_fin_in1_prev_prev_expOut_T_4 = {r_buffer_fin_in1_prev_prev_expOut_expCode, _r_buffer_fin_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] r_buffer_fin_in1_prev_prev_expOut = _r_buffer_fin_in1_prev_prev_expOut_T_2 ? _r_buffer_fin_in1_prev_prev_expOut_T_4 : _r_buffer_fin_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] r_buffer_fin_in1_prev_prev_hi = {r_buffer_fin_in1_prev_prev_sign, r_buffer_fin_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] r_buffer_fin_in1_floats_0 = {r_buffer_fin_in1_prev_prev_hi, r_buffer_fin_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire r_buffer_fin_in1_prev_isbox = &_r_buffer_fin_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire r_buffer_fin_in1_oks_0 = r_buffer_fin_in1_prev_isbox; // @[FPU.scala:332:84, :362:32]
wire [1:0] r_buffer_fin_in2_prev_unswizzled_hi = {_r_buffer_fin_in2_prev_unswizzled_T, _r_buffer_fin_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14]
wire [32:0] r_buffer_fin_in2_prev_unswizzled = {r_buffer_fin_in2_prev_unswizzled_hi, _r_buffer_fin_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14]
wire r_buffer_fin_in2_prev_prev_sign = r_buffer_fin_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31]
wire [22:0] r_buffer_fin_in2_prev_prev_fractIn = r_buffer_fin_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31]
wire [8:0] r_buffer_fin_in2_prev_prev_expIn = r_buffer_fin_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31]
wire [75:0] _r_buffer_fin_in2_prev_prev_fractOut_T = {r_buffer_fin_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28]
wire [51:0] r_buffer_fin_in2_prev_prev_fractOut = _r_buffer_fin_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}]
wire [2:0] r_buffer_fin_in2_prev_prev_expOut_expCode = r_buffer_fin_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T = {4'h0, r_buffer_fin_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31]
wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1 = _r_buffer_fin_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}]
wire [11:0] r_buffer_fin_in2_prev_prev_expOut_commonCase = _r_buffer_fin_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_T_5 = r_buffer_fin_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97]
wire _r_buffer_fin_in2_prev_prev_expOut_T = r_buffer_fin_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _r_buffer_fin_in2_prev_prev_expOut_T_1 = r_buffer_fin_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _r_buffer_fin_in2_prev_prev_expOut_T_2 = _r_buffer_fin_in2_prev_prev_expOut_T | _r_buffer_fin_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [8:0] _r_buffer_fin_in2_prev_prev_expOut_T_3 = r_buffer_fin_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69]
wire [11:0] _r_buffer_fin_in2_prev_prev_expOut_T_4 = {r_buffer_fin_in2_prev_prev_expOut_expCode, _r_buffer_fin_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [11:0] r_buffer_fin_in2_prev_prev_expOut = _r_buffer_fin_in2_prev_prev_expOut_T_2 ? _r_buffer_fin_in2_prev_prev_expOut_T_4 : _r_buffer_fin_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [12:0] r_buffer_fin_in2_prev_prev_hi = {r_buffer_fin_in2_prev_prev_sign, r_buffer_fin_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [64:0] r_buffer_fin_in2_floats_0 = {r_buffer_fin_in2_prev_prev_hi, r_buffer_fin_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8]
wire r_buffer_fin_in2_prev_isbox = &_r_buffer_fin_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}]
wire r_buffer_fin_in2_oks_0 = r_buffer_fin_in2_prev_isbox; // @[FPU.scala:332:84, :362:32]
reg r_divsqrt_val; // @[fdiv.scala:145:30]
reg r_divsqrt_killed; // @[fdiv.scala:146:29]
reg r_divsqrt_fin_ldst; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_wen; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_ren1; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_ren2; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_ren3; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_swap12; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_swap23; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_typeTagIn; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_typeTagOut; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_fromint; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_toint; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_fastpipe; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_fma; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_div; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_sqrt; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_wflags; // @[fdiv.scala:147:26]
reg r_divsqrt_fin_vec; // @[fdiv.scala:147:26]
reg [2:0] r_divsqrt_fin_rm; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_fmaCmd; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_typ; // @[fdiv.scala:147:26]
reg [1:0] r_divsqrt_fin_fmt; // @[fdiv.scala:147:26]
reg [64:0] r_divsqrt_fin_in1; // @[fdiv.scala:147:26]
reg [64:0] r_divsqrt_fin_in2; // @[fdiv.scala:147:26]
reg [64:0] r_divsqrt_fin_in3; // @[fdiv.scala:147:26]
reg [6:0] r_divsqrt_uop_uopc; // @[fdiv.scala:148:26]
reg [31:0] r_divsqrt_uop_inst; // @[fdiv.scala:148:26]
reg [31:0] r_divsqrt_uop_debug_inst; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_rvc; // @[fdiv.scala:148:26]
reg [39:0] r_divsqrt_uop_debug_pc; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_iq_type; // @[fdiv.scala:148:26]
reg [9:0] r_divsqrt_uop_fu_code; // @[fdiv.scala:148:26]
reg [3:0] r_divsqrt_uop_ctrl_br_type; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_ctrl_op1_sel; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ctrl_op2_sel; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ctrl_imm_sel; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_ctrl_op_fcn; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_fcn_dw; // @[fdiv.scala:148:26]
reg [2:0] r_divsqrt_uop_ctrl_csr_cmd; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_is_load; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_is_sta; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ctrl_is_std; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_iw_state; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_iw_p1_poisoned; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_iw_p2_poisoned; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_br; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_jalr; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_jal; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_sfb; // @[fdiv.scala:148:26]
reg [15:0] r_divsqrt_uop_br_mask; // @[fdiv.scala:148:26]
reg [3:0] r_divsqrt_uop_br_tag; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_ftq_idx; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_edge_inst; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_pc_lob; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_taken; // @[fdiv.scala:148:26]
reg [19:0] r_divsqrt_uop_imm_packed; // @[fdiv.scala:148:26]
reg [11:0] r_divsqrt_uop_csr_addr; // @[fdiv.scala:148:26]
reg [6:0] r_divsqrt_uop_rob_idx; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_ldq_idx; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_stq_idx; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_rxq_idx; // @[fdiv.scala:148:26]
reg [6:0] r_divsqrt_uop_pdst; // @[fdiv.scala:148:26]
reg [6:0] r_divsqrt_uop_prs1; // @[fdiv.scala:148:26]
reg [6:0] r_divsqrt_uop_prs2; // @[fdiv.scala:148:26]
reg [6:0] r_divsqrt_uop_prs3; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_ppred; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_prs1_busy; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_prs2_busy; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_prs3_busy; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ppred_busy; // @[fdiv.scala:148:26]
reg [6:0] r_divsqrt_uop_stale_pdst; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_exception; // @[fdiv.scala:148:26]
reg [63:0] r_divsqrt_uop_exc_cause; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_bypassable; // @[fdiv.scala:148:26]
reg [4:0] r_divsqrt_uop_mem_cmd; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_mem_size; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_mem_signed; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_fence; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_fencei; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_amo; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_uses_ldq; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_uses_stq; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_sys_pc2epc; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_is_unique; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_flush_on_commit; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ldst_is_rs1; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_ldst; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_lrs1; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_lrs2; // @[fdiv.scala:148:26]
reg [5:0] r_divsqrt_uop_lrs3; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_ldst_val; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_dst_rtype; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_lrs1_rtype; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_lrs2_rtype; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_frs3_en; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_fp_val; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_fp_single; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_xcpt_pf_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_xcpt_ae_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_xcpt_ma_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_bp_debug_if; // @[fdiv.scala:148:26]
reg r_divsqrt_uop_bp_xcpt_if; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_debug_fsrc; // @[fdiv.scala:148:26]
reg [1:0] r_divsqrt_uop_debug_tsrc; // @[fdiv.scala:148:26]
wire _output_buffer_available_T; // @[fdiv.scala:189:30]
wire output_buffer_available; // @[fdiv.scala:151:37]
wire _may_fire_input_T = r_buffer_fin_div | r_buffer_fin_sqrt; // @[fdiv.scala:99:25, :155:23]
wire _may_fire_input_T_1 = r_buffer_val & _may_fire_input_T; // @[fdiv.scala:97:29, :154:18, :155:23]
wire _may_fire_input_T_2 = ~r_divsqrt_val; // @[fdiv.scala:145:30, :156:5]
wire _may_fire_input_T_3 = _may_fire_input_T_1 & _may_fire_input_T_2; // @[fdiv.scala:154:18, :155:45, :156:5]
wire may_fire_input = _may_fire_input_T_3 & output_buffer_available; // @[fdiv.scala:151:37, :155:45, :156:20]
wire divsqrt_ready = r_buffer_fin_sqrt ? _divsqrt_io_inReady_sqrt : _divsqrt_io_inReady_div; // @[fdiv.scala:99:25, :143:23, :159:26]
wire [64:0] _divsqrt_io_b_T = r_buffer_fin_sqrt ? r_buffer_fin_in1 : r_buffer_fin_in2; // @[fdiv.scala:99:25, :163:22]
wire [15:0] _GEN_0 = io_brupdate_b1_mispredict_mask_0 & r_divsqrt_uop_br_mask; // @[util.scala:118:51]
wire [15:0] _r_divsqrt_killed_T; // @[util.scala:118:51]
assign _r_divsqrt_killed_T = _GEN_0; // @[util.scala:118:51]
wire [15:0] _r_out_val_T_1; // @[util.scala:118:51]
assign _r_out_val_T_1 = _GEN_0; // @[util.scala:118:51]
wire _r_divsqrt_killed_T_1 = |_r_divsqrt_killed_T; // @[util.scala:118:{51,59}]
wire _r_divsqrt_killed_T_2 = r_divsqrt_killed | _r_divsqrt_killed_T_1; // @[util.scala:118:59]
wire _r_divsqrt_killed_T_3 = _r_divsqrt_killed_T_2 | io_req_bits_kill_0; // @[fdiv.scala:84:7, :167:{40,88}]
wire [15:0] _r_divsqrt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_divsqrt_uop_br_mask_T_1 = r_divsqrt_uop_br_mask & _r_divsqrt_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire _r_divsqrt_killed_T_5 = |_r_divsqrt_killed_T_4; // @[util.scala:118:{51,59}]
wire _r_divsqrt_killed_T_6 = _r_divsqrt_killed_T_5 | io_req_bits_kill_0; // @[util.scala:118:59]
wire [15:0] _r_divsqrt_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_divsqrt_uop_br_mask_T_3 = r_buffer_req_uop_br_mask & _r_divsqrt_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
reg r_out_val; // @[fdiv.scala:184:26]
reg [6:0] r_out_uop_uopc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_uopc_0 = r_out_uop_uopc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_uopc_0 = r_out_uop_uopc; // @[fdiv.scala:84:7, :185:22]
reg [31:0] r_out_uop_inst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_inst_0 = r_out_uop_inst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_inst_0 = r_out_uop_inst; // @[fdiv.scala:84:7, :185:22]
reg [31:0] r_out_uop_debug_inst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_inst_0 = r_out_uop_debug_inst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_inst_0 = r_out_uop_debug_inst; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_rvc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_rvc_0 = r_out_uop_is_rvc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_rvc_0 = r_out_uop_is_rvc; // @[fdiv.scala:84:7, :185:22]
reg [39:0] r_out_uop_debug_pc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_pc_0 = r_out_uop_debug_pc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_pc_0 = r_out_uop_debug_pc; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_iq_type; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iq_type_0 = r_out_uop_iq_type; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iq_type_0 = r_out_uop_iq_type; // @[fdiv.scala:84:7, :185:22]
reg [9:0] r_out_uop_fu_code; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_fu_code_0 = r_out_uop_fu_code; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_fu_code_0 = r_out_uop_fu_code; // @[fdiv.scala:84:7, :185:22]
reg [3:0] r_out_uop_ctrl_br_type; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_br_type_0 = r_out_uop_ctrl_br_type; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = r_out_uop_ctrl_br_type; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_ctrl_op1_sel; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_out_uop_ctrl_op1_sel; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = r_out_uop_ctrl_op1_sel; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ctrl_op2_sel; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_out_uop_ctrl_op2_sel; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = r_out_uop_ctrl_op2_sel; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ctrl_imm_sel; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_out_uop_ctrl_imm_sel; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = r_out_uop_ctrl_imm_sel; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_ctrl_op_fcn; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_out_uop_ctrl_op_fcn; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = r_out_uop_ctrl_op_fcn; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = r_out_uop_ctrl_fcn_dw; // @[fdiv.scala:84:7, :185:22]
reg [2:0] r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = r_out_uop_ctrl_csr_cmd; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_is_load; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_is_load_0 = r_out_uop_ctrl_is_load; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = r_out_uop_ctrl_is_load; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_is_sta; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_out_uop_ctrl_is_sta; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = r_out_uop_ctrl_is_sta; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ctrl_is_std; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ctrl_is_std_0 = r_out_uop_ctrl_is_std; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = r_out_uop_ctrl_is_std; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_iw_state; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iw_state_0 = r_out_uop_iw_state; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iw_state_0 = r_out_uop_iw_state; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_iw_p1_poisoned; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_out_uop_iw_p1_poisoned; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = r_out_uop_iw_p1_poisoned; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_iw_p2_poisoned; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_out_uop_iw_p2_poisoned; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = r_out_uop_iw_p2_poisoned; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_br; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_br_0 = r_out_uop_is_br; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_br_0 = r_out_uop_is_br; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_jalr; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_jalr_0 = r_out_uop_is_jalr; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_jalr_0 = r_out_uop_is_jalr; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_jal; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_jal_0 = r_out_uop_is_jal; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_jal_0 = r_out_uop_is_jal; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_sfb; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_sfb_0 = r_out_uop_is_sfb; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_sfb_0 = r_out_uop_is_sfb; // @[fdiv.scala:84:7, :185:22]
reg [15:0] r_out_uop_br_mask; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_br_mask_0 = r_out_uop_br_mask; // @[fdiv.scala:84:7, :185:22]
reg [3:0] r_out_uop_br_tag; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_br_tag_0 = r_out_uop_br_tag; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_br_tag_0 = r_out_uop_br_tag; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_ftq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ftq_idx_0 = r_out_uop_ftq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ftq_idx_0 = r_out_uop_ftq_idx; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_edge_inst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_edge_inst_0 = r_out_uop_edge_inst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_edge_inst_0 = r_out_uop_edge_inst; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_pc_lob; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_pc_lob_0 = r_out_uop_pc_lob; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_pc_lob_0 = r_out_uop_pc_lob; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_taken; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_taken_0 = r_out_uop_taken; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_taken_0 = r_out_uop_taken; // @[fdiv.scala:84:7, :185:22]
reg [19:0] r_out_uop_imm_packed; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_imm_packed_0 = r_out_uop_imm_packed; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_imm_packed_0 = r_out_uop_imm_packed; // @[fdiv.scala:84:7, :185:22]
reg [11:0] r_out_uop_csr_addr; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_csr_addr_0 = r_out_uop_csr_addr; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_csr_addr_0 = r_out_uop_csr_addr; // @[fdiv.scala:84:7, :185:22]
reg [6:0] r_out_uop_rob_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_rob_idx_0 = r_out_uop_rob_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_rob_idx_0 = r_out_uop_rob_idx; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_ldq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldq_idx_0 = r_out_uop_ldq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldq_idx_0 = r_out_uop_ldq_idx; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_stq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_stq_idx_0 = r_out_uop_stq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_stq_idx_0 = r_out_uop_stq_idx; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_rxq_idx; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_rxq_idx_0 = r_out_uop_rxq_idx; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_rxq_idx_0 = r_out_uop_rxq_idx; // @[fdiv.scala:84:7, :185:22]
reg [6:0] r_out_uop_pdst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_pdst_0 = r_out_uop_pdst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_pdst_0 = r_out_uop_pdst; // @[fdiv.scala:84:7, :185:22]
reg [6:0] r_out_uop_prs1; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs1_0 = r_out_uop_prs1; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs1_0 = r_out_uop_prs1; // @[fdiv.scala:84:7, :185:22]
reg [6:0] r_out_uop_prs2; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs2_0 = r_out_uop_prs2; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs2_0 = r_out_uop_prs2; // @[fdiv.scala:84:7, :185:22]
reg [6:0] r_out_uop_prs3; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs3_0 = r_out_uop_prs3; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs3_0 = r_out_uop_prs3; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_ppred; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ppred_0 = r_out_uop_ppred; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ppred_0 = r_out_uop_ppred; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_prs1_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs1_busy_0 = r_out_uop_prs1_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs1_busy_0 = r_out_uop_prs1_busy; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_prs2_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs2_busy_0 = r_out_uop_prs2_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs2_busy_0 = r_out_uop_prs2_busy; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_prs3_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_prs3_busy_0 = r_out_uop_prs3_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_prs3_busy_0 = r_out_uop_prs3_busy; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ppred_busy; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ppred_busy_0 = r_out_uop_ppred_busy; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ppred_busy_0 = r_out_uop_ppred_busy; // @[fdiv.scala:84:7, :185:22]
reg [6:0] r_out_uop_stale_pdst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_stale_pdst_0 = r_out_uop_stale_pdst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_stale_pdst_0 = r_out_uop_stale_pdst; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_exception; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_exception_0 = r_out_uop_exception; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_exception_0 = r_out_uop_exception; // @[fdiv.scala:84:7, :185:22]
reg [63:0] r_out_uop_exc_cause; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_exc_cause_0 = r_out_uop_exc_cause; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_exc_cause_0 = r_out_uop_exc_cause; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_bypassable; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_bypassable_0 = r_out_uop_bypassable; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_bypassable_0 = r_out_uop_bypassable; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_uop_mem_cmd; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_mem_cmd_0 = r_out_uop_mem_cmd; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_mem_cmd_0 = r_out_uop_mem_cmd; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_mem_size; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_mem_size_0 = r_out_uop_mem_size; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_mem_size_0 = r_out_uop_mem_size; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_mem_signed; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_mem_signed_0 = r_out_uop_mem_signed; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_mem_signed_0 = r_out_uop_mem_signed; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_fence; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_fence_0 = r_out_uop_is_fence; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_fence_0 = r_out_uop_is_fence; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_fencei; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_fencei_0 = r_out_uop_is_fencei; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_fencei_0 = r_out_uop_is_fencei; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_amo; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_amo_0 = r_out_uop_is_amo; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_amo_0 = r_out_uop_is_amo; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_uses_ldq; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_uses_ldq_0 = r_out_uop_uses_ldq; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_uses_ldq_0 = r_out_uop_uses_ldq; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_uses_stq; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_uses_stq_0 = r_out_uop_uses_stq; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_uses_stq_0 = r_out_uop_uses_stq; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_sys_pc2epc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_out_uop_is_sys_pc2epc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = r_out_uop_is_sys_pc2epc; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_is_unique; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_is_unique_0 = r_out_uop_is_unique; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_is_unique_0 = r_out_uop_is_unique; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_flush_on_commit; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_flush_on_commit_0 = r_out_uop_flush_on_commit; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_flush_on_commit_0 = r_out_uop_flush_on_commit; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ldst_is_rs1; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_out_uop_ldst_is_rs1; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = r_out_uop_ldst_is_rs1; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_ldst; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldst_0 = r_out_uop_ldst; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldst_0 = r_out_uop_ldst; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_lrs1; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs1_0 = r_out_uop_lrs1; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs1_0 = r_out_uop_lrs1; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_lrs2; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs2_0 = r_out_uop_lrs2; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs2_0 = r_out_uop_lrs2; // @[fdiv.scala:84:7, :185:22]
reg [5:0] r_out_uop_lrs3; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs3_0 = r_out_uop_lrs3; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs3_0 = r_out_uop_lrs3; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_ldst_val; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_ldst_val_0 = r_out_uop_ldst_val; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_ldst_val_0 = r_out_uop_ldst_val; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_dst_rtype; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_dst_rtype_0 = r_out_uop_dst_rtype; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_dst_rtype_0 = r_out_uop_dst_rtype; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_lrs1_rtype; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs1_rtype_0 = r_out_uop_lrs1_rtype; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = r_out_uop_lrs1_rtype; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_lrs2_rtype; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_lrs2_rtype_0 = r_out_uop_lrs2_rtype; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = r_out_uop_lrs2_rtype; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_frs3_en; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_frs3_en_0 = r_out_uop_frs3_en; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_frs3_en_0 = r_out_uop_frs3_en; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_fp_val; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_fp_val_0 = r_out_uop_fp_val; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_fp_val_0 = r_out_uop_fp_val; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_fp_single; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_fp_single_0 = r_out_uop_fp_single; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_fp_single_0 = r_out_uop_fp_single; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_xcpt_pf_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_out_uop_xcpt_pf_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = r_out_uop_xcpt_pf_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_xcpt_ae_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_out_uop_xcpt_ae_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = r_out_uop_xcpt_ae_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_xcpt_ma_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_out_uop_xcpt_ma_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = r_out_uop_xcpt_ma_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_bp_debug_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_bp_debug_if_0 = r_out_uop_bp_debug_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_bp_debug_if_0 = r_out_uop_bp_debug_if; // @[fdiv.scala:84:7, :185:22]
reg r_out_uop_bp_xcpt_if; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_out_uop_bp_xcpt_if; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = r_out_uop_bp_xcpt_if; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_debug_fsrc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_fsrc_0 = r_out_uop_debug_fsrc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_fsrc_0 = r_out_uop_debug_fsrc; // @[fdiv.scala:84:7, :185:22]
reg [1:0] r_out_uop_debug_tsrc; // @[fdiv.scala:185:22]
assign io_resp_bits_uop_debug_tsrc_0 = r_out_uop_debug_tsrc; // @[fdiv.scala:84:7, :185:22]
assign io_resp_bits_fflags_bits_uop_debug_tsrc_0 = r_out_uop_debug_tsrc; // @[fdiv.scala:84:7, :185:22]
reg [4:0] r_out_flags_double; // @[fdiv.scala:186:31]
reg [64:0] r_out_wdata_double; // @[fdiv.scala:187:31]
wire [64:0] _io_resp_bits_data_T_4 = r_out_wdata_double; // @[package.scala:39:76]
assign _output_buffer_available_T = ~r_out_val; // @[fdiv.scala:184:26, :189:30]
assign output_buffer_available = _output_buffer_available_T; // @[fdiv.scala:151:37, :189:30]
wire [15:0] _r_out_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_out_uop_br_mask_T_1 = r_out_uop_br_mask & _r_out_uop_br_mask_T; // @[util.scala:85:{25,27}]
wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_out_uop_br_mask; // @[util.scala:118:51]
wire _T_21 = _divsqrt_io_outValid_div | _divsqrt_io_outValid_sqrt; // @[fdiv.scala:143:23, :196:33]
wire _r_out_val_T = ~r_divsqrt_killed; // @[fdiv.scala:146:29, :199:18]
wire _r_out_val_T_2 = |_r_out_val_T_1; // @[util.scala:118:{51,59}]
wire _r_out_val_T_3 = ~_r_out_val_T_2; // @[util.scala:118:59]
wire _r_out_val_T_4 = _r_out_val_T & _r_out_val_T_3; // @[fdiv.scala:199:{18,36,39}]
wire _r_out_val_T_5 = ~io_req_bits_kill_0; // @[fdiv.scala:84:7, :105:71, :199:88]
wire _r_out_val_T_6 = _r_out_val_T_4 & _r_out_val_T_5; // @[fdiv.scala:199:{36,85,88}]
wire [15:0] _r_out_uop_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_out_uop_br_mask_T_3 = r_divsqrt_uop_br_mask & _r_out_uop_br_mask_T_2; // @[util.scala:85:{25,27}]
wire [64:0] r_out_wdata_double_maskedNaN = _divsqrt_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25]
wire [2:0] _r_out_wdata_double_T = _divsqrt_io_out[63:61]; // @[FPU.scala:249:25]
wire _r_out_wdata_double_T_1 = &_r_out_wdata_double_T; // @[FPU.scala:249:{25,56}]
wire [64:0] _r_out_wdata_double_T_2 = _r_out_wdata_double_T_1 ? r_out_wdata_double_maskedNaN : _divsqrt_io_out; // @[FPU.scala:249:56, :413:25, :414:10] |
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_pbus :
input clock : Clock
input reset : Reset
output auto : { }
skip | module TLAtomicAutomata_pbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset // @[AtomicAutomata.scala:36:9]
);
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ICache :
input clock : Clock
input reset : Reset
output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s2_vaddr : UInt<39>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, flip s2_cacheable : UInt<1>, flip s2_prefetch : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<32>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, perf : { acquire : UInt<1>}, flip clock_enabled : UInt<1>, keep_clock_enabled : UInt<1>}
wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate masterNodeOut.d.bits.corrupt
invalidate masterNodeOut.d.bits.data
invalidate masterNodeOut.d.bits.denied
invalidate masterNodeOut.d.bits.sink
invalidate masterNodeOut.d.bits.source
invalidate masterNodeOut.d.bits.size
invalidate masterNodeOut.d.bits.param
invalidate masterNodeOut.d.bits.opcode
invalidate masterNodeOut.d.valid
invalidate masterNodeOut.d.ready
invalidate masterNodeOut.a.bits.corrupt
invalidate masterNodeOut.a.bits.data
invalidate masterNodeOut.a.bits.mask
invalidate masterNodeOut.a.bits.address
invalidate masterNodeOut.a.bits.source
invalidate masterNodeOut.a.bits.size
invalidate masterNodeOut.a.bits.param
invalidate masterNodeOut.a.bits.opcode
invalidate masterNodeOut.a.valid
invalidate masterNodeOut.a.ready
connect auto.master_out, masterNodeOut
regreset scratchpadOn : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s1_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_slaveValid, UInt<1>(0h0)
regreset s2_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_slaveValid, s1_slaveValid
reg s3_slaveValid : UInt<1>, clock
connect s3_slaveValid, UInt<1>(0h0)
node s0_valid = and(io.req.ready, io.req.valid)
regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg s1_vaddr : UInt<39>, clock
when s0_valid :
connect s1_vaddr, io.req.bits.addr
wire s1_tag_hit : UInt<1>[8]
node _s1_hit_T = or(s1_tag_hit[0], s1_tag_hit[1])
node _s1_hit_T_1 = or(_s1_hit_T, s1_tag_hit[2])
node _s1_hit_T_2 = or(_s1_hit_T_1, s1_tag_hit[3])
node _s1_hit_T_3 = or(_s1_hit_T_2, s1_tag_hit[4])
node _s1_hit_T_4 = or(_s1_hit_T_3, s1_tag_hit[5])
node _s1_hit_T_5 = or(_s1_hit_T_4, s1_tag_hit[6])
node _s1_hit_T_6 = or(_s1_hit_T_5, s1_tag_hit[7])
node _s1_hit_T_7 = mux(s1_slaveValid, UInt<1>(0h1), UInt<1>(0h0))
node s1_hit = or(_s1_hit_T_6, _s1_hit_T_7)
node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid, _s2_valid_T)
regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_valid, _s2_valid_T_1
reg s2_hit : UInt<1>, clock
connect s2_hit, s1_hit
reg invalidated : UInt<1>, clock
regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0)
regreset send_hint : UInt<1>, clock, reset, UInt<1>(0h0)
node _refill_fire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid)
node _refill_fire_T_1 = eq(send_hint, UInt<1>(0h0))
node refill_fire = and(_refill_fire_T, _refill_fire_T_1)
regreset hint_outstanding : UInt<1>, clock, reset, UInt<1>(0h0)
node _s2_miss_T = eq(s2_hit, UInt<1>(0h0))
node _s2_miss_T_1 = and(s2_valid, _s2_miss_T)
node _s2_miss_T_2 = eq(io.s2_kill, UInt<1>(0h0))
node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2)
node _s1_can_request_refill_T = or(s2_miss, refill_valid)
node s1_can_request_refill = eq(_s1_can_request_refill_T, UInt<1>(0h0))
reg s2_request_refill_REG : UInt<1>, clock
connect s2_request_refill_REG, s1_can_request_refill
node s2_request_refill = and(s2_miss, s2_request_refill_REG)
node _refill_paddr_T = and(s1_valid, s1_can_request_refill)
reg refill_paddr : UInt<32>, clock
when _refill_paddr_T :
connect refill_paddr, io.s1_paddr
node _refill_vaddr_T = and(s1_valid, s1_can_request_refill)
reg refill_vaddr : UInt<39>, clock
when _refill_vaddr_T :
connect refill_vaddr, s1_vaddr
node refill_tag = shr(refill_paddr, 12)
node refill_idx = bits(refill_paddr, 11, 6)
node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid)
node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0)
node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata)
node _io_req_ready_T = or(refill_one_beat, UInt<1>(0h0))
node _io_req_ready_T_1 = or(_io_req_ready_T, s3_slaveValid)
node _io_req_ready_T_2 = eq(_io_req_ready_T_1, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T_2
connect s1_valid, s0_valid
node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 4)
node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node d_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node refill_cnt = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_done = and(refill_one_beat, d_done)
node _masterNodeOut_d_ready_T = eq(s3_slaveValid, UInt<1>(0h0))
connect masterNodeOut.d.ready, _masterNodeOut_d_ready_T
inst repl_way_v0_prng of MaxPeriodFibonacciLFSR_5
connect repl_way_v0_prng.clock, clock
connect repl_way_v0_prng.reset, reset
connect repl_way_v0_prng.io.seed.valid, UInt<1>(0h0)
invalidate repl_way_v0_prng.io.seed.bits[0]
invalidate repl_way_v0_prng.io.seed.bits[1]
invalidate repl_way_v0_prng.io.seed.bits[2]
invalidate repl_way_v0_prng.io.seed.bits[3]
invalidate repl_way_v0_prng.io.seed.bits[4]
invalidate repl_way_v0_prng.io.seed.bits[5]
invalidate repl_way_v0_prng.io.seed.bits[6]
invalidate repl_way_v0_prng.io.seed.bits[7]
invalidate repl_way_v0_prng.io.seed.bits[8]
invalidate repl_way_v0_prng.io.seed.bits[9]
invalidate repl_way_v0_prng.io.seed.bits[10]
invalidate repl_way_v0_prng.io.seed.bits[11]
invalidate repl_way_v0_prng.io.seed.bits[12]
invalidate repl_way_v0_prng.io.seed.bits[13]
invalidate repl_way_v0_prng.io.seed.bits[14]
invalidate repl_way_v0_prng.io.seed.bits[15]
connect repl_way_v0_prng.io.increment, refill_fire
node repl_way_v0_lo_lo_lo = cat(repl_way_v0_prng.io.out[1], repl_way_v0_prng.io.out[0])
node repl_way_v0_lo_lo_hi = cat(repl_way_v0_prng.io.out[3], repl_way_v0_prng.io.out[2])
node repl_way_v0_lo_lo = cat(repl_way_v0_lo_lo_hi, repl_way_v0_lo_lo_lo)
node repl_way_v0_lo_hi_lo = cat(repl_way_v0_prng.io.out[5], repl_way_v0_prng.io.out[4])
node repl_way_v0_lo_hi_hi = cat(repl_way_v0_prng.io.out[7], repl_way_v0_prng.io.out[6])
node repl_way_v0_lo_hi = cat(repl_way_v0_lo_hi_hi, repl_way_v0_lo_hi_lo)
node repl_way_v0_lo = cat(repl_way_v0_lo_hi, repl_way_v0_lo_lo)
node repl_way_v0_hi_lo_lo = cat(repl_way_v0_prng.io.out[9], repl_way_v0_prng.io.out[8])
node repl_way_v0_hi_lo_hi = cat(repl_way_v0_prng.io.out[11], repl_way_v0_prng.io.out[10])
node repl_way_v0_hi_lo = cat(repl_way_v0_hi_lo_hi, repl_way_v0_hi_lo_lo)
node repl_way_v0_hi_hi_lo = cat(repl_way_v0_prng.io.out[13], repl_way_v0_prng.io.out[12])
node repl_way_v0_hi_hi_hi = cat(repl_way_v0_prng.io.out[15], repl_way_v0_prng.io.out[14])
node repl_way_v0_hi_hi = cat(repl_way_v0_hi_hi_hi, repl_way_v0_hi_hi_lo)
node repl_way_v0_hi = cat(repl_way_v0_hi_hi, repl_way_v0_hi_lo)
node _repl_way_v0_T = cat(repl_way_v0_hi, repl_way_v0_lo)
node repl_way_v0 = bits(_repl_way_v0_T, 2, 0)
node _repl_way_T = or(repl_way_v0, UInt<1>(0h0))
node _repl_way_T_1 = cat(_repl_way_T, refill_idx)
node _repl_way_T_2 = shl(UInt<1>(0h0), 2)
node _repl_way_T_3 = or(repl_way_v0, _repl_way_T_2)
node _repl_way_T_4 = or(repl_way_v0, UInt<3>(0h4))
node _repl_way_T_5 = cat(_repl_way_T_4, refill_idx)
node _repl_way_T_6 = shl(UInt<1>(0h0), 1)
node _repl_way_T_7 = or(_repl_way_T_3, _repl_way_T_6)
node _repl_way_T_8 = or(repl_way_v0, UInt<3>(0h6))
node _repl_way_T_9 = cat(_repl_way_T_8, refill_idx)
node _repl_way_T_10 = shl(UInt<1>(0h0), 0)
node repl_way = or(_repl_way_T_7, _repl_way_T_10)
node _repl_way_T_11 = cat(repl_way, refill_idx)
node _repl_way_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _repl_way_T_13 = asUInt(reset)
node _repl_way_T_14 = eq(_repl_way_T_13, UInt<1>(0h0))
when _repl_way_T_14 :
node _repl_way_T_15 = eq(_repl_way_T_12, UInt<1>(0h0))
when _repl_way_T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:413 assert(!lineInScratchpad(Cat(v, refill_idx)))\n") : repl_way_printf
assert(clock, _repl_way_T_12, UInt<1>(0h1), "") : repl_way_assert
smem rockettile_icache_tag_array : UInt<21>[8] [64]
node _tag_rdata_T = bits(io.req.bits.addr, 11, 6)
node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0))
node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid)
wire _tag_rdata_WIRE : UInt<6>
invalidate _tag_rdata_WIRE
when _tag_rdata_T_2 :
connect _tag_rdata_WIRE, _tag_rdata_T
read mport tag_rdata = rockettile_icache_tag_array[_tag_rdata_WIRE], clock
reg accruedRefillError : UInt<1>, clock
node _refillError_T = gt(refill_cnt, UInt<1>(0h0))
node _refillError_T_1 = and(_refillError_T, accruedRefillError)
node refillError = or(masterNodeOut.d.bits.corrupt, _refillError_T_1)
when refill_done :
node enc_tag = cat(refillError, refill_tag)
wire _WIRE : UInt<21>[8]
connect _WIRE[0], enc_tag
connect _WIRE[1], enc_tag
connect _WIRE[2], enc_tag
connect _WIRE[3], enc_tag
connect _WIRE[4], enc_tag
connect _WIRE[5], enc_tag
connect _WIRE[6], enc_tag
connect _WIRE[7], enc_tag
node _T_1 = eq(repl_way, UInt<1>(0h0))
node _T_2 = eq(repl_way, UInt<1>(0h1))
node _T_3 = eq(repl_way, UInt<2>(0h2))
node _T_4 = eq(repl_way, UInt<2>(0h3))
node _T_5 = eq(repl_way, UInt<3>(0h4))
node _T_6 = eq(repl_way, UInt<3>(0h5))
node _T_7 = eq(repl_way, UInt<3>(0h6))
node _T_8 = eq(repl_way, UInt<3>(0h7))
write mport MPORT = rockettile_icache_tag_array[refill_idx], clock
when _T_1 :
connect MPORT[0], _WIRE[0]
when _T_2 :
connect MPORT[1], _WIRE[1]
when _T_3 :
connect MPORT[2], _WIRE[2]
when _T_4 :
connect MPORT[3], _WIRE[3]
when _T_5 :
connect MPORT[4], _WIRE[4]
when _T_6 :
connect MPORT[5], _WIRE[5]
when _T_7 :
connect MPORT[6], _WIRE[6]
when _T_8 :
connect MPORT[7], _WIRE[7]
node _io_errors_bus_valid_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid)
node _io_errors_bus_valid_T_1 = or(masterNodeOut.d.bits.denied, masterNodeOut.d.bits.corrupt)
node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1)
connect io.errors.bus.valid, _io_errors_bus_valid_T_2
node _io_errors_bus_bits_T = shr(refill_paddr, 6)
node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6)
connect io.errors.bus.bits, _io_errors_bus_bits_T_1
regreset vb_array : UInt<512>, clock, reset, UInt<512>(0h0)
when refill_one_beat :
connect accruedRefillError, refillError
node _vb_array_T = cat(repl_way, refill_idx)
node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0))
node _vb_array_T_2 = and(refill_done, _vb_array_T_1)
node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T)
node _vb_array_T_4 = or(vb_array, _vb_array_T_3)
node _vb_array_T_5 = not(vb_array)
node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3)
node _vb_array_T_7 = not(_vb_array_T_6)
node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7)
connect vb_array, _vb_array_T_8
wire invalidate : UInt<1>
connect invalidate, io.invalidate
when invalidate :
connect vb_array, UInt<1>(0h0)
connect invalidated, UInt<1>(0h1)
wire s1_tag_disparity : UInt<1>[8]
wire s1_tl_error : UInt<1>[8]
wire s1_dout : UInt<32>[8]
invalidate s1_dout[0]
invalidate s1_dout[1]
invalidate s1_dout[2]
invalidate s1_dout[3]
invalidate s1_dout[4]
invalidate s1_dout[5]
invalidate s1_dout[6]
invalidate s1_dout[7]
reg s1s3_slaveAddr : UInt<15>, clock
reg s1s3_slaveData : UInt<32>, clock
node s1_idx = bits(io.s1_paddr, 11, 6)
node s1_tag = shr(io.s1_paddr, 12)
node _scratchpadHit_T = lt(UInt<1>(0h0), UInt<3>(0h7))
node _scratchpadHit_T_1 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_2 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_3 = eq(_scratchpadHit_T_2, UInt<1>(0h0))
node _scratchpadHit_T_4 = and(UInt<1>(0h0), _scratchpadHit_T_3)
node _scratchpadHit_T_5 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_6 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_7 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_8 = eq(_scratchpadHit_T_7, UInt<1>(0h0))
node _scratchpadHit_T_9 = and(_scratchpadHit_T_6, _scratchpadHit_T_8)
node _scratchpadHit_T_10 = mux(s1_slaveValid, _scratchpadHit_T_4, _scratchpadHit_T_9)
node scratchpadHit = and(_scratchpadHit_T, _scratchpadHit_T_10)
node _s1_vb_T = cat(UInt<1>(0h0), s1_idx)
node _s1_vb_T_1 = pad(_s1_vb_T, 9)
node _s1_vb_T_2 = dshr(vb_array, _s1_vb_T_1)
node _s1_vb_T_3 = bits(_s1_vb_T_2, 0, 0)
node _s1_vb_T_4 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb = and(_s1_vb_T_3, _s1_vb_T_4)
node tl_error = bits(tag_rdata[0], 20, 20)
node tag = bits(tag_rdata[0], 19, 0)
node _tagMatch_T = eq(tag, s1_tag)
node tagMatch = and(s1_vb, _tagMatch_T)
node _s1_tag_disparity_0_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_0_T_1 = and(s1_vb, _s1_tag_disparity_0_T)
connect s1_tag_disparity[0], _s1_tag_disparity_0_T_1
node _s1_tl_error_0_T = bits(tl_error, 0, 0)
node _s1_tl_error_0_T_1 = and(tagMatch, _s1_tl_error_0_T)
connect s1_tl_error[0], _s1_tl_error_0_T_1
node _s1_tag_hit_0_T = or(tagMatch, scratchpadHit)
connect s1_tag_hit[0], _s1_tag_hit_0_T
node s1_idx_1 = bits(io.s1_paddr, 11, 6)
node s1_tag_1 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_11 = lt(UInt<1>(0h1), UInt<3>(0h7))
node _scratchpadHit_T_12 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_13 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_14 = eq(_scratchpadHit_T_13, UInt<1>(0h1))
node _scratchpadHit_T_15 = and(UInt<1>(0h0), _scratchpadHit_T_14)
node _scratchpadHit_T_16 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_17 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_18 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_19 = eq(_scratchpadHit_T_18, UInt<1>(0h1))
node _scratchpadHit_T_20 = and(_scratchpadHit_T_17, _scratchpadHit_T_19)
node _scratchpadHit_T_21 = mux(s1_slaveValid, _scratchpadHit_T_15, _scratchpadHit_T_20)
node scratchpadHit_1 = and(_scratchpadHit_T_11, _scratchpadHit_T_21)
node _s1_vb_T_5 = cat(UInt<1>(0h1), s1_idx_1)
node _s1_vb_T_6 = pad(_s1_vb_T_5, 9)
node _s1_vb_T_7 = dshr(vb_array, _s1_vb_T_6)
node _s1_vb_T_8 = bits(_s1_vb_T_7, 0, 0)
node _s1_vb_T_9 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_1 = and(_s1_vb_T_8, _s1_vb_T_9)
node tl_error_1 = bits(tag_rdata[1], 20, 20)
node tag_1 = bits(tag_rdata[1], 19, 0)
node _tagMatch_T_1 = eq(tag_1, s1_tag_1)
node tagMatch_1 = and(s1_vb_1, _tagMatch_T_1)
node _s1_tag_disparity_1_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_1_T_1 = and(s1_vb_1, _s1_tag_disparity_1_T)
connect s1_tag_disparity[1], _s1_tag_disparity_1_T_1
node _s1_tl_error_1_T = bits(tl_error_1, 0, 0)
node _s1_tl_error_1_T_1 = and(tagMatch_1, _s1_tl_error_1_T)
connect s1_tl_error[1], _s1_tl_error_1_T_1
node _s1_tag_hit_1_T = or(tagMatch_1, scratchpadHit_1)
connect s1_tag_hit[1], _s1_tag_hit_1_T
node s1_idx_2 = bits(io.s1_paddr, 11, 6)
node s1_tag_2 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_22 = lt(UInt<2>(0h2), UInt<3>(0h7))
node _scratchpadHit_T_23 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_24 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_25 = eq(_scratchpadHit_T_24, UInt<2>(0h2))
node _scratchpadHit_T_26 = and(UInt<1>(0h0), _scratchpadHit_T_25)
node _scratchpadHit_T_27 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_28 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_29 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_30 = eq(_scratchpadHit_T_29, UInt<2>(0h2))
node _scratchpadHit_T_31 = and(_scratchpadHit_T_28, _scratchpadHit_T_30)
node _scratchpadHit_T_32 = mux(s1_slaveValid, _scratchpadHit_T_26, _scratchpadHit_T_31)
node scratchpadHit_2 = and(_scratchpadHit_T_22, _scratchpadHit_T_32)
node _s1_vb_T_10 = cat(UInt<2>(0h2), s1_idx_2)
node _s1_vb_T_11 = pad(_s1_vb_T_10, 9)
node _s1_vb_T_12 = dshr(vb_array, _s1_vb_T_11)
node _s1_vb_T_13 = bits(_s1_vb_T_12, 0, 0)
node _s1_vb_T_14 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_2 = and(_s1_vb_T_13, _s1_vb_T_14)
node tl_error_2 = bits(tag_rdata[2], 20, 20)
node tag_2 = bits(tag_rdata[2], 19, 0)
node _tagMatch_T_2 = eq(tag_2, s1_tag_2)
node tagMatch_2 = and(s1_vb_2, _tagMatch_T_2)
node _s1_tag_disparity_2_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_2_T_1 = and(s1_vb_2, _s1_tag_disparity_2_T)
connect s1_tag_disparity[2], _s1_tag_disparity_2_T_1
node _s1_tl_error_2_T = bits(tl_error_2, 0, 0)
node _s1_tl_error_2_T_1 = and(tagMatch_2, _s1_tl_error_2_T)
connect s1_tl_error[2], _s1_tl_error_2_T_1
node _s1_tag_hit_2_T = or(tagMatch_2, scratchpadHit_2)
connect s1_tag_hit[2], _s1_tag_hit_2_T
node s1_idx_3 = bits(io.s1_paddr, 11, 6)
node s1_tag_3 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_33 = lt(UInt<2>(0h3), UInt<3>(0h7))
node _scratchpadHit_T_34 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_35 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_36 = eq(_scratchpadHit_T_35, UInt<2>(0h3))
node _scratchpadHit_T_37 = and(UInt<1>(0h0), _scratchpadHit_T_36)
node _scratchpadHit_T_38 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_39 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_40 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_41 = eq(_scratchpadHit_T_40, UInt<2>(0h3))
node _scratchpadHit_T_42 = and(_scratchpadHit_T_39, _scratchpadHit_T_41)
node _scratchpadHit_T_43 = mux(s1_slaveValid, _scratchpadHit_T_37, _scratchpadHit_T_42)
node scratchpadHit_3 = and(_scratchpadHit_T_33, _scratchpadHit_T_43)
node _s1_vb_T_15 = cat(UInt<2>(0h3), s1_idx_3)
node _s1_vb_T_16 = pad(_s1_vb_T_15, 9)
node _s1_vb_T_17 = dshr(vb_array, _s1_vb_T_16)
node _s1_vb_T_18 = bits(_s1_vb_T_17, 0, 0)
node _s1_vb_T_19 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_3 = and(_s1_vb_T_18, _s1_vb_T_19)
node tl_error_3 = bits(tag_rdata[3], 20, 20)
node tag_3 = bits(tag_rdata[3], 19, 0)
node _tagMatch_T_3 = eq(tag_3, s1_tag_3)
node tagMatch_3 = and(s1_vb_3, _tagMatch_T_3)
node _s1_tag_disparity_3_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_3_T_1 = and(s1_vb_3, _s1_tag_disparity_3_T)
connect s1_tag_disparity[3], _s1_tag_disparity_3_T_1
node _s1_tl_error_3_T = bits(tl_error_3, 0, 0)
node _s1_tl_error_3_T_1 = and(tagMatch_3, _s1_tl_error_3_T)
connect s1_tl_error[3], _s1_tl_error_3_T_1
node _s1_tag_hit_3_T = or(tagMatch_3, scratchpadHit_3)
connect s1_tag_hit[3], _s1_tag_hit_3_T
node s1_idx_4 = bits(io.s1_paddr, 11, 6)
node s1_tag_4 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_44 = lt(UInt<3>(0h4), UInt<3>(0h7))
node _scratchpadHit_T_45 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_46 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_47 = eq(_scratchpadHit_T_46, UInt<3>(0h4))
node _scratchpadHit_T_48 = and(UInt<1>(0h0), _scratchpadHit_T_47)
node _scratchpadHit_T_49 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_50 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_51 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_52 = eq(_scratchpadHit_T_51, UInt<3>(0h4))
node _scratchpadHit_T_53 = and(_scratchpadHit_T_50, _scratchpadHit_T_52)
node _scratchpadHit_T_54 = mux(s1_slaveValid, _scratchpadHit_T_48, _scratchpadHit_T_53)
node scratchpadHit_4 = and(_scratchpadHit_T_44, _scratchpadHit_T_54)
node _s1_vb_T_20 = cat(UInt<3>(0h4), s1_idx_4)
node _s1_vb_T_21 = dshr(vb_array, _s1_vb_T_20)
node _s1_vb_T_22 = bits(_s1_vb_T_21, 0, 0)
node _s1_vb_T_23 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_4 = and(_s1_vb_T_22, _s1_vb_T_23)
node tl_error_4 = bits(tag_rdata[4], 20, 20)
node tag_4 = bits(tag_rdata[4], 19, 0)
node _tagMatch_T_4 = eq(tag_4, s1_tag_4)
node tagMatch_4 = and(s1_vb_4, _tagMatch_T_4)
node _s1_tag_disparity_4_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_4_T_1 = and(s1_vb_4, _s1_tag_disparity_4_T)
connect s1_tag_disparity[4], _s1_tag_disparity_4_T_1
node _s1_tl_error_4_T = bits(tl_error_4, 0, 0)
node _s1_tl_error_4_T_1 = and(tagMatch_4, _s1_tl_error_4_T)
connect s1_tl_error[4], _s1_tl_error_4_T_1
node _s1_tag_hit_4_T = or(tagMatch_4, scratchpadHit_4)
connect s1_tag_hit[4], _s1_tag_hit_4_T
node s1_idx_5 = bits(io.s1_paddr, 11, 6)
node s1_tag_5 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_55 = lt(UInt<3>(0h5), UInt<3>(0h7))
node _scratchpadHit_T_56 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_57 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_58 = eq(_scratchpadHit_T_57, UInt<3>(0h5))
node _scratchpadHit_T_59 = and(UInt<1>(0h0), _scratchpadHit_T_58)
node _scratchpadHit_T_60 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_61 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_62 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_63 = eq(_scratchpadHit_T_62, UInt<3>(0h5))
node _scratchpadHit_T_64 = and(_scratchpadHit_T_61, _scratchpadHit_T_63)
node _scratchpadHit_T_65 = mux(s1_slaveValid, _scratchpadHit_T_59, _scratchpadHit_T_64)
node scratchpadHit_5 = and(_scratchpadHit_T_55, _scratchpadHit_T_65)
node _s1_vb_T_24 = cat(UInt<3>(0h5), s1_idx_5)
node _s1_vb_T_25 = dshr(vb_array, _s1_vb_T_24)
node _s1_vb_T_26 = bits(_s1_vb_T_25, 0, 0)
node _s1_vb_T_27 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_5 = and(_s1_vb_T_26, _s1_vb_T_27)
node tl_error_5 = bits(tag_rdata[5], 20, 20)
node tag_5 = bits(tag_rdata[5], 19, 0)
node _tagMatch_T_5 = eq(tag_5, s1_tag_5)
node tagMatch_5 = and(s1_vb_5, _tagMatch_T_5)
node _s1_tag_disparity_5_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_5_T_1 = and(s1_vb_5, _s1_tag_disparity_5_T)
connect s1_tag_disparity[5], _s1_tag_disparity_5_T_1
node _s1_tl_error_5_T = bits(tl_error_5, 0, 0)
node _s1_tl_error_5_T_1 = and(tagMatch_5, _s1_tl_error_5_T)
connect s1_tl_error[5], _s1_tl_error_5_T_1
node _s1_tag_hit_5_T = or(tagMatch_5, scratchpadHit_5)
connect s1_tag_hit[5], _s1_tag_hit_5_T
node s1_idx_6 = bits(io.s1_paddr, 11, 6)
node s1_tag_6 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_66 = lt(UInt<3>(0h6), UInt<3>(0h7))
node _scratchpadHit_T_67 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_68 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_69 = eq(_scratchpadHit_T_68, UInt<3>(0h6))
node _scratchpadHit_T_70 = and(UInt<1>(0h0), _scratchpadHit_T_69)
node _scratchpadHit_T_71 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_72 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_73 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_74 = eq(_scratchpadHit_T_73, UInt<3>(0h6))
node _scratchpadHit_T_75 = and(_scratchpadHit_T_72, _scratchpadHit_T_74)
node _scratchpadHit_T_76 = mux(s1_slaveValid, _scratchpadHit_T_70, _scratchpadHit_T_75)
node scratchpadHit_6 = and(_scratchpadHit_T_66, _scratchpadHit_T_76)
node _s1_vb_T_28 = cat(UInt<3>(0h6), s1_idx_6)
node _s1_vb_T_29 = dshr(vb_array, _s1_vb_T_28)
node _s1_vb_T_30 = bits(_s1_vb_T_29, 0, 0)
node _s1_vb_T_31 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_6 = and(_s1_vb_T_30, _s1_vb_T_31)
node tl_error_6 = bits(tag_rdata[6], 20, 20)
node tag_6 = bits(tag_rdata[6], 19, 0)
node _tagMatch_T_6 = eq(tag_6, s1_tag_6)
node tagMatch_6 = and(s1_vb_6, _tagMatch_T_6)
node _s1_tag_disparity_6_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_6_T_1 = and(s1_vb_6, _s1_tag_disparity_6_T)
connect s1_tag_disparity[6], _s1_tag_disparity_6_T_1
node _s1_tl_error_6_T = bits(tl_error_6, 0, 0)
node _s1_tl_error_6_T_1 = and(tagMatch_6, _s1_tl_error_6_T)
connect s1_tl_error[6], _s1_tl_error_6_T_1
node _s1_tag_hit_6_T = or(tagMatch_6, scratchpadHit_6)
connect s1_tag_hit[6], _s1_tag_hit_6_T
node s1_idx_7 = bits(io.s1_paddr, 11, 6)
node s1_tag_7 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_77 = lt(UInt<3>(0h7), UInt<3>(0h7))
node _scratchpadHit_T_78 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_79 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_80 = eq(_scratchpadHit_T_79, UInt<3>(0h7))
node _scratchpadHit_T_81 = and(UInt<1>(0h0), _scratchpadHit_T_80)
node _scratchpadHit_T_82 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_83 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_84 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_85 = eq(_scratchpadHit_T_84, UInt<3>(0h7))
node _scratchpadHit_T_86 = and(_scratchpadHit_T_83, _scratchpadHit_T_85)
node _scratchpadHit_T_87 = mux(s1_slaveValid, _scratchpadHit_T_81, _scratchpadHit_T_86)
node scratchpadHit_7 = and(_scratchpadHit_T_77, _scratchpadHit_T_87)
node _s1_vb_T_32 = cat(UInt<3>(0h7), s1_idx_7)
node _s1_vb_T_33 = dshr(vb_array, _s1_vb_T_32)
node _s1_vb_T_34 = bits(_s1_vb_T_33, 0, 0)
node _s1_vb_T_35 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_7 = and(_s1_vb_T_34, _s1_vb_T_35)
node tl_error_7 = bits(tag_rdata[7], 20, 20)
node tag_7 = bits(tag_rdata[7], 19, 0)
node _tagMatch_T_7 = eq(tag_7, s1_tag_7)
node tagMatch_7 = and(s1_vb_7, _tagMatch_T_7)
node _s1_tag_disparity_7_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_7_T_1 = and(s1_vb_7, _s1_tag_disparity_7_T)
connect s1_tag_disparity[7], _s1_tag_disparity_7_T_1
node _s1_tl_error_7_T = bits(tl_error_7, 0, 0)
node _s1_tl_error_7_T_1 = and(tagMatch_7, _s1_tl_error_7_T)
connect s1_tl_error[7], _s1_tl_error_7_T_1
node _s1_tag_hit_7_T = or(tagMatch_7, scratchpadHit_7)
connect s1_tag_hit[7], _s1_tag_hit_7_T
node _T_9 = or(s1_valid, s1_slaveValid)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = eq(s1_tag_disparity[0], UInt<1>(0h0))
node _T_12 = and(s1_tag_hit[0], _T_11)
node _T_13 = eq(s1_tag_disparity[1], UInt<1>(0h0))
node _T_14 = and(s1_tag_hit[1], _T_13)
node _T_15 = eq(s1_tag_disparity[2], UInt<1>(0h0))
node _T_16 = and(s1_tag_hit[2], _T_15)
node _T_17 = eq(s1_tag_disparity[3], UInt<1>(0h0))
node _T_18 = and(s1_tag_hit[3], _T_17)
node _T_19 = eq(s1_tag_disparity[4], UInt<1>(0h0))
node _T_20 = and(s1_tag_hit[4], _T_19)
node _T_21 = eq(s1_tag_disparity[5], UInt<1>(0h0))
node _T_22 = and(s1_tag_hit[5], _T_21)
node _T_23 = eq(s1_tag_disparity[6], UInt<1>(0h0))
node _T_24 = and(s1_tag_hit[6], _T_23)
node _T_25 = eq(s1_tag_disparity[7], UInt<1>(0h0))
node _T_26 = and(s1_tag_hit[7], _T_25)
node _T_27 = add(_T_12, _T_14)
node _T_28 = bits(_T_27, 1, 0)
node _T_29 = add(_T_16, _T_18)
node _T_30 = bits(_T_29, 1, 0)
node _T_31 = add(_T_28, _T_30)
node _T_32 = bits(_T_31, 2, 0)
node _T_33 = add(_T_20, _T_22)
node _T_34 = bits(_T_33, 1, 0)
node _T_35 = add(_T_24, _T_26)
node _T_36 = bits(_T_35, 1, 0)
node _T_37 = add(_T_34, _T_36)
node _T_38 = bits(_T_37, 2, 0)
node _T_39 = add(_T_32, _T_38)
node _T_40 = bits(_T_39, 3, 0)
node _T_41 = leq(_T_40, UInt<1>(0h1))
node _T_42 = or(_T_10, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:521 assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U)\n") : printf
assert(clock, _T_42, UInt<1>(0h1), "") : assert
smem rockettile_icache_data_arrays_0 : UInt<32>[8] [256]
smem rockettile_icache_data_arrays_1 : UInt<32>[8] [256]
smem rockettile_icache_data_arrays_2 : UInt<32>[8] [256]
smem rockettile_icache_data_arrays_3 : UInt<32>[8] [256]
node _s0_ren_T = bits(io.req.bits.addr, 3, 2)
node _s0_ren_T_1 = eq(_s0_ren_T, UInt<1>(0h0))
node _s0_ren_T_2 = and(s0_valid, _s0_ren_T_1)
node _s0_ren_T_3 = eq(UInt<2>(0h0), UInt<1>(0h0))
node _s0_ren_T_4 = and(UInt<1>(0h0), _s0_ren_T_3)
node s0_ren = or(_s0_ren_T_2, _s0_ren_T_4)
node _wen_T = eq(invalidated, UInt<1>(0h0))
node _wen_T_1 = and(refill_one_beat, _wen_T)
node _wen_T_2 = bits(s1s3_slaveAddr, 3, 2)
node _wen_T_3 = eq(_wen_T_2, UInt<1>(0h0))
node _wen_T_4 = and(s3_slaveValid, _wen_T_3)
node wen = or(_wen_T_1, _wen_T_4)
node _mem_idx_T = shl(refill_idx, 2)
node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt)
node _mem_idx_T_2 = bits(s1s3_slaveAddr, 11, 4)
node _mem_idx_T_3 = bits(io.req.bits.addr, 11, 4)
node _mem_idx_T_4 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_3)
node _mem_idx_T_5 = mux(s3_slaveValid, _mem_idx_T_2, _mem_idx_T_4)
node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_5)
when wen :
node _data_T = bits(masterNodeOut.d.bits.data, 31, 0)
node data = mux(s3_slaveValid, s1s3_slaveData, _data_T)
node _way_T = bits(s1s3_slaveAddr, 14, 12)
node way = mux(s3_slaveValid, _way_T, repl_way)
wire _WIRE_1 : UInt<32>[8]
connect _WIRE_1[0], data
connect _WIRE_1[1], data
connect _WIRE_1[2], data
connect _WIRE_1[3], data
connect _WIRE_1[4], data
connect _WIRE_1[5], data
connect _WIRE_1[6], data
connect _WIRE_1[7], data
node _T_46 = eq(way, UInt<1>(0h0))
node _T_47 = eq(way, UInt<1>(0h1))
node _T_48 = eq(way, UInt<2>(0h2))
node _T_49 = eq(way, UInt<2>(0h3))
node _T_50 = eq(way, UInt<3>(0h4))
node _T_51 = eq(way, UInt<3>(0h5))
node _T_52 = eq(way, UInt<3>(0h6))
node _T_53 = eq(way, UInt<3>(0h7))
write mport MPORT_1 = rockettile_icache_data_arrays_0[mem_idx], clock
when _T_46 :
connect MPORT_1[0], _WIRE_1[0]
when _T_47 :
connect MPORT_1[1], _WIRE_1[1]
when _T_48 :
connect MPORT_1[2], _WIRE_1[2]
when _T_49 :
connect MPORT_1[3], _WIRE_1[3]
when _T_50 :
connect MPORT_1[4], _WIRE_1[4]
when _T_51 :
connect MPORT_1[5], _WIRE_1[5]
when _T_52 :
connect MPORT_1[6], _WIRE_1[6]
when _T_53 :
connect MPORT_1[7], _WIRE_1[7]
node _dout_T = eq(wen, UInt<1>(0h0))
node _dout_T_1 = and(_dout_T, s0_ren)
wire _dout_WIRE : UInt<8>
invalidate _dout_WIRE
when _dout_T_1 :
connect _dout_WIRE, mem_idx
read mport dout = rockettile_icache_data_arrays_0[_dout_WIRE], clock
node _T_54 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr)
node _T_55 = bits(_T_54, 3, 2)
node _T_56 = eq(_T_55, UInt<1>(0h0))
when _T_56 :
connect s1_dout, dout
node _s0_ren_T_5 = bits(io.req.bits.addr, 3, 2)
node _s0_ren_T_6 = eq(_s0_ren_T_5, UInt<1>(0h1))
node _s0_ren_T_7 = and(s0_valid, _s0_ren_T_6)
node _s0_ren_T_8 = eq(UInt<2>(0h0), UInt<1>(0h1))
node _s0_ren_T_9 = and(UInt<1>(0h0), _s0_ren_T_8)
node s0_ren_1 = or(_s0_ren_T_7, _s0_ren_T_9)
node _wen_T_5 = eq(invalidated, UInt<1>(0h0))
node _wen_T_6 = and(refill_one_beat, _wen_T_5)
node _wen_T_7 = bits(s1s3_slaveAddr, 3, 2)
node _wen_T_8 = eq(_wen_T_7, UInt<1>(0h1))
node _wen_T_9 = and(s3_slaveValid, _wen_T_8)
node wen_1 = or(_wen_T_6, _wen_T_9)
node _mem_idx_T_6 = shl(refill_idx, 2)
node _mem_idx_T_7 = or(_mem_idx_T_6, refill_cnt)
node _mem_idx_T_8 = bits(s1s3_slaveAddr, 11, 4)
node _mem_idx_T_9 = bits(io.req.bits.addr, 11, 4)
node _mem_idx_T_10 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_9)
node _mem_idx_T_11 = mux(s3_slaveValid, _mem_idx_T_8, _mem_idx_T_10)
node mem_idx_1 = mux(refill_one_beat, _mem_idx_T_7, _mem_idx_T_11)
when wen_1 :
node _data_T_1 = bits(masterNodeOut.d.bits.data, 63, 32)
node data_1 = mux(s3_slaveValid, s1s3_slaveData, _data_T_1)
node _way_T_1 = bits(s1s3_slaveAddr, 14, 12)
node way_1 = mux(s3_slaveValid, _way_T_1, repl_way)
wire _WIRE_2 : UInt<32>[8]
connect _WIRE_2[0], data_1
connect _WIRE_2[1], data_1
connect _WIRE_2[2], data_1
connect _WIRE_2[3], data_1
connect _WIRE_2[4], data_1
connect _WIRE_2[5], data_1
connect _WIRE_2[6], data_1
connect _WIRE_2[7], data_1
node _T_57 = eq(way_1, UInt<1>(0h0))
node _T_58 = eq(way_1, UInt<1>(0h1))
node _T_59 = eq(way_1, UInt<2>(0h2))
node _T_60 = eq(way_1, UInt<2>(0h3))
node _T_61 = eq(way_1, UInt<3>(0h4))
node _T_62 = eq(way_1, UInt<3>(0h5))
node _T_63 = eq(way_1, UInt<3>(0h6))
node _T_64 = eq(way_1, UInt<3>(0h7))
write mport MPORT_2 = rockettile_icache_data_arrays_1[mem_idx_1], clock
when _T_57 :
connect MPORT_2[0], _WIRE_2[0]
when _T_58 :
connect MPORT_2[1], _WIRE_2[1]
when _T_59 :
connect MPORT_2[2], _WIRE_2[2]
when _T_60 :
connect MPORT_2[3], _WIRE_2[3]
when _T_61 :
connect MPORT_2[4], _WIRE_2[4]
when _T_62 :
connect MPORT_2[5], _WIRE_2[5]
when _T_63 :
connect MPORT_2[6], _WIRE_2[6]
when _T_64 :
connect MPORT_2[7], _WIRE_2[7]
node _dout_T_2 = eq(wen_1, UInt<1>(0h0))
node _dout_T_3 = and(_dout_T_2, s0_ren_1)
wire _dout_WIRE_1 : UInt<8>
invalidate _dout_WIRE_1
when _dout_T_3 :
connect _dout_WIRE_1, mem_idx_1
read mport dout_1 = rockettile_icache_data_arrays_1[_dout_WIRE_1], clock
node _T_65 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr)
node _T_66 = bits(_T_65, 3, 2)
node _T_67 = eq(_T_66, UInt<1>(0h1))
when _T_67 :
connect s1_dout, dout_1
node _s0_ren_T_10 = bits(io.req.bits.addr, 3, 2)
node _s0_ren_T_11 = eq(_s0_ren_T_10, UInt<2>(0h2))
node _s0_ren_T_12 = and(s0_valid, _s0_ren_T_11)
node _s0_ren_T_13 = eq(UInt<2>(0h0), UInt<2>(0h2))
node _s0_ren_T_14 = and(UInt<1>(0h0), _s0_ren_T_13)
node s0_ren_2 = or(_s0_ren_T_12, _s0_ren_T_14)
node _wen_T_10 = eq(invalidated, UInt<1>(0h0))
node _wen_T_11 = and(refill_one_beat, _wen_T_10)
node _wen_T_12 = bits(s1s3_slaveAddr, 3, 2)
node _wen_T_13 = eq(_wen_T_12, UInt<2>(0h2))
node _wen_T_14 = and(s3_slaveValid, _wen_T_13)
node wen_2 = or(_wen_T_11, _wen_T_14)
node _mem_idx_T_12 = shl(refill_idx, 2)
node _mem_idx_T_13 = or(_mem_idx_T_12, refill_cnt)
node _mem_idx_T_14 = bits(s1s3_slaveAddr, 11, 4)
node _mem_idx_T_15 = bits(io.req.bits.addr, 11, 4)
node _mem_idx_T_16 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_15)
node _mem_idx_T_17 = mux(s3_slaveValid, _mem_idx_T_14, _mem_idx_T_16)
node mem_idx_2 = mux(refill_one_beat, _mem_idx_T_13, _mem_idx_T_17)
when wen_2 :
node _data_T_2 = bits(masterNodeOut.d.bits.data, 95, 64)
node data_2 = mux(s3_slaveValid, s1s3_slaveData, _data_T_2)
node _way_T_2 = bits(s1s3_slaveAddr, 14, 12)
node way_2 = mux(s3_slaveValid, _way_T_2, repl_way)
wire _WIRE_3 : UInt<32>[8]
connect _WIRE_3[0], data_2
connect _WIRE_3[1], data_2
connect _WIRE_3[2], data_2
connect _WIRE_3[3], data_2
connect _WIRE_3[4], data_2
connect _WIRE_3[5], data_2
connect _WIRE_3[6], data_2
connect _WIRE_3[7], data_2
node _T_68 = eq(way_2, UInt<1>(0h0))
node _T_69 = eq(way_2, UInt<1>(0h1))
node _T_70 = eq(way_2, UInt<2>(0h2))
node _T_71 = eq(way_2, UInt<2>(0h3))
node _T_72 = eq(way_2, UInt<3>(0h4))
node _T_73 = eq(way_2, UInt<3>(0h5))
node _T_74 = eq(way_2, UInt<3>(0h6))
node _T_75 = eq(way_2, UInt<3>(0h7))
write mport MPORT_3 = rockettile_icache_data_arrays_2[mem_idx_2], clock
when _T_68 :
connect MPORT_3[0], _WIRE_3[0]
when _T_69 :
connect MPORT_3[1], _WIRE_3[1]
when _T_70 :
connect MPORT_3[2], _WIRE_3[2]
when _T_71 :
connect MPORT_3[3], _WIRE_3[3]
when _T_72 :
connect MPORT_3[4], _WIRE_3[4]
when _T_73 :
connect MPORT_3[5], _WIRE_3[5]
when _T_74 :
connect MPORT_3[6], _WIRE_3[6]
when _T_75 :
connect MPORT_3[7], _WIRE_3[7]
node _dout_T_4 = eq(wen_2, UInt<1>(0h0))
node _dout_T_5 = and(_dout_T_4, s0_ren_2)
wire _dout_WIRE_2 : UInt<8>
invalidate _dout_WIRE_2
when _dout_T_5 :
connect _dout_WIRE_2, mem_idx_2
read mport dout_2 = rockettile_icache_data_arrays_2[_dout_WIRE_2], clock
node _T_76 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr)
node _T_77 = bits(_T_76, 3, 2)
node _T_78 = eq(_T_77, UInt<2>(0h2))
when _T_78 :
connect s1_dout, dout_2
node _s0_ren_T_15 = bits(io.req.bits.addr, 3, 2)
node _s0_ren_T_16 = eq(_s0_ren_T_15, UInt<2>(0h3))
node _s0_ren_T_17 = and(s0_valid, _s0_ren_T_16)
node _s0_ren_T_18 = eq(UInt<2>(0h0), UInt<2>(0h3))
node _s0_ren_T_19 = and(UInt<1>(0h0), _s0_ren_T_18)
node s0_ren_3 = or(_s0_ren_T_17, _s0_ren_T_19)
node _wen_T_15 = eq(invalidated, UInt<1>(0h0))
node _wen_T_16 = and(refill_one_beat, _wen_T_15)
node _wen_T_17 = bits(s1s3_slaveAddr, 3, 2)
node _wen_T_18 = eq(_wen_T_17, UInt<2>(0h3))
node _wen_T_19 = and(s3_slaveValid, _wen_T_18)
node wen_3 = or(_wen_T_16, _wen_T_19)
node _mem_idx_T_18 = shl(refill_idx, 2)
node _mem_idx_T_19 = or(_mem_idx_T_18, refill_cnt)
node _mem_idx_T_20 = bits(s1s3_slaveAddr, 11, 4)
node _mem_idx_T_21 = bits(io.req.bits.addr, 11, 4)
node _mem_idx_T_22 = mux(UInt<1>(0h0), UInt<8>(0h0), _mem_idx_T_21)
node _mem_idx_T_23 = mux(s3_slaveValid, _mem_idx_T_20, _mem_idx_T_22)
node mem_idx_3 = mux(refill_one_beat, _mem_idx_T_19, _mem_idx_T_23)
when wen_3 :
node _data_T_3 = bits(masterNodeOut.d.bits.data, 127, 96)
node data_3 = mux(s3_slaveValid, s1s3_slaveData, _data_T_3)
node _way_T_3 = bits(s1s3_slaveAddr, 14, 12)
node way_3 = mux(s3_slaveValid, _way_T_3, repl_way)
wire _WIRE_4 : UInt<32>[8]
connect _WIRE_4[0], data_3
connect _WIRE_4[1], data_3
connect _WIRE_4[2], data_3
connect _WIRE_4[3], data_3
connect _WIRE_4[4], data_3
connect _WIRE_4[5], data_3
connect _WIRE_4[6], data_3
connect _WIRE_4[7], data_3
node _T_79 = eq(way_3, UInt<1>(0h0))
node _T_80 = eq(way_3, UInt<1>(0h1))
node _T_81 = eq(way_3, UInt<2>(0h2))
node _T_82 = eq(way_3, UInt<2>(0h3))
node _T_83 = eq(way_3, UInt<3>(0h4))
node _T_84 = eq(way_3, UInt<3>(0h5))
node _T_85 = eq(way_3, UInt<3>(0h6))
node _T_86 = eq(way_3, UInt<3>(0h7))
write mport MPORT_4 = rockettile_icache_data_arrays_3[mem_idx_3], clock
when _T_79 :
connect MPORT_4[0], _WIRE_4[0]
when _T_80 :
connect MPORT_4[1], _WIRE_4[1]
when _T_81 :
connect MPORT_4[2], _WIRE_4[2]
when _T_82 :
connect MPORT_4[3], _WIRE_4[3]
when _T_83 :
connect MPORT_4[4], _WIRE_4[4]
when _T_84 :
connect MPORT_4[5], _WIRE_4[5]
when _T_85 :
connect MPORT_4[6], _WIRE_4[6]
when _T_86 :
connect MPORT_4[7], _WIRE_4[7]
node _dout_T_6 = eq(wen_3, UInt<1>(0h0))
node _dout_T_7 = and(_dout_T_6, s0_ren_3)
wire _dout_WIRE_3 : UInt<8>
invalidate _dout_WIRE_3
when _dout_T_7 :
connect _dout_WIRE_3, mem_idx_3
read mport dout_3 = rockettile_icache_data_arrays_3[_dout_WIRE_3], clock
node _T_87 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr)
node _T_88 = bits(_T_87, 3, 2)
node _T_89 = eq(_T_88, UInt<2>(0h3))
when _T_89 :
connect s1_dout, dout_3
wire s1s2_full_word_write : UInt<1>
connect s1s2_full_word_write, UInt<1>(0h0)
node s1_dont_read = and(s1_slaveValid, s1s2_full_word_write)
node s1_clk_en = or(s1_valid, s1_slaveValid)
wire _s2_tag_hit_WIRE : UInt<1>[8]
connect _s2_tag_hit_WIRE[0], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[1], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[2], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[3], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[4], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[5], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[6], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[7], UInt<1>(0h0)
node _s2_tag_hit_T = mux(s1_dont_read, _s2_tag_hit_WIRE, s1_tag_hit)
reg s2_tag_hit : UInt<1>[8], clock
when s1_clk_en :
connect s2_tag_hit, _s2_tag_hit_T
node s2_hit_way_lo_lo = cat(s2_tag_hit[1], s2_tag_hit[0])
node s2_hit_way_lo_hi = cat(s2_tag_hit[3], s2_tag_hit[2])
node s2_hit_way_lo = cat(s2_hit_way_lo_hi, s2_hit_way_lo_lo)
node s2_hit_way_hi_lo = cat(s2_tag_hit[5], s2_tag_hit[4])
node s2_hit_way_hi_hi = cat(s2_tag_hit[7], s2_tag_hit[6])
node s2_hit_way_hi = cat(s2_hit_way_hi_hi, s2_hit_way_hi_lo)
node _s2_hit_way_T = cat(s2_hit_way_hi, s2_hit_way_lo)
node s2_hit_way_hi_1 = bits(_s2_hit_way_T, 7, 4)
node s2_hit_way_lo_1 = bits(_s2_hit_way_T, 3, 0)
node _s2_hit_way_T_1 = orr(s2_hit_way_hi_1)
node _s2_hit_way_T_2 = or(s2_hit_way_hi_1, s2_hit_way_lo_1)
node s2_hit_way_hi_2 = bits(_s2_hit_way_T_2, 3, 2)
node s2_hit_way_lo_2 = bits(_s2_hit_way_T_2, 1, 0)
node _s2_hit_way_T_3 = orr(s2_hit_way_hi_2)
node _s2_hit_way_T_4 = or(s2_hit_way_hi_2, s2_hit_way_lo_2)
node _s2_hit_way_T_5 = bits(_s2_hit_way_T_4, 1, 1)
node _s2_hit_way_T_6 = cat(_s2_hit_way_T_3, _s2_hit_way_T_5)
node s2_hit_way = cat(_s2_hit_way_T_1, _s2_hit_way_T_6)
node _s2_scratchpad_word_addr_T = mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)
node _s2_scratchpad_word_addr_T_1 = bits(_s2_scratchpad_word_addr_T, 11, 2)
node s2_scratchpad_word_addr_hi = cat(s2_hit_way, _s2_scratchpad_word_addr_T_1)
node s2_scratchpad_word_addr = cat(s2_scratchpad_word_addr_hi, UInt<2>(0h0))
reg s2_dout : UInt<32>[8], clock
when s1_clk_en :
connect s2_dout, s1_dout
node _s2_way_mux_T = mux(s2_tag_hit[0], s2_dout[0], UInt<1>(0h0))
node _s2_way_mux_T_1 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>(0h0))
node _s2_way_mux_T_2 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>(0h0))
node _s2_way_mux_T_3 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>(0h0))
node _s2_way_mux_T_4 = mux(s2_tag_hit[4], s2_dout[4], UInt<1>(0h0))
node _s2_way_mux_T_5 = mux(s2_tag_hit[5], s2_dout[5], UInt<1>(0h0))
node _s2_way_mux_T_6 = mux(s2_tag_hit[6], s2_dout[6], UInt<1>(0h0))
node _s2_way_mux_T_7 = mux(s2_tag_hit[7], s2_dout[7], UInt<1>(0h0))
node _s2_way_mux_T_8 = or(_s2_way_mux_T, _s2_way_mux_T_1)
node _s2_way_mux_T_9 = or(_s2_way_mux_T_8, _s2_way_mux_T_2)
node _s2_way_mux_T_10 = or(_s2_way_mux_T_9, _s2_way_mux_T_3)
node _s2_way_mux_T_11 = or(_s2_way_mux_T_10, _s2_way_mux_T_4)
node _s2_way_mux_T_12 = or(_s2_way_mux_T_11, _s2_way_mux_T_5)
node _s2_way_mux_T_13 = or(_s2_way_mux_T_12, _s2_way_mux_T_6)
node _s2_way_mux_T_14 = or(_s2_way_mux_T_13, _s2_way_mux_T_7)
wire s2_way_mux : UInt<32>
connect s2_way_mux, _s2_way_mux_T_14
reg s2_tag_disparity_r : UInt<1>[8], clock
when s1_clk_en :
connect s2_tag_disparity_r, s1_tag_disparity
node s2_tag_disparity_lo_lo = cat(s2_tag_disparity_r[1], s2_tag_disparity_r[0])
node s2_tag_disparity_lo_hi = cat(s2_tag_disparity_r[3], s2_tag_disparity_r[2])
node s2_tag_disparity_lo = cat(s2_tag_disparity_lo_hi, s2_tag_disparity_lo_lo)
node s2_tag_disparity_hi_lo = cat(s2_tag_disparity_r[5], s2_tag_disparity_r[4])
node s2_tag_disparity_hi_hi = cat(s2_tag_disparity_r[7], s2_tag_disparity_r[6])
node s2_tag_disparity_hi = cat(s2_tag_disparity_hi_hi, s2_tag_disparity_hi_lo)
node _s2_tag_disparity_T = cat(s2_tag_disparity_hi, s2_tag_disparity_lo)
node s2_tag_disparity = orr(_s2_tag_disparity_T)
node s2_tl_error_lo_lo = cat(s1_tl_error[1], s1_tl_error[0])
node s2_tl_error_lo_hi = cat(s1_tl_error[3], s1_tl_error[2])
node s2_tl_error_lo = cat(s2_tl_error_lo_hi, s2_tl_error_lo_lo)
node s2_tl_error_hi_lo = cat(s1_tl_error[5], s1_tl_error[4])
node s2_tl_error_hi_hi = cat(s1_tl_error[7], s1_tl_error[6])
node s2_tl_error_hi = cat(s2_tl_error_hi_hi, s2_tl_error_hi_lo)
node _s2_tl_error_T = cat(s2_tl_error_hi, s2_tl_error_lo)
node _s2_tl_error_T_1 = orr(_s2_tl_error_T)
reg s2_tl_error : UInt<1>, clock
when s1_clk_en :
connect s2_tl_error, _s2_tl_error_T_1
node _s2_disparity_T = or(UInt<1>(0h0), UInt<1>(0h0))
node s2_disparity = or(s2_tag_disparity, _s2_disparity_T)
node _s1_scratchpad_hit_T = bits(s1s3_slaveAddr, 14, 6)
node _s1_scratchpad_hit_T_1 = bits(io.s1_paddr, 14, 6)
node _s1_scratchpad_hit_T_2 = and(UInt<1>(0h0), UInt<1>(0h0))
node s1_scratchpad_hit = mux(s1_slaveValid, UInt<1>(0h0), _s1_scratchpad_hit_T_2)
reg s2_scratchpad_hit : UInt<1>, clock
when s1_clk_en :
connect s2_scratchpad_hit, s1_scratchpad_hit
node _s2_report_uncorrectable_error_T = and(s2_scratchpad_hit, UInt<1>(0h0))
node _s2_report_uncorrectable_error_T_1 = eq(s1s2_full_word_write, UInt<1>(0h0))
node _s2_report_uncorrectable_error_T_2 = and(s2_slaveValid, _s2_report_uncorrectable_error_T_1)
node _s2_report_uncorrectable_error_T_3 = or(s2_valid, _s2_report_uncorrectable_error_T_2)
node s2_report_uncorrectable_error = and(_s2_report_uncorrectable_error_T, _s2_report_uncorrectable_error_T_3)
node _T_90 = and(s2_valid, s2_disparity)
when _T_90 :
connect invalidate, UInt<1>(0h1)
connect io.resp.bits.data, s2_way_mux
connect io.resp.bits.ae, s2_tl_error
connect io.resp.bits.replay, s2_disparity
node _io_resp_valid_T = and(s2_valid, s2_hit)
connect io.resp.valid, _io_resp_valid_T
connect masterNodeOut.a.valid, s2_request_refill
node _masterNodeOut_a_bits_T = shr(refill_paddr, 6)
node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6)
node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6))
node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc))
node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1)
node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2)
node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h2000))
node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4)
node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h9e012000)))
node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6)
node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8)
node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6))
node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6))
node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11)
node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12)
node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0))
node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14)
node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h9e002000)))
node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16)
node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000))
node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19)
node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h9e010000)))
node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21)
node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000))
node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24)
node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h9e010000)))
node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26)
node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2010000))
node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29)
node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h9e012000)))
node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31)
node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000))
node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34)
node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h9e010000)))
node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36)
node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0hc000000))
node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39)
node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h9c000000)))
node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41)
node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000))
node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44)
node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0h9e012000)))
node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46)
node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000))
node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49)
node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0h90000000)))
node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51)
node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_54 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23)
node _masterNodeOut_a_bits_legal_T_55 = or(_masterNodeOut_a_bits_legal_T_54, _masterNodeOut_a_bits_legal_T_28)
node _masterNodeOut_a_bits_legal_T_56 = or(_masterNodeOut_a_bits_legal_T_55, _masterNodeOut_a_bits_legal_T_33)
node _masterNodeOut_a_bits_legal_T_57 = or(_masterNodeOut_a_bits_legal_T_56, _masterNodeOut_a_bits_legal_T_38)
node _masterNodeOut_a_bits_legal_T_58 = or(_masterNodeOut_a_bits_legal_T_57, _masterNodeOut_a_bits_legal_T_43)
node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_58, _masterNodeOut_a_bits_legal_T_48)
node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_53)
node _masterNodeOut_a_bits_legal_T_61 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_60)
node _masterNodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9)
node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_61)
wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}
connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4)
connect masterNodeOut_a_bits_a.param, UInt<1>(0h0)
connect masterNodeOut_a_bits_a.size, UInt<3>(0h6)
connect masterNodeOut_a_bits_a.source, UInt<1>(0h0)
connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1
node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<4>(0h0))
node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0)
node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount)
node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 3, 0)
node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<3>(0h4))
node masterNodeOut_a_bits_a_mask_sub_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 3, 3)
node masterNodeOut_a_bits_a_mask_sub_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 3, 3)
node masterNodeOut_a_bits_a_mask_sub_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_sub_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2)
node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T)
node masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2)
node masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_sub_acc_T_1)
node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2)
node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2)
node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2)
node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T)
node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2)
node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1)
node masterNodeOut_a_bits_a_mask_sub_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_2_2)
node masterNodeOut_a_bits_a_mask_sub_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_2)
node masterNodeOut_a_bits_a_mask_sub_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_3_2)
node masterNodeOut_a_bits_a_mask_sub_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_3)
node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1)
node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1)
node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2)
node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T)
node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2)
node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1)
node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2)
node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2)
node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2)
node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3)
node masterNodeOut_a_bits_a_mask_sub_4_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_2_2, masterNodeOut_a_bits_a_mask_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_4 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_4_2)
node masterNodeOut_a_bits_a_mask_sub_4_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_2_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_4)
node masterNodeOut_a_bits_a_mask_sub_5_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_2_2, masterNodeOut_a_bits_a_mask_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_5 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_5_2)
node masterNodeOut_a_bits_a_mask_sub_5_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_2_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_5)
node masterNodeOut_a_bits_a_mask_sub_6_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_3_2, masterNodeOut_a_bits_a_mask_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_6 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_6_2)
node masterNodeOut_a_bits_a_mask_sub_6_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_3_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_6)
node masterNodeOut_a_bits_a_mask_sub_7_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_3_2, masterNodeOut_a_bits_a_mask_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_7 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_7_2)
node masterNodeOut_a_bits_a_mask_sub_7_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_3_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_7)
node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0)
node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0)
node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq)
node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T)
node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1)
node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1)
node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2)
node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2)
node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3)
node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3)
node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4)
node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4)
node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5)
node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5)
node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6)
node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6)
node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7)
node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7)
node masterNodeOut_a_bits_a_mask_eq_8 = and(masterNodeOut_a_bits_a_mask_sub_4_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_8 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_8)
node masterNodeOut_a_bits_a_mask_acc_8 = or(masterNodeOut_a_bits_a_mask_sub_4_1, _masterNodeOut_a_bits_a_mask_acc_T_8)
node masterNodeOut_a_bits_a_mask_eq_9 = and(masterNodeOut_a_bits_a_mask_sub_4_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_9 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_9)
node masterNodeOut_a_bits_a_mask_acc_9 = or(masterNodeOut_a_bits_a_mask_sub_4_1, _masterNodeOut_a_bits_a_mask_acc_T_9)
node masterNodeOut_a_bits_a_mask_eq_10 = and(masterNodeOut_a_bits_a_mask_sub_5_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_10 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_10)
node masterNodeOut_a_bits_a_mask_acc_10 = or(masterNodeOut_a_bits_a_mask_sub_5_1, _masterNodeOut_a_bits_a_mask_acc_T_10)
node masterNodeOut_a_bits_a_mask_eq_11 = and(masterNodeOut_a_bits_a_mask_sub_5_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_11 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_11)
node masterNodeOut_a_bits_a_mask_acc_11 = or(masterNodeOut_a_bits_a_mask_sub_5_1, _masterNodeOut_a_bits_a_mask_acc_T_11)
node masterNodeOut_a_bits_a_mask_eq_12 = and(masterNodeOut_a_bits_a_mask_sub_6_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_12 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_12)
node masterNodeOut_a_bits_a_mask_acc_12 = or(masterNodeOut_a_bits_a_mask_sub_6_1, _masterNodeOut_a_bits_a_mask_acc_T_12)
node masterNodeOut_a_bits_a_mask_eq_13 = and(masterNodeOut_a_bits_a_mask_sub_6_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_13 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_13)
node masterNodeOut_a_bits_a_mask_acc_13 = or(masterNodeOut_a_bits_a_mask_sub_6_1, _masterNodeOut_a_bits_a_mask_acc_T_13)
node masterNodeOut_a_bits_a_mask_eq_14 = and(masterNodeOut_a_bits_a_mask_sub_7_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_14 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_14)
node masterNodeOut_a_bits_a_mask_acc_14 = or(masterNodeOut_a_bits_a_mask_sub_7_1, _masterNodeOut_a_bits_a_mask_acc_T_14)
node masterNodeOut_a_bits_a_mask_eq_15 = and(masterNodeOut_a_bits_a_mask_sub_7_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_15 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_15)
node masterNodeOut_a_bits_a_mask_acc_15 = or(masterNodeOut_a_bits_a_mask_sub_7_1, _masterNodeOut_a_bits_a_mask_acc_T_15)
node masterNodeOut_a_bits_a_mask_lo_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc)
node masterNodeOut_a_bits_a_mask_lo_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2)
node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_lo_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo_lo)
node masterNodeOut_a_bits_a_mask_lo_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4)
node masterNodeOut_a_bits_a_mask_lo_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6)
node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_lo_hi_hi, masterNodeOut_a_bits_a_mask_lo_hi_lo)
node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo)
node masterNodeOut_a_bits_a_mask_hi_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_9, masterNodeOut_a_bits_a_mask_acc_8)
node masterNodeOut_a_bits_a_mask_hi_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_11, masterNodeOut_a_bits_a_mask_acc_10)
node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_hi_lo_hi, masterNodeOut_a_bits_a_mask_hi_lo_lo)
node masterNodeOut_a_bits_a_mask_hi_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_13, masterNodeOut_a_bits_a_mask_acc_12)
node masterNodeOut_a_bits_a_mask_hi_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_15, masterNodeOut_a_bits_a_mask_acc_14)
node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi_hi, masterNodeOut_a_bits_a_mask_hi_hi_lo)
node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo)
node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo)
connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T
invalidate masterNodeOut_a_bits_a.data
connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0)
connect masterNodeOut.a.bits, masterNodeOut_a_bits_a
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_5.bits.corrupt, UInt<1>(0h0)
connect _WIRE_5.bits.data, UInt<128>(0h0)
connect _WIRE_5.bits.mask, UInt<16>(0h0)
connect _WIRE_5.bits.address, UInt<32>(0h0)
connect _WIRE_5.bits.source, UInt<1>(0h0)
connect _WIRE_5.bits.size, UInt<4>(0h0)
connect _WIRE_5.bits.param, UInt<2>(0h0)
connect _WIRE_5.bits.opcode, UInt<3>(0h0)
connect _WIRE_5.valid, UInt<1>(0h0)
connect _WIRE_5.ready, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits, _WIRE_5.bits
connect _WIRE_6.valid, _WIRE_5.valid
connect _WIRE_6.ready, _WIRE_5.ready
connect _WIRE_6.ready, UInt<1>(0h1)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits.corrupt, UInt<1>(0h0)
connect _WIRE_7.bits.data, UInt<128>(0h0)
connect _WIRE_7.bits.address, UInt<32>(0h0)
connect _WIRE_7.bits.source, UInt<1>(0h0)
connect _WIRE_7.bits.size, UInt<4>(0h0)
connect _WIRE_7.bits.param, UInt<3>(0h0)
connect _WIRE_7.bits.opcode, UInt<3>(0h0)
connect _WIRE_7.valid, UInt<1>(0h0)
connect _WIRE_7.ready, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits, _WIRE_7.bits
connect _WIRE_8.valid, _WIRE_7.valid
connect _WIRE_8.ready, _WIRE_7.ready
connect _WIRE_8.valid, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}
connect _WIRE_9.bits.sink, UInt<6>(0h0)
connect _WIRE_9.valid, UInt<1>(0h0)
connect _WIRE_9.ready, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}
connect _WIRE_10.bits, _WIRE_9.bits
connect _WIRE_10.valid, _WIRE_9.valid
connect _WIRE_10.ready, _WIRE_9.ready
connect _WIRE_10.valid, UInt<1>(0h0)
node _T_91 = and(masterNodeOut.a.valid, UInt<1>(0h0))
node _T_92 = eq(_T_91, UInt<1>(0h0))
node _T_93 = asUInt(reset)
node _T_94 = eq(_T_93, UInt<1>(0h0))
when _T_94 :
node _T_95 = eq(_T_92, UInt<1>(0h0))
when _T_95 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:826 assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))\n") : printf_1
assert(clock, _T_92, UInt<1>(0h1), "") : assert_1
node _T_96 = eq(refill_valid, UInt<1>(0h0))
when _T_96 :
connect invalidated, UInt<1>(0h0)
when refill_fire :
connect refill_valid, UInt<1>(0h1)
when refill_done :
connect refill_valid, UInt<1>(0h0)
connect io.perf.acquire, refill_fire
node _io_keep_clock_enabled_T = or(UInt<1>(0h0), s1_valid)
node _io_keep_clock_enabled_T_1 = or(_io_keep_clock_enabled_T, s2_valid)
node _io_keep_clock_enabled_T_2 = or(_io_keep_clock_enabled_T_1, refill_valid)
node _io_keep_clock_enabled_T_3 = or(_io_keep_clock_enabled_T_2, send_hint)
node _io_keep_clock_enabled_T_4 = or(_io_keep_clock_enabled_T_3, hint_outstanding)
connect io.keep_clock_enabled, _io_keep_clock_enabled_T_4
node _T_97 = eq(send_hint, UInt<1>(0h0))
node _T_98 = eq(masterNodeOut.a.ready, UInt<1>(0h0))
node _T_99 = and(masterNodeOut.a.valid, _T_98)
node _T_100 = and(_T_97, _T_99)
node _T_101 = and(invalidate, refill_valid)
node _T_102 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_103 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_104 = and(_T_102, _T_103)
node _T_105 = eq(s2_slaveValid, UInt<1>(0h0))
node _T_106 = eq(s2_tag_disparity, UInt<1>(0h0))
node _T_107 = eq(s2_scratchpad_hit, UInt<1>(0h0))
node _T_108 = and(_T_105, s2_scratchpad_hit)
node _T_109 = and(_T_105, _T_107)
node _T_110 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_111 = and(s2_slaveValid, _T_107)
node _T_112 = and(_T_106, _T_108)
node _T_113 = and(_T_106, _T_109)
node _T_114 = and(_T_106, _T_110)
node _T_115 = and(_T_106, _T_111)
node _T_116 = and(_T_105, s2_scratchpad_hit)
node _T_117 = and(_T_105, _T_107)
node _T_118 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_119 = and(s2_slaveValid, _T_107)
node _T_120 = and(s2_tag_disparity, _T_116)
node _T_121 = and(s2_tag_disparity, _T_117)
node _T_122 = and(s2_tag_disparity, _T_118)
node _T_123 = and(s2_tag_disparity, _T_119)
node _T_124 = and(_T_104, _T_112)
node _T_125 = and(_T_104, _T_113)
node _T_126 = and(_T_104, _T_114)
node _T_127 = and(_T_104, _T_115)
node _T_128 = and(_T_104, _T_120)
node _T_129 = and(_T_104, _T_121)
node _T_130 = and(_T_104, _T_122)
node _T_131 = and(_T_104, _T_123)
node _T_132 = and(_T_105, s2_scratchpad_hit)
node _T_133 = and(_T_105, _T_107)
node _T_134 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_135 = and(s2_slaveValid, _T_107)
node _T_136 = and(_T_106, _T_132)
node _T_137 = and(_T_106, _T_133)
node _T_138 = and(_T_106, _T_134)
node _T_139 = and(_T_106, _T_135)
node _T_140 = and(_T_105, s2_scratchpad_hit)
node _T_141 = and(_T_105, _T_107)
node _T_142 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_143 = and(s2_slaveValid, _T_107)
node _T_144 = and(s2_tag_disparity, _T_140)
node _T_145 = and(s2_tag_disparity, _T_141)
node _T_146 = and(s2_tag_disparity, _T_142)
node _T_147 = and(s2_tag_disparity, _T_143)
node _T_148 = and(UInt<1>(0h0), _T_136)
node _T_149 = and(UInt<1>(0h0), _T_137)
node _T_150 = and(UInt<1>(0h0), _T_138)
node _T_151 = and(UInt<1>(0h0), _T_139)
node _T_152 = and(UInt<1>(0h0), _T_144)
node _T_153 = and(UInt<1>(0h0), _T_145)
node _T_154 = and(UInt<1>(0h0), _T_146)
node _T_155 = and(UInt<1>(0h0), _T_147)
node _T_156 = and(_T_105, s2_scratchpad_hit)
node _T_157 = and(_T_105, _T_107)
node _T_158 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_159 = and(s2_slaveValid, _T_107)
node _T_160 = and(_T_106, _T_156)
node _T_161 = and(_T_106, _T_157)
node _T_162 = and(_T_106, _T_158)
node _T_163 = and(_T_106, _T_159)
node _T_164 = and(_T_105, s2_scratchpad_hit)
node _T_165 = and(_T_105, _T_107)
node _T_166 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_167 = and(s2_slaveValid, _T_107)
node _T_168 = and(s2_tag_disparity, _T_164)
node _T_169 = and(s2_tag_disparity, _T_165)
node _T_170 = and(s2_tag_disparity, _T_166)
node _T_171 = and(s2_tag_disparity, _T_167)
node _T_172 = and(UInt<1>(0h0), _T_160)
node _T_173 = and(UInt<1>(0h0), _T_161)
node _T_174 = and(UInt<1>(0h0), _T_162)
node _T_175 = and(UInt<1>(0h0), _T_163)
node _T_176 = and(UInt<1>(0h0), _T_168)
node _T_177 = and(UInt<1>(0h0), _T_169)
node _T_178 = and(UInt<1>(0h0), _T_170)
node _T_179 = and(UInt<1>(0h0), _T_171)
node _T_180 = and(s2_valid, _T_124)
node _T_181 = and(s2_valid, _T_125)
node _T_182 = and(s2_valid, _T_126)
node _T_183 = and(s2_valid, _T_127)
node _T_184 = and(s2_valid, _T_128)
node _T_185 = and(s2_valid, _T_129)
node _T_186 = and(s2_valid, _T_130)
node _T_187 = and(s2_valid, _T_131)
node _T_188 = and(s2_valid, _T_148)
node _T_189 = and(s2_valid, _T_149)
node _T_190 = and(s2_valid, _T_150)
node _T_191 = and(s2_valid, _T_151)
node _T_192 = and(s2_valid, _T_152)
node _T_193 = and(s2_valid, _T_153)
node _T_194 = and(s2_valid, _T_154)
node _T_195 = and(s2_valid, _T_155)
node _T_196 = and(s2_valid, _T_172)
node _T_197 = and(s2_valid, _T_173)
node _T_198 = and(s2_valid, _T_174)
node _T_199 = and(s2_valid, _T_175)
node _T_200 = and(s2_valid, _T_176)
node _T_201 = and(s2_valid, _T_177)
node _T_202 = and(s2_valid, _T_178)
node _T_203 = and(s2_valid, _T_179) | module ICache( // @[ICache.scala:251:7]
input clock, // @[ICache.scala:251:7]
input reset, // @[ICache.scala:251:7]
input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_req_valid, // @[ICache.scala:256:14]
input [38:0] io_req_bits_addr, // @[ICache.scala:256:14]
input [31:0] io_s1_paddr, // @[ICache.scala:256:14]
input io_s1_kill, // @[ICache.scala:256:14]
input io_s2_kill, // @[ICache.scala:256:14]
output io_resp_valid, // @[ICache.scala:256:14]
output [31:0] io_resp_bits_data, // @[ICache.scala:256:14]
output io_resp_bits_ae, // @[ICache.scala:256:14]
input io_invalidate // @[ICache.scala:256:14]
);
wire rockettile_icache_data_arrays_3_dout_3_en; // @[ICache.scala:567:28, :590:46]
wire [31:0] data_3; // @[ICache.scala:583:71]
wire wen_3; // @[ICache.scala:570:32]
wire rockettile_icache_data_arrays_2_dout_2_en; // @[ICache.scala:567:28, :590:46]
wire [31:0] data_2; // @[ICache.scala:583:71]
wire wen_2; // @[ICache.scala:570:32]
wire rockettile_icache_data_arrays_1_dout_1_en; // @[ICache.scala:567:28, :590:46]
wire [31:0] data_1; // @[ICache.scala:583:71]
wire wen_1; // @[ICache.scala:570:32]
wire rockettile_icache_data_arrays_0_dout_en; // @[ICache.scala:567:28, :590:46]
wire [31:0] data; // @[ICache.scala:583:71]
wire wen; // @[ICache.scala:570:32]
wire tagMatch_7; // @[ICache.scala:514:26]
wire tagMatch_6; // @[ICache.scala:514:26]
wire tagMatch_5; // @[ICache.scala:514:26]
wire tagMatch_4; // @[ICache.scala:514:26]
wire tagMatch_3; // @[ICache.scala:514:26]
wire tagMatch_2; // @[ICache.scala:514:26]
wire tagMatch_1; // @[ICache.scala:514:26]
wire tagMatch; // @[ICache.scala:514:26]
wire rockettile_icache_tag_array_MPORT_mask_7; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_6; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_5; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_4; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_3; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_2; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_1; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_0; // @[ICache.scala:436:97]
wire refillError; // @[ICache.scala:430:43]
wire rockettile_icache_tag_array_tag_rdata_en; // @[ICache.scala:426:83]
wire [5:0] _tag_rdata_T; // @[ICache.scala:426:42]
wire io_req_ready; // @[ICache.scala:394:19]
wire s2_request_refill; // @[ICache.scala:385:35]
wire [255:0] _rockettile_icache_data_arrays_3_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [255:0] _rockettile_icache_data_arrays_2_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [255:0] _rockettile_icache_data_arrays_1_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [255:0] _rockettile_icache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [167:0] _rockettile_icache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire _repl_way_v0_prng_io_out_0; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_1; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_2; // @[PRNG.scala:91:22]
wire s0_valid = io_req_ready & io_req_valid; // @[Decoupled.scala:51:35]
reg s1_valid; // @[ICache.scala:341:25]
wire s1_hit = tagMatch | tagMatch_1 | tagMatch_2 | tagMatch_3 | tagMatch_4 | tagMatch_5 | tagMatch_6 | tagMatch_7; // @[ICache.scala:361:{35,40}, :514:26]
reg s2_valid; // @[ICache.scala:363:25]
reg s2_hit; // @[ICache.scala:364:23]
reg invalidated; // @[ICache.scala:367:24]
reg refill_valid; // @[ICache.scala:368:29]
wire repl_way_v0_prng_io_increment = auto_master_out_a_ready & s2_request_refill; // @[Decoupled.scala:51:35]
wire s2_miss = s2_valid & ~s2_hit & ~io_s2_kill; // @[ICache.scala:363:25, :364:23, :378:{26,29,37,40}]
reg s2_request_refill_REG; // @[ICache.scala:385:45]
assign s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala:378:{26,37}, :385:{35,45}]
reg [31:0] refill_paddr; // @[ICache.scala:386:31]
wire refill_one_beat = auto_master_out_d_valid & auto_master_out_d_bits_opcode[0]; // @[Edges.scala:106:36]
assign io_req_ready = ~refill_one_beat; // @[ICache.scala:391:39, :394:19]
wire [26:0] _r_beats1_decode_T = 27'hFFF << auto_master_out_d_bits_size; // @[package.scala:243:71]
wire [7:0] r_beats1 = auto_master_out_d_bits_opcode[0] ? ~(_r_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}]
reg [7:0] r_counter; // @[Edges.scala:229:27]
wire [7:0] _r_counter1_T = r_counter - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] refill_cnt = r_beats1 & ~_r_counter1_T; // @[Edges.scala:221:14, :230:28, :234:{25,27}]
wire refill_done = refill_one_beat & (r_counter == 8'h1 | r_beats1 == 8'h0); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}, :233:22]
wire [2:0] way = {_repl_way_v0_prng_io_out_2, _repl_way_v0_prng_io_out_1, _repl_way_v0_prng_io_out_0}; // @[PRNG.scala:91:22]
wire [7:0] _GEN = {rockettile_icache_tag_array_MPORT_mask_7, rockettile_icache_tag_array_MPORT_mask_6, rockettile_icache_tag_array_MPORT_mask_5, rockettile_icache_tag_array_MPORT_mask_4, rockettile_icache_tag_array_MPORT_mask_3, rockettile_icache_tag_array_MPORT_mask_2, rockettile_icache_tag_array_MPORT_mask_1, rockettile_icache_tag_array_MPORT_mask_0}; // @[DescribedSRAM.scala:17:26]
assign _tag_rdata_T = io_req_bits_addr[11:6]; // @[ICache.scala:426:42]
assign rockettile_icache_tag_array_tag_rdata_en = ~refill_done & s0_valid; // @[Decoupled.scala:51:35]
reg accruedRefillError; // @[ICache.scala:428:31]
assign refillError = auto_master_out_d_bits_corrupt | (|refill_cnt) & accruedRefillError; // @[Edges.scala:234:25]
assign rockettile_icache_tag_array_MPORT_mask_0 = way == 3'h0; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_1 = way == 3'h1; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_2 = way == 3'h2; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_3 = way == 3'h3; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_4 = way == 3'h4; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_5 = way == 3'h5; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_6 = way == 3'h6; // @[ICache.scala:407:35, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_7 = &way; // @[ICache.scala:407:35, :436:97]
reg [511:0] vb_array; // @[ICache.scala:448:25]
wire [511:0] _s1_vb_T_2 = vb_array >> io_s1_paddr[11:6]; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch = _s1_vb_T_2[0] & _rockettile_icache_tag_array_RW0_rdata[19:0] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_7 = vb_array >> {506'h1, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_1 = _s1_vb_T_7[0] & _rockettile_icache_tag_array_RW0_rdata[40:21] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_12 = vb_array >> {506'h2, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_2 = _s1_vb_T_12[0] & _rockettile_icache_tag_array_RW0_rdata[61:42] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_17 = vb_array >> {506'h3, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_3 = _s1_vb_T_17[0] & _rockettile_icache_tag_array_RW0_rdata[82:63] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_21 = vb_array >> {506'h4, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_4 = _s1_vb_T_21[0] & _rockettile_icache_tag_array_RW0_rdata[103:84] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_25 = vb_array >> {506'h5, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_5 = _s1_vb_T_25[0] & _rockettile_icache_tag_array_RW0_rdata[124:105] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_29 = vb_array >> {506'h6, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_6 = _s1_vb_T_29[0] & _rockettile_icache_tag_array_RW0_rdata[145:126] == io_s1_paddr[31:12]; // @[package.scala:163:13]
wire [511:0] _s1_vb_T_33 = vb_array >> {506'h7, io_s1_paddr[11:6]}; // @[ICache.scala:448:25, :508:25, :859:21]
assign tagMatch_7 = _s1_vb_T_33[0] & _rockettile_icache_tag_array_RW0_rdata[166:147] == io_s1_paddr[31:12]; // @[package.scala:163:13] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_26 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
node _source_ok_T_29 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[2])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[3])
node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[4])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[5])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[6])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_35, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_11, _T_24)
node _T_97 = and(_T_96, _T_37)
node _T_98 = and(_T_97, _T_50)
node _T_99 = and(_T_98, _T_63)
node _T_100 = and(_T_99, _T_71)
node _T_101 = and(_T_100, _T_79)
node _T_102 = and(_T_101, _T_87)
node _T_103 = and(_T_102, _T_95)
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_103, UInt<1>(0h1), "") : assert_1
node _T_107 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_107 :
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_118 = shr(io.in.a.bits.source, 2)
node _T_119 = eq(_T_118, UInt<1>(0h1))
node _T_120 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_121 = and(_T_119, _T_120)
node _T_122 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_123 = and(_T_121, _T_122)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<2>(0h2))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_130 = shr(io.in.a.bits.source, 2)
node _T_131 = eq(_T_130, UInt<2>(0h3))
node _T_132 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_133 = and(_T_131, _T_132)
node _T_134 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_137 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_138 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_140 = or(_T_111, _T_117)
node _T_141 = or(_T_140, _T_123)
node _T_142 = or(_T_141, _T_129)
node _T_143 = or(_T_142, _T_135)
node _T_144 = or(_T_143, _T_136)
node _T_145 = or(_T_144, _T_137)
node _T_146 = or(_T_145, _T_138)
node _T_147 = or(_T_146, _T_139)
node _T_148 = and(_T_110, _T_147)
node _T_149 = or(UInt<1>(0h0), _T_148)
node _T_150 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = and(_T_150, _T_155)
node _T_157 = or(UInt<1>(0h0), _T_156)
node _T_158 = and(_T_149, _T_157)
node _T_159 = asUInt(reset)
node _T_160 = eq(_T_159, UInt<1>(0h0))
when _T_160 :
node _T_161 = eq(_T_158, UInt<1>(0h0))
when _T_161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_158, UInt<1>(0h1), "") : assert_2
node _T_162 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_163 = shr(io.in.a.bits.source, 2)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_169 = shr(io.in.a.bits.source, 2)
node _T_170 = eq(_T_169, UInt<1>(0h1))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_175 = shr(io.in.a.bits.source, 2)
node _T_176 = eq(_T_175, UInt<2>(0h2))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_181 = shr(io.in.a.bits.source, 2)
node _T_182 = eq(_T_181, UInt<2>(0h3))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_188 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_189 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_190 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_162
connect _WIRE[1], _T_168
connect _WIRE[2], _T_174
connect _WIRE[3], _T_180
connect _WIRE[4], _T_186
connect _WIRE[5], _T_187
connect _WIRE[6], _T_188
connect _WIRE[7], _T_189
connect _WIRE[8], _T_190
node _T_191 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_192 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_194 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_195 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_196 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_197 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_198 = mux(_WIRE[6], _T_191, UInt<1>(0h0))
node _T_199 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_200 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_201 = or(_T_192, _T_193)
node _T_202 = or(_T_201, _T_194)
node _T_203 = or(_T_202, _T_195)
node _T_204 = or(_T_203, _T_196)
node _T_205 = or(_T_204, _T_197)
node _T_206 = or(_T_205, _T_198)
node _T_207 = or(_T_206, _T_199)
node _T_208 = or(_T_207, _T_200)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_208
node _T_209 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_210 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_211 = and(_T_209, _T_210)
node _T_212 = or(UInt<1>(0h0), _T_211)
node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = and(_T_212, _T_217)
node _T_219 = or(UInt<1>(0h0), _T_218)
node _T_220 = and(_WIRE_1, _T_219)
node _T_221 = asUInt(reset)
node _T_222 = eq(_T_221, UInt<1>(0h0))
when _T_222 :
node _T_223 = eq(_T_220, UInt<1>(0h0))
when _T_223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_220, UInt<1>(0h1), "") : assert_3
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(source_ok, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_227 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_228 = asUInt(reset)
node _T_229 = eq(_T_228, UInt<1>(0h0))
when _T_229 :
node _T_230 = eq(_T_227, UInt<1>(0h0))
when _T_230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_227, UInt<1>(0h1), "") : assert_5
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(is_aligned, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_234 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_234, UInt<1>(0h1), "") : assert_7
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_239, UInt<1>(0h1), "") : assert_8
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_243, UInt<1>(0h1), "") : assert_9
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_247 :
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_250 = and(_T_248, _T_249)
node _T_251 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_252 = shr(io.in.a.bits.source, 2)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_255 = and(_T_253, _T_254)
node _T_256 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_257 = and(_T_255, _T_256)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_258 = shr(io.in.a.bits.source, 2)
node _T_259 = eq(_T_258, UInt<1>(0h1))
node _T_260 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_261 = and(_T_259, _T_260)
node _T_262 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_263 = and(_T_261, _T_262)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_264 = shr(io.in.a.bits.source, 2)
node _T_265 = eq(_T_264, UInt<2>(0h2))
node _T_266 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_267 = and(_T_265, _T_266)
node _T_268 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_269 = and(_T_267, _T_268)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_270 = shr(io.in.a.bits.source, 2)
node _T_271 = eq(_T_270, UInt<2>(0h3))
node _T_272 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_273 = and(_T_271, _T_272)
node _T_274 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_275 = and(_T_273, _T_274)
node _T_276 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_277 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_278 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_279 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_280 = or(_T_251, _T_257)
node _T_281 = or(_T_280, _T_263)
node _T_282 = or(_T_281, _T_269)
node _T_283 = or(_T_282, _T_275)
node _T_284 = or(_T_283, _T_276)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_278)
node _T_287 = or(_T_286, _T_279)
node _T_288 = and(_T_250, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_288)
node _T_290 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = and(_T_290, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = and(_T_289, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_303 = shr(io.in.a.bits.source, 2)
node _T_304 = eq(_T_303, UInt<1>(0h0))
node _T_305 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_306 = and(_T_304, _T_305)
node _T_307 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_308 = and(_T_306, _T_307)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_309 = shr(io.in.a.bits.source, 2)
node _T_310 = eq(_T_309, UInt<1>(0h1))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<2>(0h2))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<2>(0h3))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_330 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_302
connect _WIRE_2[1], _T_308
connect _WIRE_2[2], _T_314
connect _WIRE_2[3], _T_320
connect _WIRE_2[4], _T_326
connect _WIRE_2[5], _T_327
connect _WIRE_2[6], _T_328
connect _WIRE_2[7], _T_329
connect _WIRE_2[8], _T_330
node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_332 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_333 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_335 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_338 = mux(_WIRE_2[6], _T_331, UInt<1>(0h0))
node _T_339 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = or(_T_332, _T_333)
node _T_342 = or(_T_341, _T_334)
node _T_343 = or(_T_342, _T_335)
node _T_344 = or(_T_343, _T_336)
node _T_345 = or(_T_344, _T_337)
node _T_346 = or(_T_345, _T_338)
node _T_347 = or(_T_346, _T_339)
node _T_348 = or(_T_347, _T_340)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_348
node _T_349 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_350 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_351 = and(_T_349, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_351)
node _T_353 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = and(_T_352, _T_357)
node _T_359 = or(UInt<1>(0h0), _T_358)
node _T_360 = and(_WIRE_3, _T_359)
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_360, UInt<1>(0h1), "") : assert_11
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(source_ok, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_367 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_367, UInt<1>(0h1), "") : assert_13
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(is_aligned, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_374 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_374, UInt<1>(0h1), "") : assert_15
node _T_378 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_378, UInt<1>(0h1), "") : assert_16
node _T_382 = not(io.in.a.bits.mask)
node _T_383 = eq(_T_382, UInt<1>(0h0))
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_383, UInt<1>(0h1), "") : assert_17
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_387, UInt<1>(0h1), "") : assert_18
node _T_391 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_391 :
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_396 = shr(io.in.a.bits.source, 2)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_399 = and(_T_397, _T_398)
node _T_400 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_402 = shr(io.in.a.bits.source, 2)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_408 = shr(io.in.a.bits.source, 2)
node _T_409 = eq(_T_408, UInt<2>(0h2))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_413 = and(_T_411, _T_412)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_414 = shr(io.in.a.bits.source, 2)
node _T_415 = eq(_T_414, UInt<2>(0h3))
node _T_416 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_417 = and(_T_415, _T_416)
node _T_418 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_421 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_422 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_424 = or(_T_395, _T_401)
node _T_425 = or(_T_424, _T_407)
node _T_426 = or(_T_425, _T_413)
node _T_427 = or(_T_426, _T_419)
node _T_428 = or(_T_427, _T_420)
node _T_429 = or(_T_428, _T_421)
node _T_430 = or(_T_429, _T_422)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_394, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_433, UInt<1>(0h1), "") : assert_19
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<17>(0h10000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = asUInt(reset)
node _T_449 = eq(_T_448, UInt<1>(0h0))
when _T_449 :
node _T_450 = eq(_T_447, UInt<1>(0h0))
when _T_450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_447, UInt<1>(0h1), "") : assert_20
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(source_ok, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(is_aligned, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_457 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_457, UInt<1>(0h1), "") : assert_23
node _T_461 = eq(io.in.a.bits.mask, mask)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_461, UInt<1>(0h1), "") : assert_24
node _T_465 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_465, UInt<1>(0h1), "") : assert_25
node _T_469 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_469 :
node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_471 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_472 = and(_T_470, _T_471)
node _T_473 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_474 = shr(io.in.a.bits.source, 2)
node _T_475 = eq(_T_474, UInt<1>(0h0))
node _T_476 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_477 = and(_T_475, _T_476)
node _T_478 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_480 = shr(io.in.a.bits.source, 2)
node _T_481 = eq(_T_480, UInt<1>(0h1))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_485 = and(_T_483, _T_484)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_486 = shr(io.in.a.bits.source, 2)
node _T_487 = eq(_T_486, UInt<2>(0h2))
node _T_488 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_489 = and(_T_487, _T_488)
node _T_490 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_491 = and(_T_489, _T_490)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_492 = shr(io.in.a.bits.source, 2)
node _T_493 = eq(_T_492, UInt<2>(0h3))
node _T_494 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_495 = and(_T_493, _T_494)
node _T_496 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_497 = and(_T_495, _T_496)
node _T_498 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_499 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_502 = or(_T_473, _T_479)
node _T_503 = or(_T_502, _T_485)
node _T_504 = or(_T_503, _T_491)
node _T_505 = or(_T_504, _T_497)
node _T_506 = or(_T_505, _T_498)
node _T_507 = or(_T_506, _T_499)
node _T_508 = or(_T_507, _T_500)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_472, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_510)
node _T_512 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_513 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_514 = cvt(_T_513)
node _T_515 = and(_T_514, asSInt(UInt<17>(0h10000)))
node _T_516 = asSInt(_T_515)
node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0)))
node _T_518 = and(_T_512, _T_517)
node _T_519 = or(UInt<1>(0h0), _T_518)
node _T_520 = and(_T_511, _T_519)
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_520, UInt<1>(0h1), "") : assert_26
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(source_ok, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(is_aligned, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_530 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_530, UInt<1>(0h1), "") : assert_29
node _T_534 = eq(io.in.a.bits.mask, mask)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_534, UInt<1>(0h1), "") : assert_30
node _T_538 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_538 :
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_541 = and(_T_539, _T_540)
node _T_542 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_543 = shr(io.in.a.bits.source, 2)
node _T_544 = eq(_T_543, UInt<1>(0h0))
node _T_545 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_546 = and(_T_544, _T_545)
node _T_547 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_548 = and(_T_546, _T_547)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_549 = shr(io.in.a.bits.source, 2)
node _T_550 = eq(_T_549, UInt<1>(0h1))
node _T_551 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_552 = and(_T_550, _T_551)
node _T_553 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_554 = and(_T_552, _T_553)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_555 = shr(io.in.a.bits.source, 2)
node _T_556 = eq(_T_555, UInt<2>(0h2))
node _T_557 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_558 = and(_T_556, _T_557)
node _T_559 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_560 = and(_T_558, _T_559)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_561 = shr(io.in.a.bits.source, 2)
node _T_562 = eq(_T_561, UInt<2>(0h3))
node _T_563 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_564 = and(_T_562, _T_563)
node _T_565 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_566 = and(_T_564, _T_565)
node _T_567 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_568 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_569 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_570 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_571 = or(_T_542, _T_548)
node _T_572 = or(_T_571, _T_554)
node _T_573 = or(_T_572, _T_560)
node _T_574 = or(_T_573, _T_566)
node _T_575 = or(_T_574, _T_567)
node _T_576 = or(_T_575, _T_568)
node _T_577 = or(_T_576, _T_569)
node _T_578 = or(_T_577, _T_570)
node _T_579 = and(_T_541, _T_578)
node _T_580 = or(UInt<1>(0h0), _T_579)
node _T_581 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_582 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<17>(0h10000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = and(_T_581, _T_586)
node _T_588 = or(UInt<1>(0h0), _T_587)
node _T_589 = and(_T_580, _T_588)
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_589, UInt<1>(0h1), "") : assert_31
node _T_593 = asUInt(reset)
node _T_594 = eq(_T_593, UInt<1>(0h0))
when _T_594 :
node _T_595 = eq(source_ok, UInt<1>(0h0))
when _T_595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(is_aligned, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_599 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_600 = asUInt(reset)
node _T_601 = eq(_T_600, UInt<1>(0h0))
when _T_601 :
node _T_602 = eq(_T_599, UInt<1>(0h0))
when _T_602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_599, UInt<1>(0h1), "") : assert_34
node _T_603 = not(mask)
node _T_604 = and(io.in.a.bits.mask, _T_603)
node _T_605 = eq(_T_604, UInt<1>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_605, UInt<1>(0h1), "") : assert_35
node _T_609 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_609 :
node _T_610 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_611 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_612 = and(_T_610, _T_611)
node _T_613 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_614 = shr(io.in.a.bits.source, 2)
node _T_615 = eq(_T_614, UInt<1>(0h0))
node _T_616 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_617 = and(_T_615, _T_616)
node _T_618 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_619 = and(_T_617, _T_618)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_620 = shr(io.in.a.bits.source, 2)
node _T_621 = eq(_T_620, UInt<1>(0h1))
node _T_622 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_623 = and(_T_621, _T_622)
node _T_624 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_625 = and(_T_623, _T_624)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_626 = shr(io.in.a.bits.source, 2)
node _T_627 = eq(_T_626, UInt<2>(0h2))
node _T_628 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_629 = and(_T_627, _T_628)
node _T_630 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_631 = and(_T_629, _T_630)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_632 = shr(io.in.a.bits.source, 2)
node _T_633 = eq(_T_632, UInt<2>(0h3))
node _T_634 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_635 = and(_T_633, _T_634)
node _T_636 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_641 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_642 = or(_T_613, _T_619)
node _T_643 = or(_T_642, _T_625)
node _T_644 = or(_T_643, _T_631)
node _T_645 = or(_T_644, _T_637)
node _T_646 = or(_T_645, _T_638)
node _T_647 = or(_T_646, _T_639)
node _T_648 = or(_T_647, _T_640)
node _T_649 = or(_T_648, _T_641)
node _T_650 = and(_T_612, _T_649)
node _T_651 = or(UInt<1>(0h0), _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = and(_T_651, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_660, UInt<1>(0h1), "") : assert_36
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(source_ok, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(is_aligned, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_670 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(_T_670, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_670, UInt<1>(0h1), "") : assert_39
node _T_674 = eq(io.in.a.bits.mask, mask)
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_674, UInt<1>(0h1), "") : assert_40
node _T_678 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_678 :
node _T_679 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_680 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_681 = and(_T_679, _T_680)
node _T_682 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_683 = shr(io.in.a.bits.source, 2)
node _T_684 = eq(_T_683, UInt<1>(0h0))
node _T_685 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_686 = and(_T_684, _T_685)
node _T_687 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_688 = and(_T_686, _T_687)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<1>(0h1))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_695 = shr(io.in.a.bits.source, 2)
node _T_696 = eq(_T_695, UInt<2>(0h2))
node _T_697 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_698 = and(_T_696, _T_697)
node _T_699 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_700 = and(_T_698, _T_699)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_701 = shr(io.in.a.bits.source, 2)
node _T_702 = eq(_T_701, UInt<2>(0h3))
node _T_703 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_704 = and(_T_702, _T_703)
node _T_705 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_706 = and(_T_704, _T_705)
node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_708 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_710 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_711 = or(_T_682, _T_688)
node _T_712 = or(_T_711, _T_694)
node _T_713 = or(_T_712, _T_700)
node _T_714 = or(_T_713, _T_706)
node _T_715 = or(_T_714, _T_707)
node _T_716 = or(_T_715, _T_708)
node _T_717 = or(_T_716, _T_709)
node _T_718 = or(_T_717, _T_710)
node _T_719 = and(_T_681, _T_718)
node _T_720 = or(UInt<1>(0h0), _T_719)
node _T_721 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_722 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_723 = cvt(_T_722)
node _T_724 = and(_T_723, asSInt(UInt<17>(0h10000)))
node _T_725 = asSInt(_T_724)
node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0)))
node _T_727 = and(_T_721, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_727)
node _T_729 = and(_T_720, _T_728)
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_T_729, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_729, UInt<1>(0h1), "") : assert_41
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(source_ok, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(is_aligned, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_739 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_739, UInt<1>(0h1), "") : assert_44
node _T_743 = eq(io.in.a.bits.mask, mask)
node _T_744 = asUInt(reset)
node _T_745 = eq(_T_744, UInt<1>(0h0))
when _T_745 :
node _T_746 = eq(_T_743, UInt<1>(0h0))
when _T_746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_743, UInt<1>(0h1), "") : assert_45
node _T_747 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_747 :
node _T_748 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_749 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_750 = and(_T_748, _T_749)
node _T_751 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<1>(0h0))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<1>(0h1))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_763 = and(_T_761, _T_762)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_764 = shr(io.in.a.bits.source, 2)
node _T_765 = eq(_T_764, UInt<2>(0h2))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_769 = and(_T_767, _T_768)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_770 = shr(io.in.a.bits.source, 2)
node _T_771 = eq(_T_770, UInt<2>(0h3))
node _T_772 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_773 = and(_T_771, _T_772)
node _T_774 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_775 = and(_T_773, _T_774)
node _T_776 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_777 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_779 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_780 = or(_T_751, _T_757)
node _T_781 = or(_T_780, _T_763)
node _T_782 = or(_T_781, _T_769)
node _T_783 = or(_T_782, _T_775)
node _T_784 = or(_T_783, _T_776)
node _T_785 = or(_T_784, _T_777)
node _T_786 = or(_T_785, _T_778)
node _T_787 = or(_T_786, _T_779)
node _T_788 = and(_T_750, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_791 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_792 = cvt(_T_791)
node _T_793 = and(_T_792, asSInt(UInt<17>(0h10000)))
node _T_794 = asSInt(_T_793)
node _T_795 = eq(_T_794, asSInt(UInt<1>(0h0)))
node _T_796 = and(_T_790, _T_795)
node _T_797 = or(UInt<1>(0h0), _T_796)
node _T_798 = and(_T_789, _T_797)
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(_T_798, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_798, UInt<1>(0h1), "") : assert_46
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(source_ok, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_805 = asUInt(reset)
node _T_806 = eq(_T_805, UInt<1>(0h0))
when _T_806 :
node _T_807 = eq(is_aligned, UInt<1>(0h0))
when _T_807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_808 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_809 = asUInt(reset)
node _T_810 = eq(_T_809, UInt<1>(0h0))
when _T_810 :
node _T_811 = eq(_T_808, UInt<1>(0h0))
when _T_811 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_808, UInt<1>(0h1), "") : assert_49
node _T_812 = eq(io.in.a.bits.mask, mask)
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(_T_812, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_812, UInt<1>(0h1), "") : assert_50
node _T_816 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_816, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_820 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_820, UInt<1>(0h1), "") : assert_52
node _source_ok_T_36 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_37 = shr(io.in.d.bits.source, 2)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h1))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_62 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_36
connect _source_ok_WIRE_1[1], _source_ok_T_42
connect _source_ok_WIRE_1[2], _source_ok_T_48
connect _source_ok_WIRE_1[3], _source_ok_T_54
connect _source_ok_WIRE_1[4], _source_ok_T_60
connect _source_ok_WIRE_1[5], _source_ok_T_61
connect _source_ok_WIRE_1[6], _source_ok_T_62
connect _source_ok_WIRE_1[7], _source_ok_T_63
connect _source_ok_WIRE_1[8], _source_ok_T_64
node _source_ok_T_65 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE_1[2])
node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE_1[3])
node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE_1[4])
node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[5])
node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[6])
node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_71, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_824 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_824 :
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(source_ok_1, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_828 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_828, UInt<1>(0h1), "") : assert_54
node _T_832 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_832, UInt<1>(0h1), "") : assert_55
node _T_836 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_836, UInt<1>(0h1), "") : assert_56
node _T_840 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_841 = asUInt(reset)
node _T_842 = eq(_T_841, UInt<1>(0h0))
when _T_842 :
node _T_843 = eq(_T_840, UInt<1>(0h0))
when _T_843 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_840, UInt<1>(0h1), "") : assert_57
node _T_844 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_844 :
node _T_845 = asUInt(reset)
node _T_846 = eq(_T_845, UInt<1>(0h0))
when _T_846 :
node _T_847 = eq(source_ok_1, UInt<1>(0h0))
when _T_847 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_848 = asUInt(reset)
node _T_849 = eq(_T_848, UInt<1>(0h0))
when _T_849 :
node _T_850 = eq(sink_ok, UInt<1>(0h0))
when _T_850 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_851 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(_T_851, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_851, UInt<1>(0h1), "") : assert_60
node _T_855 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_855, UInt<1>(0h1), "") : assert_61
node _T_859 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_859, UInt<1>(0h1), "") : assert_62
node _T_863 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_863, UInt<1>(0h1), "") : assert_63
node _T_867 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_868 = or(UInt<1>(0h0), _T_867)
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_868, UInt<1>(0h1), "") : assert_64
node _T_872 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_872 :
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(source_ok_1, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_876 = asUInt(reset)
node _T_877 = eq(_T_876, UInt<1>(0h0))
when _T_877 :
node _T_878 = eq(sink_ok, UInt<1>(0h0))
when _T_878 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_879 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_880 = asUInt(reset)
node _T_881 = eq(_T_880, UInt<1>(0h0))
when _T_881 :
node _T_882 = eq(_T_879, UInt<1>(0h0))
when _T_882 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_879, UInt<1>(0h1), "") : assert_67
node _T_883 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(_T_883, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_883, UInt<1>(0h1), "") : assert_68
node _T_887 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_888 = asUInt(reset)
node _T_889 = eq(_T_888, UInt<1>(0h0))
when _T_889 :
node _T_890 = eq(_T_887, UInt<1>(0h0))
when _T_890 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_887, UInt<1>(0h1), "") : assert_69
node _T_891 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_892 = or(_T_891, io.in.d.bits.corrupt)
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_892, UInt<1>(0h1), "") : assert_70
node _T_896 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_897 = or(UInt<1>(0h0), _T_896)
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_897, UInt<1>(0h1), "") : assert_71
node _T_901 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_901 :
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(source_ok_1, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_905 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(_T_905, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_905, UInt<1>(0h1), "") : assert_73
node _T_909 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(_T_909, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_909, UInt<1>(0h1), "") : assert_74
node _T_913 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_914 = or(UInt<1>(0h0), _T_913)
node _T_915 = asUInt(reset)
node _T_916 = eq(_T_915, UInt<1>(0h0))
when _T_916 :
node _T_917 = eq(_T_914, UInt<1>(0h0))
when _T_917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_914, UInt<1>(0h1), "") : assert_75
node _T_918 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_918 :
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(source_ok_1, UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_922 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_T_922, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_922, UInt<1>(0h1), "") : assert_77
node _T_926 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_927 = or(_T_926, io.in.d.bits.corrupt)
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(_T_927, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_927, UInt<1>(0h1), "") : assert_78
node _T_931 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_932 = or(UInt<1>(0h0), _T_931)
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(_T_932, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_932, UInt<1>(0h1), "") : assert_79
node _T_936 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_936 :
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(source_ok_1, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_940 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_940, UInt<1>(0h1), "") : assert_81
node _T_944 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_944, UInt<1>(0h1), "") : assert_82
node _T_948 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_949 = or(UInt<1>(0h0), _T_948)
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_949, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<17>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_953 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_953, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<17>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_957 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_957, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_961 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_T_961, UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_961, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_965 = eq(a_first, UInt<1>(0h0))
node _T_966 = and(io.in.a.valid, _T_965)
when _T_966 :
node _T_967 = eq(io.in.a.bits.opcode, opcode)
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_967, UInt<1>(0h1), "") : assert_87
node _T_971 = eq(io.in.a.bits.param, param)
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_T_971, UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_971, UInt<1>(0h1), "") : assert_88
node _T_975 = eq(io.in.a.bits.size, size)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_975, UInt<1>(0h1), "") : assert_89
node _T_979 = eq(io.in.a.bits.source, source)
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(_T_979, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_979, UInt<1>(0h1), "") : assert_90
node _T_983 = eq(io.in.a.bits.address, address)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_983, UInt<1>(0h1), "") : assert_91
node _T_987 = and(io.in.a.ready, io.in.a.valid)
node _T_988 = and(_T_987, a_first)
when _T_988 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_989 = eq(d_first, UInt<1>(0h0))
node _T_990 = and(io.in.d.valid, _T_989)
when _T_990 :
node _T_991 = eq(io.in.d.bits.opcode, opcode_1)
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_991, UInt<1>(0h1), "") : assert_92
node _T_995 = eq(io.in.d.bits.param, param_1)
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_995, UInt<1>(0h1), "") : assert_93
node _T_999 = eq(io.in.d.bits.size, size_1)
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_999, UInt<1>(0h1), "") : assert_94
node _T_1003 = eq(io.in.d.bits.source, source_1)
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_95
node _T_1007 = eq(io.in.d.bits.sink, sink)
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_96
node _T_1011 = eq(io.in.d.bits.denied, denied)
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_97
node _T_1015 = and(io.in.d.ready, io.in.d.valid)
node _T_1016 = and(_T_1015, d_first)
when _T_1016 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1017 = and(io.in.a.valid, a_first_1)
node _T_1018 = and(_T_1017, UInt<1>(0h1))
when _T_1018 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1019 = and(io.in.a.ready, io.in.a.valid)
node _T_1020 = and(_T_1019, a_first_1)
node _T_1021 = and(_T_1020, UInt<1>(0h1))
when _T_1021 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1022 = dshr(inflight, io.in.a.bits.source)
node _T_1023 = bits(_T_1022, 0, 0)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1028 = and(io.in.d.valid, d_first_1)
node _T_1029 = and(_T_1028, UInt<1>(0h1))
node _T_1030 = eq(d_release_ack, UInt<1>(0h0))
node _T_1031 = and(_T_1029, _T_1030)
when _T_1031 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1032 = and(io.in.d.ready, io.in.d.valid)
node _T_1033 = and(_T_1032, d_first_1)
node _T_1034 = and(_T_1033, UInt<1>(0h1))
node _T_1035 = eq(d_release_ack, UInt<1>(0h0))
node _T_1036 = and(_T_1034, _T_1035)
when _T_1036 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1037 = and(io.in.d.valid, d_first_1)
node _T_1038 = and(_T_1037, UInt<1>(0h1))
node _T_1039 = eq(d_release_ack, UInt<1>(0h0))
node _T_1040 = and(_T_1038, _T_1039)
when _T_1040 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1041 = dshr(inflight, io.in.d.bits.source)
node _T_1042 = bits(_T_1041, 0, 0)
node _T_1043 = or(_T_1042, same_cycle_resp)
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(_T_1043, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1043, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1047 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1048 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1049 = or(_T_1047, _T_1048)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_100
node _T_1053 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_101
else :
node _T_1057 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1058 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1059 = or(_T_1057, _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_102
node _T_1063 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_103
node _T_1067 = and(io.in.d.valid, d_first_1)
node _T_1068 = and(_T_1067, a_first_1)
node _T_1069 = and(_T_1068, io.in.a.valid)
node _T_1070 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(d_release_ack, UInt<1>(0h0))
node _T_1073 = and(_T_1071, _T_1072)
when _T_1073 :
node _T_1074 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1075 = or(_T_1074, io.in.a.ready)
node _T_1076 = asUInt(reset)
node _T_1077 = eq(_T_1076, UInt<1>(0h0))
when _T_1077 :
node _T_1078 = eq(_T_1075, UInt<1>(0h0))
when _T_1078 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1075, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_52
node _T_1079 = orr(inflight)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
node _T_1081 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1082 = or(_T_1080, _T_1081)
node _T_1083 = lt(watchdog, plusarg_reader.out)
node _T_1084 = or(_T_1082, _T_1083)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1088 = and(io.in.a.ready, io.in.a.valid)
node _T_1089 = and(io.in.d.ready, io.in.d.valid)
node _T_1090 = or(_T_1088, _T_1089)
when _T_1090 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<17>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<17>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1091 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<17>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1092 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1093 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = and(_T_1091, _T_1094)
when _T_1095 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<17>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1096 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1097 = and(_T_1096, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<17>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1098 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1099 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = and(_T_1097, _T_1100)
when _T_1101 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<17>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1102 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1103 = bits(_T_1102, 0, 0)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1108 = and(io.in.d.valid, d_first_2)
node _T_1109 = and(_T_1108, UInt<1>(0h1))
node _T_1110 = and(_T_1109, d_release_ack_1)
when _T_1110 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1111 = and(io.in.d.ready, io.in.d.valid)
node _T_1112 = and(_T_1111, d_first_2)
node _T_1113 = and(_T_1112, UInt<1>(0h1))
node _T_1114 = and(_T_1113, d_release_ack_1)
when _T_1114 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1115 = and(io.in.d.valid, d_first_2)
node _T_1116 = and(_T_1115, UInt<1>(0h1))
node _T_1117 = and(_T_1116, d_release_ack_1)
when _T_1117 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1118 = dshr(inflight_1, io.in.d.bits.source)
node _T_1119 = bits(_T_1118, 0, 0)
node _T_1120 = or(_T_1119, same_cycle_resp_1)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<17>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1124 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_108
else :
node _T_1128 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_109
node _T_1132 = and(io.in.d.valid, d_first_2)
node _T_1133 = and(_T_1132, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<17>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1134 = and(_T_1133, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<17>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1135 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1136 = and(_T_1134, _T_1135)
node _T_1137 = and(_T_1136, d_release_ack_1)
node _T_1138 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1139 = and(_T_1137, _T_1138)
when _T_1139 :
node _T_1140 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<17>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1141 = or(_T_1140, _WIRE_27.ready)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_53
node _T_1145 = orr(inflight_1)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
node _T_1147 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1148 = or(_T_1146, _T_1147)
node _T_1149 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1150 = or(_T_1148, _T_1149)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:85)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<17>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1154 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1155 = and(io.in.d.ready, io.in.d.valid)
node _T_1156 = or(_T_1154, _T_1155)
when _T_1156 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_26( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] a_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] a_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] a_first_beats1_1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] a_first_count_1 = 3'h0; // @[Edges.scala:234:25]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [259:0] _inflight_opcodes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [259:0] _inflight_sizes_T_4 = 260'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [64:0] _inflight_T_4 = 65'h1FFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [259:0] d_opcodes_clr_1 = 260'h0; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1 = 260'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [64:0] d_clr_1 = 65'h0; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1 = 65'h0; // @[Monitor.scala:775:34]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_32 = _source_ok_T_31 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_35 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {11'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire _source_ok_T_65 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_71 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1088 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1088; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1088; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] _a_first_counter_T = a_first ? 3'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_1156 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1156; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1156; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1156; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1 = d_first_beats1_decode; // @[Edges.scala:220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? 3'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_decode_1; // @[Edges.scala:220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1021 = _T_1088 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1021 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1021 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1021 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1021 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1021 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_1067 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_4 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1067 ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1034 = _T_1156 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_1034 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1034 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1034 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_decode_2; // @[Edges.scala:220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_133( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFM_small_e8_s24_1 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst divSqrtRecFNToRaw of DivSqrtRecFMToRaw_small_e8_s24_1
connect divSqrtRecFNToRaw.clock, clock
connect divSqrtRecFNToRaw.reset, reset
connect io.inReady, divSqrtRecFNToRaw.io.inReady
connect divSqrtRecFNToRaw.io.inValid, io.inValid
connect divSqrtRecFNToRaw.io.sqrtOp, io.sqrtOp
connect divSqrtRecFNToRaw.io.a, io.a
connect divSqrtRecFNToRaw.io.b, io.b
connect divSqrtRecFNToRaw.io.roundingMode, io.roundingMode
connect io.outValid_div, divSqrtRecFNToRaw.io.rawOutValid_div
connect io.outValid_sqrt, divSqrtRecFNToRaw.io.rawOutValid_sqrt
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_3
connect roundRawFNToRecFN.io.invalidExc, divSqrtRecFNToRaw.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecFNToRaw.io.infiniteExc
connect roundRawFNToRecFN.io.in.sig, divSqrtRecFNToRaw.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, divSqrtRecFNToRaw.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, divSqrtRecFNToRaw.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, divSqrtRecFNToRaw.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, divSqrtRecFNToRaw.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecFNToRaw.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, divSqrtRecFNToRaw.io.roundingModeOut
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module DivSqrtRecFM_small_e8_s24_1( // @[DivSqrtRecFN_small.scala:468:5]
input clock, // @[DivSqrtRecFN_small.scala:468:5]
input reset, // @[DivSqrtRecFN_small.scala:468:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:472:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:472:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:472:16]
input [32:0] io_a, // @[DivSqrtRecFN_small.scala:472:16]
input [32:0] io_b, // @[DivSqrtRecFN_small.scala:472:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:472:16]
output io_outValid_div, // @[DivSqrtRecFN_small.scala:472:16]
output io_outValid_sqrt, // @[DivSqrtRecFN_small.scala:472:16]
output [32:0] io_out, // @[DivSqrtRecFN_small.scala:472:16]
output [4:0] io_exceptionFlags // @[DivSqrtRecFN_small.scala:472:16]
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_invalidExc; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_infiniteExc; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isNaN; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isInf; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isZero; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_sign; // @[DivSqrtRecFN_small.scala:493:15]
wire [9:0] _divSqrtRecFNToRaw_io_rawOut_sExp; // @[DivSqrtRecFN_small.scala:493:15]
wire [26:0] _divSqrtRecFNToRaw_io_rawOut_sig; // @[DivSqrtRecFN_small.scala:493:15]
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:468:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:468:5]
wire [32:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:468:5]
wire [32:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:468:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:468:5]
wire io_detectTininess = 1'h1; // @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5]
wire io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5]
wire io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5]
wire [32:0] io_out_0; // @[DivSqrtRecFN_small.scala:468:5]
wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5]
DivSqrtRecFMToRaw_small_e8_s24_1 divSqrtRecFNToRaw ( // @[DivSqrtRecFN_small.scala:493:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_a (io_a_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_b (io_b_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_rawOutValid_div (io_outValid_div_0),
.io_rawOutValid_sqrt (io_outValid_sqrt_0),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
); // @[DivSqrtRecFN_small.scala:493:15]
RoundRawFNToRecFN_e8_s24_3 roundRawFNToRecFN ( // @[DivSqrtRecFN_small.scala:508:15]
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), // @[DivSqrtRecFN_small.scala:493:15]
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig), // @[DivSqrtRecFN_small.scala:493:15]
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut), // @[DivSqrtRecFN_small.scala:493:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[DivSqrtRecFN_small.scala:508:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_out = io_out_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntXbar_i2_o1 :
output auto : { flip anon_in_1 : UInt<1>[1], flip anon_in_0 : UInt<1>[1], anon_out : UInt<1>[2]}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : UInt<1>[1]
invalidate anonIn[0]
wire anonIn_1 : UInt<1>[1]
invalidate anonIn_1[0]
wire anonOut : UInt<1>[2]
invalidate anonOut[0]
invalidate anonOut[1]
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonOut[0], anonIn[0]
connect anonOut[1], anonIn_1[0] | module IntXbar_i2_o1( // @[Xbar.scala:22:9]
input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1 // @[LazyModuleImp.scala:107:25]
);
assign auto_anon_out_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9]
assign auto_anon_out_1 = auto_anon_in_1_0; // @[Xbar.scala:22:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_83 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_83( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_135 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RenameBusyTable :
input clock : Clock
input reset : Reset
output io : { flip ren_uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[1], busy_resps : { prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>}[1], flip rebusy_reqs : UInt<1>[1], flip wb_pdsts : UInt<6>[3], flip wb_valids : UInt<1>[3], debug : { busytable : UInt<52>}}
regreset busy_table : UInt<52>, clock, reset, UInt<52>(0h0)
node _busy_table_wb_T = dshl(UInt<1>(0h1), io.wb_pdsts[0])
node _busy_table_wb_T_1 = mux(io.wb_valids[0], UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node _busy_table_wb_T_2 = and(_busy_table_wb_T, _busy_table_wb_T_1)
node _busy_table_wb_T_3 = dshl(UInt<1>(0h1), io.wb_pdsts[1])
node _busy_table_wb_T_4 = mux(io.wb_valids[1], UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node _busy_table_wb_T_5 = and(_busy_table_wb_T_3, _busy_table_wb_T_4)
node _busy_table_wb_T_6 = dshl(UInt<1>(0h1), io.wb_pdsts[2])
node _busy_table_wb_T_7 = mux(io.wb_valids[2], UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node _busy_table_wb_T_8 = and(_busy_table_wb_T_6, _busy_table_wb_T_7)
node _busy_table_wb_T_9 = or(_busy_table_wb_T_2, _busy_table_wb_T_5)
node _busy_table_wb_T_10 = or(_busy_table_wb_T_9, _busy_table_wb_T_8)
node _busy_table_wb_T_11 = not(_busy_table_wb_T_10)
node busy_table_wb = and(busy_table, _busy_table_wb_T_11)
node _busy_table_next_T = dshl(UInt<1>(0h1), io.ren_uops[0].pdst)
node _busy_table_next_T_1 = mux(io.rebusy_reqs[0], UInt<52>(0hfffffffffffff), UInt<52>(0h0))
node _busy_table_next_T_2 = and(_busy_table_next_T, _busy_table_next_T_1)
node busy_table_next = or(busy_table_wb, _busy_table_next_T_2)
connect busy_table, busy_table_next
node _io_busy_resps_0_prs1_busy_T = dshr(busy_table, io.ren_uops[0].prs1)
node _io_busy_resps_0_prs1_busy_T_1 = bits(_io_busy_resps_0_prs1_busy_T, 0, 0)
node _io_busy_resps_0_prs1_busy_T_2 = and(UInt<1>(0h0), UInt<1>(0h0))
node _io_busy_resps_0_prs1_busy_T_3 = or(_io_busy_resps_0_prs1_busy_T_1, _io_busy_resps_0_prs1_busy_T_2)
connect io.busy_resps[0].prs1_busy, _io_busy_resps_0_prs1_busy_T_3
node _io_busy_resps_0_prs2_busy_T = dshr(busy_table, io.ren_uops[0].prs2)
node _io_busy_resps_0_prs2_busy_T_1 = bits(_io_busy_resps_0_prs2_busy_T, 0, 0)
node _io_busy_resps_0_prs2_busy_T_2 = and(UInt<1>(0h0), UInt<1>(0h0))
node _io_busy_resps_0_prs2_busy_T_3 = or(_io_busy_resps_0_prs2_busy_T_1, _io_busy_resps_0_prs2_busy_T_2)
connect io.busy_resps[0].prs2_busy, _io_busy_resps_0_prs2_busy_T_3
node _io_busy_resps_0_prs3_busy_T = dshr(busy_table, io.ren_uops[0].prs3)
node _io_busy_resps_0_prs3_busy_T_1 = bits(_io_busy_resps_0_prs3_busy_T, 0, 0)
node _io_busy_resps_0_prs3_busy_T_2 = and(UInt<1>(0h0), UInt<1>(0h0))
node _io_busy_resps_0_prs3_busy_T_3 = or(_io_busy_resps_0_prs3_busy_T_1, _io_busy_resps_0_prs3_busy_T_2)
connect io.busy_resps[0].prs3_busy, _io_busy_resps_0_prs3_busy_T_3
connect io.busy_resps[0].prs3_busy, UInt<1>(0h0)
connect io.debug.busytable, busy_table | module RenameBusyTable( // @[rename-busytable.scala:27:7]
input clock, // @[rename-busytable.scala:27:7]
input reset, // @[rename-busytable.scala:27:7]
input [6:0] io_ren_uops_0_uopc, // @[rename-busytable.scala:37:14]
input [31:0] io_ren_uops_0_inst, // @[rename-busytable.scala:37:14]
input [31:0] io_ren_uops_0_debug_inst, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_rvc, // @[rename-busytable.scala:37:14]
input [39:0] io_ren_uops_0_debug_pc, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_iq_type, // @[rename-busytable.scala:37:14]
input [9:0] io_ren_uops_0_fu_code, // @[rename-busytable.scala:37:14]
input [3:0] io_ren_uops_0_ctrl_br_type, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_ctrl_op1_sel, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_ctrl_op2_sel, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_ctrl_imm_sel, // @[rename-busytable.scala:37:14]
input [4:0] io_ren_uops_0_ctrl_op_fcn, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ctrl_fcn_dw, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_ctrl_csr_cmd, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ctrl_is_load, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ctrl_is_sta, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ctrl_is_std, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_iw_state, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_iw_p1_poisoned, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_iw_p2_poisoned, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_br, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_jalr, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_jal, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_sfb, // @[rename-busytable.scala:37:14]
input [7:0] io_ren_uops_0_br_mask, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_br_tag, // @[rename-busytable.scala:37:14]
input [3:0] io_ren_uops_0_ftq_idx, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_edge_inst, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_pc_lob, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_taken, // @[rename-busytable.scala:37:14]
input [19:0] io_ren_uops_0_imm_packed, // @[rename-busytable.scala:37:14]
input [11:0] io_ren_uops_0_csr_addr, // @[rename-busytable.scala:37:14]
input [4:0] io_ren_uops_0_rob_idx, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_ldq_idx, // @[rename-busytable.scala:37:14]
input [2:0] io_ren_uops_0_stq_idx, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_rxq_idx, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_pdst, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_prs1, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_prs2, // @[rename-busytable.scala:37:14]
input [3:0] io_ren_uops_0_ppred, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_prs1_busy, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_prs2_busy, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ppred_busy, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_stale_pdst, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_exception, // @[rename-busytable.scala:37:14]
input [63:0] io_ren_uops_0_exc_cause, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_bypassable, // @[rename-busytable.scala:37:14]
input [4:0] io_ren_uops_0_mem_cmd, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_mem_size, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_mem_signed, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_fence, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_fencei, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_amo, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_uses_ldq, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_uses_stq, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_sys_pc2epc, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_is_unique, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_flush_on_commit, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ldst_is_rs1, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_ldst, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_lrs1, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_lrs2, // @[rename-busytable.scala:37:14]
input [5:0] io_ren_uops_0_lrs3, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_ldst_val, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_dst_rtype, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_lrs1_rtype, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_lrs2_rtype, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_frs3_en, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_fp_val, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_fp_single, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_xcpt_pf_if, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_xcpt_ae_if, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_xcpt_ma_if, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_bp_debug_if, // @[rename-busytable.scala:37:14]
input io_ren_uops_0_bp_xcpt_if, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_debug_fsrc, // @[rename-busytable.scala:37:14]
input [1:0] io_ren_uops_0_debug_tsrc, // @[rename-busytable.scala:37:14]
output io_busy_resps_0_prs1_busy, // @[rename-busytable.scala:37:14]
output io_busy_resps_0_prs2_busy, // @[rename-busytable.scala:37:14]
input io_rebusy_reqs_0, // @[rename-busytable.scala:37:14]
input [5:0] io_wb_pdsts_0, // @[rename-busytable.scala:37:14]
input [5:0] io_wb_pdsts_1, // @[rename-busytable.scala:37:14]
input [5:0] io_wb_pdsts_2, // @[rename-busytable.scala:37:14]
input io_wb_valids_0, // @[rename-busytable.scala:37:14]
input io_wb_valids_1, // @[rename-busytable.scala:37:14]
input io_wb_valids_2, // @[rename-busytable.scala:37:14]
output [51:0] io_debug_busytable // @[rename-busytable.scala:37:14]
);
wire [6:0] io_ren_uops_0_uopc_0 = io_ren_uops_0_uopc; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_0_inst_0 = io_ren_uops_0_inst; // @[rename-busytable.scala:27:7]
wire [31:0] io_ren_uops_0_debug_inst_0 = io_ren_uops_0_debug_inst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_rvc_0 = io_ren_uops_0_is_rvc; // @[rename-busytable.scala:27:7]
wire [39:0] io_ren_uops_0_debug_pc_0 = io_ren_uops_0_debug_pc; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_iq_type_0 = io_ren_uops_0_iq_type; // @[rename-busytable.scala:27:7]
wire [9:0] io_ren_uops_0_fu_code_0 = io_ren_uops_0_fu_code; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_0_ctrl_br_type_0 = io_ren_uops_0_ctrl_br_type; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_ctrl_op1_sel_0 = io_ren_uops_0_ctrl_op1_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_ctrl_op2_sel_0 = io_ren_uops_0_ctrl_op2_sel; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_ctrl_imm_sel_0 = io_ren_uops_0_ctrl_imm_sel; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_ctrl_op_fcn_0 = io_ren_uops_0_ctrl_op_fcn; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ctrl_fcn_dw_0 = io_ren_uops_0_ctrl_fcn_dw; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_ctrl_csr_cmd_0 = io_ren_uops_0_ctrl_csr_cmd; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ctrl_is_load_0 = io_ren_uops_0_ctrl_is_load; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ctrl_is_sta_0 = io_ren_uops_0_ctrl_is_sta; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ctrl_is_std_0 = io_ren_uops_0_ctrl_is_std; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_iw_state_0 = io_ren_uops_0_iw_state; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_p1_poisoned_0 = io_ren_uops_0_iw_p1_poisoned; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_iw_p2_poisoned_0 = io_ren_uops_0_iw_p2_poisoned; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_br_0 = io_ren_uops_0_is_br; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_jalr_0 = io_ren_uops_0_is_jalr; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_jal_0 = io_ren_uops_0_is_jal; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_sfb_0 = io_ren_uops_0_is_sfb; // @[rename-busytable.scala:27:7]
wire [7:0] io_ren_uops_0_br_mask_0 = io_ren_uops_0_br_mask; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_br_tag_0 = io_ren_uops_0_br_tag; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_0_ftq_idx_0 = io_ren_uops_0_ftq_idx; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_edge_inst_0 = io_ren_uops_0_edge_inst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_pc_lob_0 = io_ren_uops_0_pc_lob; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_taken_0 = io_ren_uops_0_taken; // @[rename-busytable.scala:27:7]
wire [19:0] io_ren_uops_0_imm_packed_0 = io_ren_uops_0_imm_packed; // @[rename-busytable.scala:27:7]
wire [11:0] io_ren_uops_0_csr_addr_0 = io_ren_uops_0_csr_addr; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_rob_idx_0 = io_ren_uops_0_rob_idx; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_ldq_idx_0 = io_ren_uops_0_ldq_idx; // @[rename-busytable.scala:27:7]
wire [2:0] io_ren_uops_0_stq_idx_0 = io_ren_uops_0_stq_idx; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_rxq_idx_0 = io_ren_uops_0_rxq_idx; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_pdst_0 = io_ren_uops_0_pdst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_prs1_0 = io_ren_uops_0_prs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_prs2_0 = io_ren_uops_0_prs2; // @[rename-busytable.scala:27:7]
wire [3:0] io_ren_uops_0_ppred_0 = io_ren_uops_0_ppred; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_prs1_busy_0 = io_ren_uops_0_prs1_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_prs2_busy_0 = io_ren_uops_0_prs2_busy; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ppred_busy_0 = io_ren_uops_0_ppred_busy; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_stale_pdst_0 = io_ren_uops_0_stale_pdst; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_exception_0 = io_ren_uops_0_exception; // @[rename-busytable.scala:27:7]
wire [63:0] io_ren_uops_0_exc_cause_0 = io_ren_uops_0_exc_cause; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_bypassable_0 = io_ren_uops_0_bypassable; // @[rename-busytable.scala:27:7]
wire [4:0] io_ren_uops_0_mem_cmd_0 = io_ren_uops_0_mem_cmd; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_mem_size_0 = io_ren_uops_0_mem_size; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_mem_signed_0 = io_ren_uops_0_mem_signed; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_fence_0 = io_ren_uops_0_is_fence; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_fencei_0 = io_ren_uops_0_is_fencei; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_amo_0 = io_ren_uops_0_is_amo; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_uses_ldq_0 = io_ren_uops_0_uses_ldq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_uses_stq_0 = io_ren_uops_0_uses_stq; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_sys_pc2epc_0 = io_ren_uops_0_is_sys_pc2epc; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_is_unique_0 = io_ren_uops_0_is_unique; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_flush_on_commit_0 = io_ren_uops_0_flush_on_commit; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ldst_is_rs1_0 = io_ren_uops_0_ldst_is_rs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_ldst_0 = io_ren_uops_0_ldst; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_lrs1_0 = io_ren_uops_0_lrs1; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_lrs2_0 = io_ren_uops_0_lrs2; // @[rename-busytable.scala:27:7]
wire [5:0] io_ren_uops_0_lrs3_0 = io_ren_uops_0_lrs3; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_ldst_val_0 = io_ren_uops_0_ldst_val; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_dst_rtype_0 = io_ren_uops_0_dst_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_lrs1_rtype_0 = io_ren_uops_0_lrs1_rtype; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_lrs2_rtype_0 = io_ren_uops_0_lrs2_rtype; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_frs3_en_0 = io_ren_uops_0_frs3_en; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_val_0 = io_ren_uops_0_fp_val; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_fp_single_0 = io_ren_uops_0_fp_single; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_xcpt_pf_if_0 = io_ren_uops_0_xcpt_pf_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_xcpt_ae_if_0 = io_ren_uops_0_xcpt_ae_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_xcpt_ma_if_0 = io_ren_uops_0_xcpt_ma_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_bp_debug_if_0 = io_ren_uops_0_bp_debug_if; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_bp_xcpt_if_0 = io_ren_uops_0_bp_xcpt_if; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_debug_fsrc_0 = io_ren_uops_0_debug_fsrc; // @[rename-busytable.scala:27:7]
wire [1:0] io_ren_uops_0_debug_tsrc_0 = io_ren_uops_0_debug_tsrc; // @[rename-busytable.scala:27:7]
wire io_rebusy_reqs_0_0 = io_rebusy_reqs_0; // @[rename-busytable.scala:27:7]
wire [5:0] io_wb_pdsts_0_0 = io_wb_pdsts_0; // @[rename-busytable.scala:27:7]
wire [5:0] io_wb_pdsts_1_0 = io_wb_pdsts_1; // @[rename-busytable.scala:27:7]
wire [5:0] io_wb_pdsts_2_0 = io_wb_pdsts_2; // @[rename-busytable.scala:27:7]
wire io_wb_valids_0_0 = io_wb_valids_0; // @[rename-busytable.scala:27:7]
wire io_wb_valids_1_0 = io_wb_valids_1; // @[rename-busytable.scala:27:7]
wire io_wb_valids_2_0 = io_wb_valids_2; // @[rename-busytable.scala:27:7]
wire io_ren_uops_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_0_prs3_busy = 1'h0; // @[rename-busytable.scala:27:7]
wire _io_busy_resps_0_prs1_busy_T_2 = 1'h0; // @[rename-busytable.scala:67:88]
wire _io_busy_resps_0_prs2_busy_T_2 = 1'h0; // @[rename-busytable.scala:68:88]
wire _io_busy_resps_0_prs3_busy_T_2 = 1'h0; // @[rename-busytable.scala:69:88]
wire [5:0] io_ren_uops_0_prs3 = 6'h0; // @[rename-busytable.scala:27:7, :37:14]
wire _io_busy_resps_0_prs1_busy_T_3; // @[rename-busytable.scala:67:67]
wire _io_busy_resps_0_prs2_busy_T_3; // @[rename-busytable.scala:68:67]
wire io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7]
wire io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7]
wire [51:0] io_debug_busytable_0; // @[rename-busytable.scala:27:7]
reg [51:0] busy_table; // @[rename-busytable.scala:48:27]
assign io_debug_busytable_0 = busy_table; // @[rename-busytable.scala:27:7, :48:27]
wire [51:0] _io_busy_resps_0_prs3_busy_T = busy_table; // @[rename-busytable.scala:48:27, :69:45]
wire [63:0] _busy_table_wb_T = 64'h1 << io_wb_pdsts_0_0; // @[OneHot.scala:58:35]
wire [51:0] _busy_table_wb_T_1 = {52{io_wb_valids_0_0}}; // @[rename-busytable.scala:27:7, :51:54]
wire [63:0] _busy_table_wb_T_2 = {12'h0, _busy_table_wb_T[51:0] & _busy_table_wb_T_1}; // @[OneHot.scala:58:35]
wire [63:0] _busy_table_wb_T_3 = 64'h1 << io_wb_pdsts_1_0; // @[OneHot.scala:58:35]
wire [51:0] _busy_table_wb_T_4 = {52{io_wb_valids_1_0}}; // @[rename-busytable.scala:27:7, :51:54]
wire [63:0] _busy_table_wb_T_5 = {12'h0, _busy_table_wb_T_3[51:0] & _busy_table_wb_T_4}; // @[OneHot.scala:58:35]
wire [63:0] _busy_table_wb_T_6 = 64'h1 << io_wb_pdsts_2_0; // @[OneHot.scala:58:35]
wire [51:0] _busy_table_wb_T_7 = {52{io_wb_valids_2_0}}; // @[rename-busytable.scala:27:7, :51:54]
wire [63:0] _busy_table_wb_T_8 = {12'h0, _busy_table_wb_T_6[51:0] & _busy_table_wb_T_7}; // @[OneHot.scala:58:35]
wire [63:0] _busy_table_wb_T_9 = _busy_table_wb_T_2 | _busy_table_wb_T_5; // @[rename-busytable.scala:51:{48,88}]
wire [63:0] _busy_table_wb_T_10 = _busy_table_wb_T_9 | _busy_table_wb_T_8; // @[rename-busytable.scala:51:{48,88}]
wire [63:0] _busy_table_wb_T_11 = ~_busy_table_wb_T_10; // @[rename-busytable.scala:50:36, :51:88]
wire [63:0] busy_table_wb = {12'h0, _busy_table_wb_T_11[51:0] & busy_table}; // @[rename-busytable.scala:48:27, :50:{34,36}, :51:48]
wire [63:0] _busy_table_next_T = 64'h1 << io_ren_uops_0_pdst_0; // @[OneHot.scala:58:35]
wire [51:0] _busy_table_next_T_1 = {52{io_rebusy_reqs_0_0}}; // @[rename-busytable.scala:27:7, :54:55]
wire [63:0] _busy_table_next_T_2 = {12'h0, _busy_table_next_T[51:0] & _busy_table_next_T_1}; // @[OneHot.scala:58:35]
wire [63:0] busy_table_next = busy_table_wb | _busy_table_next_T_2; // @[rename-busytable.scala:50:34, :53:39, :54:49]
wire [51:0] _io_busy_resps_0_prs1_busy_T = busy_table >> io_ren_uops_0_prs1_0; // @[rename-busytable.scala:27:7, :48:27, :67:45]
wire _io_busy_resps_0_prs1_busy_T_1 = _io_busy_resps_0_prs1_busy_T[0]; // @[rename-busytable.scala:67:45]
assign _io_busy_resps_0_prs1_busy_T_3 = _io_busy_resps_0_prs1_busy_T_1; // @[rename-busytable.scala:67:{45,67}]
assign io_busy_resps_0_prs1_busy_0 = _io_busy_resps_0_prs1_busy_T_3; // @[rename-busytable.scala:27:7, :67:67]
wire [51:0] _io_busy_resps_0_prs2_busy_T = busy_table >> io_ren_uops_0_prs2_0; // @[rename-busytable.scala:27:7, :48:27, :68:45]
wire _io_busy_resps_0_prs2_busy_T_1 = _io_busy_resps_0_prs2_busy_T[0]; // @[rename-busytable.scala:68:45]
assign _io_busy_resps_0_prs2_busy_T_3 = _io_busy_resps_0_prs2_busy_T_1; // @[rename-busytable.scala:68:{45,67}]
assign io_busy_resps_0_prs2_busy_0 = _io_busy_resps_0_prs2_busy_T_3; // @[rename-busytable.scala:27:7, :68:67]
wire _io_busy_resps_0_prs3_busy_T_1 = _io_busy_resps_0_prs3_busy_T[0]; // @[rename-busytable.scala:69:45]
wire _io_busy_resps_0_prs3_busy_T_3 = _io_busy_resps_0_prs3_busy_T_1; // @[rename-busytable.scala:69:{45,67}]
always @(posedge clock) begin // @[rename-busytable.scala:27:7]
if (reset) // @[rename-busytable.scala:27:7]
busy_table <= 52'h0; // @[rename-busytable.scala:48:27]
else // @[rename-busytable.scala:27:7]
busy_table <= busy_table_next[51:0]; // @[rename-busytable.scala:48:27, :53:39, :56:14]
always @(posedge)
assign io_busy_resps_0_prs1_busy = io_busy_resps_0_prs1_busy_0; // @[rename-busytable.scala:27:7]
assign io_busy_resps_0_prs2_busy = io_busy_resps_0_prs2_busy_0; // @[rename-busytable.scala:27:7]
assign io_debug_busytable = io_debug_busytable_0; // @[rename-busytable.scala:27:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.conf, UInt<1>(0h0)
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_229 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_229( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_78 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}}
inst input_buffer of InputBuffer_78
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter5_RouteComputerReq_6
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id)
when _T_10 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1)
node _T_11 = eq(UInt<2>(0h2), io.in.flit[0].bits.flow.egress_node_id)
when _T_11 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
connect route_arbiter.io.in[2].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[2].bits.flow.egress_node_id
invalidate route_arbiter.io.in[2].bits.flow.egress_node
invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[2].bits.flow.ingress_node
invalidate route_arbiter.io.in[2].bits.flow.vnet_id
invalidate route_arbiter.io.in[2].bits.src_virt_id
connect route_arbiter.io.in[3].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[3].bits.flow.egress_node_id
invalidate route_arbiter.io.in[3].bits.flow.egress_node
invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[3].bits.flow.ingress_node
invalidate route_arbiter.io.in[3].bits.flow.vnet_id
invalidate route_arbiter.io.in[3].bits.src_virt_id
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_12 :
connect states[4].g, UInt<3>(0h2)
node _T_13 = and(io.router_req.ready, io.router_req.valid)
when _T_13 :
node _T_14 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_14, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_18 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_19 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_19 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_20 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_20 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_21 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_22 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<5>, clock, reset, UInt<5>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}[5]
wire vcalloc_vals : UInt<1>[5]
node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0))
node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15)
node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16)
node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17)
node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18)
node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20)
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23)
node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_23 = and(io.router_req.ready, io.router_req.valid)
when _T_23 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_24 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_25 = or(_T_24, vcalloc_vals[2])
node _T_26 = or(_T_25, vcalloc_vals[3])
node _T_27 = or(_T_26, vcalloc_vals[4])
when _T_27 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = bits(vcalloc_sel, 0, 0)
node _mask_T_9 = bits(vcalloc_sel, 1, 1)
node _mask_T_10 = bits(vcalloc_sel, 2, 2)
node _mask_T_11 = bits(vcalloc_sel, 3, 3)
node _mask_T_12 = bits(vcalloc_sel, 4, 4)
node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0))
node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0))
node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0))
node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0))
node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0))
node _mask_T_18 = or(_mask_T_13, _mask_T_14)
node _mask_T_19 = or(_mask_T_18, _mask_T_15)
node _mask_T_20 = or(_mask_T_19, _mask_T_16)
node _mask_T_21 = or(_mask_T_20, _mask_T_17)
wire _mask_WIRE : UInt<5>
connect _mask_WIRE, _mask_T_21
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5]
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6)
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8)
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35)
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[1]
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51)
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53)
node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58
connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[1]
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>[1]
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_76
connect _io_vcalloc_req_bits_WIRE_12[0], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_12
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78)
node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79)
node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80)
node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_85
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_14
wire _io_vcalloc_req_bits_WIRE_15 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_94
connect _io_vcalloc_req_bits_WIRE_15.egress_node_id, _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96)
node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97)
node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98)
node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_103
connect _io_vcalloc_req_bits_WIRE_15.egress_node, _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_15.ingress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_121
connect _io_vcalloc_req_bits_WIRE_15.ingress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123)
node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124)
node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125)
node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_130
connect _io_vcalloc_req_bits_WIRE_15.vnet_id, _io_vcalloc_req_bits_WIRE_20
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_15
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`3`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`0`[3]
invalidate vcalloc_reqs[1].vc_sel.`0`[4]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
connect vcalloc_vals[2], UInt<1>(0h0)
invalidate vcalloc_reqs[2].vc_sel.`0`[0]
invalidate vcalloc_reqs[2].vc_sel.`0`[1]
invalidate vcalloc_reqs[2].vc_sel.`0`[2]
invalidate vcalloc_reqs[2].vc_sel.`0`[3]
invalidate vcalloc_reqs[2].vc_sel.`0`[4]
invalidate vcalloc_reqs[2].vc_sel.`1`[0]
invalidate vcalloc_reqs[2].vc_sel.`2`[0]
invalidate vcalloc_reqs[2].vc_sel.`3`[0]
invalidate vcalloc_reqs[2].in_vc
invalidate vcalloc_reqs[2].flow.egress_node_id
invalidate vcalloc_reqs[2].flow.egress_node
invalidate vcalloc_reqs[2].flow.ingress_node_id
invalidate vcalloc_reqs[2].flow.ingress_node
invalidate vcalloc_reqs[2].flow.vnet_id
connect vcalloc_vals[3], UInt<1>(0h0)
invalidate vcalloc_reqs[3].vc_sel.`0`[0]
invalidate vcalloc_reqs[3].vc_sel.`0`[1]
invalidate vcalloc_reqs[3].vc_sel.`0`[2]
invalidate vcalloc_reqs[3].vc_sel.`0`[3]
invalidate vcalloc_reqs[3].vc_sel.`0`[4]
invalidate vcalloc_reqs[3].vc_sel.`1`[0]
invalidate vcalloc_reqs[3].vc_sel.`2`[0]
invalidate vcalloc_reqs[3].vc_sel.`3`[0]
invalidate vcalloc_reqs[3].in_vc
invalidate vcalloc_reqs[3].flow.egress_node_id
invalidate vcalloc_reqs[3].flow.egress_node
invalidate vcalloc_reqs[3].flow.ingress_node_id
invalidate vcalloc_reqs[3].flow.ingress_node
invalidate vcalloc_reqs[3].flow.vnet_id
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_28 = bits(vcalloc_sel, 4, 4)
node _T_29 = and(vcalloc_vals[4], _T_28)
node _T_30 = and(_T_29, io.vcalloc_req.ready)
when _T_30 :
connect states[4].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0)
node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5)
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0)
node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready)
node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_9
node _T_31 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_31 :
node _T_32 = bits(vcalloc_sel, 0, 0)
when _T_32 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_33 = eq(states[0].g, UInt<3>(0h2))
node _T_34 = asUInt(reset)
node _T_35 = eq(_T_34, UInt<1>(0h0))
when _T_35 :
node _T_36 = eq(_T_33, UInt<1>(0h0))
when _T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_33, UInt<1>(0h1), "") : assert_3
node _T_37 = bits(vcalloc_sel, 1, 1)
when _T_37 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_38 = eq(states[1].g, UInt<3>(0h2))
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
node _T_41 = eq(_T_38, UInt<1>(0h0))
when _T_41 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_38, UInt<1>(0h1), "") : assert_4
node _T_42 = bits(vcalloc_sel, 2, 2)
when _T_42 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_43 = eq(states[2].g, UInt<3>(0h2))
node _T_44 = asUInt(reset)
node _T_45 = eq(_T_44, UInt<1>(0h0))
when _T_45 :
node _T_46 = eq(_T_43, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_43, UInt<1>(0h1), "") : assert_5
node _T_47 = bits(vcalloc_sel, 3, 3)
when _T_47 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_48 = eq(states[3].g, UInt<3>(0h2))
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_48, UInt<1>(0h1), "") : assert_6
node _T_52 = bits(vcalloc_sel, 4, 4)
when _T_52 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_53 = eq(states[4].g, UInt<3>(0h2))
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_53, UInt<1>(0h1), "") : assert_7
inst salloc_arb of SwitchArbiter_206
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[2].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[2].bits.tail
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[2].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[3].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[3].bits.tail
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[3].bits.vc_sel.`3`[0]
node credit_available_lo = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_hi_hi = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3])
node credit_available_hi = cat(credit_available_hi_hi, states[4].vc_sel.`0`[2])
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_1 = cat(states[4].vc_sel.`1`[0], _credit_available_T)
node credit_available_hi_1 = cat(states[4].vc_sel.`3`[0], states[4].vc_sel.`2`[0])
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3])
node credit_available_hi_2 = cat(credit_available_hi_hi_1, io.out_credit_available.`0`[2])
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2)
node credit_available_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_57 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_58 = and(_T_57, input_buffer.io.deq[4].bits.tail)
when _T_58 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0)
node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9)
node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0)
node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13)
node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_17
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7)
node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8)
node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9)
node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14
node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_16
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[5]}
wire _vc_sel_WIRE : UInt<1>[5]
node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6)
node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8)
node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_13
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_22
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25)
node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26)
node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_31
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33)
node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34)
node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35)
node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_40
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_49
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_6 : UInt<1>[1]
node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51)
node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52)
node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53)
node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_58
connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_6
wire _vc_sel_WIRE_8 : UInt<1>[1]
node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_67
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
connect vc_sel.`2`, _vc_sel_WIRE_8
wire _vc_sel_WIRE_10 : UInt<1>[1]
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70)
node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71)
node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_76
connect _vc_sel_WIRE_10[0], _vc_sel_WIRE_11
connect vc_sel.`3`, _vc_sel_WIRE_10
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4])
node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3])
node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2])
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_11 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_12 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_13 = or(_virt_channel_T_12, _virt_channel_T_10)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_11)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_14
node _T_59 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_59 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6)
node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7)
node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8)
node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6)
node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7)
node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8)
node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6)
node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7)
node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8)
node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6)
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8)
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33)
node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34)
node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35)
node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`3`[0]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`0`[3]
invalidate states[1].vc_sel.`0`[4]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].g
invalidate states[2].fifo_deps
invalidate states[2].flow.egress_node_id
invalidate states[2].flow.egress_node
invalidate states[2].flow.ingress_node_id
invalidate states[2].flow.ingress_node
invalidate states[2].flow.vnet_id
invalidate states[2].vc_sel.`0`[0]
invalidate states[2].vc_sel.`0`[1]
invalidate states[2].vc_sel.`0`[2]
invalidate states[2].vc_sel.`0`[3]
invalidate states[2].vc_sel.`0`[4]
invalidate states[2].vc_sel.`1`[0]
invalidate states[2].vc_sel.`2`[0]
invalidate states[2].vc_sel.`3`[0]
invalidate states[2].g
invalidate states[3].fifo_deps
invalidate states[3].flow.egress_node_id
invalidate states[3].flow.egress_node
invalidate states[3].flow.ingress_node_id
invalidate states[3].flow.ingress_node
invalidate states[3].flow.vnet_id
invalidate states[3].vc_sel.`0`[0]
invalidate states[3].vc_sel.`0`[1]
invalidate states[3].vc_sel.`0`[2]
invalidate states[3].vc_sel.`0`[3]
invalidate states[3].vc_sel.`0`[4]
invalidate states[3].vc_sel.`1`[0]
invalidate states[3].vc_sel.`2`[0]
invalidate states[3].vc_sel.`3`[0]
invalidate states[3].g
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
node _T_60 = asUInt(reset)
when _T_60 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0) | module InputUnit_78( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [4:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [4:0] mask; // @[InputUnit.scala:250:21]
wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32]
wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71]
wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_26 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_52
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_26
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _T_1 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _T_2 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _T_3 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _T_4 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _T_5 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _T_6 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _T_7 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _T_8 = or(_T, _T_1)
node _T_9 = or(_T_8, _T_2)
node _T_10 = or(_T_9, _T_3)
node _T_11 = or(_T_10, _T_4)
node _T_12 = or(_T_11, _T_5)
node _T_13 = or(_T_12, _T_6)
node _T_14 = or(_T_13, _T_7)
node _T_15 = eq(_T_14, UInt<1>(0h0))
node _T_16 = and(io.in.valid, _T_15)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_17, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0ha)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<2>(0h3)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0hb), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<4>(0hd), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<4>(0h8), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_5, UInt<3>(0h4), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_6, UInt<4>(0he), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_7, UInt<3>(0h7), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_T_16, _route_buffer_io_enq_bits_flow_egress_node_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_T_17, _route_buffer_io_enq_bits_flow_egress_node_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_T_18, _route_buffer_io_enq_bits_flow_egress_node_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_T_19, _route_buffer_io_enq_bits_flow_egress_node_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_T_20, _route_buffer_io_enq_bits_flow_egress_node_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_T_21, _route_buffer_io_enq_bits_flow_egress_node_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_22
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<4>(0hc), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<4>(0he), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<3>(0h4), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<2>(0h2), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<4>(0ha), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = eq(UInt<3>(0h6), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = eq(UInt<4>(0h8), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_6, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_7, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_16, _route_buffer_io_enq_bits_flow_egress_node_id_T_10)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_18 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_17, _route_buffer_io_enq_bits_flow_egress_node_id_T_11)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_19 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_18, _route_buffer_io_enq_bits_flow_egress_node_id_T_12)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_20 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_19, _route_buffer_io_enq_bits_flow_egress_node_id_T_13)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_21 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_20, _route_buffer_io_enq_bits_flow_egress_node_id_T_14)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_22 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_21, _route_buffer_io_enq_bits_flow_egress_node_id_T_15)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_22
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0ha))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
connect route_q.io.enq.bits.vc_sel.`3`[0], io.router_resp.vc_sel.`3`[0]
node _T_21 = and(io.in.ready, io.in.valid)
node _T_22 = and(_T_21, io.in.bits.head)
node _T_23 = and(_T_22, at_dest)
when _T_23 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h0)
node _T_24 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
when _T_24 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_25 = eq(UInt<5>(0h1f), io.in.bits.egress_id)
when _T_25 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_26 = eq(UInt<6>(0h20), io.in.bits.egress_id)
when _T_26 :
connect route_q.io.enq.bits.vc_sel.`3`[0], UInt<1>(0h1)
node _T_27 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_28 = and(route_q.io.enq.valid, _T_27)
node _T_29 = eq(_T_28, UInt<1>(0h0))
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_53
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_26
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.vc_sel.`3`, route_q.io.deq.bits.vc_sel.`3`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`3`[0], io.vcalloc_resp.vc_sel.`3`[0]
node _T_33 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_34 = and(vcalloc_q.io.enq.valid, _T_33)
node _T_35 = eq(_T_34, UInt<1>(0h0))
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
node _T_38 = eq(_T_35, UInt<1>(0h0))
when _T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_35, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.vc_sel.`3`, vcalloc_q.io.deq.bits.vc_sel.`3`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_lo_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[0], _c_T)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`3`[0], vcalloc_q.io.deq.bits.vc_sel.`2`[0])
node _c_T_1 = cat(c_hi_1, c_lo_1)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node c_lo_2 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_2)
node c_lo_3 = cat(io.out_credit_available.`1`[0], _c_T_2)
node c_hi_3 = cat(io.out_credit_available.`3`[0], io.out_credit_available.`2`[0])
node _c_T_3 = cat(c_hi_3, c_lo_3)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(vcalloc_q.io.deq.bits.vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_12, _out_bundle_bits_out_virt_channel_T_10)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_11)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_26( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'hC; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h4; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h2; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hA; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h6; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h8; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_16 = (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 4'hB : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'hD : 4'h0); // @[Mux.scala:30:73]
wire [1:0] _GEN_0 = _route_buffer_io_enq_bits_flow_egress_node_T_16[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, 1'h0}; // @[Mux.scala:30:73]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_21 = {_route_buffer_io_enq_bits_flow_egress_node_T_16[3] | _route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_16[2] | _route_buffer_io_enq_bits_flow_egress_node_id_T_5, _GEN_0[1], _GEN_0[0] | _route_buffer_io_enq_bits_flow_egress_node_id_T_3} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'hE : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _GEN_1 = _route_buffer_io_enq_bits_flow_egress_node_T_21[2:0] | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_7}}; // @[Mux.scala:30:73]
wire [3:0] _GEN_2 = {_route_buffer_io_enq_bits_flow_egress_node_T_21[3], _GEN_1}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_2 == 4'hA; // @[Decoupled.scala:51:35]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_2 != 4'hA; // @[Decoupled.scala:51:35]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_15 :
input clock : Clock
input reset : Reset
output io : { flip in_a : { bits : UInt<32>}, flip in_b : { bits : UInt<32>}, flip in_c : { bits : UInt<32>}, out_d : { bits : UInt<32>}}
node io_out_d_m1_rec_rawIn_sign = bits(io.in_a.bits, 31, 31)
node io_out_d_m1_rec_rawIn_expIn = bits(io.in_a.bits, 30, 23)
node io_out_d_m1_rec_rawIn_fractIn = bits(io.in_a.bits, 22, 0)
node io_out_d_m1_rec_rawIn_isZeroExpIn = eq(io_out_d_m1_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_m1_rec_rawIn_isZeroFractIn = eq(io_out_d_m1_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_normDist_T = bits(io_out_d_m1_rec_rawIn_fractIn, 0, 0)
node _io_out_d_m1_rec_rawIn_normDist_T_1 = bits(io_out_d_m1_rec_rawIn_fractIn, 1, 1)
node _io_out_d_m1_rec_rawIn_normDist_T_2 = bits(io_out_d_m1_rec_rawIn_fractIn, 2, 2)
node _io_out_d_m1_rec_rawIn_normDist_T_3 = bits(io_out_d_m1_rec_rawIn_fractIn, 3, 3)
node _io_out_d_m1_rec_rawIn_normDist_T_4 = bits(io_out_d_m1_rec_rawIn_fractIn, 4, 4)
node _io_out_d_m1_rec_rawIn_normDist_T_5 = bits(io_out_d_m1_rec_rawIn_fractIn, 5, 5)
node _io_out_d_m1_rec_rawIn_normDist_T_6 = bits(io_out_d_m1_rec_rawIn_fractIn, 6, 6)
node _io_out_d_m1_rec_rawIn_normDist_T_7 = bits(io_out_d_m1_rec_rawIn_fractIn, 7, 7)
node _io_out_d_m1_rec_rawIn_normDist_T_8 = bits(io_out_d_m1_rec_rawIn_fractIn, 8, 8)
node _io_out_d_m1_rec_rawIn_normDist_T_9 = bits(io_out_d_m1_rec_rawIn_fractIn, 9, 9)
node _io_out_d_m1_rec_rawIn_normDist_T_10 = bits(io_out_d_m1_rec_rawIn_fractIn, 10, 10)
node _io_out_d_m1_rec_rawIn_normDist_T_11 = bits(io_out_d_m1_rec_rawIn_fractIn, 11, 11)
node _io_out_d_m1_rec_rawIn_normDist_T_12 = bits(io_out_d_m1_rec_rawIn_fractIn, 12, 12)
node _io_out_d_m1_rec_rawIn_normDist_T_13 = bits(io_out_d_m1_rec_rawIn_fractIn, 13, 13)
node _io_out_d_m1_rec_rawIn_normDist_T_14 = bits(io_out_d_m1_rec_rawIn_fractIn, 14, 14)
node _io_out_d_m1_rec_rawIn_normDist_T_15 = bits(io_out_d_m1_rec_rawIn_fractIn, 15, 15)
node _io_out_d_m1_rec_rawIn_normDist_T_16 = bits(io_out_d_m1_rec_rawIn_fractIn, 16, 16)
node _io_out_d_m1_rec_rawIn_normDist_T_17 = bits(io_out_d_m1_rec_rawIn_fractIn, 17, 17)
node _io_out_d_m1_rec_rawIn_normDist_T_18 = bits(io_out_d_m1_rec_rawIn_fractIn, 18, 18)
node _io_out_d_m1_rec_rawIn_normDist_T_19 = bits(io_out_d_m1_rec_rawIn_fractIn, 19, 19)
node _io_out_d_m1_rec_rawIn_normDist_T_20 = bits(io_out_d_m1_rec_rawIn_fractIn, 20, 20)
node _io_out_d_m1_rec_rawIn_normDist_T_21 = bits(io_out_d_m1_rec_rawIn_fractIn, 21, 21)
node _io_out_d_m1_rec_rawIn_normDist_T_22 = bits(io_out_d_m1_rec_rawIn_fractIn, 22, 22)
node _io_out_d_m1_rec_rawIn_normDist_T_23 = mux(_io_out_d_m1_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_m1_rec_rawIn_normDist_T_24 = mux(_io_out_d_m1_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m1_rec_rawIn_normDist_T_23)
node _io_out_d_m1_rec_rawIn_normDist_T_25 = mux(_io_out_d_m1_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m1_rec_rawIn_normDist_T_24)
node _io_out_d_m1_rec_rawIn_normDist_T_26 = mux(_io_out_d_m1_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m1_rec_rawIn_normDist_T_25)
node _io_out_d_m1_rec_rawIn_normDist_T_27 = mux(_io_out_d_m1_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m1_rec_rawIn_normDist_T_26)
node _io_out_d_m1_rec_rawIn_normDist_T_28 = mux(_io_out_d_m1_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m1_rec_rawIn_normDist_T_27)
node _io_out_d_m1_rec_rawIn_normDist_T_29 = mux(_io_out_d_m1_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m1_rec_rawIn_normDist_T_28)
node _io_out_d_m1_rec_rawIn_normDist_T_30 = mux(_io_out_d_m1_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m1_rec_rawIn_normDist_T_29)
node _io_out_d_m1_rec_rawIn_normDist_T_31 = mux(_io_out_d_m1_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m1_rec_rawIn_normDist_T_30)
node _io_out_d_m1_rec_rawIn_normDist_T_32 = mux(_io_out_d_m1_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m1_rec_rawIn_normDist_T_31)
node _io_out_d_m1_rec_rawIn_normDist_T_33 = mux(_io_out_d_m1_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m1_rec_rawIn_normDist_T_32)
node _io_out_d_m1_rec_rawIn_normDist_T_34 = mux(_io_out_d_m1_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m1_rec_rawIn_normDist_T_33)
node _io_out_d_m1_rec_rawIn_normDist_T_35 = mux(_io_out_d_m1_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m1_rec_rawIn_normDist_T_34)
node _io_out_d_m1_rec_rawIn_normDist_T_36 = mux(_io_out_d_m1_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m1_rec_rawIn_normDist_T_35)
node _io_out_d_m1_rec_rawIn_normDist_T_37 = mux(_io_out_d_m1_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m1_rec_rawIn_normDist_T_36)
node _io_out_d_m1_rec_rawIn_normDist_T_38 = mux(_io_out_d_m1_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m1_rec_rawIn_normDist_T_37)
node _io_out_d_m1_rec_rawIn_normDist_T_39 = mux(_io_out_d_m1_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m1_rec_rawIn_normDist_T_38)
node _io_out_d_m1_rec_rawIn_normDist_T_40 = mux(_io_out_d_m1_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m1_rec_rawIn_normDist_T_39)
node _io_out_d_m1_rec_rawIn_normDist_T_41 = mux(_io_out_d_m1_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m1_rec_rawIn_normDist_T_40)
node _io_out_d_m1_rec_rawIn_normDist_T_42 = mux(_io_out_d_m1_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m1_rec_rawIn_normDist_T_41)
node _io_out_d_m1_rec_rawIn_normDist_T_43 = mux(_io_out_d_m1_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m1_rec_rawIn_normDist_T_42)
node io_out_d_m1_rec_rawIn_normDist = mux(_io_out_d_m1_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m1_rec_rawIn_normDist_T_43)
node _io_out_d_m1_rec_rawIn_subnormFract_T = dshl(io_out_d_m1_rec_rawIn_fractIn, io_out_d_m1_rec_rawIn_normDist)
node _io_out_d_m1_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m1_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_m1_rec_rawIn_subnormFract = shl(_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_m1_rec_rawIn_adjustedExp_T = xor(io_out_d_m1_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, _io_out_d_m1_rec_rawIn_adjustedExp_T, io_out_d_m1_rec_rawIn_expIn)
node _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m1_rec_rawIn_adjustedExp_T_2)
node _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m1_rec_rawIn_adjustedExp_T_1, _io_out_d_m1_rec_rawIn_adjustedExp_T_3)
node io_out_d_m1_rec_rawIn_adjustedExp = tail(_io_out_d_m1_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_m1_rec_rawIn_isZero = and(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_isZeroFractIn)
node _io_out_d_m1_rec_rawIn_isSpecial_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_m1_rec_rawIn_isSpecial = eq(_io_out_d_m1_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_m1_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_m1_rec_rawIn_out_isNaN_T = eq(io_out_d_m1_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m1_rec_rawIn_isSpecial, _io_out_d_m1_rec_rawIn_out_isNaN_T)
connect io_out_d_m1_rec_rawIn.isNaN, _io_out_d_m1_rec_rawIn_out_isNaN_T_1
node _io_out_d_m1_rec_rawIn_out_isInf_T = and(io_out_d_m1_rec_rawIn_isSpecial, io_out_d_m1_rec_rawIn_isZeroFractIn)
connect io_out_d_m1_rec_rawIn.isInf, _io_out_d_m1_rec_rawIn_out_isInf_T
connect io_out_d_m1_rec_rawIn.isZero, io_out_d_m1_rec_rawIn_isZero
connect io_out_d_m1_rec_rawIn.sign, io_out_d_m1_rec_rawIn_sign
node _io_out_d_m1_rec_rawIn_out_sExp_T = bits(io_out_d_m1_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_m1_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m1_rec_rawIn_out_sExp_T)
connect io_out_d_m1_rec_rawIn.sExp, _io_out_d_m1_rec_rawIn_out_sExp_T_1
node _io_out_d_m1_rec_rawIn_out_sig_T = eq(io_out_d_m1_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_m1_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m1_rec_rawIn_out_sig_T)
node _io_out_d_m1_rec_rawIn_out_sig_T_2 = mux(io_out_d_m1_rec_rawIn_isZeroExpIn, io_out_d_m1_rec_rawIn_subnormFract, io_out_d_m1_rec_rawIn_fractIn)
node _io_out_d_m1_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2)
connect io_out_d_m1_rec_rawIn.sig, _io_out_d_m1_rec_rawIn_out_sig_T_3
node _io_out_d_m1_rec_T = bits(io_out_d_m1_rec_rawIn.sExp, 8, 6)
node _io_out_d_m1_rec_T_1 = mux(io_out_d_m1_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m1_rec_T)
node _io_out_d_m1_rec_T_2 = mux(io_out_d_m1_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_m1_rec_T_3 = or(_io_out_d_m1_rec_T_1, _io_out_d_m1_rec_T_2)
node _io_out_d_m1_rec_T_4 = cat(io_out_d_m1_rec_rawIn.sign, _io_out_d_m1_rec_T_3)
node _io_out_d_m1_rec_T_5 = bits(io_out_d_m1_rec_rawIn.sExp, 5, 0)
node _io_out_d_m1_rec_T_6 = cat(_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5)
node _io_out_d_m1_rec_T_7 = bits(io_out_d_m1_rec_rawIn.sig, 22, 0)
node io_out_d_m1_rec = cat(_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7)
node io_out_d_m2_rec_rawIn_sign = bits(io.in_b.bits, 31, 31)
node io_out_d_m2_rec_rawIn_expIn = bits(io.in_b.bits, 30, 23)
node io_out_d_m2_rec_rawIn_fractIn = bits(io.in_b.bits, 22, 0)
node io_out_d_m2_rec_rawIn_isZeroExpIn = eq(io_out_d_m2_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_m2_rec_rawIn_isZeroFractIn = eq(io_out_d_m2_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_normDist_T = bits(io_out_d_m2_rec_rawIn_fractIn, 0, 0)
node _io_out_d_m2_rec_rawIn_normDist_T_1 = bits(io_out_d_m2_rec_rawIn_fractIn, 1, 1)
node _io_out_d_m2_rec_rawIn_normDist_T_2 = bits(io_out_d_m2_rec_rawIn_fractIn, 2, 2)
node _io_out_d_m2_rec_rawIn_normDist_T_3 = bits(io_out_d_m2_rec_rawIn_fractIn, 3, 3)
node _io_out_d_m2_rec_rawIn_normDist_T_4 = bits(io_out_d_m2_rec_rawIn_fractIn, 4, 4)
node _io_out_d_m2_rec_rawIn_normDist_T_5 = bits(io_out_d_m2_rec_rawIn_fractIn, 5, 5)
node _io_out_d_m2_rec_rawIn_normDist_T_6 = bits(io_out_d_m2_rec_rawIn_fractIn, 6, 6)
node _io_out_d_m2_rec_rawIn_normDist_T_7 = bits(io_out_d_m2_rec_rawIn_fractIn, 7, 7)
node _io_out_d_m2_rec_rawIn_normDist_T_8 = bits(io_out_d_m2_rec_rawIn_fractIn, 8, 8)
node _io_out_d_m2_rec_rawIn_normDist_T_9 = bits(io_out_d_m2_rec_rawIn_fractIn, 9, 9)
node _io_out_d_m2_rec_rawIn_normDist_T_10 = bits(io_out_d_m2_rec_rawIn_fractIn, 10, 10)
node _io_out_d_m2_rec_rawIn_normDist_T_11 = bits(io_out_d_m2_rec_rawIn_fractIn, 11, 11)
node _io_out_d_m2_rec_rawIn_normDist_T_12 = bits(io_out_d_m2_rec_rawIn_fractIn, 12, 12)
node _io_out_d_m2_rec_rawIn_normDist_T_13 = bits(io_out_d_m2_rec_rawIn_fractIn, 13, 13)
node _io_out_d_m2_rec_rawIn_normDist_T_14 = bits(io_out_d_m2_rec_rawIn_fractIn, 14, 14)
node _io_out_d_m2_rec_rawIn_normDist_T_15 = bits(io_out_d_m2_rec_rawIn_fractIn, 15, 15)
node _io_out_d_m2_rec_rawIn_normDist_T_16 = bits(io_out_d_m2_rec_rawIn_fractIn, 16, 16)
node _io_out_d_m2_rec_rawIn_normDist_T_17 = bits(io_out_d_m2_rec_rawIn_fractIn, 17, 17)
node _io_out_d_m2_rec_rawIn_normDist_T_18 = bits(io_out_d_m2_rec_rawIn_fractIn, 18, 18)
node _io_out_d_m2_rec_rawIn_normDist_T_19 = bits(io_out_d_m2_rec_rawIn_fractIn, 19, 19)
node _io_out_d_m2_rec_rawIn_normDist_T_20 = bits(io_out_d_m2_rec_rawIn_fractIn, 20, 20)
node _io_out_d_m2_rec_rawIn_normDist_T_21 = bits(io_out_d_m2_rec_rawIn_fractIn, 21, 21)
node _io_out_d_m2_rec_rawIn_normDist_T_22 = bits(io_out_d_m2_rec_rawIn_fractIn, 22, 22)
node _io_out_d_m2_rec_rawIn_normDist_T_23 = mux(_io_out_d_m2_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_m2_rec_rawIn_normDist_T_24 = mux(_io_out_d_m2_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_m2_rec_rawIn_normDist_T_23)
node _io_out_d_m2_rec_rawIn_normDist_T_25 = mux(_io_out_d_m2_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_m2_rec_rawIn_normDist_T_24)
node _io_out_d_m2_rec_rawIn_normDist_T_26 = mux(_io_out_d_m2_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_m2_rec_rawIn_normDist_T_25)
node _io_out_d_m2_rec_rawIn_normDist_T_27 = mux(_io_out_d_m2_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_m2_rec_rawIn_normDist_T_26)
node _io_out_d_m2_rec_rawIn_normDist_T_28 = mux(_io_out_d_m2_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_m2_rec_rawIn_normDist_T_27)
node _io_out_d_m2_rec_rawIn_normDist_T_29 = mux(_io_out_d_m2_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_m2_rec_rawIn_normDist_T_28)
node _io_out_d_m2_rec_rawIn_normDist_T_30 = mux(_io_out_d_m2_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_m2_rec_rawIn_normDist_T_29)
node _io_out_d_m2_rec_rawIn_normDist_T_31 = mux(_io_out_d_m2_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_m2_rec_rawIn_normDist_T_30)
node _io_out_d_m2_rec_rawIn_normDist_T_32 = mux(_io_out_d_m2_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_m2_rec_rawIn_normDist_T_31)
node _io_out_d_m2_rec_rawIn_normDist_T_33 = mux(_io_out_d_m2_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_m2_rec_rawIn_normDist_T_32)
node _io_out_d_m2_rec_rawIn_normDist_T_34 = mux(_io_out_d_m2_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_m2_rec_rawIn_normDist_T_33)
node _io_out_d_m2_rec_rawIn_normDist_T_35 = mux(_io_out_d_m2_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_m2_rec_rawIn_normDist_T_34)
node _io_out_d_m2_rec_rawIn_normDist_T_36 = mux(_io_out_d_m2_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_m2_rec_rawIn_normDist_T_35)
node _io_out_d_m2_rec_rawIn_normDist_T_37 = mux(_io_out_d_m2_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_m2_rec_rawIn_normDist_T_36)
node _io_out_d_m2_rec_rawIn_normDist_T_38 = mux(_io_out_d_m2_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_m2_rec_rawIn_normDist_T_37)
node _io_out_d_m2_rec_rawIn_normDist_T_39 = mux(_io_out_d_m2_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_m2_rec_rawIn_normDist_T_38)
node _io_out_d_m2_rec_rawIn_normDist_T_40 = mux(_io_out_d_m2_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_m2_rec_rawIn_normDist_T_39)
node _io_out_d_m2_rec_rawIn_normDist_T_41 = mux(_io_out_d_m2_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_m2_rec_rawIn_normDist_T_40)
node _io_out_d_m2_rec_rawIn_normDist_T_42 = mux(_io_out_d_m2_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_m2_rec_rawIn_normDist_T_41)
node _io_out_d_m2_rec_rawIn_normDist_T_43 = mux(_io_out_d_m2_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_m2_rec_rawIn_normDist_T_42)
node io_out_d_m2_rec_rawIn_normDist = mux(_io_out_d_m2_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_m2_rec_rawIn_normDist_T_43)
node _io_out_d_m2_rec_rawIn_subnormFract_T = dshl(io_out_d_m2_rec_rawIn_fractIn, io_out_d_m2_rec_rawIn_normDist)
node _io_out_d_m2_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_m2_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_m2_rec_rawIn_subnormFract = shl(_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_m2_rec_rawIn_adjustedExp_T = xor(io_out_d_m2_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, _io_out_d_m2_rec_rawIn_adjustedExp_T, io_out_d_m2_rec_rawIn_expIn)
node _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_m2_rec_rawIn_adjustedExp_T_2)
node _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_m2_rec_rawIn_adjustedExp_T_1, _io_out_d_m2_rec_rawIn_adjustedExp_T_3)
node io_out_d_m2_rec_rawIn_adjustedExp = tail(_io_out_d_m2_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_m2_rec_rawIn_isZero = and(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_isZeroFractIn)
node _io_out_d_m2_rec_rawIn_isSpecial_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_m2_rec_rawIn_isSpecial = eq(_io_out_d_m2_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_m2_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_m2_rec_rawIn_out_isNaN_T = eq(io_out_d_m2_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = and(io_out_d_m2_rec_rawIn_isSpecial, _io_out_d_m2_rec_rawIn_out_isNaN_T)
connect io_out_d_m2_rec_rawIn.isNaN, _io_out_d_m2_rec_rawIn_out_isNaN_T_1
node _io_out_d_m2_rec_rawIn_out_isInf_T = and(io_out_d_m2_rec_rawIn_isSpecial, io_out_d_m2_rec_rawIn_isZeroFractIn)
connect io_out_d_m2_rec_rawIn.isInf, _io_out_d_m2_rec_rawIn_out_isInf_T
connect io_out_d_m2_rec_rawIn.isZero, io_out_d_m2_rec_rawIn_isZero
connect io_out_d_m2_rec_rawIn.sign, io_out_d_m2_rec_rawIn_sign
node _io_out_d_m2_rec_rawIn_out_sExp_T = bits(io_out_d_m2_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_m2_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_m2_rec_rawIn_out_sExp_T)
connect io_out_d_m2_rec_rawIn.sExp, _io_out_d_m2_rec_rawIn_out_sExp_T_1
node _io_out_d_m2_rec_rawIn_out_sig_T = eq(io_out_d_m2_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_m2_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_m2_rec_rawIn_out_sig_T)
node _io_out_d_m2_rec_rawIn_out_sig_T_2 = mux(io_out_d_m2_rec_rawIn_isZeroExpIn, io_out_d_m2_rec_rawIn_subnormFract, io_out_d_m2_rec_rawIn_fractIn)
node _io_out_d_m2_rec_rawIn_out_sig_T_3 = cat(_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2)
connect io_out_d_m2_rec_rawIn.sig, _io_out_d_m2_rec_rawIn_out_sig_T_3
node _io_out_d_m2_rec_T = bits(io_out_d_m2_rec_rawIn.sExp, 8, 6)
node _io_out_d_m2_rec_T_1 = mux(io_out_d_m2_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_m2_rec_T)
node _io_out_d_m2_rec_T_2 = mux(io_out_d_m2_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_m2_rec_T_3 = or(_io_out_d_m2_rec_T_1, _io_out_d_m2_rec_T_2)
node _io_out_d_m2_rec_T_4 = cat(io_out_d_m2_rec_rawIn.sign, _io_out_d_m2_rec_T_3)
node _io_out_d_m2_rec_T_5 = bits(io_out_d_m2_rec_rawIn.sExp, 5, 0)
node _io_out_d_m2_rec_T_6 = cat(_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5)
node _io_out_d_m2_rec_T_7 = bits(io_out_d_m2_rec_rawIn.sig, 22, 0)
node io_out_d_m2_rec = cat(_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7)
node io_out_d_self_rec_rawIn_sign = bits(io.in_c.bits, 31, 31)
node io_out_d_self_rec_rawIn_expIn = bits(io.in_c.bits, 30, 23)
node io_out_d_self_rec_rawIn_fractIn = bits(io.in_c.bits, 22, 0)
node io_out_d_self_rec_rawIn_isZeroExpIn = eq(io_out_d_self_rec_rawIn_expIn, UInt<1>(0h0))
node io_out_d_self_rec_rawIn_isZeroFractIn = eq(io_out_d_self_rec_rawIn_fractIn, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_normDist_T = bits(io_out_d_self_rec_rawIn_fractIn, 0, 0)
node _io_out_d_self_rec_rawIn_normDist_T_1 = bits(io_out_d_self_rec_rawIn_fractIn, 1, 1)
node _io_out_d_self_rec_rawIn_normDist_T_2 = bits(io_out_d_self_rec_rawIn_fractIn, 2, 2)
node _io_out_d_self_rec_rawIn_normDist_T_3 = bits(io_out_d_self_rec_rawIn_fractIn, 3, 3)
node _io_out_d_self_rec_rawIn_normDist_T_4 = bits(io_out_d_self_rec_rawIn_fractIn, 4, 4)
node _io_out_d_self_rec_rawIn_normDist_T_5 = bits(io_out_d_self_rec_rawIn_fractIn, 5, 5)
node _io_out_d_self_rec_rawIn_normDist_T_6 = bits(io_out_d_self_rec_rawIn_fractIn, 6, 6)
node _io_out_d_self_rec_rawIn_normDist_T_7 = bits(io_out_d_self_rec_rawIn_fractIn, 7, 7)
node _io_out_d_self_rec_rawIn_normDist_T_8 = bits(io_out_d_self_rec_rawIn_fractIn, 8, 8)
node _io_out_d_self_rec_rawIn_normDist_T_9 = bits(io_out_d_self_rec_rawIn_fractIn, 9, 9)
node _io_out_d_self_rec_rawIn_normDist_T_10 = bits(io_out_d_self_rec_rawIn_fractIn, 10, 10)
node _io_out_d_self_rec_rawIn_normDist_T_11 = bits(io_out_d_self_rec_rawIn_fractIn, 11, 11)
node _io_out_d_self_rec_rawIn_normDist_T_12 = bits(io_out_d_self_rec_rawIn_fractIn, 12, 12)
node _io_out_d_self_rec_rawIn_normDist_T_13 = bits(io_out_d_self_rec_rawIn_fractIn, 13, 13)
node _io_out_d_self_rec_rawIn_normDist_T_14 = bits(io_out_d_self_rec_rawIn_fractIn, 14, 14)
node _io_out_d_self_rec_rawIn_normDist_T_15 = bits(io_out_d_self_rec_rawIn_fractIn, 15, 15)
node _io_out_d_self_rec_rawIn_normDist_T_16 = bits(io_out_d_self_rec_rawIn_fractIn, 16, 16)
node _io_out_d_self_rec_rawIn_normDist_T_17 = bits(io_out_d_self_rec_rawIn_fractIn, 17, 17)
node _io_out_d_self_rec_rawIn_normDist_T_18 = bits(io_out_d_self_rec_rawIn_fractIn, 18, 18)
node _io_out_d_self_rec_rawIn_normDist_T_19 = bits(io_out_d_self_rec_rawIn_fractIn, 19, 19)
node _io_out_d_self_rec_rawIn_normDist_T_20 = bits(io_out_d_self_rec_rawIn_fractIn, 20, 20)
node _io_out_d_self_rec_rawIn_normDist_T_21 = bits(io_out_d_self_rec_rawIn_fractIn, 21, 21)
node _io_out_d_self_rec_rawIn_normDist_T_22 = bits(io_out_d_self_rec_rawIn_fractIn, 22, 22)
node _io_out_d_self_rec_rawIn_normDist_T_23 = mux(_io_out_d_self_rec_rawIn_normDist_T_1, UInt<5>(0h15), UInt<5>(0h16))
node _io_out_d_self_rec_rawIn_normDist_T_24 = mux(_io_out_d_self_rec_rawIn_normDist_T_2, UInt<5>(0h14), _io_out_d_self_rec_rawIn_normDist_T_23)
node _io_out_d_self_rec_rawIn_normDist_T_25 = mux(_io_out_d_self_rec_rawIn_normDist_T_3, UInt<5>(0h13), _io_out_d_self_rec_rawIn_normDist_T_24)
node _io_out_d_self_rec_rawIn_normDist_T_26 = mux(_io_out_d_self_rec_rawIn_normDist_T_4, UInt<5>(0h12), _io_out_d_self_rec_rawIn_normDist_T_25)
node _io_out_d_self_rec_rawIn_normDist_T_27 = mux(_io_out_d_self_rec_rawIn_normDist_T_5, UInt<5>(0h11), _io_out_d_self_rec_rawIn_normDist_T_26)
node _io_out_d_self_rec_rawIn_normDist_T_28 = mux(_io_out_d_self_rec_rawIn_normDist_T_6, UInt<5>(0h10), _io_out_d_self_rec_rawIn_normDist_T_27)
node _io_out_d_self_rec_rawIn_normDist_T_29 = mux(_io_out_d_self_rec_rawIn_normDist_T_7, UInt<4>(0hf), _io_out_d_self_rec_rawIn_normDist_T_28)
node _io_out_d_self_rec_rawIn_normDist_T_30 = mux(_io_out_d_self_rec_rawIn_normDist_T_8, UInt<4>(0he), _io_out_d_self_rec_rawIn_normDist_T_29)
node _io_out_d_self_rec_rawIn_normDist_T_31 = mux(_io_out_d_self_rec_rawIn_normDist_T_9, UInt<4>(0hd), _io_out_d_self_rec_rawIn_normDist_T_30)
node _io_out_d_self_rec_rawIn_normDist_T_32 = mux(_io_out_d_self_rec_rawIn_normDist_T_10, UInt<4>(0hc), _io_out_d_self_rec_rawIn_normDist_T_31)
node _io_out_d_self_rec_rawIn_normDist_T_33 = mux(_io_out_d_self_rec_rawIn_normDist_T_11, UInt<4>(0hb), _io_out_d_self_rec_rawIn_normDist_T_32)
node _io_out_d_self_rec_rawIn_normDist_T_34 = mux(_io_out_d_self_rec_rawIn_normDist_T_12, UInt<4>(0ha), _io_out_d_self_rec_rawIn_normDist_T_33)
node _io_out_d_self_rec_rawIn_normDist_T_35 = mux(_io_out_d_self_rec_rawIn_normDist_T_13, UInt<4>(0h9), _io_out_d_self_rec_rawIn_normDist_T_34)
node _io_out_d_self_rec_rawIn_normDist_T_36 = mux(_io_out_d_self_rec_rawIn_normDist_T_14, UInt<4>(0h8), _io_out_d_self_rec_rawIn_normDist_T_35)
node _io_out_d_self_rec_rawIn_normDist_T_37 = mux(_io_out_d_self_rec_rawIn_normDist_T_15, UInt<3>(0h7), _io_out_d_self_rec_rawIn_normDist_T_36)
node _io_out_d_self_rec_rawIn_normDist_T_38 = mux(_io_out_d_self_rec_rawIn_normDist_T_16, UInt<3>(0h6), _io_out_d_self_rec_rawIn_normDist_T_37)
node _io_out_d_self_rec_rawIn_normDist_T_39 = mux(_io_out_d_self_rec_rawIn_normDist_T_17, UInt<3>(0h5), _io_out_d_self_rec_rawIn_normDist_T_38)
node _io_out_d_self_rec_rawIn_normDist_T_40 = mux(_io_out_d_self_rec_rawIn_normDist_T_18, UInt<3>(0h4), _io_out_d_self_rec_rawIn_normDist_T_39)
node _io_out_d_self_rec_rawIn_normDist_T_41 = mux(_io_out_d_self_rec_rawIn_normDist_T_19, UInt<2>(0h3), _io_out_d_self_rec_rawIn_normDist_T_40)
node _io_out_d_self_rec_rawIn_normDist_T_42 = mux(_io_out_d_self_rec_rawIn_normDist_T_20, UInt<2>(0h2), _io_out_d_self_rec_rawIn_normDist_T_41)
node _io_out_d_self_rec_rawIn_normDist_T_43 = mux(_io_out_d_self_rec_rawIn_normDist_T_21, UInt<1>(0h1), _io_out_d_self_rec_rawIn_normDist_T_42)
node io_out_d_self_rec_rawIn_normDist = mux(_io_out_d_self_rec_rawIn_normDist_T_22, UInt<1>(0h0), _io_out_d_self_rec_rawIn_normDist_T_43)
node _io_out_d_self_rec_rawIn_subnormFract_T = dshl(io_out_d_self_rec_rawIn_fractIn, io_out_d_self_rec_rawIn_normDist)
node _io_out_d_self_rec_rawIn_subnormFract_T_1 = bits(_io_out_d_self_rec_rawIn_subnormFract_T, 21, 0)
node io_out_d_self_rec_rawIn_subnormFract = shl(_io_out_d_self_rec_rawIn_subnormFract_T_1, 1)
node _io_out_d_self_rec_rawIn_adjustedExp_T = xor(io_out_d_self_rec_rawIn_normDist, UInt<9>(0h1ff))
node _io_out_d_self_rec_rawIn_adjustedExp_T_1 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, _io_out_d_self_rec_rawIn_adjustedExp_T, io_out_d_self_rec_rawIn_expIn)
node _io_out_d_self_rec_rawIn_adjustedExp_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1))
node _io_out_d_self_rec_rawIn_adjustedExp_T_3 = or(UInt<8>(0h80), _io_out_d_self_rec_rawIn_adjustedExp_T_2)
node _io_out_d_self_rec_rawIn_adjustedExp_T_4 = add(_io_out_d_self_rec_rawIn_adjustedExp_T_1, _io_out_d_self_rec_rawIn_adjustedExp_T_3)
node io_out_d_self_rec_rawIn_adjustedExp = tail(_io_out_d_self_rec_rawIn_adjustedExp_T_4, 1)
node io_out_d_self_rec_rawIn_isZero = and(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_isZeroFractIn)
node _io_out_d_self_rec_rawIn_isSpecial_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 7)
node io_out_d_self_rec_rawIn_isSpecial = eq(_io_out_d_self_rec_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_self_rec_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_self_rec_rawIn_out_isNaN_T = eq(io_out_d_self_rec_rawIn_isZeroFractIn, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_out_isNaN_T_1 = and(io_out_d_self_rec_rawIn_isSpecial, _io_out_d_self_rec_rawIn_out_isNaN_T)
connect io_out_d_self_rec_rawIn.isNaN, _io_out_d_self_rec_rawIn_out_isNaN_T_1
node _io_out_d_self_rec_rawIn_out_isInf_T = and(io_out_d_self_rec_rawIn_isSpecial, io_out_d_self_rec_rawIn_isZeroFractIn)
connect io_out_d_self_rec_rawIn.isInf, _io_out_d_self_rec_rawIn_out_isInf_T
connect io_out_d_self_rec_rawIn.isZero, io_out_d_self_rec_rawIn_isZero
connect io_out_d_self_rec_rawIn.sign, io_out_d_self_rec_rawIn_sign
node _io_out_d_self_rec_rawIn_out_sExp_T = bits(io_out_d_self_rec_rawIn_adjustedExp, 8, 0)
node _io_out_d_self_rec_rawIn_out_sExp_T_1 = cvt(_io_out_d_self_rec_rawIn_out_sExp_T)
connect io_out_d_self_rec_rawIn.sExp, _io_out_d_self_rec_rawIn_out_sExp_T_1
node _io_out_d_self_rec_rawIn_out_sig_T = eq(io_out_d_self_rec_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_self_rec_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_self_rec_rawIn_out_sig_T)
node _io_out_d_self_rec_rawIn_out_sig_T_2 = mux(io_out_d_self_rec_rawIn_isZeroExpIn, io_out_d_self_rec_rawIn_subnormFract, io_out_d_self_rec_rawIn_fractIn)
node _io_out_d_self_rec_rawIn_out_sig_T_3 = cat(_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2)
connect io_out_d_self_rec_rawIn.sig, _io_out_d_self_rec_rawIn_out_sig_T_3
node _io_out_d_self_rec_T = bits(io_out_d_self_rec_rawIn.sExp, 8, 6)
node _io_out_d_self_rec_T_1 = mux(io_out_d_self_rec_rawIn.isZero, UInt<3>(0h0), _io_out_d_self_rec_T)
node _io_out_d_self_rec_T_2 = mux(io_out_d_self_rec_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0))
node _io_out_d_self_rec_T_3 = or(_io_out_d_self_rec_T_1, _io_out_d_self_rec_T_2)
node _io_out_d_self_rec_T_4 = cat(io_out_d_self_rec_rawIn.sign, _io_out_d_self_rec_T_3)
node _io_out_d_self_rec_T_5 = bits(io_out_d_self_rec_rawIn.sExp, 5, 0)
node _io_out_d_self_rec_T_6 = cat(_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5)
node _io_out_d_self_rec_T_7 = bits(io_out_d_self_rec_rawIn.sig, 22, 0)
node io_out_d_self_rec = cat(_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7)
inst io_out_d_m1_resizer of RecFNToRecFN_234
connect io_out_d_m1_resizer.io.in, io_out_d_m1_rec
connect io_out_d_m1_resizer.io.roundingMode, UInt<3>(0h0)
connect io_out_d_m1_resizer.io.detectTininess, UInt<1>(0h1)
inst io_out_d_m2_resizer of RecFNToRecFN_235
connect io_out_d_m2_resizer.io.in, io_out_d_m2_rec
connect io_out_d_m2_resizer.io.roundingMode, UInt<3>(0h0)
connect io_out_d_m2_resizer.io.detectTininess, UInt<1>(0h1)
inst io_out_d_muladder of MulAddRecFN_e8_s24_79
connect io_out_d_muladder.io.op, UInt<1>(0h0)
connect io_out_d_muladder.io.roundingMode, UInt<3>(0h0)
connect io_out_d_muladder.io.detectTininess, UInt<1>(0h1)
connect io_out_d_muladder.io.a, io_out_d_m1_resizer.io.out
connect io_out_d_muladder.io.b, io_out_d_m2_resizer.io.out
connect io_out_d_muladder.io.c, io_out_d_self_rec
wire io_out_d_out : { bits : UInt<32>}
node io_out_d_out_bits_rawIn_exp = bits(io_out_d_muladder.io.out, 31, 23)
node _io_out_d_out_bits_rawIn_isZero_T = bits(io_out_d_out_bits_rawIn_exp, 8, 6)
node io_out_d_out_bits_rawIn_isZero = eq(_io_out_d_out_bits_rawIn_isZero_T, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_isSpecial_T = bits(io_out_d_out_bits_rawIn_exp, 8, 7)
node io_out_d_out_bits_rawIn_isSpecial = eq(_io_out_d_out_bits_rawIn_isSpecial_T, UInt<2>(0h3))
wire io_out_d_out_bits_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _io_out_d_out_bits_rawIn_out_isNaN_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6)
node _io_out_d_out_bits_rawIn_out_isNaN_T_1 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isNaN_T)
connect io_out_d_out_bits_rawIn.isNaN, _io_out_d_out_bits_rawIn_out_isNaN_T_1
node _io_out_d_out_bits_rawIn_out_isInf_T = bits(io_out_d_out_bits_rawIn_exp, 6, 6)
node _io_out_d_out_bits_rawIn_out_isInf_T_1 = eq(_io_out_d_out_bits_rawIn_out_isInf_T, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_out_isInf_T_2 = and(io_out_d_out_bits_rawIn_isSpecial, _io_out_d_out_bits_rawIn_out_isInf_T_1)
connect io_out_d_out_bits_rawIn.isInf, _io_out_d_out_bits_rawIn_out_isInf_T_2
connect io_out_d_out_bits_rawIn.isZero, io_out_d_out_bits_rawIn_isZero
node _io_out_d_out_bits_rawIn_out_sign_T = bits(io_out_d_muladder.io.out, 32, 32)
connect io_out_d_out_bits_rawIn.sign, _io_out_d_out_bits_rawIn_out_sign_T
node _io_out_d_out_bits_rawIn_out_sExp_T = cvt(io_out_d_out_bits_rawIn_exp)
connect io_out_d_out_bits_rawIn.sExp, _io_out_d_out_bits_rawIn_out_sExp_T
node _io_out_d_out_bits_rawIn_out_sig_T = eq(io_out_d_out_bits_rawIn_isZero, UInt<1>(0h0))
node _io_out_d_out_bits_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_d_out_bits_rawIn_out_sig_T)
node _io_out_d_out_bits_rawIn_out_sig_T_2 = bits(io_out_d_muladder.io.out, 22, 0)
node _io_out_d_out_bits_rawIn_out_sig_T_3 = cat(_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2)
connect io_out_d_out_bits_rawIn.sig, _io_out_d_out_bits_rawIn_out_sig_T_3
node io_out_d_out_bits_isSubnormal = lt(io_out_d_out_bits_rawIn.sExp, asSInt(UInt<9>(0h82)))
node _io_out_d_out_bits_denormShiftDist_T = bits(io_out_d_out_bits_rawIn.sExp, 4, 0)
node _io_out_d_out_bits_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_d_out_bits_denormShiftDist_T)
node io_out_d_out_bits_denormShiftDist = tail(_io_out_d_out_bits_denormShiftDist_T_1, 1)
node _io_out_d_out_bits_denormFract_T = shr(io_out_d_out_bits_rawIn.sig, 1)
node _io_out_d_out_bits_denormFract_T_1 = dshr(_io_out_d_out_bits_denormFract_T, io_out_d_out_bits_denormShiftDist)
node io_out_d_out_bits_denormFract = bits(_io_out_d_out_bits_denormFract_T_1, 22, 0)
node _io_out_d_out_bits_expOut_T = bits(io_out_d_out_bits_rawIn.sExp, 7, 0)
node _io_out_d_out_bits_expOut_T_1 = sub(_io_out_d_out_bits_expOut_T, UInt<8>(0h81))
node _io_out_d_out_bits_expOut_T_2 = tail(_io_out_d_out_bits_expOut_T_1, 1)
node _io_out_d_out_bits_expOut_T_3 = mux(io_out_d_out_bits_isSubnormal, UInt<1>(0h0), _io_out_d_out_bits_expOut_T_2)
node _io_out_d_out_bits_expOut_T_4 = or(io_out_d_out_bits_rawIn.isNaN, io_out_d_out_bits_rawIn.isInf)
node _io_out_d_out_bits_expOut_T_5 = mux(_io_out_d_out_bits_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0))
node io_out_d_out_bits_expOut = or(_io_out_d_out_bits_expOut_T_3, _io_out_d_out_bits_expOut_T_5)
node _io_out_d_out_bits_fractOut_T = bits(io_out_d_out_bits_rawIn.sig, 22, 0)
node _io_out_d_out_bits_fractOut_T_1 = mux(io_out_d_out_bits_rawIn.isInf, UInt<1>(0h0), _io_out_d_out_bits_fractOut_T)
node io_out_d_out_bits_fractOut = mux(io_out_d_out_bits_isSubnormal, io_out_d_out_bits_denormFract, _io_out_d_out_bits_fractOut_T_1)
node io_out_d_out_bits_hi = cat(io_out_d_out_bits_rawIn.sign, io_out_d_out_bits_expOut)
node _io_out_d_out_bits_T = cat(io_out_d_out_bits_hi, io_out_d_out_bits_fractOut)
connect io_out_d_out.bits, _io_out_d_out_bits_T
connect io.out_d, io_out_d_out | module MacUnit_15( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [31:0] io_in_a_bits, // @[PE.scala:16:14]
input [31:0] io_in_b_bits, // @[PE.scala:16:14]
input [31:0] io_in_c_bits, // @[PE.scala:16:14]
output [31:0] io_out_d_bits // @[PE.scala:16:14]
);
wire io_out_d_self_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_d_m2_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire io_out_d_m1_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [32:0] _io_out_d_muladder_io_out; // @[Arithmetic.scala:376:30]
wire [32:0] _io_out_d_m2_resizer_io_out; // @[Arithmetic.scala:369:32]
wire [32:0] _io_out_d_m1_resizer_io_out; // @[Arithmetic.scala:362:32]
wire [31:0] io_in_a_bits_0 = io_in_a_bits; // @[PE.scala:14:7]
wire [31:0] io_in_b_bits_0 = io_in_b_bits; // @[PE.scala:14:7]
wire [31:0] io_in_c_bits_0 = io_in_c_bits; // @[PE.scala:14:7]
wire [31:0] io_out_d_out_bits; // @[Arithmetic.scala:387:23]
wire [31:0] io_out_d_bits_0; // @[PE.scala:14:7]
wire io_out_d_m1_rec_rawIn_sign = io_in_a_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_m1_rec_rawIn_sign_0 = io_out_d_m1_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_m1_rec_rawIn_expIn = io_in_a_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_m1_rec_rawIn_fractIn = io_in_a_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_m1_rec_rawIn_isZeroExpIn = io_out_d_m1_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_m1_rec_rawIn_isZeroFractIn = io_out_d_m1_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_m1_rec_rawIn_normDist_T = io_out_d_m1_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_1 = io_out_d_m1_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_2 = io_out_d_m1_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_3 = io_out_d_m1_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_4 = io_out_d_m1_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_5 = io_out_d_m1_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_6 = io_out_d_m1_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_7 = io_out_d_m1_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_8 = io_out_d_m1_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_9 = io_out_d_m1_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_10 = io_out_d_m1_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_11 = io_out_d_m1_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_12 = io_out_d_m1_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_13 = io_out_d_m1_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_14 = io_out_d_m1_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_15 = io_out_d_m1_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_16 = io_out_d_m1_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_17 = io_out_d_m1_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_18 = io_out_d_m1_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_19 = io_out_d_m1_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_20 = io_out_d_m1_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_21 = io_out_d_m1_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m1_rec_rawIn_normDist_T_22 = io_out_d_m1_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_23 = _io_out_d_m1_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_24 = _io_out_d_m1_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m1_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_25 = _io_out_d_m1_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m1_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_26 = _io_out_d_m1_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m1_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_27 = _io_out_d_m1_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m1_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_28 = _io_out_d_m1_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m1_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_29 = _io_out_d_m1_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m1_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_30 = _io_out_d_m1_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m1_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_31 = _io_out_d_m1_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m1_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_32 = _io_out_d_m1_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m1_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_33 = _io_out_d_m1_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m1_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_34 = _io_out_d_m1_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m1_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_35 = _io_out_d_m1_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m1_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_36 = _io_out_d_m1_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m1_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_37 = _io_out_d_m1_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m1_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_38 = _io_out_d_m1_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m1_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_39 = _io_out_d_m1_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m1_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_40 = _io_out_d_m1_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m1_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_41 = _io_out_d_m1_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m1_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_42 = _io_out_d_m1_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m1_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m1_rec_rawIn_normDist_T_43 = _io_out_d_m1_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m1_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_m1_rec_rawIn_normDist = _io_out_d_m1_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m1_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_m1_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m1_rec_rawIn_fractIn} << io_out_d_m1_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_m1_rec_rawIn_subnormFract_T_1 = _io_out_d_m1_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_m1_rec_rawIn_subnormFract = {_io_out_d_m1_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m1_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_1 = io_out_d_m1_rec_rawIn_isZeroExpIn ? _io_out_d_m1_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m1_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m1_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_m1_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m1_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_m1_rec_rawIn_adjustedExp = _io_out_d_m1_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_m1_rec_rawIn_out_sExp_T = io_out_d_m1_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_m1_rec_rawIn_isZero = io_out_d_m1_rec_rawIn_isZeroExpIn & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_m1_rec_rawIn_isZero_0 = io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_m1_rec_rawIn_isSpecial_T = io_out_d_m1_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_m1_rec_rawIn_isSpecial = &_io_out_d_m1_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_m1_rec_T_2 = io_out_d_m1_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_m1_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_m1_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_m1_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_m1_rec_rawIn_out_isNaN_T = ~io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_m1_rec_rawIn_out_isNaN_T_1 = io_out_d_m1_rec_rawIn_isSpecial & _io_out_d_m1_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_m1_rec_rawIn_isNaN = _io_out_d_m1_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_m1_rec_rawIn_out_isInf_T = io_out_d_m1_rec_rawIn_isSpecial & io_out_d_m1_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_m1_rec_rawIn_isInf = _io_out_d_m1_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_m1_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_m1_rec_rawIn_sExp = _io_out_d_m1_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_m1_rec_rawIn_out_sig_T = ~io_out_d_m1_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_m1_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m1_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_m1_rec_rawIn_out_sig_T_2 = io_out_d_m1_rec_rawIn_isZeroExpIn ? io_out_d_m1_rec_rawIn_subnormFract : io_out_d_m1_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_m1_rec_rawIn_out_sig_T_3 = {_io_out_d_m1_rec_rawIn_out_sig_T_1, _io_out_d_m1_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_m1_rec_rawIn_sig = _io_out_d_m1_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_m1_rec_T = io_out_d_m1_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_m1_rec_T_1 = io_out_d_m1_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m1_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_m1_rec_T_3 = {_io_out_d_m1_rec_T_1[2:1], _io_out_d_m1_rec_T_1[0] | _io_out_d_m1_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_m1_rec_T_4 = {io_out_d_m1_rec_rawIn_sign_0, _io_out_d_m1_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_m1_rec_T_5 = io_out_d_m1_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_m1_rec_T_6 = {_io_out_d_m1_rec_T_4, _io_out_d_m1_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_m1_rec_T_7 = io_out_d_m1_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_m1_rec = {_io_out_d_m1_rec_T_6, _io_out_d_m1_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_out_d_m2_rec_rawIn_sign = io_in_b_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_m2_rec_rawIn_sign_0 = io_out_d_m2_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_m2_rec_rawIn_expIn = io_in_b_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_m2_rec_rawIn_fractIn = io_in_b_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_m2_rec_rawIn_isZeroExpIn = io_out_d_m2_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_m2_rec_rawIn_isZeroFractIn = io_out_d_m2_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_m2_rec_rawIn_normDist_T = io_out_d_m2_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_1 = io_out_d_m2_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_2 = io_out_d_m2_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_3 = io_out_d_m2_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_4 = io_out_d_m2_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_5 = io_out_d_m2_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_6 = io_out_d_m2_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_7 = io_out_d_m2_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_8 = io_out_d_m2_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_9 = io_out_d_m2_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_10 = io_out_d_m2_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_11 = io_out_d_m2_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_12 = io_out_d_m2_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_13 = io_out_d_m2_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_14 = io_out_d_m2_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_15 = io_out_d_m2_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_16 = io_out_d_m2_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_17 = io_out_d_m2_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_18 = io_out_d_m2_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_19 = io_out_d_m2_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_20 = io_out_d_m2_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_21 = io_out_d_m2_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_m2_rec_rawIn_normDist_T_22 = io_out_d_m2_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_23 = _io_out_d_m2_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_24 = _io_out_d_m2_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_m2_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_25 = _io_out_d_m2_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_m2_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_26 = _io_out_d_m2_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_m2_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_27 = _io_out_d_m2_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_m2_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_28 = _io_out_d_m2_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_m2_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_29 = _io_out_d_m2_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_m2_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_30 = _io_out_d_m2_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_m2_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_31 = _io_out_d_m2_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_m2_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_32 = _io_out_d_m2_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_m2_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_33 = _io_out_d_m2_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_m2_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_34 = _io_out_d_m2_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_m2_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_35 = _io_out_d_m2_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_m2_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_36 = _io_out_d_m2_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_m2_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_37 = _io_out_d_m2_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_m2_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_38 = _io_out_d_m2_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_m2_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_39 = _io_out_d_m2_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_m2_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_40 = _io_out_d_m2_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_m2_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_41 = _io_out_d_m2_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_m2_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_42 = _io_out_d_m2_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_m2_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_m2_rec_rawIn_normDist_T_43 = _io_out_d_m2_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_m2_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_m2_rec_rawIn_normDist = _io_out_d_m2_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_m2_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_m2_rec_rawIn_subnormFract_T = {31'h0, io_out_d_m2_rec_rawIn_fractIn} << io_out_d_m2_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_m2_rec_rawIn_subnormFract_T_1 = _io_out_d_m2_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_m2_rec_rawIn_subnormFract = {_io_out_d_m2_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_m2_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_1 = io_out_d_m2_rec_rawIn_isZeroExpIn ? _io_out_d_m2_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_m2_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_m2_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_m2_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_m2_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_m2_rec_rawIn_adjustedExp = _io_out_d_m2_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_m2_rec_rawIn_out_sExp_T = io_out_d_m2_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_m2_rec_rawIn_isZero = io_out_d_m2_rec_rawIn_isZeroExpIn & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_m2_rec_rawIn_isZero_0 = io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_m2_rec_rawIn_isSpecial_T = io_out_d_m2_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_m2_rec_rawIn_isSpecial = &_io_out_d_m2_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_m2_rec_T_2 = io_out_d_m2_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_m2_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_m2_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_m2_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_m2_rec_rawIn_out_isNaN_T = ~io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_m2_rec_rawIn_out_isNaN_T_1 = io_out_d_m2_rec_rawIn_isSpecial & _io_out_d_m2_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_m2_rec_rawIn_isNaN = _io_out_d_m2_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_m2_rec_rawIn_out_isInf_T = io_out_d_m2_rec_rawIn_isSpecial & io_out_d_m2_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_m2_rec_rawIn_isInf = _io_out_d_m2_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_m2_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_m2_rec_rawIn_sExp = _io_out_d_m2_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_m2_rec_rawIn_out_sig_T = ~io_out_d_m2_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_m2_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_m2_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_m2_rec_rawIn_out_sig_T_2 = io_out_d_m2_rec_rawIn_isZeroExpIn ? io_out_d_m2_rec_rawIn_subnormFract : io_out_d_m2_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_m2_rec_rawIn_out_sig_T_3 = {_io_out_d_m2_rec_rawIn_out_sig_T_1, _io_out_d_m2_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_m2_rec_rawIn_sig = _io_out_d_m2_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_m2_rec_T = io_out_d_m2_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_m2_rec_T_1 = io_out_d_m2_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_m2_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_m2_rec_T_3 = {_io_out_d_m2_rec_T_1[2:1], _io_out_d_m2_rec_T_1[0] | _io_out_d_m2_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_m2_rec_T_4 = {io_out_d_m2_rec_rawIn_sign_0, _io_out_d_m2_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_m2_rec_T_5 = io_out_d_m2_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_m2_rec_T_6 = {_io_out_d_m2_rec_T_4, _io_out_d_m2_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_m2_rec_T_7 = io_out_d_m2_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_m2_rec = {_io_out_d_m2_rec_T_6, _io_out_d_m2_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire io_out_d_self_rec_rawIn_sign = io_in_c_bits_0[31]; // @[rawFloatFromFN.scala:44:18]
wire io_out_d_self_rec_rawIn_sign_0 = io_out_d_self_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] io_out_d_self_rec_rawIn_expIn = io_in_c_bits_0[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] io_out_d_self_rec_rawIn_fractIn = io_in_c_bits_0[22:0]; // @[rawFloatFromFN.scala:46:21]
wire io_out_d_self_rec_rawIn_isZeroExpIn = io_out_d_self_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire io_out_d_self_rec_rawIn_isZeroFractIn = io_out_d_self_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _io_out_d_self_rec_rawIn_normDist_T = io_out_d_self_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_1 = io_out_d_self_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_2 = io_out_d_self_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_3 = io_out_d_self_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_4 = io_out_d_self_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_5 = io_out_d_self_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_6 = io_out_d_self_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_7 = io_out_d_self_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_8 = io_out_d_self_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_9 = io_out_d_self_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_10 = io_out_d_self_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_11 = io_out_d_self_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_12 = io_out_d_self_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_13 = io_out_d_self_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_14 = io_out_d_self_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_15 = io_out_d_self_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_16 = io_out_d_self_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_17 = io_out_d_self_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_18 = io_out_d_self_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_19 = io_out_d_self_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_20 = io_out_d_self_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_21 = io_out_d_self_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _io_out_d_self_rec_rawIn_normDist_T_22 = io_out_d_self_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_23 = _io_out_d_self_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_24 = _io_out_d_self_rec_rawIn_normDist_T_2 ? 5'h14 : _io_out_d_self_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_25 = _io_out_d_self_rec_rawIn_normDist_T_3 ? 5'h13 : _io_out_d_self_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_26 = _io_out_d_self_rec_rawIn_normDist_T_4 ? 5'h12 : _io_out_d_self_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_27 = _io_out_d_self_rec_rawIn_normDist_T_5 ? 5'h11 : _io_out_d_self_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_28 = _io_out_d_self_rec_rawIn_normDist_T_6 ? 5'h10 : _io_out_d_self_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_29 = _io_out_d_self_rec_rawIn_normDist_T_7 ? 5'hF : _io_out_d_self_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_30 = _io_out_d_self_rec_rawIn_normDist_T_8 ? 5'hE : _io_out_d_self_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_31 = _io_out_d_self_rec_rawIn_normDist_T_9 ? 5'hD : _io_out_d_self_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_32 = _io_out_d_self_rec_rawIn_normDist_T_10 ? 5'hC : _io_out_d_self_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_33 = _io_out_d_self_rec_rawIn_normDist_T_11 ? 5'hB : _io_out_d_self_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_34 = _io_out_d_self_rec_rawIn_normDist_T_12 ? 5'hA : _io_out_d_self_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_35 = _io_out_d_self_rec_rawIn_normDist_T_13 ? 5'h9 : _io_out_d_self_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_36 = _io_out_d_self_rec_rawIn_normDist_T_14 ? 5'h8 : _io_out_d_self_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_37 = _io_out_d_self_rec_rawIn_normDist_T_15 ? 5'h7 : _io_out_d_self_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_38 = _io_out_d_self_rec_rawIn_normDist_T_16 ? 5'h6 : _io_out_d_self_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_39 = _io_out_d_self_rec_rawIn_normDist_T_17 ? 5'h5 : _io_out_d_self_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_40 = _io_out_d_self_rec_rawIn_normDist_T_18 ? 5'h4 : _io_out_d_self_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_41 = _io_out_d_self_rec_rawIn_normDist_T_19 ? 5'h3 : _io_out_d_self_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_42 = _io_out_d_self_rec_rawIn_normDist_T_20 ? 5'h2 : _io_out_d_self_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _io_out_d_self_rec_rawIn_normDist_T_43 = _io_out_d_self_rec_rawIn_normDist_T_21 ? 5'h1 : _io_out_d_self_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] io_out_d_self_rec_rawIn_normDist = _io_out_d_self_rec_rawIn_normDist_T_22 ? 5'h0 : _io_out_d_self_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _io_out_d_self_rec_rawIn_subnormFract_T = {31'h0, io_out_d_self_rec_rawIn_fractIn} << io_out_d_self_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _io_out_d_self_rec_rawIn_subnormFract_T_1 = _io_out_d_self_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] io_out_d_self_rec_rawIn_subnormFract = {_io_out_d_self_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T = {4'hF, ~io_out_d_self_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _io_out_d_self_rec_rawIn_adjustedExp_T_1 = io_out_d_self_rec_rawIn_isZeroExpIn ? _io_out_d_self_rec_rawIn_adjustedExp_T : {1'h0, io_out_d_self_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _io_out_d_self_rec_rawIn_adjustedExp_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _io_out_d_self_rec_rawIn_adjustedExp_T_3 = {6'h20, _io_out_d_self_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _io_out_d_self_rec_rawIn_adjustedExp_T_4 = {1'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_1} + {2'h0, _io_out_d_self_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] io_out_d_self_rec_rawIn_adjustedExp = _io_out_d_self_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _io_out_d_self_rec_rawIn_out_sExp_T = io_out_d_self_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire io_out_d_self_rec_rawIn_isZero = io_out_d_self_rec_rawIn_isZeroExpIn & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire io_out_d_self_rec_rawIn_isZero_0 = io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _io_out_d_self_rec_rawIn_isSpecial_T = io_out_d_self_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire io_out_d_self_rec_rawIn_isSpecial = &_io_out_d_self_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _io_out_d_self_rec_T_2 = io_out_d_self_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire io_out_d_self_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] io_out_d_self_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] io_out_d_self_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _io_out_d_self_rec_rawIn_out_isNaN_T = ~io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _io_out_d_self_rec_rawIn_out_isNaN_T_1 = io_out_d_self_rec_rawIn_isSpecial & _io_out_d_self_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign io_out_d_self_rec_rawIn_isNaN = _io_out_d_self_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _io_out_d_self_rec_rawIn_out_isInf_T = io_out_d_self_rec_rawIn_isSpecial & io_out_d_self_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign io_out_d_self_rec_rawIn_isInf = _io_out_d_self_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _io_out_d_self_rec_rawIn_out_sExp_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign io_out_d_self_rec_rawIn_sExp = _io_out_d_self_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _io_out_d_self_rec_rawIn_out_sig_T = ~io_out_d_self_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _io_out_d_self_rec_rawIn_out_sig_T_1 = {1'h0, _io_out_d_self_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _io_out_d_self_rec_rawIn_out_sig_T_2 = io_out_d_self_rec_rawIn_isZeroExpIn ? io_out_d_self_rec_rawIn_subnormFract : io_out_d_self_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _io_out_d_self_rec_rawIn_out_sig_T_3 = {_io_out_d_self_rec_rawIn_out_sig_T_1, _io_out_d_self_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign io_out_d_self_rec_rawIn_sig = _io_out_d_self_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _io_out_d_self_rec_T = io_out_d_self_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _io_out_d_self_rec_T_1 = io_out_d_self_rec_rawIn_isZero_0 ? 3'h0 : _io_out_d_self_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _io_out_d_self_rec_T_3 = {_io_out_d_self_rec_T_1[2:1], _io_out_d_self_rec_T_1[0] | _io_out_d_self_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _io_out_d_self_rec_T_4 = {io_out_d_self_rec_rawIn_sign_0, _io_out_d_self_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _io_out_d_self_rec_T_5 = io_out_d_self_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _io_out_d_self_rec_T_6 = {_io_out_d_self_rec_T_4, _io_out_d_self_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _io_out_d_self_rec_T_7 = io_out_d_self_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] io_out_d_self_rec = {_io_out_d_self_rec_T_6, _io_out_d_self_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12]
assign io_out_d_bits_0 = io_out_d_out_bits; // @[PE.scala:14:7]
wire [8:0] io_out_d_out_bits_rawIn_exp = _io_out_d_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _io_out_d_out_bits_rawIn_isZero_T = io_out_d_out_bits_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire io_out_d_out_bits_rawIn_isZero = _io_out_d_out_bits_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire io_out_d_out_bits_rawIn_isZero_0 = io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _io_out_d_out_bits_rawIn_isSpecial_T = io_out_d_out_bits_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire io_out_d_out_bits_rawIn_isSpecial = &_io_out_d_out_bits_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire io_out_d_out_bits_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire io_out_d_out_bits_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] io_out_d_out_bits_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] io_out_d_out_bits_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _io_out_d_out_bits_rawIn_out_isNaN_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _io_out_d_out_bits_rawIn_out_isInf_T = io_out_d_out_bits_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _io_out_d_out_bits_rawIn_out_isNaN_T_1 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign io_out_d_out_bits_rawIn_isNaN = _io_out_d_out_bits_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _io_out_d_out_bits_rawIn_out_isInf_T_1 = ~_io_out_d_out_bits_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _io_out_d_out_bits_rawIn_out_isInf_T_2 = io_out_d_out_bits_rawIn_isSpecial & _io_out_d_out_bits_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign io_out_d_out_bits_rawIn_isInf = _io_out_d_out_bits_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _io_out_d_out_bits_rawIn_out_sign_T = _io_out_d_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign io_out_d_out_bits_rawIn_sign = _io_out_d_out_bits_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _io_out_d_out_bits_rawIn_out_sExp_T = {1'h0, io_out_d_out_bits_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign io_out_d_out_bits_rawIn_sExp = _io_out_d_out_bits_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _io_out_d_out_bits_rawIn_out_sig_T = ~io_out_d_out_bits_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _io_out_d_out_bits_rawIn_out_sig_T_1 = {1'h0, _io_out_d_out_bits_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _io_out_d_out_bits_rawIn_out_sig_T_2 = _io_out_d_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _io_out_d_out_bits_rawIn_out_sig_T_3 = {_io_out_d_out_bits_rawIn_out_sig_T_1, _io_out_d_out_bits_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign io_out_d_out_bits_rawIn_sig = _io_out_d_out_bits_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire io_out_d_out_bits_isSubnormal = $signed(io_out_d_out_bits_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _io_out_d_out_bits_denormShiftDist_T = io_out_d_out_bits_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [5:0] _io_out_d_out_bits_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_d_out_bits_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}]
wire [4:0] io_out_d_out_bits_denormShiftDist = _io_out_d_out_bits_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35]
wire [23:0] _io_out_d_out_bits_denormFract_T = io_out_d_out_bits_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23]
wire [23:0] _io_out_d_out_bits_denormFract_T_1 = _io_out_d_out_bits_denormFract_T >> io_out_d_out_bits_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}]
wire [22:0] io_out_d_out_bits_denormFract = _io_out_d_out_bits_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}]
wire [7:0] _io_out_d_out_bits_expOut_T = io_out_d_out_bits_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _io_out_d_out_bits_expOut_T_1 = {1'h0, _io_out_d_out_bits_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}]
wire [7:0] _io_out_d_out_bits_expOut_T_2 = _io_out_d_out_bits_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45]
wire [7:0] _io_out_d_out_bits_expOut_T_3 = io_out_d_out_bits_isSubnormal ? 8'h0 : _io_out_d_out_bits_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45]
wire _io_out_d_out_bits_expOut_T_4 = io_out_d_out_bits_rawIn_isNaN | io_out_d_out_bits_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _io_out_d_out_bits_expOut_T_5 = {8{_io_out_d_out_bits_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}]
wire [7:0] io_out_d_out_bits_expOut = _io_out_d_out_bits_expOut_T_3 | _io_out_d_out_bits_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}]
wire [22:0] _io_out_d_out_bits_fractOut_T = io_out_d_out_bits_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] _io_out_d_out_bits_fractOut_T_1 = io_out_d_out_bits_rawIn_isInf ? 23'h0 : _io_out_d_out_bits_fractOut_T; // @[rawFloatFromRecFN.scala:55:23]
wire [22:0] io_out_d_out_bits_fractOut = io_out_d_out_bits_isSubnormal ? io_out_d_out_bits_denormFract : _io_out_d_out_bits_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20]
wire [8:0] io_out_d_out_bits_hi = {io_out_d_out_bits_rawIn_sign, io_out_d_out_bits_expOut}; // @[rawFloatFromRecFN.scala:55:23]
assign _io_out_d_out_bits_T = {io_out_d_out_bits_hi, io_out_d_out_bits_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12]
assign io_out_d_out_bits = _io_out_d_out_bits_T; // @[fNFromRecFN.scala:66:12]
RecFNToRecFN_234 io_out_d_m1_resizer ( // @[Arithmetic.scala:362:32]
.io_in (io_out_d_m1_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_m1_resizer_io_out)
); // @[Arithmetic.scala:362:32]
RecFNToRecFN_235 io_out_d_m2_resizer ( // @[Arithmetic.scala:369:32]
.io_in (io_out_d_m2_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_m2_resizer_io_out)
); // @[Arithmetic.scala:369:32]
MulAddRecFN_e8_s24_79 io_out_d_muladder ( // @[Arithmetic.scala:376:30]
.io_a (_io_out_d_m1_resizer_io_out), // @[Arithmetic.scala:362:32]
.io_b (_io_out_d_m2_resizer_io_out), // @[Arithmetic.scala:369:32]
.io_c (io_out_d_self_rec), // @[recFNFromFN.scala:50:41]
.io_out (_io_out_d_muladder_io_out)
); // @[Arithmetic.scala:376:30]
assign io_out_d_bits = io_out_d_bits_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_25 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<4>(0h8))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = and(_T_11, _T_24)
node _T_102 = and(_T_101, _T_37)
node _T_103 = and(_T_102, _T_50)
node _T_104 = and(_T_103, _T_63)
node _T_105 = and(_T_104, _T_76)
node _T_106 = and(_T_105, _T_84)
node _T_107 = and(_T_106, _T_92)
node _T_108 = and(_T_107, _T_100)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_112 :
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_117 = shr(io.in.a.bits.source, 2)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_120 = and(_T_118, _T_119)
node _T_121 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_122 = and(_T_120, _T_121)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h1))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_128 = and(_T_126, _T_127)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_129 = shr(io.in.a.bits.source, 2)
node _T_130 = eq(_T_129, UInt<2>(0h2))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_134 = and(_T_132, _T_133)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_135 = shr(io.in.a.bits.source, 2)
node _T_136 = eq(_T_135, UInt<2>(0h3))
node _T_137 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_138 = and(_T_136, _T_137)
node _T_139 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_140 = and(_T_138, _T_139)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_141 = shr(io.in.a.bits.source, 2)
node _T_142 = eq(_T_141, UInt<4>(0h8))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_9, UInt<2>(0h2))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_116, _T_122)
node _T_151 = or(_T_150, _T_128)
node _T_152 = or(_T_151, _T_134)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_146)
node _T_155 = or(_T_154, _T_147)
node _T_156 = or(_T_155, _T_148)
node _T_157 = or(_T_156, _T_149)
node _T_158 = and(_T_115, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_161 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = and(_T_160, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(_T_159, _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_168, UInt<1>(0h1), "") : assert_2
node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_178 = and(_T_176, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_179 = shr(io.in.a.bits.source, 2)
node _T_180 = eq(_T_179, UInt<1>(0h1))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_184 = and(_T_182, _T_183)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_185 = shr(io.in.a.bits.source, 2)
node _T_186 = eq(_T_185, UInt<2>(0h2))
node _T_187 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_188 = and(_T_186, _T_187)
node _T_189 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_190 = and(_T_188, _T_189)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_191 = shr(io.in.a.bits.source, 2)
node _T_192 = eq(_T_191, UInt<2>(0h3))
node _T_193 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_194 = and(_T_192, _T_193)
node _T_195 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_197 = shr(io.in.a.bits.source, 2)
node _T_198 = eq(_T_197, UInt<4>(0h8))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_14, UInt<2>(0h2))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_172
connect _WIRE[1], _T_178
connect _WIRE[2], _T_184
connect _WIRE[3], _T_190
connect _WIRE[4], _T_196
connect _WIRE[5], _T_202
connect _WIRE[6], _T_203
connect _WIRE[7], _T_204
connect _WIRE[8], _T_205
node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0))
node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_216 = or(_T_207, _T_208)
node _T_217 = or(_T_216, _T_209)
node _T_218 = or(_T_217, _T_210)
node _T_219 = or(_T_218, _T_211)
node _T_220 = or(_T_219, _T_212)
node _T_221 = or(_T_220, _T_213)
node _T_222 = or(_T_221, _T_214)
node _T_223 = or(_T_222, _T_215)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_223
node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_226 = and(_T_224, _T_225)
node _T_227 = or(UInt<1>(0h0), _T_226)
node _T_228 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = and(_T_227, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(_WIRE_1, _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_291 = shr(io.in.a.bits.source, 2)
node _T_292 = eq(_T_291, UInt<4>(0h8))
node _T_293 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_294 = and(_T_292, _T_293)
node _T_295 = leq(uncommonBits_19, UInt<2>(0h2))
node _T_296 = and(_T_294, _T_295)
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_300 = or(_T_266, _T_272)
node _T_301 = or(_T_300, _T_278)
node _T_302 = or(_T_301, _T_284)
node _T_303 = or(_T_302, _T_290)
node _T_304 = or(_T_303, _T_296)
node _T_305 = or(_T_304, _T_297)
node _T_306 = or(_T_305, _T_298)
node _T_307 = or(_T_306, _T_299)
node _T_308 = and(_T_265, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = and(_T_310, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = and(_T_309, _T_317)
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_318, UInt<1>(0h1), "") : assert_10
node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_323 = shr(io.in.a.bits.source, 2)
node _T_324 = eq(_T_323, UInt<1>(0h0))
node _T_325 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_326 = and(_T_324, _T_325)
node _T_327 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_328 = and(_T_326, _T_327)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_329 = shr(io.in.a.bits.source, 2)
node _T_330 = eq(_T_329, UInt<1>(0h1))
node _T_331 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_332 = and(_T_330, _T_331)
node _T_333 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_335 = shr(io.in.a.bits.source, 2)
node _T_336 = eq(_T_335, UInt<2>(0h2))
node _T_337 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_338 = and(_T_336, _T_337)
node _T_339 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_340 = and(_T_338, _T_339)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_341 = shr(io.in.a.bits.source, 2)
node _T_342 = eq(_T_341, UInt<2>(0h3))
node _T_343 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_344 = and(_T_342, _T_343)
node _T_345 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_346 = and(_T_344, _T_345)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_347 = shr(io.in.a.bits.source, 2)
node _T_348 = eq(_T_347, UInt<4>(0h8))
node _T_349 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_350 = and(_T_348, _T_349)
node _T_351 = leq(uncommonBits_24, UInt<2>(0h2))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_322
connect _WIRE_2[1], _T_328
connect _WIRE_2[2], _T_334
connect _WIRE_2[3], _T_340
connect _WIRE_2[4], _T_346
connect _WIRE_2[5], _T_352
connect _WIRE_2[6], _T_353
connect _WIRE_2[7], _T_354
connect _WIRE_2[8], _T_355
node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = or(_T_357, _T_358)
node _T_367 = or(_T_366, _T_359)
node _T_368 = or(_T_367, _T_360)
node _T_369 = or(_T_368, _T_361)
node _T_370 = or(_T_369, _T_362)
node _T_371 = or(_T_370, _T_363)
node _T_372 = or(_T_371, _T_364)
node _T_373 = or(_T_372, _T_365)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_373
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _T_377 = or(UInt<1>(0h0), _T_376)
node _T_378 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = and(_T_377, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = and(_WIRE_3, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_385, UInt<1>(0h1), "") : assert_11
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(source_ok, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_392, UInt<1>(0h1), "") : assert_13
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(is_aligned, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_399, UInt<1>(0h1), "") : assert_15
node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_403, UInt<1>(0h1), "") : assert_16
node _T_407 = not(io.in.a.bits.mask)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_408, UInt<1>(0h1), "") : assert_17
node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(_T_412, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_412, UInt<1>(0h1), "") : assert_18
node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_416 :
node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<1>(0h1))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h2))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_439 = shr(io.in.a.bits.source, 2)
node _T_440 = eq(_T_439, UInt<2>(0h3))
node _T_441 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_442 = and(_T_440, _T_441)
node _T_443 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_444 = and(_T_442, _T_443)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_445 = shr(io.in.a.bits.source, 2)
node _T_446 = eq(_T_445, UInt<4>(0h8))
node _T_447 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_448 = and(_T_446, _T_447)
node _T_449 = leq(uncommonBits_29, UInt<2>(0h2))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_454 = or(_T_420, _T_426)
node _T_455 = or(_T_454, _T_432)
node _T_456 = or(_T_455, _T_438)
node _T_457 = or(_T_456, _T_444)
node _T_458 = or(_T_457, _T_450)
node _T_459 = or(_T_458, _T_451)
node _T_460 = or(_T_459, _T_452)
node _T_461 = or(_T_460, _T_453)
node _T_462 = and(_T_419, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_463, UInt<1>(0h1), "") : assert_19
node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_469 = and(_T_467, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = and(_T_470, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_477, UInt<1>(0h1), "") : assert_20
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(source_ok, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_487, UInt<1>(0h1), "") : assert_23
node _T_491 = eq(io.in.a.bits.mask, mask)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_491, UInt<1>(0h1), "") : assert_24
node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_495, UInt<1>(0h1), "") : assert_25
node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_499 :
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_504 = shr(io.in.a.bits.source, 2)
node _T_505 = eq(_T_504, UInt<1>(0h0))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<4>(0h8))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_34, UInt<2>(0h2))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_537 = or(_T_503, _T_509)
node _T_538 = or(_T_537, _T_515)
node _T_539 = or(_T_538, _T_521)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_533)
node _T_542 = or(_T_541, _T_534)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = and(_T_502, _T_544)
node _T_546 = or(UInt<1>(0h0), _T_545)
node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_549 = and(_T_547, _T_548)
node _T_550 = or(UInt<1>(0h0), _T_549)
node _T_551 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_556)
node _T_558 = and(_T_546, _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_558, UInt<1>(0h1), "") : assert_26
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(source_ok, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(is_aligned, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_568, UInt<1>(0h1), "") : assert_29
node _T_572 = eq(io.in.a.bits.mask, mask)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_572, UInt<1>(0h1), "") : assert_30
node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_576 :
node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<1>(0h0))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<1>(0h1))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_593 = shr(io.in.a.bits.source, 2)
node _T_594 = eq(_T_593, UInt<2>(0h2))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_598 = and(_T_596, _T_597)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<2>(0h3))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_605 = shr(io.in.a.bits.source, 2)
node _T_606 = eq(_T_605, UInt<4>(0h8))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_39, UInt<2>(0h2))
node _T_610 = and(_T_608, _T_609)
node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_614 = or(_T_580, _T_586)
node _T_615 = or(_T_614, _T_592)
node _T_616 = or(_T_615, _T_598)
node _T_617 = or(_T_616, _T_604)
node _T_618 = or(_T_617, _T_610)
node _T_619 = or(_T_618, _T_611)
node _T_620 = or(_T_619, _T_612)
node _T_621 = or(_T_620, _T_613)
node _T_622 = and(_T_579, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = and(_T_627, _T_632)
node _T_634 = or(UInt<1>(0h0), _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_635, UInt<1>(0h1), "") : assert_31
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(source_ok, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(is_aligned, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_645, UInt<1>(0h1), "") : assert_34
node _T_649 = not(mask)
node _T_650 = and(io.in.a.bits.mask, _T_649)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_651, UInt<1>(0h1), "") : assert_35
node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_655 :
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<1>(0h1))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<2>(0h2))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_678 = shr(io.in.a.bits.source, 2)
node _T_679 = eq(_T_678, UInt<2>(0h3))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_684 = shr(io.in.a.bits.source, 2)
node _T_685 = eq(_T_684, UInt<4>(0h8))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_44, UInt<2>(0h2))
node _T_689 = and(_T_687, _T_688)
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_693 = or(_T_659, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_683)
node _T_697 = or(_T_696, _T_689)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = or(_T_699, _T_692)
node _T_701 = and(_T_658, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = and(_T_703, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = and(_T_702, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_711, UInt<1>(0h1), "") : assert_36
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_721, UInt<1>(0h1), "") : assert_39
node _T_725 = eq(io.in.a.bits.mask, mask)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_725, UInt<1>(0h1), "") : assert_40
node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_729 :
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<1>(0h1))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<2>(0h2))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<2>(0h3))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<4>(0h8))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_49, UInt<2>(0h2))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_767 = or(_T_733, _T_739)
node _T_768 = or(_T_767, _T_745)
node _T_769 = or(_T_768, _T_751)
node _T_770 = or(_T_769, _T_757)
node _T_771 = or(_T_770, _T_763)
node _T_772 = or(_T_771, _T_764)
node _T_773 = or(_T_772, _T_765)
node _T_774 = or(_T_773, _T_766)
node _T_775 = and(_T_732, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = and(_T_776, _T_784)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_785, UInt<1>(0h1), "") : assert_41
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(source_ok, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(is_aligned, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_795, UInt<1>(0h1), "") : assert_44
node _T_799 = eq(io.in.a.bits.mask, mask)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_799, UInt<1>(0h1), "") : assert_45
node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_803 :
node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<1>(0h0))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_814 = shr(io.in.a.bits.source, 2)
node _T_815 = eq(_T_814, UInt<1>(0h1))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_820 = shr(io.in.a.bits.source, 2)
node _T_821 = eq(_T_820, UInt<2>(0h2))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_825 = and(_T_823, _T_824)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_826 = shr(io.in.a.bits.source, 2)
node _T_827 = eq(_T_826, UInt<2>(0h3))
node _T_828 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_829 = and(_T_827, _T_828)
node _T_830 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_831 = and(_T_829, _T_830)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_832 = shr(io.in.a.bits.source, 2)
node _T_833 = eq(_T_832, UInt<4>(0h8))
node _T_834 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_835 = and(_T_833, _T_834)
node _T_836 = leq(uncommonBits_54, UInt<2>(0h2))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_841 = or(_T_807, _T_813)
node _T_842 = or(_T_841, _T_819)
node _T_843 = or(_T_842, _T_825)
node _T_844 = or(_T_843, _T_831)
node _T_845 = or(_T_844, _T_837)
node _T_846 = or(_T_845, _T_838)
node _T_847 = or(_T_846, _T_839)
node _T_848 = or(_T_847, _T_840)
node _T_849 = and(_T_806, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = and(_T_851, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = and(_T_850, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_859, UInt<1>(0h1), "") : assert_46
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(source_ok, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(is_aligned, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_869, UInt<1>(0h1), "") : assert_49
node _T_873 = eq(io.in.a.bits.mask, mask)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_873, UInt<1>(0h1), "") : assert_50
node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_877, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_881, UInt<1>(0h1), "") : assert_52
node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_42 = shr(io.in.d.bits.source, 2)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_48 = shr(io.in.d.bits.source, 2)
node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1))
node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 2)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 2)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_66 = shr(io.in.d.bits.source, 2)
node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8))
node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2))
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_41
connect _source_ok_WIRE_1[1], _source_ok_T_47
connect _source_ok_WIRE_1[2], _source_ok_T_53
connect _source_ok_WIRE_1[3], _source_ok_T_59
connect _source_ok_WIRE_1[4], _source_ok_T_65
connect _source_ok_WIRE_1[5], _source_ok_T_71
connect _source_ok_WIRE_1[6], _source_ok_T_72
connect _source_ok_WIRE_1[7], _source_ok_T_73
connect _source_ok_WIRE_1[8], _source_ok_T_74
node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_885 :
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok_1, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_889, UInt<1>(0h1), "") : assert_54
node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_893, UInt<1>(0h1), "") : assert_55
node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_897, UInt<1>(0h1), "") : assert_56
node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_901, UInt<1>(0h1), "") : assert_57
node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_905 :
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok_1, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(sink_ok, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_912, UInt<1>(0h1), "") : assert_60
node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_916, UInt<1>(0h1), "") : assert_61
node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_920, UInt<1>(0h1), "") : assert_62
node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_924, UInt<1>(0h1), "") : assert_63
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(UInt<1>(0h0), _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_929, UInt<1>(0h1), "") : assert_64
node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_933 :
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(source_ok_1, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(sink_ok, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_940, UInt<1>(0h1), "") : assert_67
node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_944, UInt<1>(0h1), "") : assert_68
node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_948, UInt<1>(0h1), "") : assert_69
node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_953 = or(_T_952, io.in.d.bits.corrupt)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_953, UInt<1>(0h1), "") : assert_70
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = or(UInt<1>(0h0), _T_957)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_958, UInt<1>(0h1), "") : assert_71
node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_962 :
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(source_ok_1, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_966, UInt<1>(0h1), "") : assert_73
node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_970, UInt<1>(0h1), "") : assert_74
node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_975, UInt<1>(0h1), "") : assert_75
node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_979 :
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok_1, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_983, UInt<1>(0h1), "") : assert_77
node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_988 = or(_T_987, io.in.d.bits.corrupt)
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_988, UInt<1>(0h1), "") : assert_78
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(UInt<1>(0h0), _T_992)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_993, UInt<1>(0h1), "") : assert_79
node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_997 :
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(source_ok_1, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81
node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82
node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1010 = or(UInt<1>(0h0), _T_1009)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<12>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<12>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<12>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1026 = eq(a_first, UInt<1>(0h0))
node _T_1027 = and(io.in.a.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.a.bits.opcode, opcode)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87
node _T_1032 = eq(io.in.a.bits.param, param)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88
node _T_1036 = eq(io.in.a.bits.size, size)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89
node _T_1040 = eq(io.in.a.bits.source, source)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90
node _T_1044 = eq(io.in.a.bits.address, address)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91
node _T_1048 = and(io.in.a.ready, io.in.a.valid)
node _T_1049 = and(_T_1048, a_first)
when _T_1049 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1050 = eq(d_first, UInt<1>(0h0))
node _T_1051 = and(io.in.d.valid, _T_1050)
when _T_1051 :
node _T_1052 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92
node _T_1056 = eq(io.in.d.bits.param, param_1)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93
node _T_1060 = eq(io.in.d.bits.size, size_1)
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94
node _T_1064 = eq(io.in.d.bits.source, source_1)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95
node _T_1068 = eq(io.in.d.bits.sink, sink)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96
node _T_1072 = eq(io.in.d.bits.denied, denied)
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97
node _T_1076 = and(io.in.d.ready, io.in.d.valid)
node _T_1077 = and(_T_1076, d_first)
when _T_1077 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1078 = and(io.in.a.valid, a_first_1)
node _T_1079 = and(_T_1078, UInt<1>(0h1))
when _T_1079 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1080 = and(io.in.a.ready, io.in.a.valid)
node _T_1081 = and(_T_1080, a_first_1)
node _T_1082 = and(_T_1081, UInt<1>(0h1))
when _T_1082 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1083 = dshr(inflight, io.in.a.bits.source)
node _T_1084 = bits(_T_1083, 0, 0)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1089 = and(io.in.d.valid, d_first_1)
node _T_1090 = and(_T_1089, UInt<1>(0h1))
node _T_1091 = eq(d_release_ack, UInt<1>(0h0))
node _T_1092 = and(_T_1090, _T_1091)
when _T_1092 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1093 = and(io.in.d.ready, io.in.d.valid)
node _T_1094 = and(_T_1093, d_first_1)
node _T_1095 = and(_T_1094, UInt<1>(0h1))
node _T_1096 = eq(d_release_ack, UInt<1>(0h0))
node _T_1097 = and(_T_1095, _T_1096)
when _T_1097 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1098 = and(io.in.d.valid, d_first_1)
node _T_1099 = and(_T_1098, UInt<1>(0h1))
node _T_1100 = eq(d_release_ack, UInt<1>(0h0))
node _T_1101 = and(_T_1099, _T_1100)
when _T_1101 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1102 = dshr(inflight, io.in.d.bits.source)
node _T_1103 = bits(_T_1102, 0, 0)
node _T_1104 = or(_T_1103, same_cycle_resp)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1110 = or(_T_1108, _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100
node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101
else :
node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1120 = or(_T_1118, _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102
node _T_1124 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103
node _T_1128 = and(io.in.d.valid, d_first_1)
node _T_1129 = and(_T_1128, a_first_1)
node _T_1130 = and(_T_1129, io.in.a.valid)
node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(d_release_ack, UInt<1>(0h0))
node _T_1134 = and(_T_1132, _T_1133)
when _T_1134 :
node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1136 = or(_T_1135, io.in.a.ready)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_50
node _T_1140 = orr(inflight)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1143 = or(_T_1141, _T_1142)
node _T_1144 = lt(watchdog, plusarg_reader.out)
node _T_1145 = or(_T_1143, _T_1144)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(io.in.d.ready, io.in.d.valid)
node _T_1151 = or(_T_1149, _T_1150)
when _T_1151 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<12>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<12>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1152 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<12>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1153 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1154 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = and(_T_1152, _T_1155)
when _T_1156 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<12>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1157 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1158 = and(_T_1157, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<12>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1159 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1160 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1161 = and(_T_1159, _T_1160)
node _T_1162 = and(_T_1158, _T_1161)
when _T_1162 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<12>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1163 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1164 = bits(_T_1163, 0, 0)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1169 = and(io.in.d.valid, d_first_2)
node _T_1170 = and(_T_1169, UInt<1>(0h1))
node _T_1171 = and(_T_1170, d_release_ack_1)
when _T_1171 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1172 = and(io.in.d.ready, io.in.d.valid)
node _T_1173 = and(_T_1172, d_first_2)
node _T_1174 = and(_T_1173, UInt<1>(0h1))
node _T_1175 = and(_T_1174, d_release_ack_1)
when _T_1175 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1176 = and(io.in.d.valid, d_first_2)
node _T_1177 = and(_T_1176, UInt<1>(0h1))
node _T_1178 = and(_T_1177, d_release_ack_1)
when _T_1178 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1179 = dshr(inflight_1, io.in.d.bits.source)
node _T_1180 = bits(_T_1179, 0, 0)
node _T_1181 = or(_T_1180, same_cycle_resp_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<12>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1185 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_108
else :
node _T_1189 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_109
node _T_1193 = and(io.in.d.valid, d_first_2)
node _T_1194 = and(_T_1193, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<12>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1195 = and(_T_1194, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<12>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1196 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1197 = and(_T_1195, _T_1196)
node _T_1198 = and(_T_1197, d_release_ack_1)
node _T_1199 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<12>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1202 = or(_T_1201, _WIRE_27.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_51
node _T_1206 = orr(inflight_1)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
node _T_1208 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1209 = or(_T_1207, _T_1208)
node _T_1210 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:90:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<12>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1215 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1216 = and(io.in.d.ready, io.in.d.valid)
node _T_1217 = or(_T_1215, _T_1216)
when _T_1217 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_25( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_55 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_79
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_55( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_79 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<17>(0h10000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<18>(0h2f000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<13>(0h1000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<27>(0h4000000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<13>(0h1000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_27, _T_32)
node _T_69 = or(_T_68, _T_37)
node _T_70 = or(_T_69, _T_42)
node _T_71 = or(_T_70, _T_47)
node _T_72 = or(_T_71, _T_52)
node _T_73 = or(_T_72, _T_57)
node _T_74 = or(_T_73, _T_62)
node _T_75 = or(_T_74, _T_67)
node _T_76 = and(_T_22, _T_75)
node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_78 = or(UInt<1>(0h0), _T_77)
node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = and(_T_78, _T_89)
node _T_91 = or(UInt<1>(0h0), _T_76)
node _T_92 = or(_T_91, _T_90)
node _T_93 = and(_T_21, _T_92)
node _T_94 = asUInt(reset)
node _T_95 = eq(_T_94, UInt<1>(0h0))
when _T_95 :
node _T_96 = eq(_T_93, UInt<1>(0h0))
when _T_96 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_93, UInt<1>(0h1), "") : assert_2
node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_99 = and(_T_97, _T_98)
node _T_100 = or(UInt<1>(0h0), _T_99)
node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<13>(0h1000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<18>(0h2f000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<17>(0h10000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<27>(0h4000000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = or(_T_105, _T_110)
node _T_157 = or(_T_156, _T_115)
node _T_158 = or(_T_157, _T_120)
node _T_159 = or(_T_158, _T_125)
node _T_160 = or(_T_159, _T_130)
node _T_161 = or(_T_160, _T_135)
node _T_162 = or(_T_161, _T_140)
node _T_163 = or(_T_162, _T_145)
node _T_164 = or(_T_163, _T_150)
node _T_165 = or(_T_164, _T_155)
node _T_166 = and(_T_100, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(UInt<1>(0h0), _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_168, UInt<1>(0h1), "") : assert_3
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_175 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_175, UInt<1>(0h1), "") : assert_5
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(is_aligned, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_183 = asUInt(reset)
node _T_184 = eq(_T_183, UInt<1>(0h0))
when _T_184 :
node _T_185 = eq(_T_182, UInt<1>(0h0))
when _T_185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_182, UInt<1>(0h1), "") : assert_7
node _T_186 = not(io.in.a.bits.mask)
node _T_187 = eq(_T_186, UInt<1>(0h0))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_187, UInt<1>(0h1), "") : assert_8
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_191, UInt<1>(0h1), "") : assert_9
node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_200 = and(_T_198, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<13>(0h1000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<17>(0h10000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_224 = cvt(_T_223)
node _T_225 = and(_T_224, asSInt(UInt<18>(0h2f000)))
node _T_226 = asSInt(_T_225)
node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0)))
node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<17>(0h10000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_234 = cvt(_T_233)
node _T_235 = and(_T_234, asSInt(UInt<13>(0h1000)))
node _T_236 = asSInt(_T_235)
node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0)))
node _T_238 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_239 = cvt(_T_238)
node _T_240 = and(_T_239, asSInt(UInt<27>(0h4000000)))
node _T_241 = asSInt(_T_240)
node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0)))
node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_244 = cvt(_T_243)
node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000)))
node _T_246 = asSInt(_T_245)
node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0)))
node _T_248 = or(_T_207, _T_212)
node _T_249 = or(_T_248, _T_217)
node _T_250 = or(_T_249, _T_222)
node _T_251 = or(_T_250, _T_227)
node _T_252 = or(_T_251, _T_232)
node _T_253 = or(_T_252, _T_237)
node _T_254 = or(_T_253, _T_242)
node _T_255 = or(_T_254, _T_247)
node _T_256 = and(_T_202, _T_255)
node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = or(_T_263, _T_268)
node _T_270 = and(_T_258, _T_269)
node _T_271 = or(UInt<1>(0h0), _T_256)
node _T_272 = or(_T_271, _T_270)
node _T_273 = and(_T_201, _T_272)
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(_T_273, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_273, UInt<1>(0h1), "") : assert_10
node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_279 = and(_T_277, _T_278)
node _T_280 = or(UInt<1>(0h0), _T_279)
node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<13>(0h1000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<18>(0h2f000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<17>(0h10000)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_317 = cvt(_T_316)
node _T_318 = and(_T_317, asSInt(UInt<17>(0h10000)))
node _T_319 = asSInt(_T_318)
node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0)))
node _T_321 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_322 = cvt(_T_321)
node _T_323 = and(_T_322, asSInt(UInt<27>(0h4000000)))
node _T_324 = asSInt(_T_323)
node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0)))
node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = or(_T_285, _T_290)
node _T_337 = or(_T_336, _T_295)
node _T_338 = or(_T_337, _T_300)
node _T_339 = or(_T_338, _T_305)
node _T_340 = or(_T_339, _T_310)
node _T_341 = or(_T_340, _T_315)
node _T_342 = or(_T_341, _T_320)
node _T_343 = or(_T_342, _T_325)
node _T_344 = or(_T_343, _T_330)
node _T_345 = or(_T_344, _T_335)
node _T_346 = and(_T_280, _T_345)
node _T_347 = or(UInt<1>(0h0), _T_346)
node _T_348 = and(UInt<1>(0h0), _T_347)
node _T_349 = asUInt(reset)
node _T_350 = eq(_T_349, UInt<1>(0h0))
when _T_350 :
node _T_351 = eq(_T_348, UInt<1>(0h0))
when _T_351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_348, UInt<1>(0h1), "") : assert_11
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_355 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_355, UInt<1>(0h1), "") : assert_13
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(is_aligned, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_362, UInt<1>(0h1), "") : assert_15
node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_366, UInt<1>(0h1), "") : assert_16
node _T_370 = not(io.in.a.bits.mask)
node _T_371 = eq(_T_370, UInt<1>(0h0))
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(_T_371, UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_371, UInt<1>(0h1), "") : assert_17
node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_375, UInt<1>(0h1), "") : assert_18
node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_379 :
node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
node _T_385 = or(UInt<1>(0h0), _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_385, UInt<1>(0h1), "") : assert_19
node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_391 = and(_T_389, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_394 = cvt(_T_393)
node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000)))
node _T_396 = asSInt(_T_395)
node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0)))
node _T_398 = and(_T_392, _T_397)
node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_401 = and(_T_399, _T_400)
node _T_402 = or(UInt<1>(0h0), _T_401)
node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_404 = cvt(_T_403)
node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000)))
node _T_406 = asSInt(_T_405)
node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0)))
node _T_408 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_409 = cvt(_T_408)
node _T_410 = and(_T_409, asSInt(UInt<13>(0h1000)))
node _T_411 = asSInt(_T_410)
node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0)))
node _T_413 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_414 = cvt(_T_413)
node _T_415 = and(_T_414, asSInt(UInt<17>(0h10000)))
node _T_416 = asSInt(_T_415)
node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0)))
node _T_418 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<18>(0h2f000)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<17>(0h10000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<13>(0h1000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<17>(0h10000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<27>(0h4000000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<13>(0h1000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = or(_T_407, _T_412)
node _T_454 = or(_T_453, _T_417)
node _T_455 = or(_T_454, _T_422)
node _T_456 = or(_T_455, _T_427)
node _T_457 = or(_T_456, _T_432)
node _T_458 = or(_T_457, _T_437)
node _T_459 = or(_T_458, _T_442)
node _T_460 = or(_T_459, _T_447)
node _T_461 = or(_T_460, _T_452)
node _T_462 = and(_T_402, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_398)
node _T_464 = or(_T_463, _T_462)
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_464, UInt<1>(0h1), "") : assert_20
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_471 = asUInt(reset)
node _T_472 = eq(_T_471, UInt<1>(0h0))
when _T_472 :
node _T_473 = eq(is_aligned, UInt<1>(0h0))
when _T_473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_474, UInt<1>(0h1), "") : assert_23
node _T_478 = eq(io.in.a.bits.mask, mask)
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_478, UInt<1>(0h1), "") : assert_24
node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_482, UInt<1>(0h1), "") : assert_25
node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_486 :
node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_489 = and(_T_487, _T_488)
node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_491 = and(_T_489, _T_490)
node _T_492 = or(UInt<1>(0h0), _T_491)
node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_495 = and(_T_493, _T_494)
node _T_496 = or(UInt<1>(0h0), _T_495)
node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = and(_T_496, _T_501)
node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_505 = and(_T_503, _T_504)
node _T_506 = or(UInt<1>(0h0), _T_505)
node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<13>(0h1000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<18>(0h2f000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<13>(0h1000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<17>(0h10000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<27>(0h4000000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_543 = cvt(_T_542)
node _T_544 = and(_T_543, asSInt(UInt<13>(0h1000)))
node _T_545 = asSInt(_T_544)
node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0)))
node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_548 = cvt(_T_547)
node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000)))
node _T_550 = asSInt(_T_549)
node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0)))
node _T_552 = or(_T_511, _T_516)
node _T_553 = or(_T_552, _T_521)
node _T_554 = or(_T_553, _T_526)
node _T_555 = or(_T_554, _T_531)
node _T_556 = or(_T_555, _T_536)
node _T_557 = or(_T_556, _T_541)
node _T_558 = or(_T_557, _T_546)
node _T_559 = or(_T_558, _T_551)
node _T_560 = and(_T_506, _T_559)
node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = and(_T_561, _T_566)
node _T_568 = or(UInt<1>(0h0), _T_502)
node _T_569 = or(_T_568, _T_560)
node _T_570 = or(_T_569, _T_567)
node _T_571 = and(_T_492, _T_570)
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(_T_571, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_571, UInt<1>(0h1), "") : assert_26
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(is_aligned, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_581, UInt<1>(0h1), "") : assert_29
node _T_585 = eq(io.in.a.bits.mask, mask)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_585, UInt<1>(0h1), "") : assert_30
node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_589 :
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_594 = and(_T_592, _T_593)
node _T_595 = or(UInt<1>(0h0), _T_594)
node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_598 = and(_T_596, _T_597)
node _T_599 = or(UInt<1>(0h0), _T_598)
node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_601 = cvt(_T_600)
node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000)))
node _T_603 = asSInt(_T_602)
node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0)))
node _T_605 = and(_T_599, _T_604)
node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(UInt<1>(0h0), _T_608)
node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<13>(0h1000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<18>(0h2f000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_626 = cvt(_T_625)
node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000)))
node _T_628 = asSInt(_T_627)
node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0)))
node _T_630 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<13>(0h1000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<17>(0h10000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<27>(0h4000000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_646 = cvt(_T_645)
node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000)))
node _T_648 = asSInt(_T_647)
node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0)))
node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = or(_T_614, _T_619)
node _T_656 = or(_T_655, _T_624)
node _T_657 = or(_T_656, _T_629)
node _T_658 = or(_T_657, _T_634)
node _T_659 = or(_T_658, _T_639)
node _T_660 = or(_T_659, _T_644)
node _T_661 = or(_T_660, _T_649)
node _T_662 = or(_T_661, _T_654)
node _T_663 = and(_T_609, _T_662)
node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = and(_T_664, _T_669)
node _T_671 = or(UInt<1>(0h0), _T_605)
node _T_672 = or(_T_671, _T_663)
node _T_673 = or(_T_672, _T_670)
node _T_674 = and(_T_595, _T_673)
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_674, UInt<1>(0h1), "") : assert_31
node _T_678 = asUInt(reset)
node _T_679 = eq(_T_678, UInt<1>(0h0))
when _T_679 :
node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(is_aligned, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_685 = asUInt(reset)
node _T_686 = eq(_T_685, UInt<1>(0h0))
when _T_686 :
node _T_687 = eq(_T_684, UInt<1>(0h0))
when _T_687 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_684, UInt<1>(0h1), "") : assert_34
node _T_688 = not(mask)
node _T_689 = and(io.in.a.bits.mask, _T_688)
node _T_690 = eq(_T_689, UInt<1>(0h0))
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_690, UInt<1>(0h1), "") : assert_35
node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_694 :
node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_699 = and(_T_697, _T_698)
node _T_700 = or(UInt<1>(0h0), _T_699)
node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _T_704 = or(UInt<1>(0h0), _T_703)
node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<13>(0h1000)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_721 = cvt(_T_720)
node _T_722 = and(_T_721, asSInt(UInt<18>(0h2f000)))
node _T_723 = asSInt(_T_722)
node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0)))
node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_726 = cvt(_T_725)
node _T_727 = and(_T_726, asSInt(UInt<17>(0h10000)))
node _T_728 = asSInt(_T_727)
node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0)))
node _T_730 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<13>(0h1000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_736 = cvt(_T_735)
node _T_737 = and(_T_736, asSInt(UInt<17>(0h10000)))
node _T_738 = asSInt(_T_737)
node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0)))
node _T_740 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<27>(0h4000000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<13>(0h1000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_751 = cvt(_T_750)
node _T_752 = and(_T_751, asSInt(UInt<29>(0h10000000)))
node _T_753 = asSInt(_T_752)
node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0)))
node _T_755 = or(_T_709, _T_714)
node _T_756 = or(_T_755, _T_719)
node _T_757 = or(_T_756, _T_724)
node _T_758 = or(_T_757, _T_729)
node _T_759 = or(_T_758, _T_734)
node _T_760 = or(_T_759, _T_739)
node _T_761 = or(_T_760, _T_744)
node _T_762 = or(_T_761, _T_749)
node _T_763 = or(_T_762, _T_754)
node _T_764 = and(_T_704, _T_763)
node _T_765 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_766 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<17>(0h10000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = and(_T_765, _T_770)
node _T_772 = or(UInt<1>(0h0), _T_764)
node _T_773 = or(_T_772, _T_771)
node _T_774 = and(_T_700, _T_773)
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_774, UInt<1>(0h1), "") : assert_36
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_781 = asUInt(reset)
node _T_782 = eq(_T_781, UInt<1>(0h0))
when _T_782 :
node _T_783 = eq(is_aligned, UInt<1>(0h0))
when _T_783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_784 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_785 = asUInt(reset)
node _T_786 = eq(_T_785, UInt<1>(0h0))
when _T_786 :
node _T_787 = eq(_T_784, UInt<1>(0h0))
when _T_787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_784, UInt<1>(0h1), "") : assert_39
node _T_788 = eq(io.in.a.bits.mask, mask)
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(_T_788, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_788, UInt<1>(0h1), "") : assert_40
node _T_792 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_792 :
node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_794 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_795 = and(_T_793, _T_794)
node _T_796 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_797 = and(_T_795, _T_796)
node _T_798 = or(UInt<1>(0h0), _T_797)
node _T_799 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_800 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_801 = and(_T_799, _T_800)
node _T_802 = or(UInt<1>(0h0), _T_801)
node _T_803 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<14>(0h2000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_809 = cvt(_T_808)
node _T_810 = and(_T_809, asSInt(UInt<13>(0h1000)))
node _T_811 = asSInt(_T_810)
node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0)))
node _T_813 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<18>(0h2f000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_834 = cvt(_T_833)
node _T_835 = and(_T_834, asSInt(UInt<17>(0h10000)))
node _T_836 = asSInt(_T_835)
node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0)))
node _T_838 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<27>(0h4000000)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<13>(0h1000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<29>(0h10000000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = or(_T_807, _T_812)
node _T_854 = or(_T_853, _T_817)
node _T_855 = or(_T_854, _T_822)
node _T_856 = or(_T_855, _T_827)
node _T_857 = or(_T_856, _T_832)
node _T_858 = or(_T_857, _T_837)
node _T_859 = or(_T_858, _T_842)
node _T_860 = or(_T_859, _T_847)
node _T_861 = or(_T_860, _T_852)
node _T_862 = and(_T_802, _T_861)
node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_864 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<17>(0h10000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = and(_T_863, _T_868)
node _T_870 = or(UInt<1>(0h0), _T_862)
node _T_871 = or(_T_870, _T_869)
node _T_872 = and(_T_798, _T_871)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_872, UInt<1>(0h1), "") : assert_41
node _T_876 = asUInt(reset)
node _T_877 = eq(_T_876, UInt<1>(0h0))
when _T_877 :
node _T_878 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_878 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_879 = asUInt(reset)
node _T_880 = eq(_T_879, UInt<1>(0h0))
when _T_880 :
node _T_881 = eq(is_aligned, UInt<1>(0h0))
when _T_881 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_882 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_882, UInt<1>(0h1), "") : assert_44
node _T_886 = eq(io.in.a.bits.mask, mask)
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(_T_886, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_886, UInt<1>(0h1), "") : assert_45
node _T_890 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_890 :
node _T_891 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_892 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_893 = and(_T_891, _T_892)
node _T_894 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_895 = and(_T_893, _T_894)
node _T_896 = or(UInt<1>(0h0), _T_895)
node _T_897 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_898 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_899 = and(_T_897, _T_898)
node _T_900 = or(UInt<1>(0h0), _T_899)
node _T_901 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = and(_T_900, _T_905)
node _T_907 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_908 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_909 = cvt(_T_908)
node _T_910 = and(_T_909, asSInt(UInt<14>(0h2000)))
node _T_911 = asSInt(_T_910)
node _T_912 = eq(_T_911, asSInt(UInt<1>(0h0)))
node _T_913 = xor(io.in.a.bits.address, UInt<15>(0h4000))
node _T_914 = cvt(_T_913)
node _T_915 = and(_T_914, asSInt(UInt<13>(0h1000)))
node _T_916 = asSInt(_T_915)
node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0)))
node _T_918 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_919 = cvt(_T_918)
node _T_920 = and(_T_919, asSInt(UInt<17>(0h10000)))
node _T_921 = asSInt(_T_920)
node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0)))
node _T_923 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_924 = cvt(_T_923)
node _T_925 = and(_T_924, asSInt(UInt<18>(0h2f000)))
node _T_926 = asSInt(_T_925)
node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0)))
node _T_928 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_929 = cvt(_T_928)
node _T_930 = and(_T_929, asSInt(UInt<17>(0h10000)))
node _T_931 = asSInt(_T_930)
node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0)))
node _T_933 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_934 = cvt(_T_933)
node _T_935 = and(_T_934, asSInt(UInt<13>(0h1000)))
node _T_936 = asSInt(_T_935)
node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0)))
node _T_938 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_939 = cvt(_T_938)
node _T_940 = and(_T_939, asSInt(UInt<27>(0h4000000)))
node _T_941 = asSInt(_T_940)
node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0)))
node _T_943 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_944 = cvt(_T_943)
node _T_945 = and(_T_944, asSInt(UInt<13>(0h1000)))
node _T_946 = asSInt(_T_945)
node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0)))
node _T_948 = or(_T_912, _T_917)
node _T_949 = or(_T_948, _T_922)
node _T_950 = or(_T_949, _T_927)
node _T_951 = or(_T_950, _T_932)
node _T_952 = or(_T_951, _T_937)
node _T_953 = or(_T_952, _T_942)
node _T_954 = or(_T_953, _T_947)
node _T_955 = and(_T_907, _T_954)
node _T_956 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_957 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_958 = and(_T_956, _T_957)
node _T_959 = or(UInt<1>(0h0), _T_958)
node _T_960 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_961 = cvt(_T_960)
node _T_962 = and(_T_961, asSInt(UInt<17>(0h10000)))
node _T_963 = asSInt(_T_962)
node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0)))
node _T_965 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_966 = cvt(_T_965)
node _T_967 = and(_T_966, asSInt(UInt<29>(0h10000000)))
node _T_968 = asSInt(_T_967)
node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0)))
node _T_970 = or(_T_964, _T_969)
node _T_971 = and(_T_959, _T_970)
node _T_972 = or(UInt<1>(0h0), _T_906)
node _T_973 = or(_T_972, _T_955)
node _T_974 = or(_T_973, _T_971)
node _T_975 = and(_T_896, _T_974)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_975, UInt<1>(0h1), "") : assert_46
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_982 = asUInt(reset)
node _T_983 = eq(_T_982, UInt<1>(0h0))
when _T_983 :
node _T_984 = eq(is_aligned, UInt<1>(0h0))
when _T_984 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_985 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_985, UInt<1>(0h1), "") : assert_49
node _T_989 = eq(io.in.a.bits.mask, mask)
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_T_989, UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_989, UInt<1>(0h1), "") : assert_50
node _T_993 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_993, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_997 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_997, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1001 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1001 :
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_54
node _T_1009 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_55
node _T_1013 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_56
node _T_1017 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_57
node _T_1021 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1021 :
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(sink_ok, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1028 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_60
node _T_1032 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_61
node _T_1036 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_62
node _T_1040 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_63
node _T_1044 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1045 = or(UInt<1>(0h1), _T_1044)
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_64
node _T_1049 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1049 :
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(sink_ok, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1056 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_67
node _T_1060 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_68
node _T_1064 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_69
node _T_1068 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1069 = or(_T_1068, io.in.d.bits.corrupt)
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_70
node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1074 = or(UInt<1>(0h1), _T_1073)
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_71
node _T_1078 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_73
node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_74
node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1091 = or(UInt<1>(0h1), _T_1090)
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(_T_1091, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1091, UInt<1>(0h1), "") : assert_75
node _T_1095 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1095 :
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1099 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_77
node _T_1103 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1104 = or(_T_1103, io.in.d.bits.corrupt)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_78
node _T_1108 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1109 = or(UInt<1>(0h1), _T_1108)
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_79
node _T_1113 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1113 :
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1117 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_81
node _T_1121 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_82
node _T_1125 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1126 = or(UInt<1>(0h1), _T_1125)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1130 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1134 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1138 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1142 = eq(a_first, UInt<1>(0h0))
node _T_1143 = and(io.in.a.valid, _T_1142)
when _T_1143 :
node _T_1144 = eq(io.in.a.bits.opcode, opcode)
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_87
node _T_1148 = eq(io.in.a.bits.param, param)
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_88
node _T_1152 = eq(io.in.a.bits.size, size)
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_89
node _T_1156 = eq(io.in.a.bits.source, source)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_90
node _T_1160 = eq(io.in.a.bits.address, address)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_91
node _T_1164 = and(io.in.a.ready, io.in.a.valid)
node _T_1165 = and(_T_1164, a_first)
when _T_1165 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1166 = eq(d_first, UInt<1>(0h0))
node _T_1167 = and(io.in.d.valid, _T_1166)
when _T_1167 :
node _T_1168 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_92
node _T_1172 = eq(io.in.d.bits.param, param_1)
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_93
node _T_1176 = eq(io.in.d.bits.size, size_1)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_94
node _T_1180 = eq(io.in.d.bits.source, source_1)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_95
node _T_1184 = eq(io.in.d.bits.sink, sink)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_96
node _T_1188 = eq(io.in.d.bits.denied, denied)
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_97
node _T_1192 = and(io.in.d.ready, io.in.d.valid)
node _T_1193 = and(_T_1192, d_first)
when _T_1193 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1194 = and(io.in.a.valid, a_first_1)
node _T_1195 = and(_T_1194, UInt<1>(0h1))
when _T_1195 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1196 = and(io.in.a.ready, io.in.a.valid)
node _T_1197 = and(_T_1196, a_first_1)
node _T_1198 = and(_T_1197, UInt<1>(0h1))
when _T_1198 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1199 = dshr(inflight, io.in.a.bits.source)
node _T_1200 = bits(_T_1199, 0, 0)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
node _T_1202 = asUInt(reset)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
when _T_1203 :
node _T_1204 = eq(_T_1201, UInt<1>(0h0))
when _T_1204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1201, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1205 = and(io.in.d.valid, d_first_1)
node _T_1206 = and(_T_1205, UInt<1>(0h1))
node _T_1207 = eq(d_release_ack, UInt<1>(0h0))
node _T_1208 = and(_T_1206, _T_1207)
when _T_1208 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1209 = and(io.in.d.ready, io.in.d.valid)
node _T_1210 = and(_T_1209, d_first_1)
node _T_1211 = and(_T_1210, UInt<1>(0h1))
node _T_1212 = eq(d_release_ack, UInt<1>(0h0))
node _T_1213 = and(_T_1211, _T_1212)
when _T_1213 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1214 = and(io.in.d.valid, d_first_1)
node _T_1215 = and(_T_1214, UInt<1>(0h1))
node _T_1216 = eq(d_release_ack, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
when _T_1217 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1218 = dshr(inflight, io.in.d.bits.source)
node _T_1219 = bits(_T_1218, 0, 0)
node _T_1220 = or(_T_1219, same_cycle_resp)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1224 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1225 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1226 = or(_T_1224, _T_1225)
node _T_1227 = asUInt(reset)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
when _T_1228 :
node _T_1229 = eq(_T_1226, UInt<1>(0h0))
when _T_1229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1226, UInt<1>(0h1), "") : assert_100
node _T_1230 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_101
else :
node _T_1234 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1236 = or(_T_1234, _T_1235)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_102
node _T_1240 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_103
node _T_1244 = and(io.in.d.valid, d_first_1)
node _T_1245 = and(_T_1244, a_first_1)
node _T_1246 = and(_T_1245, io.in.a.valid)
node _T_1247 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1248 = and(_T_1246, _T_1247)
node _T_1249 = eq(d_release_ack, UInt<1>(0h0))
node _T_1250 = and(_T_1248, _T_1249)
when _T_1250 :
node _T_1251 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1252 = or(_T_1251, io.in.a.ready)
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_104
node _T_1256 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1257 = orr(a_set_wo_ready)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
node _T_1259 = or(_T_1256, _T_1258)
node _T_1260 = asUInt(reset)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
when _T_1261 :
node _T_1262 = eq(_T_1259, UInt<1>(0h0))
when _T_1262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1259, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_131
node _T_1263 = orr(inflight)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
node _T_1265 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1266 = or(_T_1264, _T_1265)
node _T_1267 = lt(watchdog, plusarg_reader.out)
node _T_1268 = or(_T_1266, _T_1267)
node _T_1269 = asUInt(reset)
node _T_1270 = eq(_T_1269, UInt<1>(0h0))
when _T_1270 :
node _T_1271 = eq(_T_1268, UInt<1>(0h0))
when _T_1271 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1268, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1272 = and(io.in.a.ready, io.in.a.valid)
node _T_1273 = and(io.in.d.ready, io.in.d.valid)
node _T_1274 = or(_T_1272, _T_1273)
when _T_1274 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1275 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1276 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1277 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1278 = and(_T_1276, _T_1277)
node _T_1279 = and(_T_1275, _T_1278)
when _T_1279 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1280 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1281 = and(_T_1280, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1282 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1283 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1284 = and(_T_1282, _T_1283)
node _T_1285 = and(_T_1281, _T_1284)
when _T_1285 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1286 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1287 = bits(_T_1286, 0, 0)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1292 = and(io.in.d.valid, d_first_2)
node _T_1293 = and(_T_1292, UInt<1>(0h1))
node _T_1294 = and(_T_1293, d_release_ack_1)
when _T_1294 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1295 = and(io.in.d.ready, io.in.d.valid)
node _T_1296 = and(_T_1295, d_first_2)
node _T_1297 = and(_T_1296, UInt<1>(0h1))
node _T_1298 = and(_T_1297, d_release_ack_1)
when _T_1298 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1299 = and(io.in.d.valid, d_first_2)
node _T_1300 = and(_T_1299, UInt<1>(0h1))
node _T_1301 = and(_T_1300, d_release_ack_1)
when _T_1301 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1302 = dshr(inflight_1, io.in.d.bits.source)
node _T_1303 = bits(_T_1302, 0, 0)
node _T_1304 = or(_T_1303, same_cycle_resp_1)
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1308 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_109
else :
node _T_1312 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_110
node _T_1316 = and(io.in.d.valid, d_first_2)
node _T_1317 = and(_T_1316, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1318 = and(_T_1317, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1319 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1320 = and(_T_1318, _T_1319)
node _T_1321 = and(_T_1320, d_release_ack_1)
node _T_1322 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1323 = and(_T_1321, _T_1322)
when _T_1323 :
node _T_1324 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1325 = or(_T_1324, _WIRE_23.ready)
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(_T_1325, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1325, UInt<1>(0h1), "") : assert_111
node _T_1329 = orr(c_set_wo_ready)
when _T_1329 :
node _T_1330 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1331 = asUInt(reset)
node _T_1332 = eq(_T_1331, UInt<1>(0h0))
when _T_1332 :
node _T_1333 = eq(_T_1330, UInt<1>(0h0))
when _T_1333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1330, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_132
node _T_1334 = orr(inflight_1)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
node _T_1336 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1337 = or(_T_1335, _T_1336)
node _T_1338 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1339 = or(_T_1337, _T_1338)
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1343 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1344 = and(io.in.d.ready, io.in.d.valid)
node _T_1345 = or(_T_1343, _T_1344)
when _T_1345 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_62( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_pbus :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_4
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
wire initval : { state : UInt<2>}
connect initval.state, UInt<1>(0h0)
wire _cam_s_WIRE : { state : UInt<2>}[1]
connect _cam_s_WIRE[0], initval
regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE
reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock
reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock
node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0))
node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2))
node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3))
node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2))
node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1)
node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0))
node _a_canLogical_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canLogical_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canLogical_T_2 = cvt(_a_canLogical_T_1)
node _a_canLogical_T_3 = and(_a_canLogical_T_2, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_4 = asSInt(_a_canLogical_T_3)
node _a_canLogical_T_5 = eq(_a_canLogical_T_4, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_6 = and(_a_canLogical_T, _a_canLogical_T_5)
node _a_canLogical_T_7 = or(UInt<1>(0h0), _a_canLogical_T_6)
node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_7)
node _a_canArithmetic_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canArithmetic_T_1 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canArithmetic_T_2 = cvt(_a_canArithmetic_T_1)
node _a_canArithmetic_T_3 = and(_a_canArithmetic_T_2, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_4 = asSInt(_a_canArithmetic_T_3)
node _a_canArithmetic_T_5 = eq(_a_canArithmetic_T_4, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_6 = and(_a_canArithmetic_T, _a_canArithmetic_T_5)
node _a_canArithmetic_T_7 = or(UInt<1>(0h0), _a_canArithmetic_T_6)
node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_7)
node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3))
node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2))
node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1))
node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T)
node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0)
node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T)
node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_fifoId_T_1 = cvt(_a_fifoId_T)
node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0)))
node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2)
node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0)))
node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0))
node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T)
node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0)
node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T)
node _indexes_T = bits(cam_a[0].bits.data, 0, 0)
node _indexes_T_1 = bits(cam_d[0].data, 0, 0)
node indexes_0 = cat(_indexes_T, _indexes_T_1)
node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1)
node _indexes_T_3 = bits(cam_d[0].data, 1, 1)
node indexes_1 = cat(_indexes_T_2, _indexes_T_3)
node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2)
node _indexes_T_5 = bits(cam_d[0].data, 2, 2)
node indexes_2 = cat(_indexes_T_4, _indexes_T_5)
node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3)
node _indexes_T_7 = bits(cam_d[0].data, 3, 3)
node indexes_3 = cat(_indexes_T_6, _indexes_T_7)
node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4)
node _indexes_T_9 = bits(cam_d[0].data, 4, 4)
node indexes_4 = cat(_indexes_T_8, _indexes_T_9)
node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5)
node _indexes_T_11 = bits(cam_d[0].data, 5, 5)
node indexes_5 = cat(_indexes_T_10, _indexes_T_11)
node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6)
node _indexes_T_13 = bits(cam_d[0].data, 6, 6)
node indexes_6 = cat(_indexes_T_12, _indexes_T_13)
node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7)
node _indexes_T_15 = bits(cam_d[0].data, 7, 7)
node indexes_7 = cat(_indexes_T_14, _indexes_T_15)
node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8)
node _indexes_T_17 = bits(cam_d[0].data, 8, 8)
node indexes_8 = cat(_indexes_T_16, _indexes_T_17)
node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9)
node _indexes_T_19 = bits(cam_d[0].data, 9, 9)
node indexes_9 = cat(_indexes_T_18, _indexes_T_19)
node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10)
node _indexes_T_21 = bits(cam_d[0].data, 10, 10)
node indexes_10 = cat(_indexes_T_20, _indexes_T_21)
node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11)
node _indexes_T_23 = bits(cam_d[0].data, 11, 11)
node indexes_11 = cat(_indexes_T_22, _indexes_T_23)
node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12)
node _indexes_T_25 = bits(cam_d[0].data, 12, 12)
node indexes_12 = cat(_indexes_T_24, _indexes_T_25)
node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13)
node _indexes_T_27 = bits(cam_d[0].data, 13, 13)
node indexes_13 = cat(_indexes_T_26, _indexes_T_27)
node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14)
node _indexes_T_29 = bits(cam_d[0].data, 14, 14)
node indexes_14 = cat(_indexes_T_28, _indexes_T_29)
node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15)
node _indexes_T_31 = bits(cam_d[0].data, 15, 15)
node indexes_15 = cat(_indexes_T_30, _indexes_T_31)
node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16)
node _indexes_T_33 = bits(cam_d[0].data, 16, 16)
node indexes_16 = cat(_indexes_T_32, _indexes_T_33)
node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17)
node _indexes_T_35 = bits(cam_d[0].data, 17, 17)
node indexes_17 = cat(_indexes_T_34, _indexes_T_35)
node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18)
node _indexes_T_37 = bits(cam_d[0].data, 18, 18)
node indexes_18 = cat(_indexes_T_36, _indexes_T_37)
node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19)
node _indexes_T_39 = bits(cam_d[0].data, 19, 19)
node indexes_19 = cat(_indexes_T_38, _indexes_T_39)
node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20)
node _indexes_T_41 = bits(cam_d[0].data, 20, 20)
node indexes_20 = cat(_indexes_T_40, _indexes_T_41)
node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21)
node _indexes_T_43 = bits(cam_d[0].data, 21, 21)
node indexes_21 = cat(_indexes_T_42, _indexes_T_43)
node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22)
node _indexes_T_45 = bits(cam_d[0].data, 22, 22)
node indexes_22 = cat(_indexes_T_44, _indexes_T_45)
node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23)
node _indexes_T_47 = bits(cam_d[0].data, 23, 23)
node indexes_23 = cat(_indexes_T_46, _indexes_T_47)
node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24)
node _indexes_T_49 = bits(cam_d[0].data, 24, 24)
node indexes_24 = cat(_indexes_T_48, _indexes_T_49)
node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25)
node _indexes_T_51 = bits(cam_d[0].data, 25, 25)
node indexes_25 = cat(_indexes_T_50, _indexes_T_51)
node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26)
node _indexes_T_53 = bits(cam_d[0].data, 26, 26)
node indexes_26 = cat(_indexes_T_52, _indexes_T_53)
node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27)
node _indexes_T_55 = bits(cam_d[0].data, 27, 27)
node indexes_27 = cat(_indexes_T_54, _indexes_T_55)
node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28)
node _indexes_T_57 = bits(cam_d[0].data, 28, 28)
node indexes_28 = cat(_indexes_T_56, _indexes_T_57)
node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29)
node _indexes_T_59 = bits(cam_d[0].data, 29, 29)
node indexes_29 = cat(_indexes_T_58, _indexes_T_59)
node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30)
node _indexes_T_61 = bits(cam_d[0].data, 30, 30)
node indexes_30 = cat(_indexes_T_60, _indexes_T_61)
node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31)
node _indexes_T_63 = bits(cam_d[0].data, 31, 31)
node indexes_31 = cat(_indexes_T_62, _indexes_T_63)
node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32)
node _indexes_T_65 = bits(cam_d[0].data, 32, 32)
node indexes_32 = cat(_indexes_T_64, _indexes_T_65)
node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33)
node _indexes_T_67 = bits(cam_d[0].data, 33, 33)
node indexes_33 = cat(_indexes_T_66, _indexes_T_67)
node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34)
node _indexes_T_69 = bits(cam_d[0].data, 34, 34)
node indexes_34 = cat(_indexes_T_68, _indexes_T_69)
node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35)
node _indexes_T_71 = bits(cam_d[0].data, 35, 35)
node indexes_35 = cat(_indexes_T_70, _indexes_T_71)
node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36)
node _indexes_T_73 = bits(cam_d[0].data, 36, 36)
node indexes_36 = cat(_indexes_T_72, _indexes_T_73)
node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37)
node _indexes_T_75 = bits(cam_d[0].data, 37, 37)
node indexes_37 = cat(_indexes_T_74, _indexes_T_75)
node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38)
node _indexes_T_77 = bits(cam_d[0].data, 38, 38)
node indexes_38 = cat(_indexes_T_76, _indexes_T_77)
node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39)
node _indexes_T_79 = bits(cam_d[0].data, 39, 39)
node indexes_39 = cat(_indexes_T_78, _indexes_T_79)
node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40)
node _indexes_T_81 = bits(cam_d[0].data, 40, 40)
node indexes_40 = cat(_indexes_T_80, _indexes_T_81)
node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41)
node _indexes_T_83 = bits(cam_d[0].data, 41, 41)
node indexes_41 = cat(_indexes_T_82, _indexes_T_83)
node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42)
node _indexes_T_85 = bits(cam_d[0].data, 42, 42)
node indexes_42 = cat(_indexes_T_84, _indexes_T_85)
node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43)
node _indexes_T_87 = bits(cam_d[0].data, 43, 43)
node indexes_43 = cat(_indexes_T_86, _indexes_T_87)
node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44)
node _indexes_T_89 = bits(cam_d[0].data, 44, 44)
node indexes_44 = cat(_indexes_T_88, _indexes_T_89)
node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45)
node _indexes_T_91 = bits(cam_d[0].data, 45, 45)
node indexes_45 = cat(_indexes_T_90, _indexes_T_91)
node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46)
node _indexes_T_93 = bits(cam_d[0].data, 46, 46)
node indexes_46 = cat(_indexes_T_92, _indexes_T_93)
node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47)
node _indexes_T_95 = bits(cam_d[0].data, 47, 47)
node indexes_47 = cat(_indexes_T_94, _indexes_T_95)
node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48)
node _indexes_T_97 = bits(cam_d[0].data, 48, 48)
node indexes_48 = cat(_indexes_T_96, _indexes_T_97)
node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49)
node _indexes_T_99 = bits(cam_d[0].data, 49, 49)
node indexes_49 = cat(_indexes_T_98, _indexes_T_99)
node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50)
node _indexes_T_101 = bits(cam_d[0].data, 50, 50)
node indexes_50 = cat(_indexes_T_100, _indexes_T_101)
node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51)
node _indexes_T_103 = bits(cam_d[0].data, 51, 51)
node indexes_51 = cat(_indexes_T_102, _indexes_T_103)
node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52)
node _indexes_T_105 = bits(cam_d[0].data, 52, 52)
node indexes_52 = cat(_indexes_T_104, _indexes_T_105)
node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53)
node _indexes_T_107 = bits(cam_d[0].data, 53, 53)
node indexes_53 = cat(_indexes_T_106, _indexes_T_107)
node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54)
node _indexes_T_109 = bits(cam_d[0].data, 54, 54)
node indexes_54 = cat(_indexes_T_108, _indexes_T_109)
node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55)
node _indexes_T_111 = bits(cam_d[0].data, 55, 55)
node indexes_55 = cat(_indexes_T_110, _indexes_T_111)
node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56)
node _indexes_T_113 = bits(cam_d[0].data, 56, 56)
node indexes_56 = cat(_indexes_T_112, _indexes_T_113)
node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57)
node _indexes_T_115 = bits(cam_d[0].data, 57, 57)
node indexes_57 = cat(_indexes_T_114, _indexes_T_115)
node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58)
node _indexes_T_117 = bits(cam_d[0].data, 58, 58)
node indexes_58 = cat(_indexes_T_116, _indexes_T_117)
node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59)
node _indexes_T_119 = bits(cam_d[0].data, 59, 59)
node indexes_59 = cat(_indexes_T_118, _indexes_T_119)
node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60)
node _indexes_T_121 = bits(cam_d[0].data, 60, 60)
node indexes_60 = cat(_indexes_T_120, _indexes_T_121)
node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61)
node _indexes_T_123 = bits(cam_d[0].data, 61, 61)
node indexes_61 = cat(_indexes_T_122, _indexes_T_123)
node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62)
node _indexes_T_125 = bits(cam_d[0].data, 62, 62)
node indexes_62 = cat(_indexes_T_124, _indexes_T_125)
node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63)
node _indexes_T_127 = bits(cam_d[0].data, 63, 63)
node indexes_63 = cat(_indexes_T_126, _indexes_T_127)
node _logic_out_T = dshr(cam_a[0].lut, indexes_0)
node _logic_out_T_1 = bits(_logic_out_T, 0, 0)
node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1)
node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0)
node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2)
node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0)
node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3)
node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0)
node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4)
node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0)
node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5)
node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0)
node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6)
node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0)
node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7)
node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0)
node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8)
node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0)
node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9)
node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0)
node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10)
node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0)
node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11)
node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0)
node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12)
node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0)
node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13)
node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0)
node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14)
node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0)
node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15)
node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0)
node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16)
node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0)
node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17)
node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0)
node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18)
node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0)
node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19)
node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0)
node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20)
node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0)
node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21)
node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0)
node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22)
node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0)
node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23)
node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0)
node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24)
node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0)
node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25)
node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0)
node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26)
node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0)
node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27)
node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0)
node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28)
node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0)
node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29)
node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0)
node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30)
node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0)
node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31)
node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0)
node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32)
node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0)
node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33)
node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0)
node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34)
node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0)
node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35)
node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0)
node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36)
node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0)
node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37)
node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0)
node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38)
node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0)
node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39)
node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0)
node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40)
node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0)
node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41)
node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0)
node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42)
node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0)
node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43)
node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0)
node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44)
node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0)
node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45)
node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0)
node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46)
node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0)
node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47)
node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0)
node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48)
node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0)
node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49)
node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0)
node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50)
node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0)
node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51)
node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0)
node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52)
node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0)
node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53)
node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0)
node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54)
node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0)
node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55)
node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0)
node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56)
node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0)
node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57)
node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0)
node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58)
node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0)
node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59)
node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0)
node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60)
node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0)
node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61)
node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0)
node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62)
node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0)
node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63)
node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0)
node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1)
node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5)
node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo)
node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9)
node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13)
node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo)
node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo)
node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17)
node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21)
node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo)
node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25)
node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29)
node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo)
node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo)
node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo)
node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33)
node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37)
node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo)
node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41)
node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45)
node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo)
node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo)
node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49)
node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53)
node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo)
node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57)
node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61)
node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo)
node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo)
node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo)
node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo)
node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65)
node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69)
node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo)
node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73)
node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77)
node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo)
node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo)
node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81)
node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85)
node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo)
node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89)
node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93)
node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo)
node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo)
node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo)
node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97)
node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101)
node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo)
node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105)
node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109)
node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo)
node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo)
node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113)
node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117)
node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo)
node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121)
node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125)
node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo)
node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo)
node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo)
node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo)
node logic_out = cat(logic_out_hi, logic_out_lo)
node unsigned = bits(cam_a[0].bits.param, 1, 1)
node take_max = bits(cam_a[0].bits.param, 0, 0)
node adder = bits(cam_a[0].bits.param, 2, 2)
node _signSel_T = not(cam_a[0].bits.mask)
node _signSel_T_1 = shr(cam_a[0].bits.mask, 1)
node _signSel_T_2 = or(_signSel_T, _signSel_T_1)
node signSel = not(_signSel_T_2)
node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7)
node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15)
node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23)
node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31)
node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39)
node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47)
node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55)
node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63)
node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T)
node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2)
node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo)
node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4)
node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6)
node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo)
node signbits_a = cat(signbits_a_hi, signbits_a_lo)
node _signbits_d_T = bits(cam_d[0].data, 7, 7)
node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15)
node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23)
node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31)
node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39)
node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47)
node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55)
node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63)
node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T)
node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2)
node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo)
node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4)
node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6)
node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo)
node signbits_d = cat(signbits_d_hi, signbits_d_lo)
node _signbit_a_T = and(signbits_a, signSel)
node _signbit_a_T_1 = shl(_signbit_a_T, 1)
node signbit_a = bits(_signbit_a_T_1, 7, 0)
node _signbit_d_T = and(signbits_d, signSel)
node _signbit_d_T_1 = shl(_signbit_d_T, 1)
node signbit_d = bits(_signbit_d_T_1, 7, 0)
node _signext_a_T = shl(signbit_a, 1)
node _signext_a_T_1 = bits(_signext_a_T, 7, 0)
node _signext_a_T_2 = or(signbit_a, _signext_a_T_1)
node _signext_a_T_3 = shl(_signext_a_T_2, 2)
node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0)
node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4)
node _signext_a_T_6 = shl(_signext_a_T_5, 4)
node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0)
node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7)
node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0)
node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0)
node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1)
node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2)
node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3)
node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4)
node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5)
node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6)
node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7)
node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18)
node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20)
node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo)
node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22)
node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24)
node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo)
node signext_a = cat(signext_a_hi, signext_a_lo)
node _signext_d_T = shl(signbit_d, 1)
node _signext_d_T_1 = bits(_signext_d_T, 7, 0)
node _signext_d_T_2 = or(signbit_d, _signext_d_T_1)
node _signext_d_T_3 = shl(_signext_d_T_2, 2)
node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0)
node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4)
node _signext_d_T_6 = shl(_signext_d_T_5, 4)
node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0)
node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7)
node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0)
node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0)
node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1)
node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2)
node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3)
node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4)
node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5)
node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6)
node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7)
node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18)
node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20)
node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo)
node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22)
node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24)
node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo)
node signext_d = cat(signext_d_hi, signext_d_lo)
node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0)
node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1)
node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2)
node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3)
node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4)
node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5)
node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6)
node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7)
node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8)
node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10)
node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo)
node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12)
node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14)
node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo)
node wide_mask = cat(wide_mask_hi, wide_mask_lo)
node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask)
node a_a_ext = or(_a_a_ext_T, signext_a)
node _a_d_ext_T = and(cam_d[0].data, wide_mask)
node a_d_ext = or(_a_d_ext_T, signext_d)
node _a_d_inv_T = not(a_d_ext)
node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T)
node _adder_out_T = add(a_a_ext, a_d_inv)
node adder_out = tail(_adder_out_T, 1)
node _a_bigger_uneq_T = bits(a_a_ext, 63, 63)
node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T)
node _a_bigger_T = bits(a_a_ext, 63, 63)
node _a_bigger_T_1 = bits(a_d_ext, 63, 63)
node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1)
node _a_bigger_T_3 = bits(adder_out, 63, 63)
node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data)
node arith_out = mux(adder, adder_out, _arith_out_T)
node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0)
node amo_data = mux(_amo_data_T, logic_out, arith_out)
wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0))
node _a_allow_T_1 = or(a_isSupported, cam_free_0)
node a_allow = and(_a_allow_T, _a_allow_T_1)
node _nodeIn_a_ready_T = and(source_i.ready, a_allow)
connect nodeIn.a.ready, _nodeIn_a_ready_T
node _source_i_valid_T = and(nodeIn.a.valid, a_allow)
connect source_i.valid, _source_i_valid_T
connect source_i.bits, nodeIn.a.bits
node _T = eq(a_isSupported, UInt<1>(0h0))
when _T :
connect source_i.bits.opcode, UInt<3>(0h4)
connect source_i.bits.param, UInt<1>(0h0)
wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect source_c.valid, cam_amo_0
node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt)
node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<3>(0h6))
node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1)
node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2)
node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<1>(0h0))
node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4)
node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6)
node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8)
node source_c_bits_legal = or(UInt<1>(0h0), _source_c_bits_legal_T_9)
wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect source_c_bits_a.opcode, UInt<1>(0h0)
connect source_c_bits_a.param, UInt<1>(0h0)
connect source_c_bits_a.size, cam_a[0].bits.size
connect source_c_bits_a.source, cam_a[0].bits.source
connect source_c_bits_a.address, cam_a[0].bits.address
node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0))
node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0)
node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount)
node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0)
node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3))
node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2)
node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2)
node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit)
node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2)
node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T)
node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit)
node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2)
node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1)
node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1)
node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1)
node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2)
node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T)
node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2)
node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1)
node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2)
node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2)
node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2)
node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3)
node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0)
node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0)
node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0))
node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq)
node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T)
node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1)
node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1)
node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2)
node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2)
node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3)
node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3)
node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4)
node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4)
node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5)
node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5)
node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6)
node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6)
node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7)
node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7)
node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc)
node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2)
node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo)
node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4)
node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6)
node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo)
node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo)
connect source_c_bits_a.mask, _source_c_bits_a_mask_T
connect source_c_bits_a.data, amo_data
connect source_c_bits_a.corrupt, _source_c_bits_T
connect source_c.bits, source_c_bits_a
node _decode_T = dshl(UInt<6>(0h3f), nodeIn.a.bits.size)
node _decode_T_1 = bits(_decode_T, 5, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node opdata = eq(_opdata_T, UInt<1>(0h0))
node _T_1 = mux(opdata, decode, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(source_i.valid, source_c.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], source_c.valid)
node _winner_T_1 = and(readys[1], source_i.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_3 = eq(winner[0], UInt<1>(0h0))
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(prefixOR_1, UInt<1>(0h0))
node _T_6 = eq(winner[1], UInt<1>(0h0))
node _T_7 = or(_T_5, _T_6)
node _T_8 = and(_T_4, _T_7)
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_8, UInt<1>(0h1), "") : assert
node _T_12 = or(source_c.valid, source_i.valid)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = or(winner[0], winner[1])
node _T_15 = or(_T_13, _T_14)
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
node _T_18 = eq(_T_15, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_15, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _source_c_ready_T = and(nodeOut.a.ready, allowed[0])
connect source_c.ready, _source_c_ready_T
node _source_i_ready_T = and(nodeOut.a.ready, allowed[1])
connect source_i.ready, _source_i_ready_T
node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { }
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_6 : UInt<29>
connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6
node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_7 : UInt<7>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_8 : UInt<3>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_9 : UInt<3>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_10 : UInt<3>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
node _T_19 = and(source_i.ready, source_i.valid)
node _T_20 = eq(a_isSupported, UInt<1>(0h0))
node _T_21 = and(_T_19, _T_20)
when _T_21 :
when a_cam_sel_free_0 :
connect cam_a[0].fifoId, UInt<1>(0h0)
connect cam_a[0].bits, nodeIn.a.bits
node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0)
node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T)
node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8))
node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T)
node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2)
node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T)
node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4)
connect cam_a[0].lut, _cam_a_0_lut_T_6
when a_cam_sel_free_0 :
connect cam_s[0].state, UInt<2>(0h3)
node _T_22 = and(source_c.ready, source_c.valid)
when _T_22 :
when a_cam_sel_put_0 :
connect cam_s[0].state, UInt<1>(0h1)
node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), nodeOut.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source)
node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0)
node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0)
node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0)
node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_24 = and(_T_23, d_first)
when _T_24 :
node _T_25 = and(d_cam_sel_0, d_ackd)
when _T_25 :
connect cam_d[0].data, nodeOut.d.bits.data
connect cam_d[0].denied, nodeOut.d.bits.denied
connect cam_d[0].corrupt, nodeOut.d.bits.corrupt
when d_cam_sel_0 :
node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0))
connect cam_s[0].state, _cam_s_0_state_T
node _d_drop_T = and(d_first, d_ackd)
node d_drop = and(_d_drop_T, d_cam_sel_any)
node _d_replace_T = and(d_first, d_ack)
node d_replace = and(_d_replace_T, d_cam_sel_match_0)
node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0))
node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T)
connect nodeIn.d.valid, _nodeIn_d_valid_T_1
node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop)
connect nodeOut.d.ready, _nodeOut_d_ready_T
connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn.d.bits.data, nodeOut.d.bits.data
connect nodeIn.d.bits.denied, nodeOut.d.bits.denied
connect nodeIn.d.bits.sink, nodeOut.d.bits.sink
connect nodeIn.d.bits.source, nodeOut.d.bits.source
connect nodeIn.d.bits.size, nodeOut.d.bits.size
connect nodeIn.d.bits.param, nodeOut.d.bits.param
connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode
when d_replace :
connect nodeIn.d.bits.opcode, UInt<1>(0h1)
connect nodeIn.d.bits.data, cam_d[0].data
node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T
node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied)
connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_10 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_11 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLAtomicAutomata_pbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire source_i_ready; // @[Arbiter.scala:94:31]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala:82:28, :86:44]
wire winner_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire a_isSupported = auto_in_a_bits_opcode != 3'h3 & auto_in_a_bits_opcode != 3'h2; // @[AtomicAutomata.scala:36:9, :95:45, :96:47, :97:47, :98:{32,63}]
wire [3:0] _logic_out_T = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[0], cam_d_0_data[0]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[1], cam_d_0_data[1]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[2], cam_d_0_data[2]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[3], cam_d_0_data[3]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[4], cam_d_0_data[4]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[5], cam_d_0_data[5]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[6], cam_d_0_data[6]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[7], cam_d_0_data[7]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[8], cam_d_0_data[8]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[9], cam_d_0_data[9]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[10], cam_d_0_data[10]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[11], cam_d_0_data[11]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[12], cam_d_0_data[12]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[13], cam_d_0_data[13]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[14], cam_d_0_data[14]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[15], cam_d_0_data[15]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[16], cam_d_0_data[16]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[17], cam_d_0_data[17]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[18], cam_d_0_data[18]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[19], cam_d_0_data[19]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[20], cam_d_0_data[20]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[21], cam_d_0_data[21]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[22], cam_d_0_data[22]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[23], cam_d_0_data[23]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[24], cam_d_0_data[24]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[25], cam_d_0_data[25]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[26], cam_d_0_data[26]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[27], cam_d_0_data[27]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[28], cam_d_0_data[28]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[29], cam_d_0_data[29]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[30], cam_d_0_data[30]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[31], cam_d_0_data[31]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[32], cam_d_0_data[32]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[33], cam_d_0_data[33]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[34], cam_d_0_data[34]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[35], cam_d_0_data[35]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[36], cam_d_0_data[36]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[37], cam_d_0_data[37]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[38], cam_d_0_data[38]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[39], cam_d_0_data[39]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[40], cam_d_0_data[40]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[41], cam_d_0_data[41]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[42], cam_d_0_data[42]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[43], cam_d_0_data[43]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[44], cam_d_0_data[44]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[45], cam_d_0_data[45]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[46], cam_d_0_data[46]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[47], cam_d_0_data[47]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[48], cam_d_0_data[48]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[49], cam_d_0_data[49]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[50], cam_d_0_data[50]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[51], cam_d_0_data[51]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[52], cam_d_0_data[52]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[53], cam_d_0_data[53]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[54], cam_d_0_data[54]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[55], cam_d_0_data[55]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[56], cam_d_0_data[56]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[57], cam_d_0_data[57]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[58], cam_d_0_data[58]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[59], cam_d_0_data[59]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[60], cam_d_0_data[60]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[61], cam_d_0_data[61]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[62], cam_d_0_data[62]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[63], cam_d_0_data[63]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57]
wire [6:0] _GEN = ~(cam_a_0_bits_mask[6:0]) | cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:{25,31,39}]
wire [6:0] _signbit_a_T = {cam_a_0_bits_data[55], cam_a_0_bits_data[47], cam_a_0_bits_data[39], cam_a_0_bits_data[31], cam_a_0_bits_data[23], cam_a_0_bits_data[15], cam_a_0_bits_data[7]} & ~_GEN; // @[AtomicAutomata.scala:83:24, :119:63, :127:{23,31}, :128:29, :131:38]
wire [6:0] _signbit_d_T = {cam_d_0_data[55], cam_d_0_data[47], cam_d_0_data[39], cam_d_0_data[31], cam_d_0_data[23], cam_d_0_data[15], cam_d_0_data[7]} & ~_GEN; // @[AtomicAutomata.scala:84:24, :119:73, :127:{23,31}, :129:29, :132:38]
wire [5:0] _GEN_0 = _signbit_a_T[6:1] | _signbit_a_T[5:0]; // @[package.scala:253:{43,53}]
wire [3:0] _GEN_1 = _GEN_0[5:2] | _GEN_0[3:0]; // @[package.scala:253:{43,53}]
wire _signext_a_T_13 = _GEN_0[1] | _signbit_a_T[0]; // @[package.scala:253:43]
wire [5:0] _GEN_2 = _signbit_d_T[6:1] | _signbit_d_T[5:0]; // @[package.scala:253:{43,53}]
wire [3:0] _GEN_3 = _GEN_2[5:2] | _GEN_2[3:0]; // @[package.scala:253:{43,53}]
wire _signext_d_T_13 = _GEN_2[1] | _signbit_d_T[0]; // @[package.scala:253:43]
wire [63:0] wide_mask = {{8{cam_a_0_bits_mask[7]}}, {8{cam_a_0_bits_mask[6]}}, {8{cam_a_0_bits_mask[5]}}, {8{cam_a_0_bits_mask[4]}}, {8{cam_a_0_bits_mask[3]}}, {8{cam_a_0_bits_mask[2]}}, {8{cam_a_0_bits_mask[1]}}, {8{cam_a_0_bits_mask[0]}}}; // @[AtomicAutomata.scala:83:24, :136:40]
wire [63:0] a_a_ext = cam_a_0_bits_data & wide_mask | {{8{_GEN_1[3] | _signext_a_T_13}}, {8{_GEN_1[2] | _GEN_0[0]}}, {8{_GEN_1[1] | _signbit_a_T[0]}}, {8{_GEN_1[0]}}, {8{_signext_a_T_13}}, {8{_GEN_0[0]}}, {8{_signbit_a_T[0]}}, 8'h0}; // @[package.scala:253:43]
wire [63:0] a_d_ext = cam_d_0_data & wide_mask | {{8{_GEN_3[3] | _signext_d_T_13}}, {8{_GEN_3[2] | _GEN_2[0]}}, {8{_GEN_3[1] | _signbit_d_T[0]}}, {8{_GEN_3[0]}}, {8{_signext_d_T_13}}, {8{_GEN_2[0]}}, {8{_signbit_d_T[0]}}, 8'h0}; // @[package.scala:253:43]
wire [63:0] _adder_out_T = a_a_ext + ({64{~(cam_a_0_bits_param[2])}} ^ a_d_ext); // @[AtomicAutomata.scala:83:24, :125:39, :137:41, :138:41, :139:26, :140:33]
wire a_allow = ~((&cam_s_0_state) | winner_0) & (a_isSupported | cam_free_0); // @[AtomicAutomata.scala:82:28, :86:44, :87:44, :88:{49,57}, :98:32, :155:{23,35,53}]
wire nodeIn_a_ready = source_i_ready & a_allow; // @[AtomicAutomata.scala:155:35, :156:38]
wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 3'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = cam_a_0_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | source_c_bits_a_mask_sub_sub_size & ~(cam_a_0_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | source_c_bits_a_mask_sub_sub_size & cam_a_0_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = cam_a_0_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire source_c_bits_a_mask_sub_0_2 = ~(cam_a_0_bits_address[2]) & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = ~(cam_a_0_bits_address[2]) & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = cam_a_0_bits_address[2] & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = cam_a_0_bits_address[2] & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[AtomicAutomata.scala:36:9]
wire winner_1 = ~winner_0 & source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38]
wire _nodeOut_a_valid_T = winner_0 | source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_41 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_45
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_41( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_45 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SinkC_7 :
input clock : Clock
input reset : Reset
output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}, resp : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, set : UInt<11>, flip way : UInt<4>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}, bs_dat : { data : UInt<128>}, flip rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, rel_beat : { data : UInt<128>, corrupt : UInt<1>}}
inst c_q of Queue2_TLBundleC_a32d128s6k4z3c_7
connect c_q.clock, clock
connect c_q.reset, reset
connect c_q.io.enq.valid, io.c.valid
connect c_q.io.enq.bits.corrupt, io.c.bits.corrupt
connect c_q.io.enq.bits.data, io.c.bits.data
connect c_q.io.enq.bits.address, io.c.bits.address
connect c_q.io.enq.bits.source, io.c.bits.source
connect c_q.io.enq.bits.size, io.c.bits.size
connect c_q.io.enq.bits.param, io.c.bits.param
connect c_q.io.enq.bits.opcode, io.c.bits.opcode
connect io.c.ready, c_q.io.enq.ready
node _offset_T = bits(c_q.io.deq.bits.address, 0, 0)
node _offset_T_1 = bits(c_q.io.deq.bits.address, 1, 1)
node _offset_T_2 = bits(c_q.io.deq.bits.address, 2, 2)
node _offset_T_3 = bits(c_q.io.deq.bits.address, 3, 3)
node _offset_T_4 = bits(c_q.io.deq.bits.address, 4, 4)
node _offset_T_5 = bits(c_q.io.deq.bits.address, 5, 5)
node _offset_T_6 = bits(c_q.io.deq.bits.address, 9, 9)
node _offset_T_7 = bits(c_q.io.deq.bits.address, 10, 10)
node _offset_T_8 = bits(c_q.io.deq.bits.address, 11, 11)
node _offset_T_9 = bits(c_q.io.deq.bits.address, 12, 12)
node _offset_T_10 = bits(c_q.io.deq.bits.address, 13, 13)
node _offset_T_11 = bits(c_q.io.deq.bits.address, 14, 14)
node _offset_T_12 = bits(c_q.io.deq.bits.address, 15, 15)
node _offset_T_13 = bits(c_q.io.deq.bits.address, 16, 16)
node _offset_T_14 = bits(c_q.io.deq.bits.address, 17, 17)
node _offset_T_15 = bits(c_q.io.deq.bits.address, 18, 18)
node _offset_T_16 = bits(c_q.io.deq.bits.address, 19, 19)
node _offset_T_17 = bits(c_q.io.deq.bits.address, 20, 20)
node _offset_T_18 = bits(c_q.io.deq.bits.address, 21, 21)
node _offset_T_19 = bits(c_q.io.deq.bits.address, 22, 22)
node _offset_T_20 = bits(c_q.io.deq.bits.address, 23, 23)
node _offset_T_21 = bits(c_q.io.deq.bits.address, 24, 24)
node _offset_T_22 = bits(c_q.io.deq.bits.address, 25, 25)
node _offset_T_23 = bits(c_q.io.deq.bits.address, 26, 26)
node _offset_T_24 = bits(c_q.io.deq.bits.address, 27, 27)
node _offset_T_25 = bits(c_q.io.deq.bits.address, 31, 31)
node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1)
node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T)
node offset_lo_lo_hi_hi = cat(_offset_T_5, _offset_T_4)
node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, _offset_T_3)
node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo)
node offset_lo_hi_lo_hi = cat(_offset_T_8, _offset_T_7)
node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_6)
node offset_lo_hi_hi_lo = cat(_offset_T_10, _offset_T_9)
node offset_lo_hi_hi_hi = cat(_offset_T_12, _offset_T_11)
node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo)
node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo)
node offset_lo = cat(offset_lo_hi, offset_lo_lo)
node offset_hi_lo_lo_hi = cat(_offset_T_15, _offset_T_14)
node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_13)
node offset_hi_lo_hi_hi = cat(_offset_T_18, _offset_T_17)
node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, _offset_T_16)
node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo)
node offset_hi_hi_lo_hi = cat(_offset_T_21, _offset_T_20)
node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, _offset_T_19)
node offset_hi_hi_hi_lo = cat(_offset_T_23, _offset_T_22)
node offset_hi_hi_hi_hi = cat(_offset_T_25, _offset_T_24)
node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo)
node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo)
node offset_hi = cat(offset_hi_hi, offset_hi_lo)
node offset = cat(offset_hi, offset_lo)
node set = shr(offset, 6)
node tag = shr(set, 11)
node tag_1 = bits(tag, 8, 0)
node set_1 = bits(set, 10, 0)
node offset_1 = bits(offset, 5, 0)
node _T = and(c_q.io.deq.ready, c_q.io.deq.valid)
node _r_beats1_decode_T = dshl(UInt<6>(0h3f), c_q.io.deq.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 4)
node r_beats1_opdata = bits(c_q.io.deq.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node last = or(_r_last_T, _r_last_T_1)
node r_3 = and(last, _T)
node _r_count_T = not(r_counter1)
node beat = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node hasData = bits(c_q.io.deq.bits.opcode, 0, 0)
node _raw_resp_T = eq(c_q.io.deq.bits.opcode, UInt<3>(0h4))
node _raw_resp_T_1 = eq(c_q.io.deq.bits.opcode, UInt<3>(0h5))
node raw_resp = or(_raw_resp_T, _raw_resp_T_1)
reg resp_r : UInt<1>, clock
when c_q.io.deq.valid :
connect resp_r, raw_resp
node resp = mux(c_q.io.deq.valid, raw_resp, resp_r)
node _T_1 = and(c_q.io.deq.valid, c_q.io.deq.bits.corrupt)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unavailable\n at SinkC.scala:90 assert (!(c.valid && c.bits.corrupt), \"Data poisoning unavailable\")\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
reg io_set_r : UInt<11>, clock
when c_q.io.deq.valid :
connect io_set_r, set_1
node _io_set_T = mux(c_q.io.deq.valid, set_1, io_set_r)
connect io.set, _io_set_T
wire bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<4>, set : UInt<11>, beat : UInt<2>, mask : UInt<2>}}
inst io_bs_adr_q of Queue1_BankedStoreInnerAddress_7
connect io_bs_adr_q.clock, clock
connect io_bs_adr_q.reset, reset
connect io_bs_adr_q.io.enq.valid, bs_adr.valid
connect io_bs_adr_q.io.enq.bits.mask, bs_adr.bits.mask
connect io_bs_adr_q.io.enq.bits.beat, bs_adr.bits.beat
connect io_bs_adr_q.io.enq.bits.set, bs_adr.bits.set
connect io_bs_adr_q.io.enq.bits.way, bs_adr.bits.way
connect io_bs_adr_q.io.enq.bits.noop, bs_adr.bits.noop
connect bs_adr.ready, io_bs_adr_q.io.enq.ready
connect io.bs_adr.bits, io_bs_adr_q.io.deq.bits
connect io.bs_adr.valid, io_bs_adr_q.io.deq.valid
connect io_bs_adr_q.io.deq.ready, io.bs_adr.ready
node _io_bs_dat_data_T = and(bs_adr.ready, bs_adr.valid)
reg io_bs_dat_data_r : UInt<128>, clock
when _io_bs_dat_data_T :
connect io_bs_dat_data_r, c_q.io.deq.bits.data
connect io.bs_dat.data, io_bs_dat_data_r
node _bs_adr_valid_T = eq(first, UInt<1>(0h0))
node _bs_adr_valid_T_1 = and(c_q.io.deq.valid, hasData)
node _bs_adr_valid_T_2 = or(_bs_adr_valid_T, _bs_adr_valid_T_1)
node _bs_adr_valid_T_3 = and(resp, _bs_adr_valid_T_2)
connect bs_adr.valid, _bs_adr_valid_T_3
node _bs_adr_bits_noop_T = eq(c_q.io.deq.valid, UInt<1>(0h0))
connect bs_adr.bits.noop, _bs_adr_bits_noop_T
connect bs_adr.bits.way, io.way
connect bs_adr.bits.set, io.set
node _bs_adr_bits_beat_T = add(beat, bs_adr.ready)
node _bs_adr_bits_beat_T_1 = tail(_bs_adr_bits_beat_T, 1)
reg bs_adr_bits_beat_r : UInt<2>, clock
when c_q.io.deq.valid :
connect bs_adr_bits_beat_r, _bs_adr_bits_beat_T_1
node _bs_adr_bits_beat_T_2 = mux(c_q.io.deq.valid, beat, bs_adr_bits_beat_r)
connect bs_adr.bits.beat, _bs_adr_bits_beat_T_2
node _bs_adr_bits_mask_T = not(UInt<2>(0h0))
connect bs_adr.bits.mask, _bs_adr_bits_mask_T
node _T_6 = eq(bs_adr.ready, UInt<1>(0h0))
node _T_7 = and(bs_adr.valid, _T_6)
node _io_resp_valid_T = and(resp, c_q.io.deq.valid)
node _io_resp_valid_T_1 = or(first, last)
node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1)
node _io_resp_valid_T_3 = eq(hasData, UInt<1>(0h0))
node _io_resp_valid_T_4 = or(_io_resp_valid_T_3, bs_adr.ready)
node _io_resp_valid_T_5 = and(_io_resp_valid_T_2, _io_resp_valid_T_4)
connect io.resp.valid, _io_resp_valid_T_5
connect io.resp.bits.last, last
connect io.resp.bits.set, set_1
connect io.resp.bits.tag, tag_1
connect io.resp.bits.source, c_q.io.deq.bits.source
connect io.resp.bits.param, c_q.io.deq.bits.param
connect io.resp.bits.data, hasData
inst putbuffer of ListBuffer_PutBufferCEntry_q2_e8_7
connect putbuffer.clock, clock
connect putbuffer.reset, reset
regreset lists : UInt<2>, clock, reset, UInt<2>(0h0)
wire lists_set : UInt<2>
connect lists_set, UInt<2>(0h0)
wire lists_clr : UInt<2>
connect lists_clr, UInt<2>(0h0)
node _lists_T = or(lists, lists_set)
node _lists_T_1 = not(lists_clr)
node _lists_T_2 = and(_lists_T, _lists_T_1)
connect lists, _lists_T_2
node _free_T = andr(lists)
node free = eq(_free_T, UInt<1>(0h0))
node _freeOH_T = not(lists)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 1, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = bits(_freeOH_T_3, 1, 0)
node _freeOH_T_5 = shl(_freeOH_T_4, 1)
node _freeOH_T_6 = not(_freeOH_T_5)
node _freeOH_T_7 = not(lists)
node freeOH = and(_freeOH_T_6, _freeOH_T_7)
node freeIdx_hi = bits(freeOH, 2, 2)
node freeIdx_lo = bits(freeOH, 1, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node _freeIdx_T_2 = bits(_freeIdx_T_1, 1, 1)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_2)
node _req_block_T = eq(io.req.ready, UInt<1>(0h0))
node req_block = and(first, _req_block_T)
node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0))
node buf_block = and(hasData, _buf_block_T)
node _set_block_T = and(hasData, first)
node _set_block_T_1 = eq(free, UInt<1>(0h0))
node set_block = and(_set_block_T, _set_block_T_1)
node _T_8 = eq(raw_resp, UInt<1>(0h0))
node _T_9 = and(c_q.io.deq.valid, _T_8)
node _T_10 = and(_T_9, req_block)
node _T_11 = eq(raw_resp, UInt<1>(0h0))
node _T_12 = and(c_q.io.deq.valid, _T_11)
node _T_13 = and(_T_12, buf_block)
node _T_14 = eq(raw_resp, UInt<1>(0h0))
node _T_15 = and(c_q.io.deq.valid, _T_14)
node _T_16 = and(_T_15, set_block)
node _q_io_deq_ready_T = eq(hasData, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, bs_adr.ready)
node _q_io_deq_ready_T_2 = eq(req_block, UInt<1>(0h0))
node _q_io_deq_ready_T_3 = eq(buf_block, UInt<1>(0h0))
node _q_io_deq_ready_T_4 = and(_q_io_deq_ready_T_2, _q_io_deq_ready_T_3)
node _q_io_deq_ready_T_5 = eq(set_block, UInt<1>(0h0))
node _q_io_deq_ready_T_6 = and(_q_io_deq_ready_T_4, _q_io_deq_ready_T_5)
node _q_io_deq_ready_T_7 = mux(raw_resp, _q_io_deq_ready_T_1, _q_io_deq_ready_T_6)
connect c_q.io.deq.ready, _q_io_deq_ready_T_7
node _io_req_valid_T = eq(resp, UInt<1>(0h0))
node _io_req_valid_T_1 = and(_io_req_valid_T, c_q.io.deq.valid)
node _io_req_valid_T_2 = and(_io_req_valid_T_1, first)
node _io_req_valid_T_3 = eq(buf_block, UInt<1>(0h0))
node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3)
node _io_req_valid_T_5 = eq(set_block, UInt<1>(0h0))
node _io_req_valid_T_6 = and(_io_req_valid_T_4, _io_req_valid_T_5)
connect io.req.valid, _io_req_valid_T_6
node _putbuffer_io_push_valid_T = eq(resp, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_1 = and(_putbuffer_io_push_valid_T, c_q.io.deq.valid)
node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T_1, hasData)
node _putbuffer_io_push_valid_T_3 = eq(req_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3)
node _putbuffer_io_push_valid_T_5 = eq(set_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_6 = and(_putbuffer_io_push_valid_T_4, _putbuffer_io_push_valid_T_5)
connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_6
node _T_17 = eq(resp, UInt<1>(0h0))
node _T_18 = and(_T_17, c_q.io.deq.valid)
node _T_19 = and(_T_18, first)
node _T_20 = and(_T_19, hasData)
node _T_21 = eq(req_block, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(buf_block, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
when _T_24 :
connect lists_set, freeOH
reg put_r : UInt<2>, clock
when first :
connect put_r, freeIdx
node put = mux(first, freeIdx, put_r)
wire _WIRE : UInt<1>[3]
connect _WIRE[0], UInt<1>(0h0)
connect _WIRE[1], UInt<1>(0h0)
connect _WIRE[2], UInt<1>(0h1)
connect io.req.bits.prio, _WIRE
connect io.req.bits.control, UInt<1>(0h0)
connect io.req.bits.opcode, c_q.io.deq.bits.opcode
connect io.req.bits.param, c_q.io.deq.bits.param
connect io.req.bits.size, c_q.io.deq.bits.size
connect io.req.bits.source, c_q.io.deq.bits.source
connect io.req.bits.offset, offset_1
connect io.req.bits.set, set_1
connect io.req.bits.tag, tag_1
connect io.req.bits.put, put
connect putbuffer.io.push.bits.index, put
connect putbuffer.io.push.bits.data.data, c_q.io.deq.bits.data
connect putbuffer.io.push.bits.data.corrupt, c_q.io.deq.bits.corrupt
connect putbuffer.io.pop.bits, io.rel_pop.bits.index
node _putbuffer_io_pop_valid_T = and(io.rel_pop.ready, io.rel_pop.valid)
connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T
node _io_rel_pop_ready_T = bits(io.rel_pop.bits.index, 0, 0)
node _io_rel_pop_ready_T_1 = dshr(putbuffer.io.valid, _io_rel_pop_ready_T)
node _io_rel_pop_ready_T_2 = bits(_io_rel_pop_ready_T_1, 0, 0)
connect io.rel_pop.ready, _io_rel_pop_ready_T_2
connect io.rel_beat, putbuffer.io.data
node _T_25 = and(io.rel_pop.ready, io.rel_pop.valid)
node _T_26 = and(_T_25, io.rel_pop.bits.last)
when _T_26 :
node lists_clr_shiftAmount = bits(io.rel_pop.bits.index, 0, 0)
node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount)
node _lists_clr_T_1 = bits(_lists_clr_T, 1, 0)
connect lists_clr, _lists_clr_T_1 | module SinkC_7( // @[SinkC.scala:41:7]
input clock, // @[SinkC.scala:41:7]
input reset, // @[SinkC.scala:41:7]
input io_req_ready, // @[SinkC.scala:43:14]
output io_req_valid, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_param, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_size, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_source, // @[SinkC.scala:43:14]
output [8:0] io_req_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_put, // @[SinkC.scala:43:14]
output [10:0] io_req_bits_set, // @[SinkC.scala:43:14]
output io_resp_valid, // @[SinkC.scala:43:14]
output io_resp_bits_last, // @[SinkC.scala:43:14]
output [10:0] io_resp_bits_set, // @[SinkC.scala:43:14]
output [8:0] io_resp_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_resp_bits_source, // @[SinkC.scala:43:14]
output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14]
output io_resp_bits_data, // @[SinkC.scala:43:14]
output io_c_ready, // @[SinkC.scala:43:14]
input io_c_valid, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_param, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_size, // @[SinkC.scala:43:14]
input [5:0] io_c_bits_source, // @[SinkC.scala:43:14]
input [31:0] io_c_bits_address, // @[SinkC.scala:43:14]
input [127:0] io_c_bits_data, // @[SinkC.scala:43:14]
input io_c_bits_corrupt, // @[SinkC.scala:43:14]
output [10:0] io_set, // @[SinkC.scala:43:14]
input [3:0] io_way, // @[SinkC.scala:43:14]
input io_bs_adr_ready, // @[SinkC.scala:43:14]
output io_bs_adr_valid, // @[SinkC.scala:43:14]
output io_bs_adr_bits_noop, // @[SinkC.scala:43:14]
output [3:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14]
output [10:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14]
output [1:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14]
output [1:0] io_bs_adr_bits_mask, // @[SinkC.scala:43:14]
output [127:0] io_bs_dat_data, // @[SinkC.scala:43:14]
output io_rel_pop_ready, // @[SinkC.scala:43:14]
input io_rel_pop_valid, // @[SinkC.scala:43:14]
input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14]
input io_rel_pop_bits_last, // @[SinkC.scala:43:14]
output [127:0] io_rel_beat_data, // @[SinkC.scala:43:14]
output io_rel_beat_corrupt // @[SinkC.scala:43:14]
);
wire [10:0] io_set_0; // @[SinkC.scala:41:7]
wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27]
wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27]
wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [127:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire io_req_ready_0 = io_req_ready; // @[SinkC.scala:41:7]
wire io_c_valid_0 = io_c_valid; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_opcode_0 = io_c_bits_opcode; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_param_0 = io_c_bits_param; // @[SinkC.scala:41:7]
wire [2:0] io_c_bits_size_0 = io_c_bits_size; // @[SinkC.scala:41:7]
wire [5:0] io_c_bits_source_0 = io_c_bits_source; // @[SinkC.scala:41:7]
wire [31:0] io_c_bits_address_0 = io_c_bits_address; // @[SinkC.scala:41:7]
wire [127:0] io_c_bits_data_0 = io_c_bits_data; // @[SinkC.scala:41:7]
wire io_c_bits_corrupt_0 = io_c_bits_corrupt; // @[SinkC.scala:41:7]
wire [3:0] io_way_0 = io_way; // @[SinkC.scala:41:7]
wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SinkC.scala:41:7]
wire io_rel_pop_valid_0 = io_rel_pop_valid; // @[SinkC.scala:41:7]
wire [5:0] io_rel_pop_bits_index_0 = io_rel_pop_bits_index; // @[SinkC.scala:41:7]
wire io_rel_pop_bits_last_0 = io_rel_pop_bits_last; // @[SinkC.scala:41:7]
wire io_req_bits_prio_0 = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_prio_1 = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_control = 1'h0; // @[SinkC.scala:41:7]
wire io_req_bits_prio_2 = 1'h1; // @[SinkC.scala:41:7]
wire [1:0] bs_adr_bits_mask = 2'h3; // @[SinkC.scala:96:22]
wire [1:0] _bs_adr_bits_mask_T = 2'h3; // @[SinkC.scala:104:25]
wire _io_req_valid_T_6; // @[SinkC.scala:136:61]
wire [8:0] tag_1; // @[Parameters.scala:217:9]
wire [5:0] offset_1; // @[Parameters.scala:217:50]
wire [10:0] set_1; // @[Parameters.scala:217:28]
wire _io_resp_valid_T_5; // @[SinkC.scala:107:57]
wire last; // @[Edges.scala:232:33]
wire hasData; // @[Edges.scala:102:36]
wire [10:0] _io_set_T; // @[SinkC.scala:92:18]
wire [10:0] bs_adr_bits_set = io_set_0; // @[SinkC.scala:41:7, :96:22]
wire [3:0] bs_adr_bits_way = io_way_0; // @[SinkC.scala:41:7, :96:22]
wire _io_rel_pop_ready_T_2; // @[SinkC.scala:160:43]
wire [2:0] io_req_bits_opcode_0; // @[SinkC.scala:41:7]
wire [2:0] io_req_bits_param_0; // @[SinkC.scala:41:7]
wire [2:0] io_req_bits_size_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_source_0; // @[SinkC.scala:41:7]
wire [8:0] io_req_bits_tag_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_offset_0; // @[SinkC.scala:41:7]
wire [5:0] io_req_bits_put_0; // @[SinkC.scala:41:7]
wire [10:0] io_req_bits_set_0; // @[SinkC.scala:41:7]
wire io_req_valid_0; // @[SinkC.scala:41:7]
wire io_resp_bits_last_0; // @[SinkC.scala:41:7]
wire [10:0] io_resp_bits_set_0; // @[SinkC.scala:41:7]
wire [8:0] io_resp_bits_tag_0; // @[SinkC.scala:41:7]
wire [5:0] io_resp_bits_source_0; // @[SinkC.scala:41:7]
wire [2:0] io_resp_bits_param_0; // @[SinkC.scala:41:7]
wire io_resp_bits_data_0; // @[SinkC.scala:41:7]
wire io_resp_valid_0; // @[SinkC.scala:41:7]
wire io_c_ready_0; // @[SinkC.scala:41:7]
wire io_bs_adr_bits_noop_0; // @[SinkC.scala:41:7]
wire [3:0] io_bs_adr_bits_way_0; // @[SinkC.scala:41:7]
wire [10:0] io_bs_adr_bits_set_0; // @[SinkC.scala:41:7]
wire [1:0] io_bs_adr_bits_beat_0; // @[SinkC.scala:41:7]
wire [1:0] io_bs_adr_bits_mask_0; // @[SinkC.scala:41:7]
wire io_bs_adr_valid_0; // @[SinkC.scala:41:7]
wire [127:0] io_bs_dat_data_0; // @[SinkC.scala:41:7]
wire io_rel_pop_ready_0; // @[SinkC.scala:41:7]
wire [127:0] io_rel_beat_data_0; // @[SinkC.scala:41:7]
wire io_rel_beat_corrupt_0; // @[SinkC.scala:41:7]
wire _offset_T = _c_q_io_deq_bits_address[0]; // @[Decoupled.scala:362:21]
wire _offset_T_1 = _c_q_io_deq_bits_address[1]; // @[Decoupled.scala:362:21]
wire _offset_T_2 = _c_q_io_deq_bits_address[2]; // @[Decoupled.scala:362:21]
wire _offset_T_3 = _c_q_io_deq_bits_address[3]; // @[Decoupled.scala:362:21]
wire _offset_T_4 = _c_q_io_deq_bits_address[4]; // @[Decoupled.scala:362:21]
wire _offset_T_5 = _c_q_io_deq_bits_address[5]; // @[Decoupled.scala:362:21]
wire _offset_T_6 = _c_q_io_deq_bits_address[9]; // @[Decoupled.scala:362:21]
wire _offset_T_7 = _c_q_io_deq_bits_address[10]; // @[Decoupled.scala:362:21]
wire _offset_T_8 = _c_q_io_deq_bits_address[11]; // @[Decoupled.scala:362:21]
wire _offset_T_9 = _c_q_io_deq_bits_address[12]; // @[Decoupled.scala:362:21]
wire _offset_T_10 = _c_q_io_deq_bits_address[13]; // @[Decoupled.scala:362:21]
wire _offset_T_11 = _c_q_io_deq_bits_address[14]; // @[Decoupled.scala:362:21]
wire _offset_T_12 = _c_q_io_deq_bits_address[15]; // @[Decoupled.scala:362:21]
wire _offset_T_13 = _c_q_io_deq_bits_address[16]; // @[Decoupled.scala:362:21]
wire _offset_T_14 = _c_q_io_deq_bits_address[17]; // @[Decoupled.scala:362:21]
wire _offset_T_15 = _c_q_io_deq_bits_address[18]; // @[Decoupled.scala:362:21]
wire _offset_T_16 = _c_q_io_deq_bits_address[19]; // @[Decoupled.scala:362:21]
wire _offset_T_17 = _c_q_io_deq_bits_address[20]; // @[Decoupled.scala:362:21]
wire _offset_T_18 = _c_q_io_deq_bits_address[21]; // @[Decoupled.scala:362:21]
wire _offset_T_19 = _c_q_io_deq_bits_address[22]; // @[Decoupled.scala:362:21]
wire _offset_T_20 = _c_q_io_deq_bits_address[23]; // @[Decoupled.scala:362:21]
wire _offset_T_21 = _c_q_io_deq_bits_address[24]; // @[Decoupled.scala:362:21]
wire _offset_T_22 = _c_q_io_deq_bits_address[25]; // @[Decoupled.scala:362:21]
wire _offset_T_23 = _c_q_io_deq_bits_address[26]; // @[Decoupled.scala:362:21]
wire _offset_T_24 = _c_q_io_deq_bits_address[27]; // @[Decoupled.scala:362:21]
wire _offset_T_25 = _c_q_io_deq_bits_address[31]; // @[Decoupled.scala:362:21]
wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_lo_hi_hi = {_offset_T_5, _offset_T_4}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, _offset_T_3}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_lo_hi_lo_hi = {_offset_T_8, _offset_T_7}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_6}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_lo = {_offset_T_10, _offset_T_9}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_hi = {_offset_T_12, _offset_T_11}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_lo_lo_hi = {_offset_T_15, _offset_T_14}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_13}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_lo_hi_hi = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, _offset_T_16}; // @[Parameters.scala:214:{21,47}]
wire [5:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_hi_lo_hi = {_offset_T_21, _offset_T_20}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, _offset_T_19}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_lo = {_offset_T_23, _offset_T_22}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_hi = {_offset_T_25, _offset_T_24}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [12:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21]
wire [25:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21]
wire [19:0] set = offset[25:6]; // @[Parameters.scala:214:21, :215:22]
wire [8:0] tag = set[19:11]; // @[Parameters.scala:215:22, :216:19]
assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9]
assign io_req_bits_tag_0 = tag_1; // @[SinkC.scala:41:7]
assign io_resp_bits_tag_0 = tag_1; // @[SinkC.scala:41:7]
assign set_1 = set[10:0]; // @[Parameters.scala:215:22, :217:28]
assign io_req_bits_set_0 = set_1; // @[SinkC.scala:41:7]
assign io_resp_bits_set_0 = set_1; // @[SinkC.scala:41:7]
assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50]
assign io_req_bits_offset_0 = offset_1; // @[SinkC.scala:41:7]
wire _q_io_deq_ready_T_7; // @[SinkC.scala:134:19]
wire _T = _q_io_deq_ready_T_7 & _c_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21]
wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [5:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] r_beats1_decode = _r_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire r_beats1_opdata = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
assign hasData = _c_q_io_deq_bits_opcode[0]; // @[Decoupled.scala:362:21]
wire [1:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] r_counter; // @[Edges.scala:229:27]
wire [2:0] _r_counter1_T = {1'h0, r_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] r_counter1 = _r_counter1_T[1:0]; // @[Edges.scala:230:28]
wire first = r_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
assign last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
assign io_resp_bits_last_0 = last; // @[Edges.scala:232:33]
wire r_3 = last & _T; // @[Decoupled.scala:51:35]
wire [1:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] beat = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _r_counter_T = first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
assign io_resp_bits_data_0 = hasData; // @[Edges.scala:102:36]
wire _raw_resp_T = _c_q_io_deq_bits_opcode == 3'h4; // @[Decoupled.scala:362:21]
wire _raw_resp_T_1 = _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21]
wire raw_resp = _raw_resp_T | _raw_resp_T_1; // @[SinkC.scala:78:{34,58,75}]
reg resp_r; // @[SinkC.scala:79:48]
wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_61 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = or(_T_667, _T_672)
node _T_709 = or(_T_708, _T_677)
node _T_710 = or(_T_709, _T_682)
node _T_711 = or(_T_710, _T_687)
node _T_712 = or(_T_711, _T_692)
node _T_713 = or(_T_712, _T_697)
node _T_714 = or(_T_713, _T_702)
node _T_715 = or(_T_714, _T_707)
node _T_716 = and(_T_662, _T_715)
node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_716)
node _T_725 = or(_T_724, _T_723)
node _T_726 = and(_T_658, _T_725)
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_726, UInt<1>(0h1), "") : assert_36
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(is_aligned, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_737 = asUInt(reset)
node _T_738 = eq(_T_737, UInt<1>(0h0))
when _T_738 :
node _T_739 = eq(_T_736, UInt<1>(0h0))
when _T_739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_736, UInt<1>(0h1), "") : assert_39
node _T_740 = eq(io.in.a.bits.mask, mask)
node _T_741 = asUInt(reset)
node _T_742 = eq(_T_741, UInt<1>(0h0))
when _T_742 :
node _T_743 = eq(_T_740, UInt<1>(0h0))
when _T_743 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_740, UInt<1>(0h1), "") : assert_40
node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_744 :
node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _T_754 = or(UInt<1>(0h0), _T_753)
node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_759, _T_764)
node _T_801 = or(_T_800, _T_769)
node _T_802 = or(_T_801, _T_774)
node _T_803 = or(_T_802, _T_779)
node _T_804 = or(_T_803, _T_784)
node _T_805 = or(_T_804, _T_789)
node _T_806 = or(_T_805, _T_794)
node _T_807 = or(_T_806, _T_799)
node _T_808 = and(_T_754, _T_807)
node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = and(_T_809, _T_814)
node _T_816 = or(UInt<1>(0h0), _T_808)
node _T_817 = or(_T_816, _T_815)
node _T_818 = and(_T_750, _T_817)
node _T_819 = asUInt(reset)
node _T_820 = eq(_T_819, UInt<1>(0h0))
when _T_820 :
node _T_821 = eq(_T_818, UInt<1>(0h0))
when _T_821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_818, UInt<1>(0h1), "") : assert_41
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(is_aligned, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_828, UInt<1>(0h1), "") : assert_44
node _T_832 = eq(io.in.a.bits.mask, mask)
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_832, UInt<1>(0h1), "") : assert_45
node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_836 :
node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_855 = cvt(_T_854)
node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000)))
node _T_857 = asSInt(_T_856)
node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0)))
node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_860 = cvt(_T_859)
node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000)))
node _T_862 = asSInt(_T_861)
node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0)))
node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = or(_T_858, _T_863)
node _T_890 = or(_T_889, _T_868)
node _T_891 = or(_T_890, _T_873)
node _T_892 = or(_T_891, _T_878)
node _T_893 = or(_T_892, _T_883)
node _T_894 = or(_T_893, _T_888)
node _T_895 = and(_T_853, _T_894)
node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_898 = and(_T_896, _T_897)
node _T_899 = or(UInt<1>(0h0), _T_898)
node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_901 = cvt(_T_900)
node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000)))
node _T_903 = asSInt(_T_902)
node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0)))
node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_906 = cvt(_T_905)
node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000)))
node _T_908 = asSInt(_T_907)
node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0)))
node _T_910 = or(_T_904, _T_909)
node _T_911 = and(_T_899, _T_910)
node _T_912 = or(UInt<1>(0h0), _T_852)
node _T_913 = or(_T_912, _T_895)
node _T_914 = or(_T_913, _T_911)
node _T_915 = and(_T_842, _T_914)
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_915, UInt<1>(0h1), "") : assert_46
node _T_919 = asUInt(reset)
node _T_920 = eq(_T_919, UInt<1>(0h0))
when _T_920 :
node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(is_aligned, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_925, UInt<1>(0h1), "") : assert_49
node _T_929 = eq(io.in.a.bits.mask, mask)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_929, UInt<1>(0h1), "") : assert_50
node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_933, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_937, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20))
node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_941 :
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_945, UInt<1>(0h1), "") : assert_54
node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(_T_949, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_949, UInt<1>(0h1), "") : assert_55
node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_953, UInt<1>(0h1), "") : assert_56
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_957, UInt<1>(0h1), "") : assert_57
node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_961 :
node _T_962 = asUInt(reset)
node _T_963 = eq(_T_962, UInt<1>(0h0))
when _T_963 :
node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_964 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(sink_ok, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_968, UInt<1>(0h1), "") : assert_60
node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_972, UInt<1>(0h1), "") : assert_61
node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_976, UInt<1>(0h1), "") : assert_62
node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_981 = asUInt(reset)
node _T_982 = eq(_T_981, UInt<1>(0h0))
when _T_982 :
node _T_983 = eq(_T_980, UInt<1>(0h0))
when _T_983 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_980, UInt<1>(0h1), "") : assert_63
node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_985 = or(UInt<1>(0h1), _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_985, UInt<1>(0h1), "") : assert_64
node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_989 :
node _T_990 = asUInt(reset)
node _T_991 = eq(_T_990, UInt<1>(0h0))
when _T_991 :
node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_992 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(sink_ok, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_996, UInt<1>(0h1), "") : assert_67
node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68
node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69
node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1009 = or(_T_1008, io.in.d.bits.corrupt)
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70
node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1014 = or(UInt<1>(0h1), _T_1013)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71
node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73
node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74
node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1031 = or(UInt<1>(0h1), _T_1030)
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75
node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1035 :
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77
node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1044 = or(_T_1043, io.in.d.bits.corrupt)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78
node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1049 = or(UInt<1>(0h1), _T_1048)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79
node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1053 :
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81
node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82
node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1066 = or(UInt<1>(0h1), _T_1065)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_4.bits.sink, UInt<5>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1082 = eq(a_first, UInt<1>(0h0))
node _T_1083 = and(io.in.a.valid, _T_1082)
when _T_1083 :
node _T_1084 = eq(io.in.a.bits.opcode, opcode)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87
node _T_1088 = eq(io.in.a.bits.param, param)
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88
node _T_1092 = eq(io.in.a.bits.size, size)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89
node _T_1096 = eq(io.in.a.bits.source, source)
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90
node _T_1100 = eq(io.in.a.bits.address, address)
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91
node _T_1104 = and(io.in.a.ready, io.in.a.valid)
node _T_1105 = and(_T_1104, a_first)
when _T_1105 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1106 = eq(d_first, UInt<1>(0h0))
node _T_1107 = and(io.in.d.valid, _T_1106)
when _T_1107 :
node _T_1108 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92
node _T_1112 = eq(io.in.d.bits.param, param_1)
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93
node _T_1116 = eq(io.in.d.bits.size, size_1)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94
node _T_1120 = eq(io.in.d.bits.source, source_1)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95
node _T_1124 = eq(io.in.d.bits.sink, sink)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96
node _T_1128 = eq(io.in.d.bits.denied, denied)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97
node _T_1132 = and(io.in.d.ready, io.in.d.valid)
node _T_1133 = and(_T_1132, d_first)
when _T_1133 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1134 = and(io.in.a.valid, a_first_1)
node _T_1135 = and(_T_1134, UInt<1>(0h1))
when _T_1135 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1136 = and(io.in.a.ready, io.in.a.valid)
node _T_1137 = and(_T_1136, a_first_1)
node _T_1138 = and(_T_1137, UInt<1>(0h1))
when _T_1138 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1139 = dshr(inflight, io.in.a.bits.source)
node _T_1140 = bits(_T_1139, 0, 0)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1145 = and(io.in.d.valid, d_first_1)
node _T_1146 = and(_T_1145, UInt<1>(0h1))
node _T_1147 = eq(d_release_ack, UInt<1>(0h0))
node _T_1148 = and(_T_1146, _T_1147)
when _T_1148 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1149 = and(io.in.d.ready, io.in.d.valid)
node _T_1150 = and(_T_1149, d_first_1)
node _T_1151 = and(_T_1150, UInt<1>(0h1))
node _T_1152 = eq(d_release_ack, UInt<1>(0h0))
node _T_1153 = and(_T_1151, _T_1152)
when _T_1153 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1154 = and(io.in.d.valid, d_first_1)
node _T_1155 = and(_T_1154, UInt<1>(0h1))
node _T_1156 = eq(d_release_ack, UInt<1>(0h0))
node _T_1157 = and(_T_1155, _T_1156)
when _T_1157 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1158 = dshr(inflight, io.in.d.bits.source)
node _T_1159 = bits(_T_1158, 0, 0)
node _T_1160 = or(_T_1159, same_cycle_resp)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1166 = or(_T_1164, _T_1165)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100
node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101
else :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102
node _T_1180 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103
node _T_1184 = and(io.in.d.valid, d_first_1)
node _T_1185 = and(_T_1184, a_first_1)
node _T_1186 = and(_T_1185, io.in.a.valid)
node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(d_release_ack, UInt<1>(0h0))
node _T_1190 = and(_T_1188, _T_1189)
when _T_1190 :
node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1192 = or(_T_1191, io.in.a.ready)
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104
node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1197 = orr(a_set_wo_ready)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = or(_T_1196, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_148
node _T_1203 = orr(inflight)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1206 = or(_T_1204, _T_1205)
node _T_1207 = lt(watchdog, plusarg_reader.out)
node _T_1208 = or(_T_1206, _T_1207)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1212 = and(io.in.a.ready, io.in.a.valid)
node _T_1213 = and(io.in.d.ready, io.in.d.valid)
node _T_1214 = or(_T_1212, _T_1213)
when _T_1214 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1215 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1218 = and(_T_1216, _T_1217)
node _T_1219 = and(_T_1215, _T_1218)
when _T_1219 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1221 = and(_T_1220, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1224 = and(_T_1222, _T_1223)
node _T_1225 = and(_T_1221, _T_1224)
when _T_1225 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1227 = bits(_T_1226, 0, 0)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1232 = and(io.in.d.valid, d_first_2)
node _T_1233 = and(_T_1232, UInt<1>(0h1))
node _T_1234 = and(_T_1233, d_release_ack_1)
when _T_1234 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1235 = and(io.in.d.ready, io.in.d.valid)
node _T_1236 = and(_T_1235, d_first_2)
node _T_1237 = and(_T_1236, UInt<1>(0h1))
node _T_1238 = and(_T_1237, d_release_ack_1)
when _T_1238 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1239 = and(io.in.d.valid, d_first_2)
node _T_1240 = and(_T_1239, UInt<1>(0h1))
node _T_1241 = and(_T_1240, d_release_ack_1)
when _T_1241 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1242 = dshr(inflight_1, io.in.d.bits.source)
node _T_1243 = bits(_T_1242, 0, 0)
node _T_1244 = or(_T_1243, same_cycle_resp_1)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109
else :
node _T_1252 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110
node _T_1256 = and(io.in.d.valid, d_first_2)
node _T_1257 = and(_T_1256, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1258 = and(_T_1257, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1260 = and(_T_1258, _T_1259)
node _T_1261 = and(_T_1260, d_release_ack_1)
node _T_1262 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1263 = and(_T_1261, _T_1262)
when _T_1263 :
node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1265 = or(_T_1264, _WIRE_23.ready)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111
node _T_1269 = orr(c_set_wo_ready)
when _T_1269 :
node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1271 = asUInt(reset)
node _T_1272 = eq(_T_1271, UInt<1>(0h0))
when _T_1272 :
node _T_1273 = eq(_T_1270, UInt<1>(0h0))
when _T_1273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_149
node _T_1274 = orr(inflight_1)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1277 = or(_T_1275, _T_1276)
node _T_1278 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1279 = or(_T_1277, _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1284 = and(io.in.d.ready, io.in.d.valid)
node _T_1285 = or(_T_1283, _T_1284)
when _T_1285 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_61( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire _GEN = io_in_d_valid & d_first_1; // @[Monitor.scala:674:26]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
wire d_clr = _GEN & _GEN_0; // @[Monitor.scala:673:46, :674:{26,71,74}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire d_clr_1 = io_in_d_valid & d_first_2 & io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46, :784:26, :788:70]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_256 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_256( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_20 :
input clock : Clock
input reset : Reset
output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}}, resp : { `4` : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `3` : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `2` : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `1` : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, `0` : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}}
connect io.req.`0`.ready, UInt<1>(0h1)
node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id)
node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node)
node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id)
node _addr_T = cat(addr_hi, addr_lo)
node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T)
wire decoded_plaInput : UInt<20>
node decoded_invInputs = not(decoded_plaInput)
wire decoded_plaOutput : UInt<40>
node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16)
node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14)
node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_lo_lo_lo)
node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11, decoded_andMatrixOutputs_andMatrixInput_12)
node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10)
node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo)
node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo)
node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7, decoded_andMatrixOutputs_andMatrixInput_8)
node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_5, decoded_andMatrixOutputs_andMatrixInput_6)
node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_hi_lo_lo)
node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo)
node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo)
node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo)
node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T)
node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1)
node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1)
node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_lo_lo_lo_1)
node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_1, decoded_andMatrixOutputs_andMatrixInput_12_1)
node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1)
node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1)
node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1)
node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_1, decoded_andMatrixOutputs_andMatrixInput_8_1)
node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_5_1, decoded_andMatrixOutputs_andMatrixInput_6_1)
node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_hi_lo_lo_1)
node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1)
node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1)
node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1)
node decoded_andMatrixOutputs_24_2 = andr(_decoded_andMatrixOutputs_T_1)
node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_14_2, decoded_andMatrixOutputs_andMatrixInput_15_2)
node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2)
node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo_2)
node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2)
node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2)
node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2)
node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2)
node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2)
node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo_2)
node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2)
node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2)
node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2)
node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2)
node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_2)
node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_15_3, decoded_andMatrixOutputs_andMatrixInput_16_2)
node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_13_3, decoded_andMatrixOutputs_andMatrixInput_14_3)
node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_3)
node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_11_3, decoded_andMatrixOutputs_andMatrixInput_12_3)
node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_andMatrixOutputs_andMatrixInput_10_3)
node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3)
node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3)
node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_3, decoded_andMatrixOutputs_andMatrixInput_8_3)
node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_3)
node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3)
node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3)
node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3)
node decoded_andMatrixOutputs_25_2 = andr(_decoded_andMatrixOutputs_T_3)
node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_15_4, decoded_andMatrixOutputs_andMatrixInput_16_3)
node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_13_4, decoded_andMatrixOutputs_andMatrixInput_14_4)
node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_lo_lo_lo_4)
node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_11_4, decoded_andMatrixOutputs_andMatrixInput_12_4)
node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_4)
node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4)
node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4)
node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4)
node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4)
node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_4)
node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_4)
node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4)
node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4)
node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4)
node decoded_andMatrixOutputs_33_2 = andr(_decoded_andMatrixOutputs_T_4)
node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_15_5, decoded_andMatrixOutputs_andMatrixInput_16_4)
node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_5, decoded_andMatrixOutputs_andMatrixInput_14_5)
node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_5)
node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_5)
node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_5)
node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5)
node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5)
node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5)
node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5)
node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_5)
node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_5)
node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5)
node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5)
node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5)
node decoded_andMatrixOutputs_27_2 = andr(_decoded_andMatrixOutputs_T_5)
node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6)
node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_andMatrixInput_14_6)
node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6)
node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6)
node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6)
node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6)
node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6)
node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_6)
node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6)
node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6)
node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6)
node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6)
node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_6)
node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_15_6, decoded_andMatrixOutputs_andMatrixInput_16_5)
node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_13_7, decoded_andMatrixOutputs_andMatrixInput_14_7)
node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_lo_lo_lo_6)
node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_11_7, decoded_andMatrixOutputs_andMatrixInput_12_7)
node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_7)
node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7)
node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7)
node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_andMatrixOutputs_andMatrixInput_8_7)
node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_andMatrixOutputs_andMatrixInput_6_7)
node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_7)
node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7)
node decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7)
node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_7)
node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7)
node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7)
node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7)
node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_7)
node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_15_7, decoded_andMatrixOutputs_andMatrixInput_16_6)
node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_13_8, decoded_andMatrixOutputs_andMatrixInput_14_8)
node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_7)
node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_11_8, decoded_andMatrixOutputs_andMatrixInput_12_8)
node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_andMatrixOutputs_andMatrixInput_10_8)
node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8)
node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8)
node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_7_8, decoded_andMatrixOutputs_andMatrixInput_8_8)
node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8)
node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_8)
node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8)
node decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8)
node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_8)
node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_8)
node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8)
node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8)
node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_8)
node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_15_8, decoded_andMatrixOutputs_andMatrixInput_16_7)
node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_13_9, decoded_andMatrixOutputs_andMatrixInput_14_9)
node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_lo_lo_lo_8)
node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_11_9, decoded_andMatrixOutputs_andMatrixInput_12_9)
node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_andMatrixOutputs_andMatrixInput_10_9)
node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9)
node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9)
node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_7_9, decoded_andMatrixOutputs_andMatrixInput_8_9)
node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9)
node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_9)
node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9)
node decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9)
node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_9)
node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_9)
node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9)
node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9)
node decoded_andMatrixOutputs_40_2 = andr(_decoded_andMatrixOutputs_T_9)
node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_15_9, decoded_andMatrixOutputs_andMatrixInput_16_8)
node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_13_10, decoded_andMatrixOutputs_andMatrixInput_14_10)
node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_lo_lo_lo_9)
node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_11_10, decoded_andMatrixOutputs_andMatrixInput_12_10)
node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_10)
node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10)
node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10)
node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10)
node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10)
node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_10)
node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10)
node decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10)
node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_10)
node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_10)
node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10)
node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10)
node decoded_andMatrixOutputs_41_2 = andr(_decoded_andMatrixOutputs_T_10)
node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_15_10, decoded_andMatrixOutputs_andMatrixInput_16_9)
node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_13_11, decoded_andMatrixOutputs_andMatrixInput_14_11)
node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_lo_lo_lo_10)
node decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_11_11, decoded_andMatrixOutputs_andMatrixInput_12_11)
node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_11)
node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_lo_hi_lo_11)
node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11)
node decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_7_11, decoded_andMatrixOutputs_andMatrixInput_8_11)
node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11)
node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_11)
node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11)
node decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11)
node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_11)
node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_11)
node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11)
node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11)
node decoded_andMatrixOutputs_43_2 = andr(_decoded_andMatrixOutputs_T_11)
node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_14_12, decoded_andMatrixOutputs_andMatrixInput_15_11)
node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_12_12, decoded_andMatrixOutputs_andMatrixInput_13_12)
node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_lo_lo_lo_11)
node decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_10_12, decoded_andMatrixOutputs_andMatrixInput_11_12)
node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_andMatrixOutputs_andMatrixInput_9_12)
node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_lo_hi_lo_12)
node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12)
node decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12)
node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12)
node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_hi_lo_lo_12)
node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_12)
node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12)
node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_12)
node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12)
node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12)
node decoded_andMatrixOutputs_29_2 = andr(_decoded_andMatrixOutputs_T_12)
node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_15_12, decoded_andMatrixOutputs_andMatrixInput_16_10)
node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_13_13, decoded_andMatrixOutputs_andMatrixInput_14_13)
node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_lo_lo_lo_12)
node decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_11_13, decoded_andMatrixOutputs_andMatrixInput_12_13)
node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_andMatrixOutputs_andMatrixInput_10_13)
node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_lo_hi_lo_13)
node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13)
node decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_7_13, decoded_andMatrixOutputs_andMatrixInput_8_13)
node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_5_13, decoded_andMatrixOutputs_andMatrixInput_6_13)
node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_hi_lo_lo_13)
node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_andMatrixOutputs_andMatrixInput_4_13)
node decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13)
node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_2_13)
node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_13)
node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13)
node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13)
node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_13)
node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_15_13, decoded_andMatrixOutputs_andMatrixInput_16_11)
node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_13_14, decoded_andMatrixOutputs_andMatrixInput_14_14)
node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_lo_lo_lo_13)
node decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_11_14, decoded_andMatrixOutputs_andMatrixInput_12_14)
node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_andMatrixOutputs_andMatrixInput_10_14)
node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_lo_hi_lo_14)
node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14)
node decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_7_14, decoded_andMatrixOutputs_andMatrixInput_8_14)
node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_5_14, decoded_andMatrixOutputs_andMatrixInput_6_14)
node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_hi_lo_lo_14)
node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14)
node decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14)
node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_14)
node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_hi_hi_lo_14)
node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14)
node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14)
node decoded_andMatrixOutputs_22_2 = andr(_decoded_andMatrixOutputs_T_14)
node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_15_14, decoded_andMatrixOutputs_andMatrixInput_16_12)
node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_13_15, decoded_andMatrixOutputs_andMatrixInput_14_15)
node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_lo_lo_lo_14)
node decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_11_15, decoded_andMatrixOutputs_andMatrixInput_12_15)
node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_andMatrixOutputs_andMatrixInput_10_15)
node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_lo_hi_lo_15)
node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15)
node decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_15)
node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15)
node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_hi_lo_lo_15)
node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15)
node decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15)
node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_15)
node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_hi_hi_lo_15)
node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15)
node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15)
node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_15)
node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_12_16, decoded_andMatrixOutputs_andMatrixInput_13_16)
node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_andMatrixInput_14_16)
node decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_16)
node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_8_16, decoded_andMatrixOutputs_andMatrixInput_9_16)
node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_16)
node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16)
node decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_andMatrixOutputs_andMatrixInput_7_16)
node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_16, decoded_andMatrixOutputs_andMatrixInput_5_16)
node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_hi_lo_lo_16)
node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_2_16, decoded_andMatrixOutputs_andMatrixInput_3_16)
node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16)
node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_16)
node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16)
node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16)
node decoded_andMatrixOutputs_35_2 = andr(_decoded_andMatrixOutputs_T_16)
node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_15_15, decoded_andMatrixOutputs_andMatrixInput_16_13)
node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_13_17, decoded_andMatrixOutputs_andMatrixInput_14_17)
node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_lo_lo_lo_15)
node decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_11_17, decoded_andMatrixOutputs_andMatrixInput_12_17)
node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_andMatrixOutputs_andMatrixInput_10_17)
node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_lo_hi_lo_17)
node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17)
node decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_7_17, decoded_andMatrixOutputs_andMatrixInput_8_17)
node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17)
node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_hi_lo_lo_17)
node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17)
node decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17)
node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_17)
node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_17)
node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17)
node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17)
node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_17)
node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_15_16, decoded_andMatrixOutputs_andMatrixInput_16_14)
node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_13_18, decoded_andMatrixOutputs_andMatrixInput_14_18)
node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_lo_lo_lo_16)
node decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_11_18, decoded_andMatrixOutputs_andMatrixInput_12_18)
node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_andMatrixOutputs_andMatrixInput_10_18)
node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_lo_hi_lo_18)
node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18)
node decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_7_18, decoded_andMatrixOutputs_andMatrixInput_8_18)
node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_5_18, decoded_andMatrixOutputs_andMatrixInput_6_18)
node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_hi_lo_lo_18)
node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_andMatrixOutputs_andMatrixInput_4_18)
node decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18)
node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_18)
node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_18)
node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18)
node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18)
node decoded_andMatrixOutputs_31_2 = andr(_decoded_andMatrixOutputs_T_18)
node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_15_17, decoded_andMatrixOutputs_andMatrixInput_16_15)
node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_13_19, decoded_andMatrixOutputs_andMatrixInput_14_19)
node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_lo_lo_lo_17)
node decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_11_19, decoded_andMatrixOutputs_andMatrixInput_12_19)
node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_andMatrixOutputs_andMatrixInput_10_19)
node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_lo_hi_lo_19)
node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19)
node decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_19, decoded_andMatrixOutputs_andMatrixInput_8_19)
node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_5_19, decoded_andMatrixOutputs_andMatrixInput_6_19)
node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_hi_lo_lo_19)
node decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_andMatrixOutputs_andMatrixInput_4_19)
node decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19)
node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_19)
node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_19)
node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19)
node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19)
node decoded_andMatrixOutputs_38_2 = andr(_decoded_andMatrixOutputs_T_19)
node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_12_20, decoded_andMatrixOutputs_andMatrixInput_13_20)
node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_andMatrixInput_14_20)
node decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_10_20, decoded_andMatrixOutputs_andMatrixInput_11_20)
node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_8_20, decoded_andMatrixOutputs_andMatrixInput_9_20)
node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_lo_hi_lo_20)
node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20)
node decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20)
node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_4_20, decoded_andMatrixOutputs_andMatrixInput_5_20)
node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_hi_lo_lo_20)
node decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_2_20, decoded_andMatrixOutputs_andMatrixInput_3_20)
node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20)
node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_hi_hi_lo_20)
node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20)
node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20)
node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_20)
node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_14_21, decoded_andMatrixOutputs_andMatrixInput_15_18)
node decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_12_21, decoded_andMatrixOutputs_andMatrixInput_13_21)
node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_lo_lo_hi_21, decoded_andMatrixOutputs_lo_lo_lo_18)
node decoded_andMatrixOutputs_lo_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_10_21, decoded_andMatrixOutputs_andMatrixInput_11_21)
node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_8_21, decoded_andMatrixOutputs_andMatrixInput_9_21)
node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_lo_hi_lo_21)
node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21)
node decoded_andMatrixOutputs_hi_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_andMatrixOutputs_andMatrixInput_7_21)
node decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_4_21, decoded_andMatrixOutputs_andMatrixInput_5_21)
node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_hi_lo_hi_21, decoded_andMatrixOutputs_hi_lo_lo_21)
node decoded_andMatrixOutputs_hi_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_2_21, decoded_andMatrixOutputs_andMatrixInput_3_21)
node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21)
node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_hi_hi_lo_21)
node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21)
node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21)
node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_21)
node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_15_19, decoded_andMatrixOutputs_andMatrixInput_16_16)
node decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_13_22, decoded_andMatrixOutputs_andMatrixInput_14_22)
node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_lo_lo_hi_22, decoded_andMatrixOutputs_lo_lo_lo_19)
node decoded_andMatrixOutputs_lo_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_11_22, decoded_andMatrixOutputs_andMatrixInput_12_22)
node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_andMatrixOutputs_andMatrixInput_10_22)
node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_lo_hi_lo_22)
node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22)
node decoded_andMatrixOutputs_hi_lo_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_7_22, decoded_andMatrixOutputs_andMatrixInput_8_22)
node decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_5_22, decoded_andMatrixOutputs_andMatrixInput_6_22)
node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_hi_lo_hi_22, decoded_andMatrixOutputs_hi_lo_lo_22)
node decoded_andMatrixOutputs_hi_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_andMatrixOutputs_andMatrixInput_4_22)
node decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22)
node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_2_22)
node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_hi_hi_lo_22)
node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22)
node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22)
node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_22)
node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_15_20, decoded_andMatrixOutputs_andMatrixInput_16_17)
node decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_13_23, decoded_andMatrixOutputs_andMatrixInput_14_23)
node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_lo_lo_hi_23, decoded_andMatrixOutputs_lo_lo_lo_20)
node decoded_andMatrixOutputs_lo_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_11_23, decoded_andMatrixOutputs_andMatrixInput_12_23)
node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_andMatrixOutputs_andMatrixInput_10_23)
node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_lo_hi_lo_23)
node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23)
node decoded_andMatrixOutputs_hi_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_7_23, decoded_andMatrixOutputs_andMatrixInput_8_23)
node decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_5_23, decoded_andMatrixOutputs_andMatrixInput_6_23)
node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_hi_lo_hi_23, decoded_andMatrixOutputs_hi_lo_lo_23)
node decoded_andMatrixOutputs_hi_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_andMatrixOutputs_andMatrixInput_4_23)
node decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23)
node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_2_23)
node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_hi_hi_lo_23)
node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23)
node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23)
node decoded_andMatrixOutputs_32_2 = andr(_decoded_andMatrixOutputs_T_23)
node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_12_24, decoded_andMatrixOutputs_andMatrixInput_13_24)
node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_andMatrixInput_14_24)
node decoded_andMatrixOutputs_lo_hi_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_10_24, decoded_andMatrixOutputs_andMatrixInput_11_24)
node decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_8_24, decoded_andMatrixOutputs_andMatrixInput_9_24)
node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_lo_hi_lo_24)
node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24)
node decoded_andMatrixOutputs_hi_lo_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_andMatrixOutputs_andMatrixInput_7_24)
node decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_4_24, decoded_andMatrixOutputs_andMatrixInput_5_24)
node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_hi_lo_hi_24, decoded_andMatrixOutputs_hi_lo_lo_24)
node decoded_andMatrixOutputs_hi_hi_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_2_24, decoded_andMatrixOutputs_andMatrixInput_3_24)
node decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24)
node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_hi_hi_lo_24)
node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24)
node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_24)
node decoded_andMatrixOutputs_42_2 = andr(_decoded_andMatrixOutputs_T_24)
node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_15_21, decoded_andMatrixOutputs_andMatrixInput_16_18)
node decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_13_25, decoded_andMatrixOutputs_andMatrixInput_14_25)
node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_lo_lo_hi_25, decoded_andMatrixOutputs_lo_lo_lo_21)
node decoded_andMatrixOutputs_lo_hi_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_11_25, decoded_andMatrixOutputs_andMatrixInput_12_25)
node decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_andMatrixOutputs_andMatrixInput_10_25)
node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_25, decoded_andMatrixOutputs_lo_hi_lo_25)
node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25)
node decoded_andMatrixOutputs_hi_lo_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_7_25, decoded_andMatrixOutputs_andMatrixInput_8_25)
node decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_5_25, decoded_andMatrixOutputs_andMatrixInput_6_25)
node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_hi_lo_hi_25, decoded_andMatrixOutputs_hi_lo_lo_25)
node decoded_andMatrixOutputs_hi_hi_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_andMatrixOutputs_andMatrixInput_4_25)
node decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25)
node decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_25)
node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_hi_hi_lo_25)
node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25)
node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_25)
node decoded_andMatrixOutputs_36_2 = andr(_decoded_andMatrixOutputs_T_25)
node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(decoded_plaInput, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(decoded_plaInput, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_15_22, decoded_andMatrixOutputs_andMatrixInput_16_19)
node decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_13_26, decoded_andMatrixOutputs_andMatrixInput_14_26)
node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_lo_lo_hi_26, decoded_andMatrixOutputs_lo_lo_lo_22)
node decoded_andMatrixOutputs_lo_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_11_26, decoded_andMatrixOutputs_andMatrixInput_12_26)
node decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_andMatrixOutputs_andMatrixInput_10_26)
node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_lo_hi_hi_26, decoded_andMatrixOutputs_lo_hi_lo_26)
node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26)
node decoded_andMatrixOutputs_hi_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_7_26, decoded_andMatrixOutputs_andMatrixInput_8_26)
node decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_5_26, decoded_andMatrixOutputs_andMatrixInput_6_26)
node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_hi_lo_hi_26, decoded_andMatrixOutputs_hi_lo_lo_26)
node decoded_andMatrixOutputs_hi_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_andMatrixOutputs_andMatrixInput_4_26)
node decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26)
node decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_26)
node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_hi_hi_lo_26)
node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26)
node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_26)
node decoded_andMatrixOutputs_28_2 = andr(_decoded_andMatrixOutputs_T_26)
node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_15_23, decoded_andMatrixOutputs_andMatrixInput_16_20)
node decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_13_27, decoded_andMatrixOutputs_andMatrixInput_14_27)
node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_lo_lo_hi_27, decoded_andMatrixOutputs_lo_lo_lo_23)
node decoded_andMatrixOutputs_lo_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_11_27, decoded_andMatrixOutputs_andMatrixInput_12_27)
node decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_andMatrixOutputs_andMatrixInput_10_27)
node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_lo_hi_hi_27, decoded_andMatrixOutputs_lo_hi_lo_27)
node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27)
node decoded_andMatrixOutputs_hi_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_7_27, decoded_andMatrixOutputs_andMatrixInput_8_27)
node decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_5_27, decoded_andMatrixOutputs_andMatrixInput_6_27)
node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_hi_lo_hi_27, decoded_andMatrixOutputs_hi_lo_lo_27)
node decoded_andMatrixOutputs_hi_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_andMatrixOutputs_andMatrixInput_4_27)
node decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27)
node decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_27)
node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_27, decoded_andMatrixOutputs_hi_hi_lo_27)
node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27)
node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_27)
node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_27)
node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_15_24, decoded_andMatrixOutputs_andMatrixInput_16_21)
node decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_13_28, decoded_andMatrixOutputs_andMatrixInput_14_28)
node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_lo_lo_hi_28, decoded_andMatrixOutputs_lo_lo_lo_24)
node decoded_andMatrixOutputs_lo_hi_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_11_28, decoded_andMatrixOutputs_andMatrixInput_12_28)
node decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_andMatrixOutputs_andMatrixInput_10_28)
node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_lo_hi_hi_28, decoded_andMatrixOutputs_lo_hi_lo_28)
node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28)
node decoded_andMatrixOutputs_hi_lo_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_7_28, decoded_andMatrixOutputs_andMatrixInput_8_28)
node decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_5_28, decoded_andMatrixOutputs_andMatrixInput_6_28)
node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_hi_lo_hi_28, decoded_andMatrixOutputs_hi_lo_lo_28)
node decoded_andMatrixOutputs_hi_hi_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_andMatrixOutputs_andMatrixInput_4_28)
node decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28)
node decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_28)
node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_28, decoded_andMatrixOutputs_hi_hi_lo_28)
node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28)
node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_28)
node decoded_andMatrixOutputs_21_2 = andr(_decoded_andMatrixOutputs_T_28)
node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_14_29, decoded_andMatrixOutputs_andMatrixInput_15_25)
node decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_12_29, decoded_andMatrixOutputs_andMatrixInput_13_29)
node decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_andMatrixOutputs_lo_lo_hi_29, decoded_andMatrixOutputs_lo_lo_lo_25)
node decoded_andMatrixOutputs_lo_hi_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_10_29, decoded_andMatrixOutputs_andMatrixInput_11_29)
node decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_8_29, decoded_andMatrixOutputs_andMatrixInput_9_29)
node decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_andMatrixOutputs_lo_hi_hi_29, decoded_andMatrixOutputs_lo_hi_lo_29)
node decoded_andMatrixOutputs_lo_29 = cat(decoded_andMatrixOutputs_lo_hi_29, decoded_andMatrixOutputs_lo_lo_29)
node decoded_andMatrixOutputs_hi_lo_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_andMatrixOutputs_andMatrixInput_7_29)
node decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_4_29, decoded_andMatrixOutputs_andMatrixInput_5_29)
node decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_andMatrixOutputs_hi_lo_hi_29, decoded_andMatrixOutputs_hi_lo_lo_29)
node decoded_andMatrixOutputs_hi_hi_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_2_29, decoded_andMatrixOutputs_andMatrixInput_3_29)
node decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29)
node decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_hi_29, decoded_andMatrixOutputs_hi_hi_lo_29)
node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_29, decoded_andMatrixOutputs_hi_lo_29)
node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_29)
node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_29)
node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_15_26, decoded_andMatrixOutputs_andMatrixInput_16_22)
node decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_13_30, decoded_andMatrixOutputs_andMatrixInput_14_30)
node decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_andMatrixOutputs_lo_lo_hi_30, decoded_andMatrixOutputs_lo_lo_lo_26)
node decoded_andMatrixOutputs_lo_hi_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_11_30, decoded_andMatrixOutputs_andMatrixInput_12_30)
node decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_andMatrixOutputs_andMatrixInput_10_30)
node decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_andMatrixOutputs_lo_hi_hi_30, decoded_andMatrixOutputs_lo_hi_lo_30)
node decoded_andMatrixOutputs_lo_30 = cat(decoded_andMatrixOutputs_lo_hi_30, decoded_andMatrixOutputs_lo_lo_30)
node decoded_andMatrixOutputs_hi_lo_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_7_30, decoded_andMatrixOutputs_andMatrixInput_8_30)
node decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_5_30, decoded_andMatrixOutputs_andMatrixInput_6_30)
node decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_andMatrixOutputs_hi_lo_hi_30, decoded_andMatrixOutputs_hi_lo_lo_30)
node decoded_andMatrixOutputs_hi_hi_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_andMatrixOutputs_andMatrixInput_4_30)
node decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30)
node decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_30)
node decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_30, decoded_andMatrixOutputs_hi_hi_lo_30)
node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_30, decoded_andMatrixOutputs_hi_lo_30)
node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_30)
node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_30)
node decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_15_27, decoded_andMatrixOutputs_andMatrixInput_16_23)
node decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_13_31, decoded_andMatrixOutputs_andMatrixInput_14_31)
node decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_andMatrixOutputs_lo_lo_hi_31, decoded_andMatrixOutputs_lo_lo_lo_27)
node decoded_andMatrixOutputs_lo_hi_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_11_31, decoded_andMatrixOutputs_andMatrixInput_12_31)
node decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_andMatrixOutputs_andMatrixInput_10_31)
node decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_andMatrixOutputs_lo_hi_hi_31, decoded_andMatrixOutputs_lo_hi_lo_31)
node decoded_andMatrixOutputs_lo_31 = cat(decoded_andMatrixOutputs_lo_hi_31, decoded_andMatrixOutputs_lo_lo_31)
node decoded_andMatrixOutputs_hi_lo_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_7_31, decoded_andMatrixOutputs_andMatrixInput_8_31)
node decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_5_31, decoded_andMatrixOutputs_andMatrixInput_6_31)
node decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_andMatrixOutputs_hi_lo_hi_31, decoded_andMatrixOutputs_hi_lo_lo_31)
node decoded_andMatrixOutputs_hi_hi_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_andMatrixOutputs_andMatrixInput_4_31)
node decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_andMatrixOutputs_andMatrixInput_1_31)
node decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_31)
node decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_31, decoded_andMatrixOutputs_hi_hi_lo_31)
node decoded_andMatrixOutputs_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_31, decoded_andMatrixOutputs_hi_lo_31)
node _decoded_andMatrixOutputs_T_31 = cat(decoded_andMatrixOutputs_hi_31, decoded_andMatrixOutputs_lo_31)
node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_31)
node decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_28 = cat(decoded_andMatrixOutputs_andMatrixInput_15_28, decoded_andMatrixOutputs_andMatrixInput_16_24)
node decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_13_32, decoded_andMatrixOutputs_andMatrixInput_14_32)
node decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_andMatrixOutputs_lo_lo_hi_32, decoded_andMatrixOutputs_lo_lo_lo_28)
node decoded_andMatrixOutputs_lo_hi_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_11_32, decoded_andMatrixOutputs_andMatrixInput_12_32)
node decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_andMatrixOutputs_andMatrixInput_10_32)
node decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_andMatrixOutputs_lo_hi_hi_32, decoded_andMatrixOutputs_lo_hi_lo_32)
node decoded_andMatrixOutputs_lo_32 = cat(decoded_andMatrixOutputs_lo_hi_32, decoded_andMatrixOutputs_lo_lo_32)
node decoded_andMatrixOutputs_hi_lo_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_7_32, decoded_andMatrixOutputs_andMatrixInput_8_32)
node decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_5_32, decoded_andMatrixOutputs_andMatrixInput_6_32)
node decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_andMatrixOutputs_hi_lo_hi_32, decoded_andMatrixOutputs_hi_lo_lo_32)
node decoded_andMatrixOutputs_hi_hi_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_andMatrixOutputs_andMatrixInput_4_32)
node decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_andMatrixOutputs_andMatrixInput_1_32)
node decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_24, decoded_andMatrixOutputs_andMatrixInput_2_32)
node decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_hi_32, decoded_andMatrixOutputs_hi_hi_lo_32)
node decoded_andMatrixOutputs_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_32, decoded_andMatrixOutputs_hi_lo_32)
node _decoded_andMatrixOutputs_T_32 = cat(decoded_andMatrixOutputs_hi_32, decoded_andMatrixOutputs_lo_32)
node decoded_andMatrixOutputs_39_2 = andr(_decoded_andMatrixOutputs_T_32)
node decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_12_33, decoded_andMatrixOutputs_andMatrixInput_13_33)
node decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_andMatrixOutputs_lo_lo_hi_33, decoded_andMatrixOutputs_andMatrixInput_14_33)
node decoded_andMatrixOutputs_lo_hi_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_10_33, decoded_andMatrixOutputs_andMatrixInput_11_33)
node decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_8_33, decoded_andMatrixOutputs_andMatrixInput_9_33)
node decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_andMatrixOutputs_lo_hi_hi_33, decoded_andMatrixOutputs_lo_hi_lo_33)
node decoded_andMatrixOutputs_lo_33 = cat(decoded_andMatrixOutputs_lo_hi_33, decoded_andMatrixOutputs_lo_lo_33)
node decoded_andMatrixOutputs_hi_lo_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_andMatrixOutputs_andMatrixInput_7_33)
node decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_4_33, decoded_andMatrixOutputs_andMatrixInput_5_33)
node decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_andMatrixOutputs_hi_lo_hi_33, decoded_andMatrixOutputs_hi_lo_lo_33)
node decoded_andMatrixOutputs_hi_hi_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_2_33, decoded_andMatrixOutputs_andMatrixInput_3_33)
node decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_andMatrixOutputs_andMatrixInput_1_33)
node decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_hi_33, decoded_andMatrixOutputs_hi_hi_lo_33)
node decoded_andMatrixOutputs_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_33, decoded_andMatrixOutputs_hi_lo_33)
node _decoded_andMatrixOutputs_T_33 = cat(decoded_andMatrixOutputs_hi_33, decoded_andMatrixOutputs_lo_33)
node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_33)
node decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_29 = cat(decoded_andMatrixOutputs_andMatrixInput_15_29, decoded_andMatrixOutputs_andMatrixInput_16_25)
node decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_13_34, decoded_andMatrixOutputs_andMatrixInput_14_34)
node decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_andMatrixOutputs_lo_lo_hi_34, decoded_andMatrixOutputs_lo_lo_lo_29)
node decoded_andMatrixOutputs_lo_hi_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_11_34, decoded_andMatrixOutputs_andMatrixInput_12_34)
node decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_andMatrixOutputs_andMatrixInput_10_34)
node decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_andMatrixOutputs_lo_hi_hi_34, decoded_andMatrixOutputs_lo_hi_lo_34)
node decoded_andMatrixOutputs_lo_34 = cat(decoded_andMatrixOutputs_lo_hi_34, decoded_andMatrixOutputs_lo_lo_34)
node decoded_andMatrixOutputs_hi_lo_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_7_34, decoded_andMatrixOutputs_andMatrixInput_8_34)
node decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_5_34, decoded_andMatrixOutputs_andMatrixInput_6_34)
node decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_andMatrixOutputs_hi_lo_hi_34, decoded_andMatrixOutputs_hi_lo_lo_34)
node decoded_andMatrixOutputs_hi_hi_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_andMatrixOutputs_andMatrixInput_4_34)
node decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_andMatrixOutputs_andMatrixInput_1_34)
node decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_25, decoded_andMatrixOutputs_andMatrixInput_2_34)
node decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_hi_34, decoded_andMatrixOutputs_hi_hi_lo_34)
node decoded_andMatrixOutputs_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_34, decoded_andMatrixOutputs_hi_lo_34)
node _decoded_andMatrixOutputs_T_34 = cat(decoded_andMatrixOutputs_hi_34, decoded_andMatrixOutputs_lo_34)
node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_34)
node decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_30 = cat(decoded_andMatrixOutputs_andMatrixInput_15_30, decoded_andMatrixOutputs_andMatrixInput_16_26)
node decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_13_35, decoded_andMatrixOutputs_andMatrixInput_14_35)
node decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_andMatrixOutputs_lo_lo_hi_35, decoded_andMatrixOutputs_lo_lo_lo_30)
node decoded_andMatrixOutputs_lo_hi_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_11_35, decoded_andMatrixOutputs_andMatrixInput_12_35)
node decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_andMatrixOutputs_andMatrixInput_10_35)
node decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_andMatrixOutputs_lo_hi_hi_35, decoded_andMatrixOutputs_lo_hi_lo_35)
node decoded_andMatrixOutputs_lo_35 = cat(decoded_andMatrixOutputs_lo_hi_35, decoded_andMatrixOutputs_lo_lo_35)
node decoded_andMatrixOutputs_hi_lo_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_7_35, decoded_andMatrixOutputs_andMatrixInput_8_35)
node decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_5_35, decoded_andMatrixOutputs_andMatrixInput_6_35)
node decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_andMatrixOutputs_hi_lo_hi_35, decoded_andMatrixOutputs_hi_lo_lo_35)
node decoded_andMatrixOutputs_hi_hi_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_andMatrixOutputs_andMatrixInput_4_35)
node decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_andMatrixOutputs_andMatrixInput_1_35)
node decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_26, decoded_andMatrixOutputs_andMatrixInput_2_35)
node decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_hi_35, decoded_andMatrixOutputs_hi_hi_lo_35)
node decoded_andMatrixOutputs_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_35, decoded_andMatrixOutputs_hi_lo_35)
node _decoded_andMatrixOutputs_T_35 = cat(decoded_andMatrixOutputs_hi_35, decoded_andMatrixOutputs_lo_35)
node decoded_andMatrixOutputs_34_2 = andr(_decoded_andMatrixOutputs_T_35)
node decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_plaInput, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(decoded_invInputs, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_31 = cat(decoded_andMatrixOutputs_andMatrixInput_15_31, decoded_andMatrixOutputs_andMatrixInput_16_27)
node decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_13_36, decoded_andMatrixOutputs_andMatrixInput_14_36)
node decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_andMatrixOutputs_lo_lo_hi_36, decoded_andMatrixOutputs_lo_lo_lo_31)
node decoded_andMatrixOutputs_lo_hi_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_11_36, decoded_andMatrixOutputs_andMatrixInput_12_36)
node decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_andMatrixOutputs_andMatrixInput_10_36)
node decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_andMatrixOutputs_lo_hi_hi_36, decoded_andMatrixOutputs_lo_hi_lo_36)
node decoded_andMatrixOutputs_lo_36 = cat(decoded_andMatrixOutputs_lo_hi_36, decoded_andMatrixOutputs_lo_lo_36)
node decoded_andMatrixOutputs_hi_lo_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_7_36, decoded_andMatrixOutputs_andMatrixInput_8_36)
node decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_5_36, decoded_andMatrixOutputs_andMatrixInput_6_36)
node decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_andMatrixOutputs_hi_lo_hi_36, decoded_andMatrixOutputs_hi_lo_lo_36)
node decoded_andMatrixOutputs_hi_hi_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_andMatrixOutputs_andMatrixInput_4_36)
node decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_andMatrixOutputs_andMatrixInput_1_36)
node decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_27, decoded_andMatrixOutputs_andMatrixInput_2_36)
node decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_hi_36, decoded_andMatrixOutputs_hi_hi_lo_36)
node decoded_andMatrixOutputs_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_36, decoded_andMatrixOutputs_hi_lo_36)
node _decoded_andMatrixOutputs_T_36 = cat(decoded_andMatrixOutputs_hi_36, decoded_andMatrixOutputs_lo_36)
node decoded_andMatrixOutputs_30_2 = andr(_decoded_andMatrixOutputs_T_36)
node decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_12_37, decoded_andMatrixOutputs_andMatrixInput_13_37)
node decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_andMatrixOutputs_lo_lo_hi_37, decoded_andMatrixOutputs_andMatrixInput_14_37)
node decoded_andMatrixOutputs_lo_hi_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_10_37, decoded_andMatrixOutputs_andMatrixInput_11_37)
node decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_8_37, decoded_andMatrixOutputs_andMatrixInput_9_37)
node decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_andMatrixOutputs_lo_hi_hi_37, decoded_andMatrixOutputs_lo_hi_lo_37)
node decoded_andMatrixOutputs_lo_37 = cat(decoded_andMatrixOutputs_lo_hi_37, decoded_andMatrixOutputs_lo_lo_37)
node decoded_andMatrixOutputs_hi_lo_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_andMatrixOutputs_andMatrixInput_7_37)
node decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_4_37, decoded_andMatrixOutputs_andMatrixInput_5_37)
node decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_andMatrixOutputs_hi_lo_hi_37, decoded_andMatrixOutputs_hi_lo_lo_37)
node decoded_andMatrixOutputs_hi_hi_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_2_37, decoded_andMatrixOutputs_andMatrixInput_3_37)
node decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_andMatrixOutputs_andMatrixInput_1_37)
node decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_hi_37, decoded_andMatrixOutputs_hi_hi_lo_37)
node decoded_andMatrixOutputs_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_37, decoded_andMatrixOutputs_hi_lo_37)
node _decoded_andMatrixOutputs_T_37 = cat(decoded_andMatrixOutputs_hi_37, decoded_andMatrixOutputs_lo_37)
node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_37)
node decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_14_38, decoded_andMatrixOutputs_andMatrixInput_15_32)
node decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_12_38, decoded_andMatrixOutputs_andMatrixInput_13_38)
node decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_andMatrixOutputs_lo_lo_hi_38, decoded_andMatrixOutputs_lo_lo_lo_32)
node decoded_andMatrixOutputs_lo_hi_lo_38 = cat(decoded_andMatrixOutputs_andMatrixInput_10_38, decoded_andMatrixOutputs_andMatrixInput_11_38)
node decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_8_38, decoded_andMatrixOutputs_andMatrixInput_9_38)
node decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_andMatrixOutputs_lo_hi_hi_38, decoded_andMatrixOutputs_lo_hi_lo_38)
node decoded_andMatrixOutputs_lo_38 = cat(decoded_andMatrixOutputs_lo_hi_38, decoded_andMatrixOutputs_lo_lo_38)
node decoded_andMatrixOutputs_hi_lo_lo_38 = cat(decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_andMatrixOutputs_andMatrixInput_7_38)
node decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_4_38, decoded_andMatrixOutputs_andMatrixInput_5_38)
node decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_andMatrixOutputs_hi_lo_hi_38, decoded_andMatrixOutputs_hi_lo_lo_38)
node decoded_andMatrixOutputs_hi_hi_lo_38 = cat(decoded_andMatrixOutputs_andMatrixInput_2_38, decoded_andMatrixOutputs_andMatrixInput_3_38)
node decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_andMatrixOutputs_andMatrixInput_1_38)
node decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_hi_38, decoded_andMatrixOutputs_hi_hi_lo_38)
node decoded_andMatrixOutputs_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_38, decoded_andMatrixOutputs_hi_lo_38)
node _decoded_andMatrixOutputs_T_38 = cat(decoded_andMatrixOutputs_hi_38, decoded_andMatrixOutputs_lo_38)
node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_38)
node decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_28 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_15_33, decoded_andMatrixOutputs_andMatrixInput_16_28)
node decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_13_39, decoded_andMatrixOutputs_andMatrixInput_14_39)
node decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_andMatrixOutputs_lo_lo_hi_39, decoded_andMatrixOutputs_lo_lo_lo_33)
node decoded_andMatrixOutputs_lo_hi_lo_39 = cat(decoded_andMatrixOutputs_andMatrixInput_11_39, decoded_andMatrixOutputs_andMatrixInput_12_39)
node decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_andMatrixOutputs_andMatrixInput_10_39)
node decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_andMatrixOutputs_lo_hi_hi_39, decoded_andMatrixOutputs_lo_hi_lo_39)
node decoded_andMatrixOutputs_lo_39 = cat(decoded_andMatrixOutputs_lo_hi_39, decoded_andMatrixOutputs_lo_lo_39)
node decoded_andMatrixOutputs_hi_lo_lo_39 = cat(decoded_andMatrixOutputs_andMatrixInput_7_39, decoded_andMatrixOutputs_andMatrixInput_8_39)
node decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_5_39, decoded_andMatrixOutputs_andMatrixInput_6_39)
node decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_andMatrixOutputs_hi_lo_hi_39, decoded_andMatrixOutputs_hi_lo_lo_39)
node decoded_andMatrixOutputs_hi_hi_lo_39 = cat(decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_andMatrixOutputs_andMatrixInput_4_39)
node decoded_andMatrixOutputs_hi_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_andMatrixOutputs_andMatrixInput_1_39)
node decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_28, decoded_andMatrixOutputs_andMatrixInput_2_39)
node decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_hi_39, decoded_andMatrixOutputs_hi_hi_lo_39)
node decoded_andMatrixOutputs_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_39, decoded_andMatrixOutputs_hi_lo_39)
node _decoded_andMatrixOutputs_T_39 = cat(decoded_andMatrixOutputs_hi_39, decoded_andMatrixOutputs_lo_39)
node decoded_andMatrixOutputs_37_2 = andr(_decoded_andMatrixOutputs_T_39)
node decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_invInputs, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_29 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_15_34, decoded_andMatrixOutputs_andMatrixInput_16_29)
node decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_13_40, decoded_andMatrixOutputs_andMatrixInput_14_40)
node decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_andMatrixOutputs_lo_lo_hi_40, decoded_andMatrixOutputs_lo_lo_lo_34)
node decoded_andMatrixOutputs_lo_hi_lo_40 = cat(decoded_andMatrixOutputs_andMatrixInput_11_40, decoded_andMatrixOutputs_andMatrixInput_12_40)
node decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_andMatrixOutputs_andMatrixInput_10_40)
node decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_andMatrixOutputs_lo_hi_hi_40, decoded_andMatrixOutputs_lo_hi_lo_40)
node decoded_andMatrixOutputs_lo_40 = cat(decoded_andMatrixOutputs_lo_hi_40, decoded_andMatrixOutputs_lo_lo_40)
node decoded_andMatrixOutputs_hi_lo_lo_40 = cat(decoded_andMatrixOutputs_andMatrixInput_7_40, decoded_andMatrixOutputs_andMatrixInput_8_40)
node decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_5_40, decoded_andMatrixOutputs_andMatrixInput_6_40)
node decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_andMatrixOutputs_hi_lo_hi_40, decoded_andMatrixOutputs_hi_lo_lo_40)
node decoded_andMatrixOutputs_hi_hi_lo_40 = cat(decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_andMatrixOutputs_andMatrixInput_4_40)
node decoded_andMatrixOutputs_hi_hi_hi_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_andMatrixOutputs_andMatrixInput_1_40)
node decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_29, decoded_andMatrixOutputs_andMatrixInput_2_40)
node decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_hi_40, decoded_andMatrixOutputs_hi_hi_lo_40)
node decoded_andMatrixOutputs_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_40, decoded_andMatrixOutputs_hi_lo_40)
node _decoded_andMatrixOutputs_T_40 = cat(decoded_andMatrixOutputs_hi_40, decoded_andMatrixOutputs_lo_40)
node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_40)
node decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_andMatrixOutputs_andMatrixInput_12_41, decoded_andMatrixOutputs_andMatrixInput_13_41)
node decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_andMatrixOutputs_lo_lo_hi_41, decoded_andMatrixOutputs_andMatrixInput_14_41)
node decoded_andMatrixOutputs_lo_hi_lo_41 = cat(decoded_andMatrixOutputs_andMatrixInput_10_41, decoded_andMatrixOutputs_andMatrixInput_11_41)
node decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_andMatrixOutputs_andMatrixInput_8_41, decoded_andMatrixOutputs_andMatrixInput_9_41)
node decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_andMatrixOutputs_lo_hi_hi_41, decoded_andMatrixOutputs_lo_hi_lo_41)
node decoded_andMatrixOutputs_lo_41 = cat(decoded_andMatrixOutputs_lo_hi_41, decoded_andMatrixOutputs_lo_lo_41)
node decoded_andMatrixOutputs_hi_lo_lo_41 = cat(decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_andMatrixOutputs_andMatrixInput_7_41)
node decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_andMatrixOutputs_andMatrixInput_4_41, decoded_andMatrixOutputs_andMatrixInput_5_41)
node decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_andMatrixOutputs_hi_lo_hi_41, decoded_andMatrixOutputs_hi_lo_lo_41)
node decoded_andMatrixOutputs_hi_hi_lo_41 = cat(decoded_andMatrixOutputs_andMatrixInput_2_41, decoded_andMatrixOutputs_andMatrixInput_3_41)
node decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_andMatrixOutputs_andMatrixInput_1_41)
node decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_andMatrixOutputs_hi_hi_hi_41, decoded_andMatrixOutputs_hi_hi_lo_41)
node decoded_andMatrixOutputs_hi_41 = cat(decoded_andMatrixOutputs_hi_hi_41, decoded_andMatrixOutputs_hi_lo_41)
node _decoded_andMatrixOutputs_T_41 = cat(decoded_andMatrixOutputs_hi_41, decoded_andMatrixOutputs_lo_41)
node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_41)
node decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_invInputs, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_35 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_30 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_15_35, decoded_andMatrixOutputs_andMatrixInput_16_30)
node decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_andMatrixOutputs_andMatrixInput_13_42, decoded_andMatrixOutputs_andMatrixInput_14_42)
node decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_andMatrixOutputs_lo_lo_hi_42, decoded_andMatrixOutputs_lo_lo_lo_35)
node decoded_andMatrixOutputs_lo_hi_lo_42 = cat(decoded_andMatrixOutputs_andMatrixInput_11_42, decoded_andMatrixOutputs_andMatrixInput_12_42)
node decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_andMatrixOutputs_andMatrixInput_10_42)
node decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_andMatrixOutputs_lo_hi_hi_42, decoded_andMatrixOutputs_lo_hi_lo_42)
node decoded_andMatrixOutputs_lo_42 = cat(decoded_andMatrixOutputs_lo_hi_42, decoded_andMatrixOutputs_lo_lo_42)
node decoded_andMatrixOutputs_hi_lo_lo_42 = cat(decoded_andMatrixOutputs_andMatrixInput_7_42, decoded_andMatrixOutputs_andMatrixInput_8_42)
node decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_andMatrixOutputs_andMatrixInput_5_42, decoded_andMatrixOutputs_andMatrixInput_6_42)
node decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_andMatrixOutputs_hi_lo_hi_42, decoded_andMatrixOutputs_hi_lo_lo_42)
node decoded_andMatrixOutputs_hi_hi_lo_42 = cat(decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_andMatrixOutputs_andMatrixInput_4_42)
node decoded_andMatrixOutputs_hi_hi_hi_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_andMatrixOutputs_andMatrixInput_1_42)
node decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_30, decoded_andMatrixOutputs_andMatrixInput_2_42)
node decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_andMatrixOutputs_hi_hi_hi_42, decoded_andMatrixOutputs_hi_hi_lo_42)
node decoded_andMatrixOutputs_hi_42 = cat(decoded_andMatrixOutputs_hi_hi_42, decoded_andMatrixOutputs_hi_lo_42)
node _decoded_andMatrixOutputs_T_42 = cat(decoded_andMatrixOutputs_hi_42, decoded_andMatrixOutputs_lo_42)
node decoded_andMatrixOutputs_23_2 = andr(_decoded_andMatrixOutputs_T_42)
node decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_invInputs, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_invInputs, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_plaInput, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_invInputs, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_plaInput, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_plaInput, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_invInputs, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(decoded_invInputs, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(decoded_plaInput, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(decoded_plaInput, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_36 = bits(decoded_invInputs, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_31 = bits(decoded_plaInput, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_15_36, decoded_andMatrixOutputs_andMatrixInput_16_31)
node decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_andMatrixOutputs_andMatrixInput_13_43, decoded_andMatrixOutputs_andMatrixInput_14_43)
node decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_andMatrixOutputs_lo_lo_hi_43, decoded_andMatrixOutputs_lo_lo_lo_36)
node decoded_andMatrixOutputs_lo_hi_lo_43 = cat(decoded_andMatrixOutputs_andMatrixInput_11_43, decoded_andMatrixOutputs_andMatrixInput_12_43)
node decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_andMatrixOutputs_andMatrixInput_10_43)
node decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_andMatrixOutputs_lo_hi_hi_43, decoded_andMatrixOutputs_lo_hi_lo_43)
node decoded_andMatrixOutputs_lo_43 = cat(decoded_andMatrixOutputs_lo_hi_43, decoded_andMatrixOutputs_lo_lo_43)
node decoded_andMatrixOutputs_hi_lo_lo_43 = cat(decoded_andMatrixOutputs_andMatrixInput_7_43, decoded_andMatrixOutputs_andMatrixInput_8_43)
node decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_andMatrixOutputs_andMatrixInput_5_43, decoded_andMatrixOutputs_andMatrixInput_6_43)
node decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_andMatrixOutputs_hi_lo_hi_43, decoded_andMatrixOutputs_hi_lo_lo_43)
node decoded_andMatrixOutputs_hi_hi_lo_43 = cat(decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_andMatrixOutputs_andMatrixInput_4_43)
node decoded_andMatrixOutputs_hi_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_andMatrixOutputs_andMatrixInput_1_43)
node decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_31, decoded_andMatrixOutputs_andMatrixInput_2_43)
node decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_andMatrixOutputs_hi_hi_hi_43, decoded_andMatrixOutputs_hi_hi_lo_43)
node decoded_andMatrixOutputs_hi_43 = cat(decoded_andMatrixOutputs_hi_hi_43, decoded_andMatrixOutputs_hi_lo_43)
node _decoded_andMatrixOutputs_T_43 = cat(decoded_andMatrixOutputs_hi_43, decoded_andMatrixOutputs_lo_43)
node decoded_andMatrixOutputs_26_2 = andr(_decoded_andMatrixOutputs_T_43)
node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_15_2)
node decoded_orMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2)
node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_andMatrixOutputs_42_2)
node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo)
node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T)
node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_15_2)
node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2)
node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_42_2)
node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1)
node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2)
node decoded_orMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_15_2)
node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2)
node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_42_2)
node _decoded_orMatrixOutputs_T_4 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_2)
node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4)
node decoded_orMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_15_2)
node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2)
node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_42_2)
node _decoded_orMatrixOutputs_T_6 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_3)
node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6)
node decoded_orMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_26_2)
node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2)
node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_28_2)
node _decoded_orMatrixOutputs_T_8 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_4)
node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8)
node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2)
node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_5, decoded_andMatrixOutputs_8_2)
node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10)
node decoded_orMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_40_2, decoded_andMatrixOutputs_38_2)
node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_6, decoded_andMatrixOutputs_30_2)
node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12)
node decoded_orMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_23_2)
node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo)
node decoded_orMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_32_2)
node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_13_2)
node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_5, decoded_orMatrixOutputs_hi_lo)
node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_5)
node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14)
node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_23_2)
node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_lo_6 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1)
node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_32_2)
node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_13_2)
node decoded_orMatrixOutputs_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_6, decoded_orMatrixOutputs_hi_lo_1)
node _decoded_orMatrixOutputs_T_16 = cat(decoded_orMatrixOutputs_hi_8, decoded_orMatrixOutputs_lo_6)
node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16)
node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_23_2)
node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2)
node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_32_2)
node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_13_2)
node decoded_orMatrixOutputs_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_7, decoded_orMatrixOutputs_hi_lo_2)
node _decoded_orMatrixOutputs_T_18 = cat(decoded_orMatrixOutputs_hi_9, decoded_orMatrixOutputs_lo_7)
node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18)
node decoded_orMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_23_2)
node decoded_orMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_orMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_lo_8 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3)
node decoded_orMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_32_2)
node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_13_2)
node decoded_orMatrixOutputs_hi_10 = cat(decoded_orMatrixOutputs_hi_hi_8, decoded_orMatrixOutputs_hi_lo_3)
node _decoded_orMatrixOutputs_T_20 = cat(decoded_orMatrixOutputs_hi_10, decoded_orMatrixOutputs_lo_8)
node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20)
node decoded_orMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_23_2)
node decoded_orMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_36_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_orMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_lo_9 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4)
node decoded_orMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_32_2)
node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_13_2)
node decoded_orMatrixOutputs_hi_11 = cat(decoded_orMatrixOutputs_hi_hi_9, decoded_orMatrixOutputs_hi_lo_4)
node _decoded_orMatrixOutputs_T_22 = cat(decoded_orMatrixOutputs_hi_11, decoded_orMatrixOutputs_lo_9)
node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22)
node decoded_orMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_10 = cat(decoded_orMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_13_2)
node _decoded_orMatrixOutputs_T_24 = cat(decoded_orMatrixOutputs_hi_12, decoded_orMatrixOutputs_lo_10)
node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24)
node decoded_orMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_39_2)
node decoded_orMatrixOutputs_lo_11 = cat(decoded_orMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_16_2)
node decoded_orMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_4_2)
node decoded_orMatrixOutputs_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_13_2)
node _decoded_orMatrixOutputs_T_26 = cat(decoded_orMatrixOutputs_hi_13, decoded_orMatrixOutputs_lo_11)
node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26)
node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_lo_5 = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_7_2)
node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_21_2)
node decoded_orMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_31_2, decoded_andMatrixOutputs_3_2)
node decoded_orMatrixOutputs_lo_hi_7 = cat(decoded_orMatrixOutputs_lo_hi_hi_5, decoded_orMatrixOutputs_lo_hi_lo)
node decoded_orMatrixOutputs_lo_12 = cat(decoded_orMatrixOutputs_lo_hi_7, decoded_orMatrixOutputs_lo_lo_5)
node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_41_2, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_lo_5 = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_11_2)
node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_9_2)
node decoded_orMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_hi_5, decoded_orMatrixOutputs_hi_hi_lo)
node decoded_orMatrixOutputs_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_12, decoded_orMatrixOutputs_hi_lo_5)
node _decoded_orMatrixOutputs_T_28 = cat(decoded_orMatrixOutputs_hi_14, decoded_orMatrixOutputs_lo_12)
node _decoded_orMatrixOutputs_T_29 = orr(_decoded_orMatrixOutputs_T_28)
node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_lo_6 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_7_2)
node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_21_2)
node decoded_orMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_31_2, decoded_andMatrixOutputs_3_2)
node decoded_orMatrixOutputs_lo_hi_8 = cat(decoded_orMatrixOutputs_lo_hi_hi_6, decoded_orMatrixOutputs_lo_hi_lo_1)
node decoded_orMatrixOutputs_lo_13 = cat(decoded_orMatrixOutputs_lo_hi_8, decoded_orMatrixOutputs_lo_lo_6)
node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_41_2, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_lo_6 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_11_2)
node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_9_2)
node decoded_orMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_hi_6, decoded_orMatrixOutputs_hi_hi_lo_1)
node decoded_orMatrixOutputs_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_13, decoded_orMatrixOutputs_hi_lo_6)
node _decoded_orMatrixOutputs_T_30 = cat(decoded_orMatrixOutputs_hi_15, decoded_orMatrixOutputs_lo_13)
node _decoded_orMatrixOutputs_T_31 = orr(_decoded_orMatrixOutputs_T_30)
node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_lo_7 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_7_2)
node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_21_2)
node decoded_orMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_31_2, decoded_andMatrixOutputs_3_2)
node decoded_orMatrixOutputs_lo_hi_9 = cat(decoded_orMatrixOutputs_lo_hi_hi_7, decoded_orMatrixOutputs_lo_hi_lo_2)
node decoded_orMatrixOutputs_lo_14 = cat(decoded_orMatrixOutputs_lo_hi_9, decoded_orMatrixOutputs_lo_lo_7)
node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_41_2, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_lo_7 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_11_2)
node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_9_2)
node decoded_orMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_14 = cat(decoded_orMatrixOutputs_hi_hi_hi_7, decoded_orMatrixOutputs_hi_hi_lo_2)
node decoded_orMatrixOutputs_hi_16 = cat(decoded_orMatrixOutputs_hi_hi_14, decoded_orMatrixOutputs_hi_lo_7)
node _decoded_orMatrixOutputs_T_32 = cat(decoded_orMatrixOutputs_hi_16, decoded_orMatrixOutputs_lo_14)
node _decoded_orMatrixOutputs_T_33 = orr(_decoded_orMatrixOutputs_T_32)
node decoded_orMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_lo_8 = cat(decoded_orMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_7_2)
node decoded_orMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_21_2)
node decoded_orMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_31_2, decoded_andMatrixOutputs_3_2)
node decoded_orMatrixOutputs_lo_hi_10 = cat(decoded_orMatrixOutputs_lo_hi_hi_8, decoded_orMatrixOutputs_lo_hi_lo_3)
node decoded_orMatrixOutputs_lo_15 = cat(decoded_orMatrixOutputs_lo_hi_10, decoded_orMatrixOutputs_lo_lo_8)
node decoded_orMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_41_2, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_lo_8 = cat(decoded_orMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_11_2)
node decoded_orMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_9_2)
node decoded_orMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_15 = cat(decoded_orMatrixOutputs_hi_hi_hi_8, decoded_orMatrixOutputs_hi_hi_lo_3)
node decoded_orMatrixOutputs_hi_17 = cat(decoded_orMatrixOutputs_hi_hi_15, decoded_orMatrixOutputs_hi_lo_8)
node _decoded_orMatrixOutputs_T_34 = cat(decoded_orMatrixOutputs_hi_17, decoded_orMatrixOutputs_lo_15)
node _decoded_orMatrixOutputs_T_35 = orr(_decoded_orMatrixOutputs_T_34)
node decoded_orMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_lo_9 = cat(decoded_orMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_7_2)
node decoded_orMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_21_2)
node decoded_orMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_31_2, decoded_andMatrixOutputs_3_2)
node decoded_orMatrixOutputs_lo_hi_11 = cat(decoded_orMatrixOutputs_lo_hi_hi_9, decoded_orMatrixOutputs_lo_hi_lo_4)
node decoded_orMatrixOutputs_lo_16 = cat(decoded_orMatrixOutputs_lo_hi_11, decoded_orMatrixOutputs_lo_lo_9)
node decoded_orMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_41_2, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_lo_9 = cat(decoded_orMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_11_2)
node decoded_orMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_9_2)
node decoded_orMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_16 = cat(decoded_orMatrixOutputs_hi_hi_hi_9, decoded_orMatrixOutputs_hi_hi_lo_4)
node decoded_orMatrixOutputs_hi_18 = cat(decoded_orMatrixOutputs_hi_hi_16, decoded_orMatrixOutputs_hi_lo_9)
node _decoded_orMatrixOutputs_T_36 = cat(decoded_orMatrixOutputs_hi_18, decoded_orMatrixOutputs_lo_16)
node _decoded_orMatrixOutputs_T_37 = orr(_decoded_orMatrixOutputs_T_36)
node decoded_orMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_21_2, decoded_andMatrixOutputs_1_2)
node decoded_orMatrixOutputs_lo_lo_10 = cat(decoded_orMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_31_2)
node decoded_orMatrixOutputs_lo_hi_12 = cat(decoded_orMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_19_2)
node decoded_orMatrixOutputs_lo_17 = cat(decoded_orMatrixOutputs_lo_hi_12, decoded_orMatrixOutputs_lo_lo_10)
node decoded_orMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_41_2)
node decoded_orMatrixOutputs_hi_lo_10 = cat(decoded_orMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_17 = cat(decoded_orMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_25_2)
node decoded_orMatrixOutputs_hi_19 = cat(decoded_orMatrixOutputs_hi_hi_17, decoded_orMatrixOutputs_hi_lo_10)
node _decoded_orMatrixOutputs_T_38 = cat(decoded_orMatrixOutputs_hi_19, decoded_orMatrixOutputs_lo_17)
node _decoded_orMatrixOutputs_T_39 = orr(_decoded_orMatrixOutputs_T_38)
node decoded_orMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_21_2, decoded_andMatrixOutputs_1_2)
node decoded_orMatrixOutputs_lo_lo_11 = cat(decoded_orMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_34_2)
node decoded_orMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_11_2, decoded_andMatrixOutputs_31_2)
node decoded_orMatrixOutputs_lo_hi_13 = cat(decoded_orMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_19_2)
node decoded_orMatrixOutputs_lo_18 = cat(decoded_orMatrixOutputs_lo_hi_13, decoded_orMatrixOutputs_lo_lo_11)
node decoded_orMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_9_2, decoded_andMatrixOutputs_41_2)
node decoded_orMatrixOutputs_hi_lo_11 = cat(decoded_orMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_43_2)
node decoded_orMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_24_2)
node decoded_orMatrixOutputs_hi_hi_18 = cat(decoded_orMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_25_2)
node decoded_orMatrixOutputs_hi_20 = cat(decoded_orMatrixOutputs_hi_hi_18, decoded_orMatrixOutputs_hi_lo_11)
node _decoded_orMatrixOutputs_T_40 = cat(decoded_orMatrixOutputs_hi_20, decoded_orMatrixOutputs_lo_18)
node _decoded_orMatrixOutputs_T_41 = orr(_decoded_orMatrixOutputs_T_40)
node decoded_orMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_5_2)
node decoded_orMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2)
node decoded_orMatrixOutputs_hi_21 = cat(decoded_orMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_14_2)
node _decoded_orMatrixOutputs_T_42 = cat(decoded_orMatrixOutputs_hi_21, decoded_orMatrixOutputs_lo_19)
node _decoded_orMatrixOutputs_T_43 = orr(_decoded_orMatrixOutputs_T_42)
node decoded_orMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_5_2)
node decoded_orMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2)
node decoded_orMatrixOutputs_hi_22 = cat(decoded_orMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_14_2)
node _decoded_orMatrixOutputs_T_44 = cat(decoded_orMatrixOutputs_hi_22, decoded_orMatrixOutputs_lo_20)
node _decoded_orMatrixOutputs_T_45 = orr(_decoded_orMatrixOutputs_T_44)
node decoded_orMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_5_2)
node decoded_orMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2)
node decoded_orMatrixOutputs_hi_23 = cat(decoded_orMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_14_2)
node _decoded_orMatrixOutputs_T_46 = cat(decoded_orMatrixOutputs_hi_23, decoded_orMatrixOutputs_lo_21)
node _decoded_orMatrixOutputs_T_47 = orr(_decoded_orMatrixOutputs_T_46)
node decoded_orMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_5_2)
node decoded_orMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2)
node decoded_orMatrixOutputs_hi_24 = cat(decoded_orMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_14_2)
node _decoded_orMatrixOutputs_T_48 = cat(decoded_orMatrixOutputs_hi_24, decoded_orMatrixOutputs_lo_22)
node _decoded_orMatrixOutputs_T_49 = orr(_decoded_orMatrixOutputs_T_48)
node decoded_orMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_37_2)
node decoded_orMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2)
node decoded_orMatrixOutputs_hi_25 = cat(decoded_orMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_12_2)
node _decoded_orMatrixOutputs_T_50 = cat(decoded_orMatrixOutputs_hi_25, decoded_orMatrixOutputs_lo_23)
node _decoded_orMatrixOutputs_T_51 = orr(_decoded_orMatrixOutputs_T_50)
node decoded_orMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_20_2, decoded_andMatrixOutputs_29_2)
node _decoded_orMatrixOutputs_T_52 = cat(decoded_orMatrixOutputs_hi_26, decoded_andMatrixOutputs_0_2)
node _decoded_orMatrixOutputs_T_53 = orr(_decoded_orMatrixOutputs_T_52)
node decoded_orMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_33_2, decoded_andMatrixOutputs_22_2)
node _decoded_orMatrixOutputs_T_54 = cat(decoded_orMatrixOutputs_hi_27, decoded_andMatrixOutputs_6_2)
node _decoded_orMatrixOutputs_T_55 = orr(_decoded_orMatrixOutputs_T_54)
node decoded_orMatrixOutputs_lo_lo_lo_lo = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1)
node decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_7)
node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_hi, _decoded_orMatrixOutputs_T_5)
node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo_lo)
node decoded_orMatrixOutputs_lo_lo_hi_lo = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_11)
node decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_17, _decoded_orMatrixOutputs_T_15)
node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_hi, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_hi_7 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_orMatrixOutputs_lo_lo_hi_lo)
node decoded_orMatrixOutputs_lo_lo_12 = cat(decoded_orMatrixOutputs_lo_lo_hi_7, decoded_orMatrixOutputs_lo_lo_lo)
node decoded_orMatrixOutputs_lo_hi_lo_lo = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19)
node decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(_decoded_orMatrixOutputs_T_27, _decoded_orMatrixOutputs_T_25)
node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_hi, _decoded_orMatrixOutputs_T_23)
node decoded_orMatrixOutputs_lo_hi_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_orMatrixOutputs_lo_hi_lo_lo)
node decoded_orMatrixOutputs_lo_hi_hi_lo = cat(_decoded_orMatrixOutputs_T_29, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_35, _decoded_orMatrixOutputs_T_33)
node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_hi, _decoded_orMatrixOutputs_T_31)
node decoded_orMatrixOutputs_lo_hi_hi_12 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_orMatrixOutputs_lo_hi_hi_lo)
node decoded_orMatrixOutputs_lo_hi_14 = cat(decoded_orMatrixOutputs_lo_hi_hi_12, decoded_orMatrixOutputs_lo_hi_lo_5)
node decoded_orMatrixOutputs_lo_24 = cat(decoded_orMatrixOutputs_lo_hi_14, decoded_orMatrixOutputs_lo_lo_12)
node decoded_orMatrixOutputs_hi_lo_lo_lo = cat(_decoded_orMatrixOutputs_T_39, _decoded_orMatrixOutputs_T_37)
node decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(_decoded_orMatrixOutputs_T_43, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_hi, _decoded_orMatrixOutputs_T_41)
node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_orMatrixOutputs_hi_lo_lo_lo)
node decoded_orMatrixOutputs_hi_lo_hi_lo = cat(_decoded_orMatrixOutputs_T_47, _decoded_orMatrixOutputs_T_45)
node decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_53, _decoded_orMatrixOutputs_T_51)
node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_hi, _decoded_orMatrixOutputs_T_49)
node decoded_orMatrixOutputs_hi_lo_hi_7 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_orMatrixOutputs_hi_lo_hi_lo)
node decoded_orMatrixOutputs_hi_lo_12 = cat(decoded_orMatrixOutputs_hi_lo_hi_7, decoded_orMatrixOutputs_hi_lo_lo)
node decoded_orMatrixOutputs_hi_hi_lo_lo = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_55)
node decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_hi, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_lo_5 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_orMatrixOutputs_hi_hi_lo_lo)
node decoded_orMatrixOutputs_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_hi, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_hi_lo)
node decoded_orMatrixOutputs_hi_hi_24 = cat(decoded_orMatrixOutputs_hi_hi_hi_12, decoded_orMatrixOutputs_hi_hi_lo_5)
node decoded_orMatrixOutputs_hi_28 = cat(decoded_orMatrixOutputs_hi_hi_24, decoded_orMatrixOutputs_hi_lo_12)
node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_28, decoded_orMatrixOutputs_lo_24)
node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0)
node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1)
node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2)
node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3)
node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4)
node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5)
node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6)
node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7)
node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8)
node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9)
node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10)
node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11)
node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12)
node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13)
node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14)
node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15)
node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16)
node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17)
node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18)
node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19)
node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20)
node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21)
node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22)
node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23)
node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs, 24, 24)
node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs, 25, 25)
node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs, 26, 26)
node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs, 27, 27)
node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs, 28, 28)
node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs, 29, 29)
node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs, 30, 30)
node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs, 31, 31)
node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs, 32, 32)
node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs, 33, 33)
node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs, 34, 34)
node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs, 35, 35)
node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs, 36, 36)
node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs, 37, 37)
node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs, 38, 38)
node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs, 39, 39)
node decoded_invMatrixOutputs_lo_lo_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T)
node decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_4, _decoded_invMatrixOutputs_T_3)
node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _decoded_invMatrixOutputs_T_2)
node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo_lo)
node decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_decoded_invMatrixOutputs_T_6, _decoded_invMatrixOutputs_T_5)
node decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_9, _decoded_invMatrixOutputs_T_8)
node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _decoded_invMatrixOutputs_T_7)
node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_invMatrixOutputs_lo_lo_hi_lo)
node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo)
node decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10)
node decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13)
node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _decoded_invMatrixOutputs_T_12)
node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_invMatrixOutputs_lo_hi_lo_lo)
node decoded_invMatrixOutputs_lo_hi_hi_lo = cat(_decoded_invMatrixOutputs_T_16, _decoded_invMatrixOutputs_T_15)
node decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18)
node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _decoded_invMatrixOutputs_T_17)
node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_invMatrixOutputs_lo_hi_hi_lo)
node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo)
node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo)
node decoded_invMatrixOutputs_hi_lo_lo_lo = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20)
node decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_24, _decoded_invMatrixOutputs_T_23)
node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _decoded_invMatrixOutputs_T_22)
node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_invMatrixOutputs_hi_lo_lo_lo)
node decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25)
node decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28)
node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _decoded_invMatrixOutputs_T_27)
node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_invMatrixOutputs_hi_lo_hi_lo)
node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo)
node decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_decoded_invMatrixOutputs_T_31, _decoded_invMatrixOutputs_T_30)
node decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_34, _decoded_invMatrixOutputs_T_33)
node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _decoded_invMatrixOutputs_T_32)
node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_invMatrixOutputs_hi_hi_lo_lo)
node decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_decoded_invMatrixOutputs_T_36, _decoded_invMatrixOutputs_T_35)
node decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_39, _decoded_invMatrixOutputs_T_38)
node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _decoded_invMatrixOutputs_T_37)
node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_hi_lo)
node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo)
node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo)
node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo)
connect decoded_plaOutput, decoded_invMatrixOutputs
connect decoded_plaInput, addr
node _decoded_T = bits(decoded_plaOutput, 31, 0)
node _decoded_T_1 = shl(UInt<16>(0hffff), 16)
node _decoded_T_2 = xor(UInt<32>(0hffffffff), _decoded_T_1)
node _decoded_T_3 = shr(_decoded_T, 16)
node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2)
node _decoded_T_5 = bits(_decoded_T, 15, 0)
node _decoded_T_6 = shl(_decoded_T_5, 16)
node _decoded_T_7 = not(_decoded_T_2)
node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7)
node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8)
node _decoded_T_10 = bits(_decoded_T_2, 23, 0)
node _decoded_T_11 = shl(_decoded_T_10, 8)
node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11)
node _decoded_T_13 = shr(_decoded_T_9, 8)
node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12)
node _decoded_T_15 = bits(_decoded_T_9, 23, 0)
node _decoded_T_16 = shl(_decoded_T_15, 8)
node _decoded_T_17 = not(_decoded_T_12)
node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17)
node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18)
node _decoded_T_20 = bits(_decoded_T_12, 27, 0)
node _decoded_T_21 = shl(_decoded_T_20, 4)
node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21)
node _decoded_T_23 = shr(_decoded_T_19, 4)
node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22)
node _decoded_T_25 = bits(_decoded_T_19, 27, 0)
node _decoded_T_26 = shl(_decoded_T_25, 4)
node _decoded_T_27 = not(_decoded_T_22)
node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27)
node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28)
node _decoded_T_30 = bits(_decoded_T_22, 29, 0)
node _decoded_T_31 = shl(_decoded_T_30, 2)
node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31)
node _decoded_T_33 = shr(_decoded_T_29, 2)
node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32)
node _decoded_T_35 = bits(_decoded_T_29, 29, 0)
node _decoded_T_36 = shl(_decoded_T_35, 2)
node _decoded_T_37 = not(_decoded_T_32)
node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37)
node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38)
node _decoded_T_40 = bits(_decoded_T_32, 30, 0)
node _decoded_T_41 = shl(_decoded_T_40, 1)
node _decoded_T_42 = xor(_decoded_T_32, _decoded_T_41)
node _decoded_T_43 = shr(_decoded_T_39, 1)
node _decoded_T_44 = and(_decoded_T_43, _decoded_T_42)
node _decoded_T_45 = bits(_decoded_T_39, 30, 0)
node _decoded_T_46 = shl(_decoded_T_45, 1)
node _decoded_T_47 = not(_decoded_T_42)
node _decoded_T_48 = and(_decoded_T_46, _decoded_T_47)
node _decoded_T_49 = or(_decoded_T_44, _decoded_T_48)
node _decoded_T_50 = bits(decoded_plaOutput, 39, 32)
node _decoded_T_51 = shl(UInt<4>(0hf), 4)
node _decoded_T_52 = xor(UInt<8>(0hff), _decoded_T_51)
node _decoded_T_53 = shr(_decoded_T_50, 4)
node _decoded_T_54 = and(_decoded_T_53, _decoded_T_52)
node _decoded_T_55 = bits(_decoded_T_50, 3, 0)
node _decoded_T_56 = shl(_decoded_T_55, 4)
node _decoded_T_57 = not(_decoded_T_52)
node _decoded_T_58 = and(_decoded_T_56, _decoded_T_57)
node _decoded_T_59 = or(_decoded_T_54, _decoded_T_58)
node _decoded_T_60 = bits(_decoded_T_52, 5, 0)
node _decoded_T_61 = shl(_decoded_T_60, 2)
node _decoded_T_62 = xor(_decoded_T_52, _decoded_T_61)
node _decoded_T_63 = shr(_decoded_T_59, 2)
node _decoded_T_64 = and(_decoded_T_63, _decoded_T_62)
node _decoded_T_65 = bits(_decoded_T_59, 5, 0)
node _decoded_T_66 = shl(_decoded_T_65, 2)
node _decoded_T_67 = not(_decoded_T_62)
node _decoded_T_68 = and(_decoded_T_66, _decoded_T_67)
node _decoded_T_69 = or(_decoded_T_64, _decoded_T_68)
node _decoded_T_70 = bits(_decoded_T_62, 6, 0)
node _decoded_T_71 = shl(_decoded_T_70, 1)
node _decoded_T_72 = xor(_decoded_T_62, _decoded_T_71)
node _decoded_T_73 = shr(_decoded_T_69, 1)
node _decoded_T_74 = and(_decoded_T_73, _decoded_T_72)
node _decoded_T_75 = bits(_decoded_T_69, 6, 0)
node _decoded_T_76 = shl(_decoded_T_75, 1)
node _decoded_T_77 = not(_decoded_T_72)
node _decoded_T_78 = and(_decoded_T_76, _decoded_T_77)
node _decoded_T_79 = or(_decoded_T_74, _decoded_T_78)
node decoded = cat(_decoded_T_49, _decoded_T_79)
node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0)
connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T
node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1)
connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T
node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2)
connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T
node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3)
connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T
node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4)
connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T
node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5)
connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T
node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6)
connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T
node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7)
connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T
node _io_resp_0_vc_sel_1_0_T = bits(decoded, 8, 8)
connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T
node _io_resp_0_vc_sel_1_1_T = bits(decoded, 9, 9)
connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T
node _io_resp_0_vc_sel_1_2_T = bits(decoded, 10, 10)
connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T
node _io_resp_0_vc_sel_1_3_T = bits(decoded, 11, 11)
connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T
node _io_resp_0_vc_sel_1_4_T = bits(decoded, 12, 12)
connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T
node _io_resp_0_vc_sel_1_5_T = bits(decoded, 13, 13)
connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T
node _io_resp_0_vc_sel_1_6_T = bits(decoded, 14, 14)
connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T
node _io_resp_0_vc_sel_1_7_T = bits(decoded, 15, 15)
connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T
node _io_resp_0_vc_sel_2_0_T = bits(decoded, 16, 16)
connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T
node _io_resp_0_vc_sel_2_1_T = bits(decoded, 17, 17)
connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T
node _io_resp_0_vc_sel_2_2_T = bits(decoded, 18, 18)
connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T
node _io_resp_0_vc_sel_2_3_T = bits(decoded, 19, 19)
connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T
node _io_resp_0_vc_sel_2_4_T = bits(decoded, 20, 20)
connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T
node _io_resp_0_vc_sel_2_5_T = bits(decoded, 21, 21)
connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T
node _io_resp_0_vc_sel_2_6_T = bits(decoded, 22, 22)
connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T
node _io_resp_0_vc_sel_2_7_T = bits(decoded, 23, 23)
connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T
node _io_resp_0_vc_sel_3_0_T = bits(decoded, 24, 24)
connect io.resp.`0`.vc_sel.`3`[0], _io_resp_0_vc_sel_3_0_T
node _io_resp_0_vc_sel_3_1_T = bits(decoded, 25, 25)
connect io.resp.`0`.vc_sel.`3`[1], _io_resp_0_vc_sel_3_1_T
node _io_resp_0_vc_sel_3_2_T = bits(decoded, 26, 26)
connect io.resp.`0`.vc_sel.`3`[2], _io_resp_0_vc_sel_3_2_T
node _io_resp_0_vc_sel_3_3_T = bits(decoded, 27, 27)
connect io.resp.`0`.vc_sel.`3`[3], _io_resp_0_vc_sel_3_3_T
node _io_resp_0_vc_sel_3_4_T = bits(decoded, 28, 28)
connect io.resp.`0`.vc_sel.`3`[4], _io_resp_0_vc_sel_3_4_T
node _io_resp_0_vc_sel_3_5_T = bits(decoded, 29, 29)
connect io.resp.`0`.vc_sel.`3`[5], _io_resp_0_vc_sel_3_5_T
node _io_resp_0_vc_sel_3_6_T = bits(decoded, 30, 30)
connect io.resp.`0`.vc_sel.`3`[6], _io_resp_0_vc_sel_3_6_T
node _io_resp_0_vc_sel_3_7_T = bits(decoded, 31, 31)
connect io.resp.`0`.vc_sel.`3`[7], _io_resp_0_vc_sel_3_7_T
node _io_resp_0_vc_sel_4_0_T = bits(decoded, 32, 32)
connect io.resp.`0`.vc_sel.`4`[0], _io_resp_0_vc_sel_4_0_T
node _io_resp_0_vc_sel_4_1_T = bits(decoded, 33, 33)
connect io.resp.`0`.vc_sel.`4`[1], _io_resp_0_vc_sel_4_1_T
node _io_resp_0_vc_sel_4_2_T = bits(decoded, 34, 34)
connect io.resp.`0`.vc_sel.`4`[2], _io_resp_0_vc_sel_4_2_T
node _io_resp_0_vc_sel_4_3_T = bits(decoded, 35, 35)
connect io.resp.`0`.vc_sel.`4`[3], _io_resp_0_vc_sel_4_3_T
node _io_resp_0_vc_sel_4_4_T = bits(decoded, 36, 36)
connect io.resp.`0`.vc_sel.`4`[4], _io_resp_0_vc_sel_4_4_T
node _io_resp_0_vc_sel_4_5_T = bits(decoded, 37, 37)
connect io.resp.`0`.vc_sel.`4`[5], _io_resp_0_vc_sel_4_5_T
node _io_resp_0_vc_sel_4_6_T = bits(decoded, 38, 38)
connect io.resp.`0`.vc_sel.`4`[6], _io_resp_0_vc_sel_4_6_T
node _io_resp_0_vc_sel_4_7_T = bits(decoded, 39, 39)
connect io.resp.`0`.vc_sel.`4`[7], _io_resp_0_vc_sel_4_7_T
connect io.req.`1`.ready, UInt<1>(0h1)
node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id)
node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node)
node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id)
node _addr_T_1 = cat(addr_hi_1, addr_lo_1)
node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1)
wire decoded_plaInput_1 : UInt<20>
node decoded_invInputs_1 = not(decoded_plaInput_1)
wire decoded_plaOutput_1 : UInt<40>
node decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_plaInput_1, 2, 2)
node decoded_andMatrixOutputs_hi_44 = cat(decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_andMatrixOutputs_andMatrixInput_1_44)
node _decoded_andMatrixOutputs_T_44 = cat(decoded_andMatrixOutputs_hi_44, decoded_andMatrixOutputs_andMatrixInput_2_44)
node decoded_andMatrixOutputs_23_2_1 = andr(_decoded_andMatrixOutputs_T_44)
node decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_andMatrixOutputs_andMatrixInput_12_44, decoded_andMatrixOutputs_andMatrixInput_13_44)
node decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_andMatrixOutputs_lo_lo_hi_44, decoded_andMatrixOutputs_andMatrixInput_14_44)
node decoded_andMatrixOutputs_lo_hi_lo_44 = cat(decoded_andMatrixOutputs_andMatrixInput_10_44, decoded_andMatrixOutputs_andMatrixInput_11_44)
node decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_andMatrixOutputs_andMatrixInput_8_44, decoded_andMatrixOutputs_andMatrixInput_9_44)
node decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_andMatrixOutputs_lo_hi_hi_44, decoded_andMatrixOutputs_lo_hi_lo_44)
node decoded_andMatrixOutputs_lo_44 = cat(decoded_andMatrixOutputs_lo_hi_44, decoded_andMatrixOutputs_lo_lo_44)
node decoded_andMatrixOutputs_hi_lo_lo_44 = cat(decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_andMatrixOutputs_andMatrixInput_7_44)
node decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_andMatrixOutputs_andMatrixInput_4_44, decoded_andMatrixOutputs_andMatrixInput_5_44)
node decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_andMatrixOutputs_hi_lo_hi_44, decoded_andMatrixOutputs_hi_lo_lo_44)
node decoded_andMatrixOutputs_hi_hi_lo_44 = cat(decoded_andMatrixOutputs_andMatrixInput_2_45, decoded_andMatrixOutputs_andMatrixInput_3_44)
node decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_andMatrixOutputs_andMatrixInput_1_45)
node decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_andMatrixOutputs_hi_hi_hi_44, decoded_andMatrixOutputs_hi_hi_lo_44)
node decoded_andMatrixOutputs_hi_45 = cat(decoded_andMatrixOutputs_hi_hi_44, decoded_andMatrixOutputs_hi_lo_44)
node _decoded_andMatrixOutputs_T_45 = cat(decoded_andMatrixOutputs_hi_45, decoded_andMatrixOutputs_lo_44)
node decoded_andMatrixOutputs_11_2_1 = andr(_decoded_andMatrixOutputs_T_45)
node decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_12_45, decoded_andMatrixOutputs_andMatrixInput_13_45)
node decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_andMatrixOutputs_lo_lo_hi_45, decoded_andMatrixOutputs_andMatrixInput_14_45)
node decoded_andMatrixOutputs_lo_hi_lo_45 = cat(decoded_andMatrixOutputs_andMatrixInput_10_45, decoded_andMatrixOutputs_andMatrixInput_11_45)
node decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_8_45, decoded_andMatrixOutputs_andMatrixInput_9_45)
node decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_andMatrixOutputs_lo_hi_hi_45, decoded_andMatrixOutputs_lo_hi_lo_45)
node decoded_andMatrixOutputs_lo_45 = cat(decoded_andMatrixOutputs_lo_hi_45, decoded_andMatrixOutputs_lo_lo_45)
node decoded_andMatrixOutputs_hi_lo_lo_45 = cat(decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_andMatrixOutputs_andMatrixInput_7_45)
node decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_4_45, decoded_andMatrixOutputs_andMatrixInput_5_45)
node decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_andMatrixOutputs_hi_lo_hi_45, decoded_andMatrixOutputs_hi_lo_lo_45)
node decoded_andMatrixOutputs_hi_hi_lo_45 = cat(decoded_andMatrixOutputs_andMatrixInput_2_46, decoded_andMatrixOutputs_andMatrixInput_3_45)
node decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_andMatrixOutputs_andMatrixInput_1_46)
node decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_andMatrixOutputs_hi_hi_hi_45, decoded_andMatrixOutputs_hi_hi_lo_45)
node decoded_andMatrixOutputs_hi_46 = cat(decoded_andMatrixOutputs_hi_hi_45, decoded_andMatrixOutputs_hi_lo_45)
node _decoded_andMatrixOutputs_T_46 = cat(decoded_andMatrixOutputs_hi_46, decoded_andMatrixOutputs_lo_45)
node decoded_andMatrixOutputs_12_2_1 = andr(_decoded_andMatrixOutputs_T_46)
node decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_12_46, decoded_andMatrixOutputs_andMatrixInput_13_46)
node decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_andMatrixOutputs_lo_lo_hi_46, decoded_andMatrixOutputs_andMatrixInput_14_46)
node decoded_andMatrixOutputs_lo_hi_lo_46 = cat(decoded_andMatrixOutputs_andMatrixInput_10_46, decoded_andMatrixOutputs_andMatrixInput_11_46)
node decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_8_46, decoded_andMatrixOutputs_andMatrixInput_9_46)
node decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_andMatrixOutputs_lo_hi_hi_46, decoded_andMatrixOutputs_lo_hi_lo_46)
node decoded_andMatrixOutputs_lo_46 = cat(decoded_andMatrixOutputs_lo_hi_46, decoded_andMatrixOutputs_lo_lo_46)
node decoded_andMatrixOutputs_hi_lo_lo_46 = cat(decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_andMatrixOutputs_andMatrixInput_7_46)
node decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_4_46, decoded_andMatrixOutputs_andMatrixInput_5_46)
node decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_andMatrixOutputs_hi_lo_hi_46, decoded_andMatrixOutputs_hi_lo_lo_46)
node decoded_andMatrixOutputs_hi_hi_lo_46 = cat(decoded_andMatrixOutputs_andMatrixInput_2_47, decoded_andMatrixOutputs_andMatrixInput_3_46)
node decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_andMatrixOutputs_andMatrixInput_1_47)
node decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_andMatrixOutputs_hi_hi_hi_46, decoded_andMatrixOutputs_hi_hi_lo_46)
node decoded_andMatrixOutputs_hi_47 = cat(decoded_andMatrixOutputs_hi_hi_46, decoded_andMatrixOutputs_hi_lo_46)
node _decoded_andMatrixOutputs_T_47 = cat(decoded_andMatrixOutputs_hi_47, decoded_andMatrixOutputs_lo_46)
node decoded_andMatrixOutputs_54_2 = andr(_decoded_andMatrixOutputs_T_47)
node decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_12_47, decoded_andMatrixOutputs_andMatrixInput_13_47)
node decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_andMatrixOutputs_lo_lo_hi_47, decoded_andMatrixOutputs_andMatrixInput_14_47)
node decoded_andMatrixOutputs_lo_hi_lo_47 = cat(decoded_andMatrixOutputs_andMatrixInput_10_47, decoded_andMatrixOutputs_andMatrixInput_11_47)
node decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_8_47, decoded_andMatrixOutputs_andMatrixInput_9_47)
node decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_andMatrixOutputs_lo_hi_hi_47, decoded_andMatrixOutputs_lo_hi_lo_47)
node decoded_andMatrixOutputs_lo_47 = cat(decoded_andMatrixOutputs_lo_hi_47, decoded_andMatrixOutputs_lo_lo_47)
node decoded_andMatrixOutputs_hi_lo_lo_47 = cat(decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_andMatrixOutputs_andMatrixInput_7_47)
node decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_4_47, decoded_andMatrixOutputs_andMatrixInput_5_47)
node decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_andMatrixOutputs_hi_lo_hi_47, decoded_andMatrixOutputs_hi_lo_lo_47)
node decoded_andMatrixOutputs_hi_hi_lo_47 = cat(decoded_andMatrixOutputs_andMatrixInput_2_48, decoded_andMatrixOutputs_andMatrixInput_3_47)
node decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_andMatrixOutputs_andMatrixInput_1_48)
node decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_andMatrixOutputs_hi_hi_hi_47, decoded_andMatrixOutputs_hi_hi_lo_47)
node decoded_andMatrixOutputs_hi_48 = cat(decoded_andMatrixOutputs_hi_hi_47, decoded_andMatrixOutputs_hi_lo_47)
node _decoded_andMatrixOutputs_T_48 = cat(decoded_andMatrixOutputs_hi_48, decoded_andMatrixOutputs_lo_47)
node decoded_andMatrixOutputs_27_2_1 = andr(_decoded_andMatrixOutputs_T_48)
node decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_andMatrixOutputs_andMatrixInput_12_48, decoded_andMatrixOutputs_andMatrixInput_13_48)
node decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_andMatrixOutputs_lo_lo_hi_48, decoded_andMatrixOutputs_andMatrixInput_14_48)
node decoded_andMatrixOutputs_lo_hi_lo_48 = cat(decoded_andMatrixOutputs_andMatrixInput_10_48, decoded_andMatrixOutputs_andMatrixInput_11_48)
node decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_andMatrixOutputs_andMatrixInput_8_48, decoded_andMatrixOutputs_andMatrixInput_9_48)
node decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_andMatrixOutputs_lo_hi_hi_48, decoded_andMatrixOutputs_lo_hi_lo_48)
node decoded_andMatrixOutputs_lo_48 = cat(decoded_andMatrixOutputs_lo_hi_48, decoded_andMatrixOutputs_lo_lo_48)
node decoded_andMatrixOutputs_hi_lo_lo_48 = cat(decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_andMatrixOutputs_andMatrixInput_7_48)
node decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_andMatrixOutputs_andMatrixInput_4_48, decoded_andMatrixOutputs_andMatrixInput_5_48)
node decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_andMatrixOutputs_hi_lo_hi_48, decoded_andMatrixOutputs_hi_lo_lo_48)
node decoded_andMatrixOutputs_hi_hi_lo_48 = cat(decoded_andMatrixOutputs_andMatrixInput_2_49, decoded_andMatrixOutputs_andMatrixInput_3_48)
node decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_andMatrixOutputs_andMatrixInput_1_49)
node decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_andMatrixOutputs_hi_hi_hi_48, decoded_andMatrixOutputs_hi_hi_lo_48)
node decoded_andMatrixOutputs_hi_49 = cat(decoded_andMatrixOutputs_hi_hi_48, decoded_andMatrixOutputs_hi_lo_48)
node _decoded_andMatrixOutputs_T_49 = cat(decoded_andMatrixOutputs_hi_49, decoded_andMatrixOutputs_lo_48)
node decoded_andMatrixOutputs_51_2 = andr(_decoded_andMatrixOutputs_T_49)
node decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_37 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_32 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_15_37, decoded_andMatrixOutputs_andMatrixInput_16_32)
node decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_andMatrixOutputs_andMatrixInput_13_49, decoded_andMatrixOutputs_andMatrixInput_14_49)
node decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_andMatrixOutputs_lo_lo_hi_49, decoded_andMatrixOutputs_lo_lo_lo_37)
node decoded_andMatrixOutputs_lo_hi_lo_49 = cat(decoded_andMatrixOutputs_andMatrixInput_11_49, decoded_andMatrixOutputs_andMatrixInput_12_49)
node decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_andMatrixOutputs_andMatrixInput_10_49)
node decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_andMatrixOutputs_lo_hi_hi_49, decoded_andMatrixOutputs_lo_hi_lo_49)
node decoded_andMatrixOutputs_lo_49 = cat(decoded_andMatrixOutputs_lo_hi_49, decoded_andMatrixOutputs_lo_lo_49)
node decoded_andMatrixOutputs_hi_lo_lo_49 = cat(decoded_andMatrixOutputs_andMatrixInput_7_49, decoded_andMatrixOutputs_andMatrixInput_8_49)
node decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_andMatrixOutputs_andMatrixInput_5_49, decoded_andMatrixOutputs_andMatrixInput_6_49)
node decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_andMatrixOutputs_hi_lo_hi_49, decoded_andMatrixOutputs_hi_lo_lo_49)
node decoded_andMatrixOutputs_hi_hi_lo_49 = cat(decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_andMatrixOutputs_andMatrixInput_4_49)
node decoded_andMatrixOutputs_hi_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_andMatrixOutputs_andMatrixInput_1_50)
node decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_32, decoded_andMatrixOutputs_andMatrixInput_2_50)
node decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_andMatrixOutputs_hi_hi_hi_49, decoded_andMatrixOutputs_hi_hi_lo_49)
node decoded_andMatrixOutputs_hi_50 = cat(decoded_andMatrixOutputs_hi_hi_49, decoded_andMatrixOutputs_hi_lo_49)
node _decoded_andMatrixOutputs_T_50 = cat(decoded_andMatrixOutputs_hi_50, decoded_andMatrixOutputs_lo_49)
node decoded_andMatrixOutputs_43_2_1 = andr(_decoded_andMatrixOutputs_T_50)
node decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_andMatrixOutputs_andMatrixInput_12_50, decoded_andMatrixOutputs_andMatrixInput_13_50)
node decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_andMatrixOutputs_lo_lo_hi_50, decoded_andMatrixOutputs_andMatrixInput_14_50)
node decoded_andMatrixOutputs_lo_hi_lo_50 = cat(decoded_andMatrixOutputs_andMatrixInput_10_50, decoded_andMatrixOutputs_andMatrixInput_11_50)
node decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_andMatrixOutputs_andMatrixInput_8_50, decoded_andMatrixOutputs_andMatrixInput_9_50)
node decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_andMatrixOutputs_lo_hi_hi_50, decoded_andMatrixOutputs_lo_hi_lo_50)
node decoded_andMatrixOutputs_lo_50 = cat(decoded_andMatrixOutputs_lo_hi_50, decoded_andMatrixOutputs_lo_lo_50)
node decoded_andMatrixOutputs_hi_lo_lo_50 = cat(decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_andMatrixOutputs_andMatrixInput_7_50)
node decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_andMatrixOutputs_andMatrixInput_4_50, decoded_andMatrixOutputs_andMatrixInput_5_50)
node decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_andMatrixOutputs_hi_lo_hi_50, decoded_andMatrixOutputs_hi_lo_lo_50)
node decoded_andMatrixOutputs_hi_hi_lo_50 = cat(decoded_andMatrixOutputs_andMatrixInput_2_51, decoded_andMatrixOutputs_andMatrixInput_3_50)
node decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_andMatrixOutputs_andMatrixInput_1_51)
node decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_andMatrixOutputs_hi_hi_hi_50, decoded_andMatrixOutputs_hi_hi_lo_50)
node decoded_andMatrixOutputs_hi_51 = cat(decoded_andMatrixOutputs_hi_hi_50, decoded_andMatrixOutputs_hi_lo_50)
node _decoded_andMatrixOutputs_T_51 = cat(decoded_andMatrixOutputs_hi_51, decoded_andMatrixOutputs_lo_50)
node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_51)
node decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_38 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_33 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_38 = cat(decoded_andMatrixOutputs_andMatrixInput_15_38, decoded_andMatrixOutputs_andMatrixInput_16_33)
node decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_andMatrixOutputs_andMatrixInput_13_51, decoded_andMatrixOutputs_andMatrixInput_14_51)
node decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_andMatrixOutputs_lo_lo_hi_51, decoded_andMatrixOutputs_lo_lo_lo_38)
node decoded_andMatrixOutputs_lo_hi_lo_51 = cat(decoded_andMatrixOutputs_andMatrixInput_11_51, decoded_andMatrixOutputs_andMatrixInput_12_51)
node decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_andMatrixOutputs_andMatrixInput_10_51)
node decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_andMatrixOutputs_lo_hi_hi_51, decoded_andMatrixOutputs_lo_hi_lo_51)
node decoded_andMatrixOutputs_lo_51 = cat(decoded_andMatrixOutputs_lo_hi_51, decoded_andMatrixOutputs_lo_lo_51)
node decoded_andMatrixOutputs_hi_lo_lo_51 = cat(decoded_andMatrixOutputs_andMatrixInput_7_51, decoded_andMatrixOutputs_andMatrixInput_8_51)
node decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_andMatrixOutputs_andMatrixInput_5_51, decoded_andMatrixOutputs_andMatrixInput_6_51)
node decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_andMatrixOutputs_hi_lo_hi_51, decoded_andMatrixOutputs_hi_lo_lo_51)
node decoded_andMatrixOutputs_hi_hi_lo_51 = cat(decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_andMatrixOutputs_andMatrixInput_4_51)
node decoded_andMatrixOutputs_hi_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_andMatrixOutputs_andMatrixInput_1_52)
node decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_33, decoded_andMatrixOutputs_andMatrixInput_2_52)
node decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_andMatrixOutputs_hi_hi_hi_51, decoded_andMatrixOutputs_hi_hi_lo_51)
node decoded_andMatrixOutputs_hi_52 = cat(decoded_andMatrixOutputs_hi_hi_51, decoded_andMatrixOutputs_hi_lo_51)
node _decoded_andMatrixOutputs_T_52 = cat(decoded_andMatrixOutputs_hi_52, decoded_andMatrixOutputs_lo_51)
node decoded_andMatrixOutputs_38_2_1 = andr(_decoded_andMatrixOutputs_T_52)
node decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_andMatrixOutputs_andMatrixInput_12_52, decoded_andMatrixOutputs_andMatrixInput_13_52)
node decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_andMatrixOutputs_lo_lo_hi_52, decoded_andMatrixOutputs_andMatrixInput_14_52)
node decoded_andMatrixOutputs_lo_hi_lo_52 = cat(decoded_andMatrixOutputs_andMatrixInput_10_52, decoded_andMatrixOutputs_andMatrixInput_11_52)
node decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_andMatrixOutputs_andMatrixInput_8_52, decoded_andMatrixOutputs_andMatrixInput_9_52)
node decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_andMatrixOutputs_lo_hi_hi_52, decoded_andMatrixOutputs_lo_hi_lo_52)
node decoded_andMatrixOutputs_lo_52 = cat(decoded_andMatrixOutputs_lo_hi_52, decoded_andMatrixOutputs_lo_lo_52)
node decoded_andMatrixOutputs_hi_lo_lo_52 = cat(decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_andMatrixOutputs_andMatrixInput_7_52)
node decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_andMatrixOutputs_andMatrixInput_4_52, decoded_andMatrixOutputs_andMatrixInput_5_52)
node decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_andMatrixOutputs_hi_lo_hi_52, decoded_andMatrixOutputs_hi_lo_lo_52)
node decoded_andMatrixOutputs_hi_hi_lo_52 = cat(decoded_andMatrixOutputs_andMatrixInput_2_53, decoded_andMatrixOutputs_andMatrixInput_3_52)
node decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_andMatrixOutputs_andMatrixInput_1_53)
node decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_andMatrixOutputs_hi_hi_hi_52, decoded_andMatrixOutputs_hi_hi_lo_52)
node decoded_andMatrixOutputs_hi_53 = cat(decoded_andMatrixOutputs_hi_hi_52, decoded_andMatrixOutputs_hi_lo_52)
node _decoded_andMatrixOutputs_T_53 = cat(decoded_andMatrixOutputs_hi_53, decoded_andMatrixOutputs_lo_52)
node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_53)
node decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_39 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_34 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_39 = cat(decoded_andMatrixOutputs_andMatrixInput_15_39, decoded_andMatrixOutputs_andMatrixInput_16_34)
node decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_andMatrixOutputs_andMatrixInput_13_53, decoded_andMatrixOutputs_andMatrixInput_14_53)
node decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_andMatrixOutputs_lo_lo_hi_53, decoded_andMatrixOutputs_lo_lo_lo_39)
node decoded_andMatrixOutputs_lo_hi_lo_53 = cat(decoded_andMatrixOutputs_andMatrixInput_11_53, decoded_andMatrixOutputs_andMatrixInput_12_53)
node decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_andMatrixOutputs_andMatrixInput_9_53, decoded_andMatrixOutputs_andMatrixInput_10_53)
node decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_andMatrixOutputs_lo_hi_hi_53, decoded_andMatrixOutputs_lo_hi_lo_53)
node decoded_andMatrixOutputs_lo_53 = cat(decoded_andMatrixOutputs_lo_hi_53, decoded_andMatrixOutputs_lo_lo_53)
node decoded_andMatrixOutputs_hi_lo_lo_53 = cat(decoded_andMatrixOutputs_andMatrixInput_7_53, decoded_andMatrixOutputs_andMatrixInput_8_53)
node decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_andMatrixOutputs_andMatrixInput_5_53, decoded_andMatrixOutputs_andMatrixInput_6_53)
node decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_andMatrixOutputs_hi_lo_hi_53, decoded_andMatrixOutputs_hi_lo_lo_53)
node decoded_andMatrixOutputs_hi_hi_lo_53 = cat(decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_andMatrixOutputs_andMatrixInput_4_53)
node decoded_andMatrixOutputs_hi_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_andMatrixOutputs_andMatrixInput_1_54)
node decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_34, decoded_andMatrixOutputs_andMatrixInput_2_54)
node decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_andMatrixOutputs_hi_hi_hi_53, decoded_andMatrixOutputs_hi_hi_lo_53)
node decoded_andMatrixOutputs_hi_54 = cat(decoded_andMatrixOutputs_hi_hi_53, decoded_andMatrixOutputs_hi_lo_53)
node _decoded_andMatrixOutputs_T_54 = cat(decoded_andMatrixOutputs_hi_54, decoded_andMatrixOutputs_lo_53)
node decoded_andMatrixOutputs_20_2_1 = andr(_decoded_andMatrixOutputs_T_54)
node decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_andMatrixOutputs_andMatrixInput_12_54, decoded_andMatrixOutputs_andMatrixInput_13_54)
node decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_andMatrixOutputs_lo_lo_hi_54, decoded_andMatrixOutputs_andMatrixInput_14_54)
node decoded_andMatrixOutputs_lo_hi_lo_54 = cat(decoded_andMatrixOutputs_andMatrixInput_10_54, decoded_andMatrixOutputs_andMatrixInput_11_54)
node decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_andMatrixOutputs_andMatrixInput_8_54, decoded_andMatrixOutputs_andMatrixInput_9_54)
node decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_andMatrixOutputs_lo_hi_hi_54, decoded_andMatrixOutputs_lo_hi_lo_54)
node decoded_andMatrixOutputs_lo_54 = cat(decoded_andMatrixOutputs_lo_hi_54, decoded_andMatrixOutputs_lo_lo_54)
node decoded_andMatrixOutputs_hi_lo_lo_54 = cat(decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_andMatrixOutputs_andMatrixInput_7_54)
node decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_andMatrixOutputs_andMatrixInput_4_54, decoded_andMatrixOutputs_andMatrixInput_5_54)
node decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_andMatrixOutputs_hi_lo_hi_54, decoded_andMatrixOutputs_hi_lo_lo_54)
node decoded_andMatrixOutputs_hi_hi_lo_54 = cat(decoded_andMatrixOutputs_andMatrixInput_2_55, decoded_andMatrixOutputs_andMatrixInput_3_54)
node decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_andMatrixOutputs_andMatrixInput_1_55)
node decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_andMatrixOutputs_hi_hi_hi_54, decoded_andMatrixOutputs_hi_hi_lo_54)
node decoded_andMatrixOutputs_hi_55 = cat(decoded_andMatrixOutputs_hi_hi_54, decoded_andMatrixOutputs_hi_lo_54)
node _decoded_andMatrixOutputs_T_55 = cat(decoded_andMatrixOutputs_hi_55, decoded_andMatrixOutputs_lo_54)
node decoded_andMatrixOutputs_9_2_1 = andr(_decoded_andMatrixOutputs_T_55)
node decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_40 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_35 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_40 = cat(decoded_andMatrixOutputs_andMatrixInput_15_40, decoded_andMatrixOutputs_andMatrixInput_16_35)
node decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_andMatrixOutputs_andMatrixInput_13_55, decoded_andMatrixOutputs_andMatrixInput_14_55)
node decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_andMatrixOutputs_lo_lo_hi_55, decoded_andMatrixOutputs_lo_lo_lo_40)
node decoded_andMatrixOutputs_lo_hi_lo_55 = cat(decoded_andMatrixOutputs_andMatrixInput_11_55, decoded_andMatrixOutputs_andMatrixInput_12_55)
node decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_andMatrixOutputs_andMatrixInput_10_55)
node decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_andMatrixOutputs_lo_hi_hi_55, decoded_andMatrixOutputs_lo_hi_lo_55)
node decoded_andMatrixOutputs_lo_55 = cat(decoded_andMatrixOutputs_lo_hi_55, decoded_andMatrixOutputs_lo_lo_55)
node decoded_andMatrixOutputs_hi_lo_lo_55 = cat(decoded_andMatrixOutputs_andMatrixInput_7_55, decoded_andMatrixOutputs_andMatrixInput_8_55)
node decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_andMatrixOutputs_andMatrixInput_6_55)
node decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_andMatrixOutputs_hi_lo_hi_55, decoded_andMatrixOutputs_hi_lo_lo_55)
node decoded_andMatrixOutputs_hi_hi_lo_55 = cat(decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_andMatrixOutputs_andMatrixInput_4_55)
node decoded_andMatrixOutputs_hi_hi_hi_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_andMatrixOutputs_andMatrixInput_1_56)
node decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_35, decoded_andMatrixOutputs_andMatrixInput_2_56)
node decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_andMatrixOutputs_hi_hi_hi_55, decoded_andMatrixOutputs_hi_hi_lo_55)
node decoded_andMatrixOutputs_hi_56 = cat(decoded_andMatrixOutputs_hi_hi_55, decoded_andMatrixOutputs_hi_lo_55)
node _decoded_andMatrixOutputs_T_56 = cat(decoded_andMatrixOutputs_hi_56, decoded_andMatrixOutputs_lo_55)
node decoded_andMatrixOutputs_37_2_1 = andr(_decoded_andMatrixOutputs_T_56)
node decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_andMatrixOutputs_andMatrixInput_12_56, decoded_andMatrixOutputs_andMatrixInput_13_56)
node decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_andMatrixOutputs_lo_lo_hi_56, decoded_andMatrixOutputs_andMatrixInput_14_56)
node decoded_andMatrixOutputs_lo_hi_lo_56 = cat(decoded_andMatrixOutputs_andMatrixInput_10_56, decoded_andMatrixOutputs_andMatrixInput_11_56)
node decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_andMatrixOutputs_andMatrixInput_8_56, decoded_andMatrixOutputs_andMatrixInput_9_56)
node decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_andMatrixOutputs_lo_hi_hi_56, decoded_andMatrixOutputs_lo_hi_lo_56)
node decoded_andMatrixOutputs_lo_56 = cat(decoded_andMatrixOutputs_lo_hi_56, decoded_andMatrixOutputs_lo_lo_56)
node decoded_andMatrixOutputs_hi_lo_lo_56 = cat(decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_andMatrixOutputs_andMatrixInput_7_56)
node decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_andMatrixOutputs_andMatrixInput_4_56, decoded_andMatrixOutputs_andMatrixInput_5_56)
node decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_andMatrixOutputs_hi_lo_hi_56, decoded_andMatrixOutputs_hi_lo_lo_56)
node decoded_andMatrixOutputs_hi_hi_lo_56 = cat(decoded_andMatrixOutputs_andMatrixInput_2_57, decoded_andMatrixOutputs_andMatrixInput_3_56)
node decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_andMatrixOutputs_andMatrixInput_1_57)
node decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_andMatrixOutputs_hi_hi_hi_56, decoded_andMatrixOutputs_hi_hi_lo_56)
node decoded_andMatrixOutputs_hi_57 = cat(decoded_andMatrixOutputs_hi_hi_56, decoded_andMatrixOutputs_hi_lo_56)
node _decoded_andMatrixOutputs_T_57 = cat(decoded_andMatrixOutputs_hi_57, decoded_andMatrixOutputs_lo_56)
node decoded_andMatrixOutputs_55_2 = andr(_decoded_andMatrixOutputs_T_57)
node decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_41 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_36 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_41 = cat(decoded_andMatrixOutputs_andMatrixInput_15_41, decoded_andMatrixOutputs_andMatrixInput_16_36)
node decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_andMatrixOutputs_andMatrixInput_13_57, decoded_andMatrixOutputs_andMatrixInput_14_57)
node decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_andMatrixOutputs_lo_lo_hi_57, decoded_andMatrixOutputs_lo_lo_lo_41)
node decoded_andMatrixOutputs_lo_hi_lo_57 = cat(decoded_andMatrixOutputs_andMatrixInput_11_57, decoded_andMatrixOutputs_andMatrixInput_12_57)
node decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_andMatrixOutputs_andMatrixInput_10_57)
node decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_andMatrixOutputs_lo_hi_hi_57, decoded_andMatrixOutputs_lo_hi_lo_57)
node decoded_andMatrixOutputs_lo_57 = cat(decoded_andMatrixOutputs_lo_hi_57, decoded_andMatrixOutputs_lo_lo_57)
node decoded_andMatrixOutputs_hi_lo_lo_57 = cat(decoded_andMatrixOutputs_andMatrixInput_7_57, decoded_andMatrixOutputs_andMatrixInput_8_57)
node decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_andMatrixOutputs_andMatrixInput_5_57, decoded_andMatrixOutputs_andMatrixInput_6_57)
node decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_andMatrixOutputs_hi_lo_hi_57, decoded_andMatrixOutputs_hi_lo_lo_57)
node decoded_andMatrixOutputs_hi_hi_lo_57 = cat(decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_andMatrixOutputs_andMatrixInput_4_57)
node decoded_andMatrixOutputs_hi_hi_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_andMatrixOutputs_andMatrixInput_1_58)
node decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_36, decoded_andMatrixOutputs_andMatrixInput_2_58)
node decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_andMatrixOutputs_hi_hi_hi_57, decoded_andMatrixOutputs_hi_hi_lo_57)
node decoded_andMatrixOutputs_hi_58 = cat(decoded_andMatrixOutputs_hi_hi_57, decoded_andMatrixOutputs_hi_lo_57)
node _decoded_andMatrixOutputs_T_58 = cat(decoded_andMatrixOutputs_hi_58, decoded_andMatrixOutputs_lo_57)
node decoded_andMatrixOutputs_13_2_1 = andr(_decoded_andMatrixOutputs_T_58)
node decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_andMatrixOutputs_andMatrixInput_12_58, decoded_andMatrixOutputs_andMatrixInput_13_58)
node decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_andMatrixOutputs_lo_lo_hi_58, decoded_andMatrixOutputs_andMatrixInput_14_58)
node decoded_andMatrixOutputs_lo_hi_lo_58 = cat(decoded_andMatrixOutputs_andMatrixInput_10_58, decoded_andMatrixOutputs_andMatrixInput_11_58)
node decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_andMatrixOutputs_andMatrixInput_8_58, decoded_andMatrixOutputs_andMatrixInput_9_58)
node decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_andMatrixOutputs_lo_hi_hi_58, decoded_andMatrixOutputs_lo_hi_lo_58)
node decoded_andMatrixOutputs_lo_58 = cat(decoded_andMatrixOutputs_lo_hi_58, decoded_andMatrixOutputs_lo_lo_58)
node decoded_andMatrixOutputs_hi_lo_lo_58 = cat(decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_andMatrixOutputs_andMatrixInput_7_58)
node decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_andMatrixOutputs_andMatrixInput_4_58, decoded_andMatrixOutputs_andMatrixInput_5_58)
node decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_andMatrixOutputs_hi_lo_hi_58, decoded_andMatrixOutputs_hi_lo_lo_58)
node decoded_andMatrixOutputs_hi_hi_lo_58 = cat(decoded_andMatrixOutputs_andMatrixInput_2_59, decoded_andMatrixOutputs_andMatrixInput_3_58)
node decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_andMatrixOutputs_andMatrixInput_1_59)
node decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_andMatrixOutputs_hi_hi_hi_58, decoded_andMatrixOutputs_hi_hi_lo_58)
node decoded_andMatrixOutputs_hi_59 = cat(decoded_andMatrixOutputs_hi_hi_58, decoded_andMatrixOutputs_hi_lo_58)
node _decoded_andMatrixOutputs_T_59 = cat(decoded_andMatrixOutputs_hi_59, decoded_andMatrixOutputs_lo_58)
node decoded_andMatrixOutputs_29_2_1 = andr(_decoded_andMatrixOutputs_T_59)
node decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_andMatrixOutputs_andMatrixInput_12_59, decoded_andMatrixOutputs_andMatrixInput_13_59)
node decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_andMatrixOutputs_lo_lo_hi_59, decoded_andMatrixOutputs_andMatrixInput_14_59)
node decoded_andMatrixOutputs_lo_hi_lo_59 = cat(decoded_andMatrixOutputs_andMatrixInput_10_59, decoded_andMatrixOutputs_andMatrixInput_11_59)
node decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_andMatrixOutputs_andMatrixInput_8_59, decoded_andMatrixOutputs_andMatrixInput_9_59)
node decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_andMatrixOutputs_lo_hi_hi_59, decoded_andMatrixOutputs_lo_hi_lo_59)
node decoded_andMatrixOutputs_lo_59 = cat(decoded_andMatrixOutputs_lo_hi_59, decoded_andMatrixOutputs_lo_lo_59)
node decoded_andMatrixOutputs_hi_lo_lo_59 = cat(decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_andMatrixOutputs_andMatrixInput_7_59)
node decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_andMatrixOutputs_andMatrixInput_4_59, decoded_andMatrixOutputs_andMatrixInput_5_59)
node decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_andMatrixOutputs_hi_lo_hi_59, decoded_andMatrixOutputs_hi_lo_lo_59)
node decoded_andMatrixOutputs_hi_hi_lo_59 = cat(decoded_andMatrixOutputs_andMatrixInput_2_60, decoded_andMatrixOutputs_andMatrixInput_3_59)
node decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_andMatrixOutputs_andMatrixInput_1_60)
node decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_andMatrixOutputs_hi_hi_hi_59, decoded_andMatrixOutputs_hi_hi_lo_59)
node decoded_andMatrixOutputs_hi_60 = cat(decoded_andMatrixOutputs_hi_hi_59, decoded_andMatrixOutputs_hi_lo_59)
node _decoded_andMatrixOutputs_T_60 = cat(decoded_andMatrixOutputs_hi_60, decoded_andMatrixOutputs_lo_59)
node decoded_andMatrixOutputs_46_2 = andr(_decoded_andMatrixOutputs_T_60)
node decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_60 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_42 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_37 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_42 = cat(decoded_andMatrixOutputs_andMatrixInput_15_42, decoded_andMatrixOutputs_andMatrixInput_16_37)
node decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_andMatrixOutputs_andMatrixInput_13_60, decoded_andMatrixOutputs_andMatrixInput_14_60)
node decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_andMatrixOutputs_lo_lo_hi_60, decoded_andMatrixOutputs_lo_lo_lo_42)
node decoded_andMatrixOutputs_lo_hi_lo_60 = cat(decoded_andMatrixOutputs_andMatrixInput_11_60, decoded_andMatrixOutputs_andMatrixInput_12_60)
node decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_andMatrixOutputs_andMatrixInput_10_60)
node decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_andMatrixOutputs_lo_hi_hi_60, decoded_andMatrixOutputs_lo_hi_lo_60)
node decoded_andMatrixOutputs_lo_60 = cat(decoded_andMatrixOutputs_lo_hi_60, decoded_andMatrixOutputs_lo_lo_60)
node decoded_andMatrixOutputs_hi_lo_lo_60 = cat(decoded_andMatrixOutputs_andMatrixInput_7_60, decoded_andMatrixOutputs_andMatrixInput_8_60)
node decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_andMatrixOutputs_andMatrixInput_5_60, decoded_andMatrixOutputs_andMatrixInput_6_60)
node decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_andMatrixOutputs_hi_lo_hi_60, decoded_andMatrixOutputs_hi_lo_lo_60)
node decoded_andMatrixOutputs_hi_hi_lo_60 = cat(decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_andMatrixOutputs_andMatrixInput_4_60)
node decoded_andMatrixOutputs_hi_hi_hi_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_andMatrixOutputs_andMatrixInput_1_61)
node decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_37, decoded_andMatrixOutputs_andMatrixInput_2_61)
node decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_andMatrixOutputs_hi_hi_hi_60, decoded_andMatrixOutputs_hi_hi_lo_60)
node decoded_andMatrixOutputs_hi_61 = cat(decoded_andMatrixOutputs_hi_hi_60, decoded_andMatrixOutputs_hi_lo_60)
node _decoded_andMatrixOutputs_T_61 = cat(decoded_andMatrixOutputs_hi_61, decoded_andMatrixOutputs_lo_60)
node decoded_andMatrixOutputs_50_2 = andr(_decoded_andMatrixOutputs_T_61)
node decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_61 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_andMatrixOutputs_andMatrixInput_12_61, decoded_andMatrixOutputs_andMatrixInput_13_61)
node decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_andMatrixOutputs_lo_lo_hi_61, decoded_andMatrixOutputs_andMatrixInput_14_61)
node decoded_andMatrixOutputs_lo_hi_lo_61 = cat(decoded_andMatrixOutputs_andMatrixInput_10_61, decoded_andMatrixOutputs_andMatrixInput_11_61)
node decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_andMatrixOutputs_andMatrixInput_8_61, decoded_andMatrixOutputs_andMatrixInput_9_61)
node decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_andMatrixOutputs_lo_hi_hi_61, decoded_andMatrixOutputs_lo_hi_lo_61)
node decoded_andMatrixOutputs_lo_61 = cat(decoded_andMatrixOutputs_lo_hi_61, decoded_andMatrixOutputs_lo_lo_61)
node decoded_andMatrixOutputs_hi_lo_lo_61 = cat(decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_andMatrixOutputs_andMatrixInput_7_61)
node decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_andMatrixOutputs_andMatrixInput_4_61, decoded_andMatrixOutputs_andMatrixInput_5_61)
node decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_andMatrixOutputs_hi_lo_hi_61, decoded_andMatrixOutputs_hi_lo_lo_61)
node decoded_andMatrixOutputs_hi_hi_lo_61 = cat(decoded_andMatrixOutputs_andMatrixInput_2_62, decoded_andMatrixOutputs_andMatrixInput_3_61)
node decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_andMatrixOutputs_andMatrixInput_1_62)
node decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_andMatrixOutputs_hi_hi_hi_61, decoded_andMatrixOutputs_hi_hi_lo_61)
node decoded_andMatrixOutputs_hi_62 = cat(decoded_andMatrixOutputs_hi_hi_61, decoded_andMatrixOutputs_hi_lo_61)
node _decoded_andMatrixOutputs_T_62 = cat(decoded_andMatrixOutputs_hi_62, decoded_andMatrixOutputs_lo_61)
node decoded_andMatrixOutputs_8_2_1 = andr(_decoded_andMatrixOutputs_T_62)
node decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_62 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_andMatrixOutputs_andMatrixInput_12_62, decoded_andMatrixOutputs_andMatrixInput_13_62)
node decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_andMatrixOutputs_lo_lo_hi_62, decoded_andMatrixOutputs_andMatrixInput_14_62)
node decoded_andMatrixOutputs_lo_hi_lo_62 = cat(decoded_andMatrixOutputs_andMatrixInput_10_62, decoded_andMatrixOutputs_andMatrixInput_11_62)
node decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_andMatrixOutputs_andMatrixInput_8_62, decoded_andMatrixOutputs_andMatrixInput_9_62)
node decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_andMatrixOutputs_lo_hi_hi_62, decoded_andMatrixOutputs_lo_hi_lo_62)
node decoded_andMatrixOutputs_lo_62 = cat(decoded_andMatrixOutputs_lo_hi_62, decoded_andMatrixOutputs_lo_lo_62)
node decoded_andMatrixOutputs_hi_lo_lo_62 = cat(decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_andMatrixOutputs_andMatrixInput_7_62)
node decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_andMatrixOutputs_andMatrixInput_4_62, decoded_andMatrixOutputs_andMatrixInput_5_62)
node decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_andMatrixOutputs_hi_lo_hi_62, decoded_andMatrixOutputs_hi_lo_lo_62)
node decoded_andMatrixOutputs_hi_hi_lo_62 = cat(decoded_andMatrixOutputs_andMatrixInput_2_63, decoded_andMatrixOutputs_andMatrixInput_3_62)
node decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_andMatrixOutputs_andMatrixInput_1_63)
node decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_andMatrixOutputs_hi_hi_hi_62, decoded_andMatrixOutputs_hi_hi_lo_62)
node decoded_andMatrixOutputs_hi_63 = cat(decoded_andMatrixOutputs_hi_hi_62, decoded_andMatrixOutputs_hi_lo_62)
node _decoded_andMatrixOutputs_T_63 = cat(decoded_andMatrixOutputs_hi_63, decoded_andMatrixOutputs_lo_62)
node decoded_andMatrixOutputs_49_2 = andr(_decoded_andMatrixOutputs_T_63)
node decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_63 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_43 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_38 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_43 = cat(decoded_andMatrixOutputs_andMatrixInput_15_43, decoded_andMatrixOutputs_andMatrixInput_16_38)
node decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_andMatrixOutputs_andMatrixInput_13_63, decoded_andMatrixOutputs_andMatrixInput_14_63)
node decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_andMatrixOutputs_lo_lo_hi_63, decoded_andMatrixOutputs_lo_lo_lo_43)
node decoded_andMatrixOutputs_lo_hi_lo_63 = cat(decoded_andMatrixOutputs_andMatrixInput_11_63, decoded_andMatrixOutputs_andMatrixInput_12_63)
node decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_andMatrixOutputs_andMatrixInput_10_63)
node decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_andMatrixOutputs_lo_hi_hi_63, decoded_andMatrixOutputs_lo_hi_lo_63)
node decoded_andMatrixOutputs_lo_63 = cat(decoded_andMatrixOutputs_lo_hi_63, decoded_andMatrixOutputs_lo_lo_63)
node decoded_andMatrixOutputs_hi_lo_lo_63 = cat(decoded_andMatrixOutputs_andMatrixInput_7_63, decoded_andMatrixOutputs_andMatrixInput_8_63)
node decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_andMatrixOutputs_andMatrixInput_5_63, decoded_andMatrixOutputs_andMatrixInput_6_63)
node decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_andMatrixOutputs_hi_lo_hi_63, decoded_andMatrixOutputs_hi_lo_lo_63)
node decoded_andMatrixOutputs_hi_hi_lo_63 = cat(decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_andMatrixOutputs_andMatrixInput_4_63)
node decoded_andMatrixOutputs_hi_hi_hi_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_andMatrixOutputs_andMatrixInput_1_64)
node decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_38, decoded_andMatrixOutputs_andMatrixInput_2_64)
node decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_andMatrixOutputs_hi_hi_hi_63, decoded_andMatrixOutputs_hi_hi_lo_63)
node decoded_andMatrixOutputs_hi_64 = cat(decoded_andMatrixOutputs_hi_hi_63, decoded_andMatrixOutputs_hi_lo_63)
node _decoded_andMatrixOutputs_T_64 = cat(decoded_andMatrixOutputs_hi_64, decoded_andMatrixOutputs_lo_63)
node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_64)
node decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_64 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_44 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_39 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_44 = cat(decoded_andMatrixOutputs_andMatrixInput_15_44, decoded_andMatrixOutputs_andMatrixInput_16_39)
node decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_andMatrixOutputs_andMatrixInput_13_64, decoded_andMatrixOutputs_andMatrixInput_14_64)
node decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_andMatrixOutputs_lo_lo_hi_64, decoded_andMatrixOutputs_lo_lo_lo_44)
node decoded_andMatrixOutputs_lo_hi_lo_64 = cat(decoded_andMatrixOutputs_andMatrixInput_11_64, decoded_andMatrixOutputs_andMatrixInput_12_64)
node decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_andMatrixOutputs_andMatrixInput_10_64)
node decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_andMatrixOutputs_lo_hi_hi_64, decoded_andMatrixOutputs_lo_hi_lo_64)
node decoded_andMatrixOutputs_lo_64 = cat(decoded_andMatrixOutputs_lo_hi_64, decoded_andMatrixOutputs_lo_lo_64)
node decoded_andMatrixOutputs_hi_lo_lo_64 = cat(decoded_andMatrixOutputs_andMatrixInput_7_64, decoded_andMatrixOutputs_andMatrixInput_8_64)
node decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_andMatrixOutputs_andMatrixInput_5_64, decoded_andMatrixOutputs_andMatrixInput_6_64)
node decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_andMatrixOutputs_hi_lo_hi_64, decoded_andMatrixOutputs_hi_lo_lo_64)
node decoded_andMatrixOutputs_hi_hi_lo_64 = cat(decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_andMatrixOutputs_andMatrixInput_4_64)
node decoded_andMatrixOutputs_hi_hi_hi_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_andMatrixOutputs_andMatrixInput_1_65)
node decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_39, decoded_andMatrixOutputs_andMatrixInput_2_65)
node decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_andMatrixOutputs_hi_hi_hi_64, decoded_andMatrixOutputs_hi_hi_lo_64)
node decoded_andMatrixOutputs_hi_65 = cat(decoded_andMatrixOutputs_hi_hi_64, decoded_andMatrixOutputs_hi_lo_64)
node _decoded_andMatrixOutputs_T_65 = cat(decoded_andMatrixOutputs_hi_65, decoded_andMatrixOutputs_lo_64)
node decoded_andMatrixOutputs_15_2_1 = andr(_decoded_andMatrixOutputs_T_65)
node decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_65 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_45 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_40 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_45 = cat(decoded_andMatrixOutputs_andMatrixInput_15_45, decoded_andMatrixOutputs_andMatrixInput_16_40)
node decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_andMatrixOutputs_andMatrixInput_13_65, decoded_andMatrixOutputs_andMatrixInput_14_65)
node decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_andMatrixOutputs_lo_lo_hi_65, decoded_andMatrixOutputs_lo_lo_lo_45)
node decoded_andMatrixOutputs_lo_hi_lo_65 = cat(decoded_andMatrixOutputs_andMatrixInput_11_65, decoded_andMatrixOutputs_andMatrixInput_12_65)
node decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_andMatrixOutputs_andMatrixInput_10_65)
node decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_andMatrixOutputs_lo_hi_hi_65, decoded_andMatrixOutputs_lo_hi_lo_65)
node decoded_andMatrixOutputs_lo_65 = cat(decoded_andMatrixOutputs_lo_hi_65, decoded_andMatrixOutputs_lo_lo_65)
node decoded_andMatrixOutputs_hi_lo_lo_65 = cat(decoded_andMatrixOutputs_andMatrixInput_7_65, decoded_andMatrixOutputs_andMatrixInput_8_65)
node decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_andMatrixOutputs_andMatrixInput_5_65, decoded_andMatrixOutputs_andMatrixInput_6_65)
node decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_andMatrixOutputs_hi_lo_hi_65, decoded_andMatrixOutputs_hi_lo_lo_65)
node decoded_andMatrixOutputs_hi_hi_lo_65 = cat(decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_andMatrixOutputs_andMatrixInput_4_65)
node decoded_andMatrixOutputs_hi_hi_hi_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_andMatrixOutputs_andMatrixInput_1_66)
node decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_40, decoded_andMatrixOutputs_andMatrixInput_2_66)
node decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_andMatrixOutputs_hi_hi_hi_65, decoded_andMatrixOutputs_hi_hi_lo_65)
node decoded_andMatrixOutputs_hi_66 = cat(decoded_andMatrixOutputs_hi_hi_65, decoded_andMatrixOutputs_hi_lo_65)
node _decoded_andMatrixOutputs_T_66 = cat(decoded_andMatrixOutputs_hi_66, decoded_andMatrixOutputs_lo_65)
node decoded_andMatrixOutputs_16_2_1 = andr(_decoded_andMatrixOutputs_T_66)
node decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_66 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_46 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_41 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_46 = cat(decoded_andMatrixOutputs_andMatrixInput_15_46, decoded_andMatrixOutputs_andMatrixInput_16_41)
node decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_andMatrixOutputs_andMatrixInput_13_66, decoded_andMatrixOutputs_andMatrixInput_14_66)
node decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_andMatrixOutputs_lo_lo_hi_66, decoded_andMatrixOutputs_lo_lo_lo_46)
node decoded_andMatrixOutputs_lo_hi_lo_66 = cat(decoded_andMatrixOutputs_andMatrixInput_11_66, decoded_andMatrixOutputs_andMatrixInput_12_66)
node decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_andMatrixOutputs_andMatrixInput_10_66)
node decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_andMatrixOutputs_lo_hi_hi_66, decoded_andMatrixOutputs_lo_hi_lo_66)
node decoded_andMatrixOutputs_lo_66 = cat(decoded_andMatrixOutputs_lo_hi_66, decoded_andMatrixOutputs_lo_lo_66)
node decoded_andMatrixOutputs_hi_lo_lo_66 = cat(decoded_andMatrixOutputs_andMatrixInput_7_66, decoded_andMatrixOutputs_andMatrixInput_8_66)
node decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_andMatrixOutputs_andMatrixInput_5_66, decoded_andMatrixOutputs_andMatrixInput_6_66)
node decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_andMatrixOutputs_hi_lo_hi_66, decoded_andMatrixOutputs_hi_lo_lo_66)
node decoded_andMatrixOutputs_hi_hi_lo_66 = cat(decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_andMatrixOutputs_andMatrixInput_4_66)
node decoded_andMatrixOutputs_hi_hi_hi_hi_41 = cat(decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_andMatrixOutputs_andMatrixInput_1_67)
node decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_41, decoded_andMatrixOutputs_andMatrixInput_2_67)
node decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_andMatrixOutputs_hi_hi_hi_66, decoded_andMatrixOutputs_hi_hi_lo_66)
node decoded_andMatrixOutputs_hi_67 = cat(decoded_andMatrixOutputs_hi_hi_66, decoded_andMatrixOutputs_hi_lo_66)
node _decoded_andMatrixOutputs_T_67 = cat(decoded_andMatrixOutputs_hi_67, decoded_andMatrixOutputs_lo_66)
node decoded_andMatrixOutputs_33_2_1 = andr(_decoded_andMatrixOutputs_T_67)
node decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_67 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_andMatrixOutputs_andMatrixInput_12_67, decoded_andMatrixOutputs_andMatrixInput_13_67)
node decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_andMatrixOutputs_lo_lo_hi_67, decoded_andMatrixOutputs_andMatrixInput_14_67)
node decoded_andMatrixOutputs_lo_hi_lo_67 = cat(decoded_andMatrixOutputs_andMatrixInput_10_67, decoded_andMatrixOutputs_andMatrixInput_11_67)
node decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_andMatrixOutputs_andMatrixInput_8_67, decoded_andMatrixOutputs_andMatrixInput_9_67)
node decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_andMatrixOutputs_lo_hi_hi_67, decoded_andMatrixOutputs_lo_hi_lo_67)
node decoded_andMatrixOutputs_lo_67 = cat(decoded_andMatrixOutputs_lo_hi_67, decoded_andMatrixOutputs_lo_lo_67)
node decoded_andMatrixOutputs_hi_lo_lo_67 = cat(decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_andMatrixOutputs_andMatrixInput_7_67)
node decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_andMatrixOutputs_andMatrixInput_4_67, decoded_andMatrixOutputs_andMatrixInput_5_67)
node decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_andMatrixOutputs_hi_lo_hi_67, decoded_andMatrixOutputs_hi_lo_lo_67)
node decoded_andMatrixOutputs_hi_hi_lo_67 = cat(decoded_andMatrixOutputs_andMatrixInput_2_68, decoded_andMatrixOutputs_andMatrixInput_3_67)
node decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_andMatrixOutputs_andMatrixInput_1_68)
node decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_andMatrixOutputs_hi_hi_hi_67, decoded_andMatrixOutputs_hi_hi_lo_67)
node decoded_andMatrixOutputs_hi_68 = cat(decoded_andMatrixOutputs_hi_hi_67, decoded_andMatrixOutputs_hi_lo_67)
node _decoded_andMatrixOutputs_T_68 = cat(decoded_andMatrixOutputs_hi_68, decoded_andMatrixOutputs_lo_67)
node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_68)
node decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_68 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_68 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_47 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_42 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_47 = cat(decoded_andMatrixOutputs_andMatrixInput_15_47, decoded_andMatrixOutputs_andMatrixInput_16_42)
node decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_andMatrixOutputs_andMatrixInput_13_68, decoded_andMatrixOutputs_andMatrixInput_14_68)
node decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_andMatrixOutputs_lo_lo_hi_68, decoded_andMatrixOutputs_lo_lo_lo_47)
node decoded_andMatrixOutputs_lo_hi_lo_68 = cat(decoded_andMatrixOutputs_andMatrixInput_11_68, decoded_andMatrixOutputs_andMatrixInput_12_68)
node decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_andMatrixOutputs_andMatrixInput_10_68)
node decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_andMatrixOutputs_lo_hi_hi_68, decoded_andMatrixOutputs_lo_hi_lo_68)
node decoded_andMatrixOutputs_lo_68 = cat(decoded_andMatrixOutputs_lo_hi_68, decoded_andMatrixOutputs_lo_lo_68)
node decoded_andMatrixOutputs_hi_lo_lo_68 = cat(decoded_andMatrixOutputs_andMatrixInput_7_68, decoded_andMatrixOutputs_andMatrixInput_8_68)
node decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_andMatrixOutputs_andMatrixInput_5_68, decoded_andMatrixOutputs_andMatrixInput_6_68)
node decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_andMatrixOutputs_hi_lo_hi_68, decoded_andMatrixOutputs_hi_lo_lo_68)
node decoded_andMatrixOutputs_hi_hi_lo_68 = cat(decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_andMatrixOutputs_andMatrixInput_4_68)
node decoded_andMatrixOutputs_hi_hi_hi_hi_42 = cat(decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_andMatrixOutputs_andMatrixInput_1_69)
node decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_42, decoded_andMatrixOutputs_andMatrixInput_2_69)
node decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_andMatrixOutputs_hi_hi_hi_68, decoded_andMatrixOutputs_hi_hi_lo_68)
node decoded_andMatrixOutputs_hi_69 = cat(decoded_andMatrixOutputs_hi_hi_68, decoded_andMatrixOutputs_hi_lo_68)
node _decoded_andMatrixOutputs_T_69 = cat(decoded_andMatrixOutputs_hi_69, decoded_andMatrixOutputs_lo_68)
node decoded_andMatrixOutputs_53_2 = andr(_decoded_andMatrixOutputs_T_69)
node decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_69 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_69 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_andMatrixOutputs_andMatrixInput_12_69, decoded_andMatrixOutputs_andMatrixInput_13_69)
node decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_andMatrixOutputs_lo_lo_hi_69, decoded_andMatrixOutputs_andMatrixInput_14_69)
node decoded_andMatrixOutputs_lo_hi_lo_69 = cat(decoded_andMatrixOutputs_andMatrixInput_10_69, decoded_andMatrixOutputs_andMatrixInput_11_69)
node decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_andMatrixOutputs_andMatrixInput_8_69, decoded_andMatrixOutputs_andMatrixInput_9_69)
node decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_andMatrixOutputs_lo_hi_hi_69, decoded_andMatrixOutputs_lo_hi_lo_69)
node decoded_andMatrixOutputs_lo_69 = cat(decoded_andMatrixOutputs_lo_hi_69, decoded_andMatrixOutputs_lo_lo_69)
node decoded_andMatrixOutputs_hi_lo_lo_69 = cat(decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_andMatrixOutputs_andMatrixInput_7_69)
node decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_andMatrixOutputs_andMatrixInput_4_69, decoded_andMatrixOutputs_andMatrixInput_5_69)
node decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_andMatrixOutputs_hi_lo_hi_69, decoded_andMatrixOutputs_hi_lo_lo_69)
node decoded_andMatrixOutputs_hi_hi_lo_69 = cat(decoded_andMatrixOutputs_andMatrixInput_2_70, decoded_andMatrixOutputs_andMatrixInput_3_69)
node decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_andMatrixOutputs_andMatrixInput_1_70)
node decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_andMatrixOutputs_hi_hi_hi_69, decoded_andMatrixOutputs_hi_hi_lo_69)
node decoded_andMatrixOutputs_hi_70 = cat(decoded_andMatrixOutputs_hi_hi_69, decoded_andMatrixOutputs_hi_lo_69)
node _decoded_andMatrixOutputs_T_70 = cat(decoded_andMatrixOutputs_hi_70, decoded_andMatrixOutputs_lo_69)
node decoded_andMatrixOutputs_31_2_1 = andr(_decoded_andMatrixOutputs_T_70)
node decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_70 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_70 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_70 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_48 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_43 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_48 = cat(decoded_andMatrixOutputs_andMatrixInput_15_48, decoded_andMatrixOutputs_andMatrixInput_16_43)
node decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_andMatrixOutputs_andMatrixInput_13_70, decoded_andMatrixOutputs_andMatrixInput_14_70)
node decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_andMatrixOutputs_lo_lo_hi_70, decoded_andMatrixOutputs_lo_lo_lo_48)
node decoded_andMatrixOutputs_lo_hi_lo_70 = cat(decoded_andMatrixOutputs_andMatrixInput_11_70, decoded_andMatrixOutputs_andMatrixInput_12_70)
node decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_andMatrixOutputs_andMatrixInput_10_70)
node decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_andMatrixOutputs_lo_hi_hi_70, decoded_andMatrixOutputs_lo_hi_lo_70)
node decoded_andMatrixOutputs_lo_70 = cat(decoded_andMatrixOutputs_lo_hi_70, decoded_andMatrixOutputs_lo_lo_70)
node decoded_andMatrixOutputs_hi_lo_lo_70 = cat(decoded_andMatrixOutputs_andMatrixInput_7_70, decoded_andMatrixOutputs_andMatrixInput_8_70)
node decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_andMatrixOutputs_andMatrixInput_5_70, decoded_andMatrixOutputs_andMatrixInput_6_70)
node decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_andMatrixOutputs_hi_lo_hi_70, decoded_andMatrixOutputs_hi_lo_lo_70)
node decoded_andMatrixOutputs_hi_hi_lo_70 = cat(decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_andMatrixOutputs_andMatrixInput_4_70)
node decoded_andMatrixOutputs_hi_hi_hi_hi_43 = cat(decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_andMatrixOutputs_andMatrixInput_1_71)
node decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_43, decoded_andMatrixOutputs_andMatrixInput_2_71)
node decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_andMatrixOutputs_hi_hi_hi_70, decoded_andMatrixOutputs_hi_hi_lo_70)
node decoded_andMatrixOutputs_hi_71 = cat(decoded_andMatrixOutputs_hi_hi_70, decoded_andMatrixOutputs_hi_lo_70)
node _decoded_andMatrixOutputs_T_71 = cat(decoded_andMatrixOutputs_hi_71, decoded_andMatrixOutputs_lo_70)
node decoded_andMatrixOutputs_30_2_1 = andr(_decoded_andMatrixOutputs_T_71)
node decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_71 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_71 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_71 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_andMatrixOutputs_andMatrixInput_12_71, decoded_andMatrixOutputs_andMatrixInput_13_71)
node decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_andMatrixOutputs_lo_lo_hi_71, decoded_andMatrixOutputs_andMatrixInput_14_71)
node decoded_andMatrixOutputs_lo_hi_lo_71 = cat(decoded_andMatrixOutputs_andMatrixInput_10_71, decoded_andMatrixOutputs_andMatrixInput_11_71)
node decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_andMatrixOutputs_andMatrixInput_8_71, decoded_andMatrixOutputs_andMatrixInput_9_71)
node decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_andMatrixOutputs_lo_hi_hi_71, decoded_andMatrixOutputs_lo_hi_lo_71)
node decoded_andMatrixOutputs_lo_71 = cat(decoded_andMatrixOutputs_lo_hi_71, decoded_andMatrixOutputs_lo_lo_71)
node decoded_andMatrixOutputs_hi_lo_lo_71 = cat(decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_andMatrixOutputs_andMatrixInput_7_71)
node decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_andMatrixOutputs_andMatrixInput_4_71, decoded_andMatrixOutputs_andMatrixInput_5_71)
node decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_andMatrixOutputs_hi_lo_hi_71, decoded_andMatrixOutputs_hi_lo_lo_71)
node decoded_andMatrixOutputs_hi_hi_lo_71 = cat(decoded_andMatrixOutputs_andMatrixInput_2_72, decoded_andMatrixOutputs_andMatrixInput_3_71)
node decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_andMatrixOutputs_andMatrixInput_1_72)
node decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_andMatrixOutputs_hi_hi_hi_71, decoded_andMatrixOutputs_hi_hi_lo_71)
node decoded_andMatrixOutputs_hi_72 = cat(decoded_andMatrixOutputs_hi_hi_71, decoded_andMatrixOutputs_hi_lo_71)
node _decoded_andMatrixOutputs_T_72 = cat(decoded_andMatrixOutputs_hi_72, decoded_andMatrixOutputs_lo_71)
node decoded_andMatrixOutputs_10_2_1 = andr(_decoded_andMatrixOutputs_T_72)
node decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_72 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_72 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_72 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_49 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_44 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_49 = cat(decoded_andMatrixOutputs_andMatrixInput_15_49, decoded_andMatrixOutputs_andMatrixInput_16_44)
node decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_andMatrixOutputs_andMatrixInput_13_72, decoded_andMatrixOutputs_andMatrixInput_14_72)
node decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_andMatrixOutputs_lo_lo_hi_72, decoded_andMatrixOutputs_lo_lo_lo_49)
node decoded_andMatrixOutputs_lo_hi_lo_72 = cat(decoded_andMatrixOutputs_andMatrixInput_11_72, decoded_andMatrixOutputs_andMatrixInput_12_72)
node decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_andMatrixOutputs_andMatrixInput_10_72)
node decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_andMatrixOutputs_lo_hi_hi_72, decoded_andMatrixOutputs_lo_hi_lo_72)
node decoded_andMatrixOutputs_lo_72 = cat(decoded_andMatrixOutputs_lo_hi_72, decoded_andMatrixOutputs_lo_lo_72)
node decoded_andMatrixOutputs_hi_lo_lo_72 = cat(decoded_andMatrixOutputs_andMatrixInput_7_72, decoded_andMatrixOutputs_andMatrixInput_8_72)
node decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_andMatrixOutputs_andMatrixInput_5_72, decoded_andMatrixOutputs_andMatrixInput_6_72)
node decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_andMatrixOutputs_hi_lo_hi_72, decoded_andMatrixOutputs_hi_lo_lo_72)
node decoded_andMatrixOutputs_hi_hi_lo_72 = cat(decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_andMatrixOutputs_andMatrixInput_4_72)
node decoded_andMatrixOutputs_hi_hi_hi_hi_44 = cat(decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_andMatrixOutputs_andMatrixInput_1_73)
node decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_44, decoded_andMatrixOutputs_andMatrixInput_2_73)
node decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_andMatrixOutputs_hi_hi_hi_72, decoded_andMatrixOutputs_hi_hi_lo_72)
node decoded_andMatrixOutputs_hi_73 = cat(decoded_andMatrixOutputs_hi_hi_72, decoded_andMatrixOutputs_hi_lo_72)
node _decoded_andMatrixOutputs_T_73 = cat(decoded_andMatrixOutputs_hi_73, decoded_andMatrixOutputs_lo_72)
node decoded_andMatrixOutputs_22_2_1 = andr(_decoded_andMatrixOutputs_T_73)
node decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_73 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_73 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_73 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_andMatrixOutputs_andMatrixInput_12_73, decoded_andMatrixOutputs_andMatrixInput_13_73)
node decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_andMatrixOutputs_lo_lo_hi_73, decoded_andMatrixOutputs_andMatrixInput_14_73)
node decoded_andMatrixOutputs_lo_hi_lo_73 = cat(decoded_andMatrixOutputs_andMatrixInput_10_73, decoded_andMatrixOutputs_andMatrixInput_11_73)
node decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_andMatrixOutputs_andMatrixInput_8_73, decoded_andMatrixOutputs_andMatrixInput_9_73)
node decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_andMatrixOutputs_lo_hi_hi_73, decoded_andMatrixOutputs_lo_hi_lo_73)
node decoded_andMatrixOutputs_lo_73 = cat(decoded_andMatrixOutputs_lo_hi_73, decoded_andMatrixOutputs_lo_lo_73)
node decoded_andMatrixOutputs_hi_lo_lo_73 = cat(decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_andMatrixOutputs_andMatrixInput_7_73)
node decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_andMatrixOutputs_andMatrixInput_4_73, decoded_andMatrixOutputs_andMatrixInput_5_73)
node decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_andMatrixOutputs_hi_lo_hi_73, decoded_andMatrixOutputs_hi_lo_lo_73)
node decoded_andMatrixOutputs_hi_hi_lo_73 = cat(decoded_andMatrixOutputs_andMatrixInput_2_74, decoded_andMatrixOutputs_andMatrixInput_3_73)
node decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_andMatrixOutputs_andMatrixInput_1_74)
node decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_andMatrixOutputs_hi_hi_hi_73, decoded_andMatrixOutputs_hi_hi_lo_73)
node decoded_andMatrixOutputs_hi_74 = cat(decoded_andMatrixOutputs_hi_hi_73, decoded_andMatrixOutputs_hi_lo_73)
node _decoded_andMatrixOutputs_T_74 = cat(decoded_andMatrixOutputs_hi_74, decoded_andMatrixOutputs_lo_73)
node decoded_andMatrixOutputs_52_2 = andr(_decoded_andMatrixOutputs_T_74)
node decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_plaInput_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_74 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_74 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_74 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_50 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_45 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_50 = cat(decoded_andMatrixOutputs_andMatrixInput_15_50, decoded_andMatrixOutputs_andMatrixInput_16_45)
node decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_andMatrixOutputs_andMatrixInput_13_74, decoded_andMatrixOutputs_andMatrixInput_14_74)
node decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_andMatrixOutputs_lo_lo_hi_74, decoded_andMatrixOutputs_lo_lo_lo_50)
node decoded_andMatrixOutputs_lo_hi_lo_74 = cat(decoded_andMatrixOutputs_andMatrixInput_11_74, decoded_andMatrixOutputs_andMatrixInput_12_74)
node decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_andMatrixOutputs_andMatrixInput_10_74)
node decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_andMatrixOutputs_lo_hi_hi_74, decoded_andMatrixOutputs_lo_hi_lo_74)
node decoded_andMatrixOutputs_lo_74 = cat(decoded_andMatrixOutputs_lo_hi_74, decoded_andMatrixOutputs_lo_lo_74)
node decoded_andMatrixOutputs_hi_lo_lo_74 = cat(decoded_andMatrixOutputs_andMatrixInput_7_74, decoded_andMatrixOutputs_andMatrixInput_8_74)
node decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_andMatrixOutputs_andMatrixInput_5_74, decoded_andMatrixOutputs_andMatrixInput_6_74)
node decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_andMatrixOutputs_hi_lo_hi_74, decoded_andMatrixOutputs_hi_lo_lo_74)
node decoded_andMatrixOutputs_hi_hi_lo_74 = cat(decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_andMatrixOutputs_andMatrixInput_4_74)
node decoded_andMatrixOutputs_hi_hi_hi_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_andMatrixOutputs_andMatrixInput_1_75)
node decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_45, decoded_andMatrixOutputs_andMatrixInput_2_75)
node decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_andMatrixOutputs_hi_hi_hi_74, decoded_andMatrixOutputs_hi_hi_lo_74)
node decoded_andMatrixOutputs_hi_75 = cat(decoded_andMatrixOutputs_hi_hi_74, decoded_andMatrixOutputs_hi_lo_74)
node _decoded_andMatrixOutputs_T_75 = cat(decoded_andMatrixOutputs_hi_75, decoded_andMatrixOutputs_lo_74)
node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_75)
node decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_75 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_75 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_75 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_andMatrixOutputs_andMatrixInput_12_75, decoded_andMatrixOutputs_andMatrixInput_13_75)
node decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_andMatrixOutputs_lo_lo_hi_75, decoded_andMatrixOutputs_andMatrixInput_14_75)
node decoded_andMatrixOutputs_lo_hi_lo_75 = cat(decoded_andMatrixOutputs_andMatrixInput_10_75, decoded_andMatrixOutputs_andMatrixInput_11_75)
node decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_andMatrixOutputs_andMatrixInput_8_75, decoded_andMatrixOutputs_andMatrixInput_9_75)
node decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_andMatrixOutputs_lo_hi_hi_75, decoded_andMatrixOutputs_lo_hi_lo_75)
node decoded_andMatrixOutputs_lo_75 = cat(decoded_andMatrixOutputs_lo_hi_75, decoded_andMatrixOutputs_lo_lo_75)
node decoded_andMatrixOutputs_hi_lo_lo_75 = cat(decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_andMatrixOutputs_andMatrixInput_7_75)
node decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_andMatrixOutputs_andMatrixInput_4_75, decoded_andMatrixOutputs_andMatrixInput_5_75)
node decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_andMatrixOutputs_hi_lo_hi_75, decoded_andMatrixOutputs_hi_lo_lo_75)
node decoded_andMatrixOutputs_hi_hi_lo_75 = cat(decoded_andMatrixOutputs_andMatrixInput_2_76, decoded_andMatrixOutputs_andMatrixInput_3_75)
node decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_andMatrixOutputs_andMatrixInput_1_76)
node decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_andMatrixOutputs_hi_hi_hi_75, decoded_andMatrixOutputs_hi_hi_lo_75)
node decoded_andMatrixOutputs_hi_76 = cat(decoded_andMatrixOutputs_hi_hi_75, decoded_andMatrixOutputs_hi_lo_75)
node _decoded_andMatrixOutputs_T_76 = cat(decoded_andMatrixOutputs_hi_76, decoded_andMatrixOutputs_lo_75)
node decoded_andMatrixOutputs_36_2_1 = andr(_decoded_andMatrixOutputs_T_76)
node decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_76 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_76 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_76 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_andMatrixOutputs_andMatrixInput_12_76, decoded_andMatrixOutputs_andMatrixInput_13_76)
node decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_andMatrixOutputs_lo_lo_hi_76, decoded_andMatrixOutputs_andMatrixInput_14_76)
node decoded_andMatrixOutputs_lo_hi_lo_76 = cat(decoded_andMatrixOutputs_andMatrixInput_10_76, decoded_andMatrixOutputs_andMatrixInput_11_76)
node decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_andMatrixOutputs_andMatrixInput_8_76, decoded_andMatrixOutputs_andMatrixInput_9_76)
node decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_andMatrixOutputs_lo_hi_hi_76, decoded_andMatrixOutputs_lo_hi_lo_76)
node decoded_andMatrixOutputs_lo_76 = cat(decoded_andMatrixOutputs_lo_hi_76, decoded_andMatrixOutputs_lo_lo_76)
node decoded_andMatrixOutputs_hi_lo_lo_76 = cat(decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_andMatrixOutputs_andMatrixInput_7_76)
node decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_andMatrixOutputs_andMatrixInput_4_76, decoded_andMatrixOutputs_andMatrixInput_5_76)
node decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_andMatrixOutputs_hi_lo_hi_76, decoded_andMatrixOutputs_hi_lo_lo_76)
node decoded_andMatrixOutputs_hi_hi_lo_76 = cat(decoded_andMatrixOutputs_andMatrixInput_2_77, decoded_andMatrixOutputs_andMatrixInput_3_76)
node decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_andMatrixOutputs_andMatrixInput_1_77)
node decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_andMatrixOutputs_hi_hi_hi_76, decoded_andMatrixOutputs_hi_hi_lo_76)
node decoded_andMatrixOutputs_hi_77 = cat(decoded_andMatrixOutputs_hi_hi_76, decoded_andMatrixOutputs_hi_lo_76)
node _decoded_andMatrixOutputs_T_77 = cat(decoded_andMatrixOutputs_hi_77, decoded_andMatrixOutputs_lo_76)
node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_77)
node decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_77 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_77 = bits(decoded_plaInput_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_77 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_51 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_46 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_51 = cat(decoded_andMatrixOutputs_andMatrixInput_15_51, decoded_andMatrixOutputs_andMatrixInput_16_46)
node decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_andMatrixOutputs_andMatrixInput_13_77, decoded_andMatrixOutputs_andMatrixInput_14_77)
node decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_andMatrixOutputs_lo_lo_hi_77, decoded_andMatrixOutputs_lo_lo_lo_51)
node decoded_andMatrixOutputs_lo_hi_lo_77 = cat(decoded_andMatrixOutputs_andMatrixInput_11_77, decoded_andMatrixOutputs_andMatrixInput_12_77)
node decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_andMatrixOutputs_andMatrixInput_10_77)
node decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_andMatrixOutputs_lo_hi_hi_77, decoded_andMatrixOutputs_lo_hi_lo_77)
node decoded_andMatrixOutputs_lo_77 = cat(decoded_andMatrixOutputs_lo_hi_77, decoded_andMatrixOutputs_lo_lo_77)
node decoded_andMatrixOutputs_hi_lo_lo_77 = cat(decoded_andMatrixOutputs_andMatrixInput_7_77, decoded_andMatrixOutputs_andMatrixInput_8_77)
node decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_andMatrixOutputs_andMatrixInput_5_77, decoded_andMatrixOutputs_andMatrixInput_6_77)
node decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_andMatrixOutputs_hi_lo_hi_77, decoded_andMatrixOutputs_hi_lo_lo_77)
node decoded_andMatrixOutputs_hi_hi_lo_77 = cat(decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_andMatrixOutputs_andMatrixInput_4_77)
node decoded_andMatrixOutputs_hi_hi_hi_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_andMatrixOutputs_andMatrixInput_1_78)
node decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_46, decoded_andMatrixOutputs_andMatrixInput_2_78)
node decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_andMatrixOutputs_hi_hi_hi_77, decoded_andMatrixOutputs_hi_hi_lo_77)
node decoded_andMatrixOutputs_hi_78 = cat(decoded_andMatrixOutputs_hi_hi_77, decoded_andMatrixOutputs_hi_lo_77)
node _decoded_andMatrixOutputs_T_78 = cat(decoded_andMatrixOutputs_hi_78, decoded_andMatrixOutputs_lo_77)
node decoded_andMatrixOutputs_44_2 = andr(_decoded_andMatrixOutputs_T_78)
node decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_78 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_78 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_78 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_andMatrixOutputs_andMatrixInput_12_78, decoded_andMatrixOutputs_andMatrixInput_13_78)
node decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_andMatrixOutputs_lo_lo_hi_78, decoded_andMatrixOutputs_andMatrixInput_14_78)
node decoded_andMatrixOutputs_lo_hi_lo_78 = cat(decoded_andMatrixOutputs_andMatrixInput_10_78, decoded_andMatrixOutputs_andMatrixInput_11_78)
node decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_andMatrixOutputs_andMatrixInput_8_78, decoded_andMatrixOutputs_andMatrixInput_9_78)
node decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_andMatrixOutputs_lo_hi_hi_78, decoded_andMatrixOutputs_lo_hi_lo_78)
node decoded_andMatrixOutputs_lo_78 = cat(decoded_andMatrixOutputs_lo_hi_78, decoded_andMatrixOutputs_lo_lo_78)
node decoded_andMatrixOutputs_hi_lo_lo_78 = cat(decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_andMatrixOutputs_andMatrixInput_7_78)
node decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_andMatrixOutputs_andMatrixInput_4_78, decoded_andMatrixOutputs_andMatrixInput_5_78)
node decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_andMatrixOutputs_hi_lo_hi_78, decoded_andMatrixOutputs_hi_lo_lo_78)
node decoded_andMatrixOutputs_hi_hi_lo_78 = cat(decoded_andMatrixOutputs_andMatrixInput_2_79, decoded_andMatrixOutputs_andMatrixInput_3_78)
node decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_andMatrixOutputs_andMatrixInput_1_79)
node decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_andMatrixOutputs_hi_hi_hi_78, decoded_andMatrixOutputs_hi_hi_lo_78)
node decoded_andMatrixOutputs_hi_79 = cat(decoded_andMatrixOutputs_hi_hi_78, decoded_andMatrixOutputs_hi_lo_78)
node _decoded_andMatrixOutputs_T_79 = cat(decoded_andMatrixOutputs_hi_79, decoded_andMatrixOutputs_lo_78)
node decoded_andMatrixOutputs_26_2_1 = andr(_decoded_andMatrixOutputs_T_79)
node decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_plaInput_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_79 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_79 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_79 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_andMatrixOutputs_andMatrixInput_12_79, decoded_andMatrixOutputs_andMatrixInput_13_79)
node decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_andMatrixOutputs_lo_lo_hi_79, decoded_andMatrixOutputs_andMatrixInput_14_79)
node decoded_andMatrixOutputs_lo_hi_lo_79 = cat(decoded_andMatrixOutputs_andMatrixInput_10_79, decoded_andMatrixOutputs_andMatrixInput_11_79)
node decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_andMatrixOutputs_andMatrixInput_8_79, decoded_andMatrixOutputs_andMatrixInput_9_79)
node decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_andMatrixOutputs_lo_hi_hi_79, decoded_andMatrixOutputs_lo_hi_lo_79)
node decoded_andMatrixOutputs_lo_79 = cat(decoded_andMatrixOutputs_lo_hi_79, decoded_andMatrixOutputs_lo_lo_79)
node decoded_andMatrixOutputs_hi_lo_lo_79 = cat(decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_andMatrixOutputs_andMatrixInput_7_79)
node decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_andMatrixOutputs_andMatrixInput_4_79, decoded_andMatrixOutputs_andMatrixInput_5_79)
node decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_andMatrixOutputs_hi_lo_hi_79, decoded_andMatrixOutputs_hi_lo_lo_79)
node decoded_andMatrixOutputs_hi_hi_lo_79 = cat(decoded_andMatrixOutputs_andMatrixInput_2_80, decoded_andMatrixOutputs_andMatrixInput_3_79)
node decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_andMatrixOutputs_andMatrixInput_1_80)
node decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_andMatrixOutputs_hi_hi_hi_79, decoded_andMatrixOutputs_hi_hi_lo_79)
node decoded_andMatrixOutputs_hi_80 = cat(decoded_andMatrixOutputs_hi_hi_79, decoded_andMatrixOutputs_hi_lo_79)
node _decoded_andMatrixOutputs_T_80 = cat(decoded_andMatrixOutputs_hi_80, decoded_andMatrixOutputs_lo_79)
node decoded_andMatrixOutputs_19_2_1 = andr(_decoded_andMatrixOutputs_T_80)
node decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_80 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_80 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_80 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_52 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_47 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_52 = cat(decoded_andMatrixOutputs_andMatrixInput_15_52, decoded_andMatrixOutputs_andMatrixInput_16_47)
node decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_andMatrixOutputs_andMatrixInput_13_80, decoded_andMatrixOutputs_andMatrixInput_14_80)
node decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_andMatrixOutputs_lo_lo_hi_80, decoded_andMatrixOutputs_lo_lo_lo_52)
node decoded_andMatrixOutputs_lo_hi_lo_80 = cat(decoded_andMatrixOutputs_andMatrixInput_11_80, decoded_andMatrixOutputs_andMatrixInput_12_80)
node decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_andMatrixOutputs_andMatrixInput_10_80)
node decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_andMatrixOutputs_lo_hi_hi_80, decoded_andMatrixOutputs_lo_hi_lo_80)
node decoded_andMatrixOutputs_lo_80 = cat(decoded_andMatrixOutputs_lo_hi_80, decoded_andMatrixOutputs_lo_lo_80)
node decoded_andMatrixOutputs_hi_lo_lo_80 = cat(decoded_andMatrixOutputs_andMatrixInput_7_80, decoded_andMatrixOutputs_andMatrixInput_8_80)
node decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_andMatrixOutputs_andMatrixInput_5_80, decoded_andMatrixOutputs_andMatrixInput_6_80)
node decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_andMatrixOutputs_hi_lo_hi_80, decoded_andMatrixOutputs_hi_lo_lo_80)
node decoded_andMatrixOutputs_hi_hi_lo_80 = cat(decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_andMatrixOutputs_andMatrixInput_4_80)
node decoded_andMatrixOutputs_hi_hi_hi_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_andMatrixOutputs_andMatrixInput_1_81)
node decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_47, decoded_andMatrixOutputs_andMatrixInput_2_81)
node decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_andMatrixOutputs_hi_hi_hi_80, decoded_andMatrixOutputs_hi_hi_lo_80)
node decoded_andMatrixOutputs_hi_81 = cat(decoded_andMatrixOutputs_hi_hi_80, decoded_andMatrixOutputs_hi_lo_80)
node _decoded_andMatrixOutputs_T_81 = cat(decoded_andMatrixOutputs_hi_81, decoded_andMatrixOutputs_lo_80)
node decoded_andMatrixOutputs_17_2_1 = andr(_decoded_andMatrixOutputs_T_81)
node decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_81 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_81 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_81 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_53 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_48 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_53 = cat(decoded_andMatrixOutputs_andMatrixInput_15_53, decoded_andMatrixOutputs_andMatrixInput_16_48)
node decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_andMatrixOutputs_andMatrixInput_13_81, decoded_andMatrixOutputs_andMatrixInput_14_81)
node decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_andMatrixOutputs_lo_lo_hi_81, decoded_andMatrixOutputs_lo_lo_lo_53)
node decoded_andMatrixOutputs_lo_hi_lo_81 = cat(decoded_andMatrixOutputs_andMatrixInput_11_81, decoded_andMatrixOutputs_andMatrixInput_12_81)
node decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_andMatrixOutputs_andMatrixInput_10_81)
node decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_andMatrixOutputs_lo_hi_hi_81, decoded_andMatrixOutputs_lo_hi_lo_81)
node decoded_andMatrixOutputs_lo_81 = cat(decoded_andMatrixOutputs_lo_hi_81, decoded_andMatrixOutputs_lo_lo_81)
node decoded_andMatrixOutputs_hi_lo_lo_81 = cat(decoded_andMatrixOutputs_andMatrixInput_7_81, decoded_andMatrixOutputs_andMatrixInput_8_81)
node decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_andMatrixOutputs_andMatrixInput_5_81, decoded_andMatrixOutputs_andMatrixInput_6_81)
node decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_andMatrixOutputs_hi_lo_hi_81, decoded_andMatrixOutputs_hi_lo_lo_81)
node decoded_andMatrixOutputs_hi_hi_lo_81 = cat(decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_andMatrixOutputs_andMatrixInput_4_81)
node decoded_andMatrixOutputs_hi_hi_hi_hi_48 = cat(decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_andMatrixOutputs_andMatrixInput_1_82)
node decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_48, decoded_andMatrixOutputs_andMatrixInput_2_82)
node decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_andMatrixOutputs_hi_hi_hi_81, decoded_andMatrixOutputs_hi_hi_lo_81)
node decoded_andMatrixOutputs_hi_82 = cat(decoded_andMatrixOutputs_hi_hi_81, decoded_andMatrixOutputs_hi_lo_81)
node _decoded_andMatrixOutputs_T_82 = cat(decoded_andMatrixOutputs_hi_82, decoded_andMatrixOutputs_lo_81)
node decoded_andMatrixOutputs_40_2_1 = andr(_decoded_andMatrixOutputs_T_82)
node decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_82 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_82 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_82 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_andMatrixOutputs_andMatrixInput_12_82, decoded_andMatrixOutputs_andMatrixInput_13_82)
node decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_andMatrixOutputs_lo_lo_hi_82, decoded_andMatrixOutputs_andMatrixInput_14_82)
node decoded_andMatrixOutputs_lo_hi_lo_82 = cat(decoded_andMatrixOutputs_andMatrixInput_10_82, decoded_andMatrixOutputs_andMatrixInput_11_82)
node decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_andMatrixOutputs_andMatrixInput_8_82, decoded_andMatrixOutputs_andMatrixInput_9_82)
node decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_andMatrixOutputs_lo_hi_hi_82, decoded_andMatrixOutputs_lo_hi_lo_82)
node decoded_andMatrixOutputs_lo_82 = cat(decoded_andMatrixOutputs_lo_hi_82, decoded_andMatrixOutputs_lo_lo_82)
node decoded_andMatrixOutputs_hi_lo_lo_82 = cat(decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_andMatrixOutputs_andMatrixInput_7_82)
node decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_andMatrixOutputs_andMatrixInput_4_82, decoded_andMatrixOutputs_andMatrixInput_5_82)
node decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_andMatrixOutputs_hi_lo_hi_82, decoded_andMatrixOutputs_hi_lo_lo_82)
node decoded_andMatrixOutputs_hi_hi_lo_82 = cat(decoded_andMatrixOutputs_andMatrixInput_2_83, decoded_andMatrixOutputs_andMatrixInput_3_82)
node decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_andMatrixOutputs_andMatrixInput_1_83)
node decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_andMatrixOutputs_hi_hi_hi_82, decoded_andMatrixOutputs_hi_hi_lo_82)
node decoded_andMatrixOutputs_hi_83 = cat(decoded_andMatrixOutputs_hi_hi_82, decoded_andMatrixOutputs_hi_lo_82)
node _decoded_andMatrixOutputs_T_83 = cat(decoded_andMatrixOutputs_hi_83, decoded_andMatrixOutputs_lo_82)
node decoded_andMatrixOutputs_34_2_1 = andr(_decoded_andMatrixOutputs_T_83)
node decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_83 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_83 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_83 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_54 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_49 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_54 = cat(decoded_andMatrixOutputs_andMatrixInput_15_54, decoded_andMatrixOutputs_andMatrixInput_16_49)
node decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_andMatrixOutputs_andMatrixInput_13_83, decoded_andMatrixOutputs_andMatrixInput_14_83)
node decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_andMatrixOutputs_lo_lo_hi_83, decoded_andMatrixOutputs_lo_lo_lo_54)
node decoded_andMatrixOutputs_lo_hi_lo_83 = cat(decoded_andMatrixOutputs_andMatrixInput_11_83, decoded_andMatrixOutputs_andMatrixInput_12_83)
node decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_andMatrixOutputs_andMatrixInput_10_83)
node decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_andMatrixOutputs_lo_hi_hi_83, decoded_andMatrixOutputs_lo_hi_lo_83)
node decoded_andMatrixOutputs_lo_83 = cat(decoded_andMatrixOutputs_lo_hi_83, decoded_andMatrixOutputs_lo_lo_83)
node decoded_andMatrixOutputs_hi_lo_lo_83 = cat(decoded_andMatrixOutputs_andMatrixInput_7_83, decoded_andMatrixOutputs_andMatrixInput_8_83)
node decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_andMatrixOutputs_andMatrixInput_5_83, decoded_andMatrixOutputs_andMatrixInput_6_83)
node decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_andMatrixOutputs_hi_lo_hi_83, decoded_andMatrixOutputs_hi_lo_lo_83)
node decoded_andMatrixOutputs_hi_hi_lo_83 = cat(decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_andMatrixOutputs_andMatrixInput_4_83)
node decoded_andMatrixOutputs_hi_hi_hi_hi_49 = cat(decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_andMatrixOutputs_andMatrixInput_1_84)
node decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_49, decoded_andMatrixOutputs_andMatrixInput_2_84)
node decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_andMatrixOutputs_hi_hi_hi_83, decoded_andMatrixOutputs_hi_hi_lo_83)
node decoded_andMatrixOutputs_hi_84 = cat(decoded_andMatrixOutputs_hi_hi_83, decoded_andMatrixOutputs_hi_lo_83)
node _decoded_andMatrixOutputs_T_84 = cat(decoded_andMatrixOutputs_hi_84, decoded_andMatrixOutputs_lo_83)
node decoded_andMatrixOutputs_41_2_1 = andr(_decoded_andMatrixOutputs_T_84)
node decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_plaInput_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_plaInput_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_84 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_84 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_84 = bits(decoded_plaInput_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_55 = bits(decoded_invInputs_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_50 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_55 = cat(decoded_andMatrixOutputs_andMatrixInput_15_55, decoded_andMatrixOutputs_andMatrixInput_16_50)
node decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_andMatrixOutputs_andMatrixInput_13_84, decoded_andMatrixOutputs_andMatrixInput_14_84)
node decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_andMatrixOutputs_lo_lo_hi_84, decoded_andMatrixOutputs_lo_lo_lo_55)
node decoded_andMatrixOutputs_lo_hi_lo_84 = cat(decoded_andMatrixOutputs_andMatrixInput_11_84, decoded_andMatrixOutputs_andMatrixInput_12_84)
node decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_andMatrixOutputs_andMatrixInput_10_84)
node decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_andMatrixOutputs_lo_hi_hi_84, decoded_andMatrixOutputs_lo_hi_lo_84)
node decoded_andMatrixOutputs_lo_84 = cat(decoded_andMatrixOutputs_lo_hi_84, decoded_andMatrixOutputs_lo_lo_84)
node decoded_andMatrixOutputs_hi_lo_lo_84 = cat(decoded_andMatrixOutputs_andMatrixInput_7_84, decoded_andMatrixOutputs_andMatrixInput_8_84)
node decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_andMatrixOutputs_andMatrixInput_5_84, decoded_andMatrixOutputs_andMatrixInput_6_84)
node decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_andMatrixOutputs_hi_lo_hi_84, decoded_andMatrixOutputs_hi_lo_lo_84)
node decoded_andMatrixOutputs_hi_hi_lo_84 = cat(decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_andMatrixOutputs_andMatrixInput_4_84)
node decoded_andMatrixOutputs_hi_hi_hi_hi_50 = cat(decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_andMatrixOutputs_andMatrixInput_1_85)
node decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_50, decoded_andMatrixOutputs_andMatrixInput_2_85)
node decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_andMatrixOutputs_hi_hi_hi_84, decoded_andMatrixOutputs_hi_hi_lo_84)
node decoded_andMatrixOutputs_hi_85 = cat(decoded_andMatrixOutputs_hi_hi_84, decoded_andMatrixOutputs_hi_lo_84)
node _decoded_andMatrixOutputs_T_85 = cat(decoded_andMatrixOutputs_hi_85, decoded_andMatrixOutputs_lo_84)
node decoded_andMatrixOutputs_32_2_1 = andr(_decoded_andMatrixOutputs_T_85)
node decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_85 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_85 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_85 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_andMatrixOutputs_andMatrixInput_12_85, decoded_andMatrixOutputs_andMatrixInput_13_85)
node decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_andMatrixOutputs_lo_lo_hi_85, decoded_andMatrixOutputs_andMatrixInput_14_85)
node decoded_andMatrixOutputs_lo_hi_lo_85 = cat(decoded_andMatrixOutputs_andMatrixInput_10_85, decoded_andMatrixOutputs_andMatrixInput_11_85)
node decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_andMatrixOutputs_andMatrixInput_8_85, decoded_andMatrixOutputs_andMatrixInput_9_85)
node decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_andMatrixOutputs_lo_hi_hi_85, decoded_andMatrixOutputs_lo_hi_lo_85)
node decoded_andMatrixOutputs_lo_85 = cat(decoded_andMatrixOutputs_lo_hi_85, decoded_andMatrixOutputs_lo_lo_85)
node decoded_andMatrixOutputs_hi_lo_lo_85 = cat(decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_andMatrixOutputs_andMatrixInput_7_85)
node decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_andMatrixOutputs_andMatrixInput_4_85, decoded_andMatrixOutputs_andMatrixInput_5_85)
node decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_andMatrixOutputs_hi_lo_hi_85, decoded_andMatrixOutputs_hi_lo_lo_85)
node decoded_andMatrixOutputs_hi_hi_lo_85 = cat(decoded_andMatrixOutputs_andMatrixInput_2_86, decoded_andMatrixOutputs_andMatrixInput_3_85)
node decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_andMatrixOutputs_andMatrixInput_1_86)
node decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_andMatrixOutputs_hi_hi_hi_85, decoded_andMatrixOutputs_hi_hi_lo_85)
node decoded_andMatrixOutputs_hi_86 = cat(decoded_andMatrixOutputs_hi_hi_85, decoded_andMatrixOutputs_hi_lo_85)
node _decoded_andMatrixOutputs_T_86 = cat(decoded_andMatrixOutputs_hi_86, decoded_andMatrixOutputs_lo_85)
node decoded_andMatrixOutputs_28_2_1 = andr(_decoded_andMatrixOutputs_T_86)
node decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_86 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_86 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_86 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_andMatrixOutputs_andMatrixInput_12_86, decoded_andMatrixOutputs_andMatrixInput_13_86)
node decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_andMatrixOutputs_lo_lo_hi_86, decoded_andMatrixOutputs_andMatrixInput_14_86)
node decoded_andMatrixOutputs_lo_hi_lo_86 = cat(decoded_andMatrixOutputs_andMatrixInput_10_86, decoded_andMatrixOutputs_andMatrixInput_11_86)
node decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_andMatrixOutputs_andMatrixInput_8_86, decoded_andMatrixOutputs_andMatrixInput_9_86)
node decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_andMatrixOutputs_lo_hi_hi_86, decoded_andMatrixOutputs_lo_hi_lo_86)
node decoded_andMatrixOutputs_lo_86 = cat(decoded_andMatrixOutputs_lo_hi_86, decoded_andMatrixOutputs_lo_lo_86)
node decoded_andMatrixOutputs_hi_lo_lo_86 = cat(decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_andMatrixOutputs_andMatrixInput_7_86)
node decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_andMatrixOutputs_andMatrixInput_4_86, decoded_andMatrixOutputs_andMatrixInput_5_86)
node decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_andMatrixOutputs_hi_lo_hi_86, decoded_andMatrixOutputs_hi_lo_lo_86)
node decoded_andMatrixOutputs_hi_hi_lo_86 = cat(decoded_andMatrixOutputs_andMatrixInput_2_87, decoded_andMatrixOutputs_andMatrixInput_3_86)
node decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_andMatrixOutputs_andMatrixInput_1_87)
node decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_andMatrixOutputs_hi_hi_hi_86, decoded_andMatrixOutputs_hi_hi_lo_86)
node decoded_andMatrixOutputs_hi_87 = cat(decoded_andMatrixOutputs_hi_hi_86, decoded_andMatrixOutputs_hi_lo_86)
node _decoded_andMatrixOutputs_T_87 = cat(decoded_andMatrixOutputs_hi_87, decoded_andMatrixOutputs_lo_86)
node decoded_andMatrixOutputs_47_2 = andr(_decoded_andMatrixOutputs_T_87)
node decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_87 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_87 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_87 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_andMatrixOutputs_andMatrixInput_12_87, decoded_andMatrixOutputs_andMatrixInput_13_87)
node decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_andMatrixOutputs_lo_lo_hi_87, decoded_andMatrixOutputs_andMatrixInput_14_87)
node decoded_andMatrixOutputs_lo_hi_lo_87 = cat(decoded_andMatrixOutputs_andMatrixInput_10_87, decoded_andMatrixOutputs_andMatrixInput_11_87)
node decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_andMatrixOutputs_andMatrixInput_8_87, decoded_andMatrixOutputs_andMatrixInput_9_87)
node decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_andMatrixOutputs_lo_hi_hi_87, decoded_andMatrixOutputs_lo_hi_lo_87)
node decoded_andMatrixOutputs_lo_87 = cat(decoded_andMatrixOutputs_lo_hi_87, decoded_andMatrixOutputs_lo_lo_87)
node decoded_andMatrixOutputs_hi_lo_lo_87 = cat(decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_andMatrixOutputs_andMatrixInput_7_87)
node decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_andMatrixOutputs_andMatrixInput_4_87, decoded_andMatrixOutputs_andMatrixInput_5_87)
node decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_andMatrixOutputs_hi_lo_hi_87, decoded_andMatrixOutputs_hi_lo_lo_87)
node decoded_andMatrixOutputs_hi_hi_lo_87 = cat(decoded_andMatrixOutputs_andMatrixInput_2_88, decoded_andMatrixOutputs_andMatrixInput_3_87)
node decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_andMatrixOutputs_andMatrixInput_1_88)
node decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_andMatrixOutputs_hi_hi_hi_87, decoded_andMatrixOutputs_hi_hi_lo_87)
node decoded_andMatrixOutputs_hi_88 = cat(decoded_andMatrixOutputs_hi_hi_87, decoded_andMatrixOutputs_hi_lo_87)
node _decoded_andMatrixOutputs_T_88 = cat(decoded_andMatrixOutputs_hi_88, decoded_andMatrixOutputs_lo_87)
node decoded_andMatrixOutputs_45_2 = andr(_decoded_andMatrixOutputs_T_88)
node decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_88 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_88 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_88 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_andMatrixOutputs_andMatrixInput_12_88, decoded_andMatrixOutputs_andMatrixInput_13_88)
node decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_andMatrixOutputs_lo_lo_hi_88, decoded_andMatrixOutputs_andMatrixInput_14_88)
node decoded_andMatrixOutputs_lo_hi_lo_88 = cat(decoded_andMatrixOutputs_andMatrixInput_10_88, decoded_andMatrixOutputs_andMatrixInput_11_88)
node decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_andMatrixOutputs_andMatrixInput_8_88, decoded_andMatrixOutputs_andMatrixInput_9_88)
node decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_andMatrixOutputs_lo_hi_hi_88, decoded_andMatrixOutputs_lo_hi_lo_88)
node decoded_andMatrixOutputs_lo_88 = cat(decoded_andMatrixOutputs_lo_hi_88, decoded_andMatrixOutputs_lo_lo_88)
node decoded_andMatrixOutputs_hi_lo_lo_88 = cat(decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_andMatrixOutputs_andMatrixInput_7_88)
node decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_andMatrixOutputs_andMatrixInput_4_88, decoded_andMatrixOutputs_andMatrixInput_5_88)
node decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_andMatrixOutputs_hi_lo_hi_88, decoded_andMatrixOutputs_hi_lo_lo_88)
node decoded_andMatrixOutputs_hi_hi_lo_88 = cat(decoded_andMatrixOutputs_andMatrixInput_2_89, decoded_andMatrixOutputs_andMatrixInput_3_88)
node decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_andMatrixOutputs_andMatrixInput_1_89)
node decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_andMatrixOutputs_hi_hi_hi_88, decoded_andMatrixOutputs_hi_hi_lo_88)
node decoded_andMatrixOutputs_hi_89 = cat(decoded_andMatrixOutputs_hi_hi_88, decoded_andMatrixOutputs_hi_lo_88)
node _decoded_andMatrixOutputs_T_89 = cat(decoded_andMatrixOutputs_hi_89, decoded_andMatrixOutputs_lo_88)
node decoded_andMatrixOutputs_35_2_1 = andr(_decoded_andMatrixOutputs_T_89)
node decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_89 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_89 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_89 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_56 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_51 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_56 = cat(decoded_andMatrixOutputs_andMatrixInput_15_56, decoded_andMatrixOutputs_andMatrixInput_16_51)
node decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_andMatrixOutputs_andMatrixInput_13_89, decoded_andMatrixOutputs_andMatrixInput_14_89)
node decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_andMatrixOutputs_lo_lo_hi_89, decoded_andMatrixOutputs_lo_lo_lo_56)
node decoded_andMatrixOutputs_lo_hi_lo_89 = cat(decoded_andMatrixOutputs_andMatrixInput_11_89, decoded_andMatrixOutputs_andMatrixInput_12_89)
node decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_andMatrixOutputs_andMatrixInput_10_89)
node decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_andMatrixOutputs_lo_hi_hi_89, decoded_andMatrixOutputs_lo_hi_lo_89)
node decoded_andMatrixOutputs_lo_89 = cat(decoded_andMatrixOutputs_lo_hi_89, decoded_andMatrixOutputs_lo_lo_89)
node decoded_andMatrixOutputs_hi_lo_lo_89 = cat(decoded_andMatrixOutputs_andMatrixInput_7_89, decoded_andMatrixOutputs_andMatrixInput_8_89)
node decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_andMatrixOutputs_andMatrixInput_5_89, decoded_andMatrixOutputs_andMatrixInput_6_89)
node decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_andMatrixOutputs_hi_lo_hi_89, decoded_andMatrixOutputs_hi_lo_lo_89)
node decoded_andMatrixOutputs_hi_hi_lo_89 = cat(decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_andMatrixOutputs_andMatrixInput_4_89)
node decoded_andMatrixOutputs_hi_hi_hi_hi_51 = cat(decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_andMatrixOutputs_andMatrixInput_1_90)
node decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_51, decoded_andMatrixOutputs_andMatrixInput_2_90)
node decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_andMatrixOutputs_hi_hi_hi_89, decoded_andMatrixOutputs_hi_hi_lo_89)
node decoded_andMatrixOutputs_hi_90 = cat(decoded_andMatrixOutputs_hi_hi_89, decoded_andMatrixOutputs_hi_lo_89)
node _decoded_andMatrixOutputs_T_90 = cat(decoded_andMatrixOutputs_hi_90, decoded_andMatrixOutputs_lo_89)
node decoded_andMatrixOutputs_14_2_1 = andr(_decoded_andMatrixOutputs_T_90)
node decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_90 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_90 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_90 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_57 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_52 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_57 = cat(decoded_andMatrixOutputs_andMatrixInput_15_57, decoded_andMatrixOutputs_andMatrixInput_16_52)
node decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_andMatrixOutputs_andMatrixInput_13_90, decoded_andMatrixOutputs_andMatrixInput_14_90)
node decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_andMatrixOutputs_lo_lo_hi_90, decoded_andMatrixOutputs_lo_lo_lo_57)
node decoded_andMatrixOutputs_lo_hi_lo_90 = cat(decoded_andMatrixOutputs_andMatrixInput_11_90, decoded_andMatrixOutputs_andMatrixInput_12_90)
node decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_andMatrixOutputs_andMatrixInput_10_90)
node decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_andMatrixOutputs_lo_hi_hi_90, decoded_andMatrixOutputs_lo_hi_lo_90)
node decoded_andMatrixOutputs_lo_90 = cat(decoded_andMatrixOutputs_lo_hi_90, decoded_andMatrixOutputs_lo_lo_90)
node decoded_andMatrixOutputs_hi_lo_lo_90 = cat(decoded_andMatrixOutputs_andMatrixInput_7_90, decoded_andMatrixOutputs_andMatrixInput_8_90)
node decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_andMatrixOutputs_andMatrixInput_5_90, decoded_andMatrixOutputs_andMatrixInput_6_90)
node decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_andMatrixOutputs_hi_lo_hi_90, decoded_andMatrixOutputs_hi_lo_lo_90)
node decoded_andMatrixOutputs_hi_hi_lo_90 = cat(decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_andMatrixOutputs_andMatrixInput_4_90)
node decoded_andMatrixOutputs_hi_hi_hi_hi_52 = cat(decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_andMatrixOutputs_andMatrixInput_1_91)
node decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_52, decoded_andMatrixOutputs_andMatrixInput_2_91)
node decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_andMatrixOutputs_hi_hi_hi_90, decoded_andMatrixOutputs_hi_hi_lo_90)
node decoded_andMatrixOutputs_hi_91 = cat(decoded_andMatrixOutputs_hi_hi_90, decoded_andMatrixOutputs_hi_lo_90)
node _decoded_andMatrixOutputs_T_91 = cat(decoded_andMatrixOutputs_hi_91, decoded_andMatrixOutputs_lo_90)
node decoded_andMatrixOutputs_21_2_1 = andr(_decoded_andMatrixOutputs_T_91)
node decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_91 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_91 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_91 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_andMatrixOutputs_andMatrixInput_12_91, decoded_andMatrixOutputs_andMatrixInput_13_91)
node decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_andMatrixOutputs_lo_lo_hi_91, decoded_andMatrixOutputs_andMatrixInput_14_91)
node decoded_andMatrixOutputs_lo_hi_lo_91 = cat(decoded_andMatrixOutputs_andMatrixInput_10_91, decoded_andMatrixOutputs_andMatrixInput_11_91)
node decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_andMatrixOutputs_andMatrixInput_8_91, decoded_andMatrixOutputs_andMatrixInput_9_91)
node decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_andMatrixOutputs_lo_hi_hi_91, decoded_andMatrixOutputs_lo_hi_lo_91)
node decoded_andMatrixOutputs_lo_91 = cat(decoded_andMatrixOutputs_lo_hi_91, decoded_andMatrixOutputs_lo_lo_91)
node decoded_andMatrixOutputs_hi_lo_lo_91 = cat(decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_andMatrixOutputs_andMatrixInput_7_91)
node decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_andMatrixOutputs_andMatrixInput_4_91, decoded_andMatrixOutputs_andMatrixInput_5_91)
node decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_andMatrixOutputs_hi_lo_hi_91, decoded_andMatrixOutputs_hi_lo_lo_91)
node decoded_andMatrixOutputs_hi_hi_lo_91 = cat(decoded_andMatrixOutputs_andMatrixInput_2_92, decoded_andMatrixOutputs_andMatrixInput_3_91)
node decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_andMatrixOutputs_andMatrixInput_1_92)
node decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_andMatrixOutputs_hi_hi_hi_91, decoded_andMatrixOutputs_hi_hi_lo_91)
node decoded_andMatrixOutputs_hi_92 = cat(decoded_andMatrixOutputs_hi_hi_91, decoded_andMatrixOutputs_hi_lo_91)
node _decoded_andMatrixOutputs_T_92 = cat(decoded_andMatrixOutputs_hi_92, decoded_andMatrixOutputs_lo_91)
node decoded_andMatrixOutputs_42_2_1 = andr(_decoded_andMatrixOutputs_T_92)
node decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_92 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_92 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_92 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_andMatrixOutputs_andMatrixInput_12_92, decoded_andMatrixOutputs_andMatrixInput_13_92)
node decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_andMatrixOutputs_lo_lo_hi_92, decoded_andMatrixOutputs_andMatrixInput_14_92)
node decoded_andMatrixOutputs_lo_hi_lo_92 = cat(decoded_andMatrixOutputs_andMatrixInput_10_92, decoded_andMatrixOutputs_andMatrixInput_11_92)
node decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_andMatrixOutputs_andMatrixInput_8_92, decoded_andMatrixOutputs_andMatrixInput_9_92)
node decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_andMatrixOutputs_lo_hi_hi_92, decoded_andMatrixOutputs_lo_hi_lo_92)
node decoded_andMatrixOutputs_lo_92 = cat(decoded_andMatrixOutputs_lo_hi_92, decoded_andMatrixOutputs_lo_lo_92)
node decoded_andMatrixOutputs_hi_lo_lo_92 = cat(decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_andMatrixOutputs_andMatrixInput_7_92)
node decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_andMatrixOutputs_andMatrixInput_4_92, decoded_andMatrixOutputs_andMatrixInput_5_92)
node decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_andMatrixOutputs_hi_lo_hi_92, decoded_andMatrixOutputs_hi_lo_lo_92)
node decoded_andMatrixOutputs_hi_hi_lo_92 = cat(decoded_andMatrixOutputs_andMatrixInput_2_93, decoded_andMatrixOutputs_andMatrixInput_3_92)
node decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_andMatrixOutputs_andMatrixInput_1_93)
node decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_andMatrixOutputs_hi_hi_hi_92, decoded_andMatrixOutputs_hi_hi_lo_92)
node decoded_andMatrixOutputs_hi_93 = cat(decoded_andMatrixOutputs_hi_hi_92, decoded_andMatrixOutputs_hi_lo_92)
node _decoded_andMatrixOutputs_T_93 = cat(decoded_andMatrixOutputs_hi_93, decoded_andMatrixOutputs_lo_92)
node decoded_andMatrixOutputs_24_2_1 = andr(_decoded_andMatrixOutputs_T_93)
node decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_93 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_93 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_93 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_58 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_53 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_58 = cat(decoded_andMatrixOutputs_andMatrixInput_15_58, decoded_andMatrixOutputs_andMatrixInput_16_53)
node decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_andMatrixOutputs_andMatrixInput_13_93, decoded_andMatrixOutputs_andMatrixInput_14_93)
node decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_andMatrixOutputs_lo_lo_hi_93, decoded_andMatrixOutputs_lo_lo_lo_58)
node decoded_andMatrixOutputs_lo_hi_lo_93 = cat(decoded_andMatrixOutputs_andMatrixInput_11_93, decoded_andMatrixOutputs_andMatrixInput_12_93)
node decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_andMatrixOutputs_andMatrixInput_10_93)
node decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_andMatrixOutputs_lo_hi_hi_93, decoded_andMatrixOutputs_lo_hi_lo_93)
node decoded_andMatrixOutputs_lo_93 = cat(decoded_andMatrixOutputs_lo_hi_93, decoded_andMatrixOutputs_lo_lo_93)
node decoded_andMatrixOutputs_hi_lo_lo_93 = cat(decoded_andMatrixOutputs_andMatrixInput_7_93, decoded_andMatrixOutputs_andMatrixInput_8_93)
node decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_andMatrixOutputs_andMatrixInput_5_93, decoded_andMatrixOutputs_andMatrixInput_6_93)
node decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_andMatrixOutputs_hi_lo_hi_93, decoded_andMatrixOutputs_hi_lo_lo_93)
node decoded_andMatrixOutputs_hi_hi_lo_93 = cat(decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_andMatrixOutputs_andMatrixInput_4_93)
node decoded_andMatrixOutputs_hi_hi_hi_hi_53 = cat(decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_andMatrixOutputs_andMatrixInput_1_94)
node decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_53, decoded_andMatrixOutputs_andMatrixInput_2_94)
node decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_andMatrixOutputs_hi_hi_hi_93, decoded_andMatrixOutputs_hi_hi_lo_93)
node decoded_andMatrixOutputs_hi_94 = cat(decoded_andMatrixOutputs_hi_hi_93, decoded_andMatrixOutputs_hi_lo_93)
node _decoded_andMatrixOutputs_T_94 = cat(decoded_andMatrixOutputs_hi_94, decoded_andMatrixOutputs_lo_93)
node decoded_andMatrixOutputs_39_2_1 = andr(_decoded_andMatrixOutputs_T_94)
node decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_94 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_94 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_94 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_59 = bits(decoded_plaInput_1, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_54 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_59 = cat(decoded_andMatrixOutputs_andMatrixInput_15_59, decoded_andMatrixOutputs_andMatrixInput_16_54)
node decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_andMatrixOutputs_andMatrixInput_13_94, decoded_andMatrixOutputs_andMatrixInput_14_94)
node decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_andMatrixOutputs_lo_lo_hi_94, decoded_andMatrixOutputs_lo_lo_lo_59)
node decoded_andMatrixOutputs_lo_hi_lo_94 = cat(decoded_andMatrixOutputs_andMatrixInput_11_94, decoded_andMatrixOutputs_andMatrixInput_12_94)
node decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_andMatrixOutputs_andMatrixInput_10_94)
node decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_andMatrixOutputs_lo_hi_hi_94, decoded_andMatrixOutputs_lo_hi_lo_94)
node decoded_andMatrixOutputs_lo_94 = cat(decoded_andMatrixOutputs_lo_hi_94, decoded_andMatrixOutputs_lo_lo_94)
node decoded_andMatrixOutputs_hi_lo_lo_94 = cat(decoded_andMatrixOutputs_andMatrixInput_7_94, decoded_andMatrixOutputs_andMatrixInput_8_94)
node decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_andMatrixOutputs_andMatrixInput_5_94, decoded_andMatrixOutputs_andMatrixInput_6_94)
node decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_andMatrixOutputs_hi_lo_hi_94, decoded_andMatrixOutputs_hi_lo_lo_94)
node decoded_andMatrixOutputs_hi_hi_lo_94 = cat(decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_andMatrixOutputs_andMatrixInput_4_94)
node decoded_andMatrixOutputs_hi_hi_hi_hi_54 = cat(decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_andMatrixOutputs_andMatrixInput_1_95)
node decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_54, decoded_andMatrixOutputs_andMatrixInput_2_95)
node decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_andMatrixOutputs_hi_hi_hi_94, decoded_andMatrixOutputs_hi_hi_lo_94)
node decoded_andMatrixOutputs_hi_95 = cat(decoded_andMatrixOutputs_hi_hi_94, decoded_andMatrixOutputs_hi_lo_94)
node _decoded_andMatrixOutputs_T_95 = cat(decoded_andMatrixOutputs_hi_95, decoded_andMatrixOutputs_lo_94)
node decoded_andMatrixOutputs_7_2_1 = andr(_decoded_andMatrixOutputs_T_95)
node decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_95 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_95 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_14_95 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_andMatrixOutputs_andMatrixInput_12_95, decoded_andMatrixOutputs_andMatrixInput_13_95)
node decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_andMatrixOutputs_lo_lo_hi_95, decoded_andMatrixOutputs_andMatrixInput_14_95)
node decoded_andMatrixOutputs_lo_hi_lo_95 = cat(decoded_andMatrixOutputs_andMatrixInput_10_95, decoded_andMatrixOutputs_andMatrixInput_11_95)
node decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_andMatrixOutputs_andMatrixInput_8_95, decoded_andMatrixOutputs_andMatrixInput_9_95)
node decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_andMatrixOutputs_lo_hi_hi_95, decoded_andMatrixOutputs_lo_hi_lo_95)
node decoded_andMatrixOutputs_lo_95 = cat(decoded_andMatrixOutputs_lo_hi_95, decoded_andMatrixOutputs_lo_lo_95)
node decoded_andMatrixOutputs_hi_lo_lo_95 = cat(decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_andMatrixOutputs_andMatrixInput_7_95)
node decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_andMatrixOutputs_andMatrixInput_4_95, decoded_andMatrixOutputs_andMatrixInput_5_95)
node decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_andMatrixOutputs_hi_lo_hi_95, decoded_andMatrixOutputs_hi_lo_lo_95)
node decoded_andMatrixOutputs_hi_hi_lo_95 = cat(decoded_andMatrixOutputs_andMatrixInput_2_96, decoded_andMatrixOutputs_andMatrixInput_3_95)
node decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_andMatrixOutputs_andMatrixInput_1_96)
node decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_andMatrixOutputs_hi_hi_hi_95, decoded_andMatrixOutputs_hi_hi_lo_95)
node decoded_andMatrixOutputs_hi_96 = cat(decoded_andMatrixOutputs_hi_hi_95, decoded_andMatrixOutputs_hi_lo_95)
node _decoded_andMatrixOutputs_T_96 = cat(decoded_andMatrixOutputs_hi_96, decoded_andMatrixOutputs_lo_95)
node decoded_andMatrixOutputs_18_2_1 = andr(_decoded_andMatrixOutputs_T_96)
node decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_invInputs_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_invInputs_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_96 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_96 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_14_96 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_andMatrixOutputs_andMatrixInput_12_96, decoded_andMatrixOutputs_andMatrixInput_13_96)
node decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_andMatrixOutputs_lo_lo_hi_96, decoded_andMatrixOutputs_andMatrixInput_14_96)
node decoded_andMatrixOutputs_lo_hi_lo_96 = cat(decoded_andMatrixOutputs_andMatrixInput_10_96, decoded_andMatrixOutputs_andMatrixInput_11_96)
node decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_andMatrixOutputs_andMatrixInput_8_96, decoded_andMatrixOutputs_andMatrixInput_9_96)
node decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_andMatrixOutputs_lo_hi_hi_96, decoded_andMatrixOutputs_lo_hi_lo_96)
node decoded_andMatrixOutputs_lo_96 = cat(decoded_andMatrixOutputs_lo_hi_96, decoded_andMatrixOutputs_lo_lo_96)
node decoded_andMatrixOutputs_hi_lo_lo_96 = cat(decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_andMatrixOutputs_andMatrixInput_7_96)
node decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_andMatrixOutputs_andMatrixInput_4_96, decoded_andMatrixOutputs_andMatrixInput_5_96)
node decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_andMatrixOutputs_hi_lo_hi_96, decoded_andMatrixOutputs_hi_lo_lo_96)
node decoded_andMatrixOutputs_hi_hi_lo_96 = cat(decoded_andMatrixOutputs_andMatrixInput_2_97, decoded_andMatrixOutputs_andMatrixInput_3_96)
node decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_andMatrixOutputs_andMatrixInput_1_97)
node decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_andMatrixOutputs_hi_hi_hi_96, decoded_andMatrixOutputs_hi_hi_lo_96)
node decoded_andMatrixOutputs_hi_97 = cat(decoded_andMatrixOutputs_hi_hi_96, decoded_andMatrixOutputs_hi_lo_96)
node _decoded_andMatrixOutputs_T_97 = cat(decoded_andMatrixOutputs_hi_97, decoded_andMatrixOutputs_lo_96)
node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_97)
node decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_invInputs_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_97 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_97 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_97 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_60 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_55 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_60 = cat(decoded_andMatrixOutputs_andMatrixInput_15_60, decoded_andMatrixOutputs_andMatrixInput_16_55)
node decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_andMatrixOutputs_andMatrixInput_13_97, decoded_andMatrixOutputs_andMatrixInput_14_97)
node decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_andMatrixOutputs_lo_lo_hi_97, decoded_andMatrixOutputs_lo_lo_lo_60)
node decoded_andMatrixOutputs_lo_hi_lo_97 = cat(decoded_andMatrixOutputs_andMatrixInput_11_97, decoded_andMatrixOutputs_andMatrixInput_12_97)
node decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_andMatrixOutputs_andMatrixInput_10_97)
node decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_andMatrixOutputs_lo_hi_hi_97, decoded_andMatrixOutputs_lo_hi_lo_97)
node decoded_andMatrixOutputs_lo_97 = cat(decoded_andMatrixOutputs_lo_hi_97, decoded_andMatrixOutputs_lo_lo_97)
node decoded_andMatrixOutputs_hi_lo_lo_97 = cat(decoded_andMatrixOutputs_andMatrixInput_7_97, decoded_andMatrixOutputs_andMatrixInput_8_97)
node decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_andMatrixOutputs_andMatrixInput_5_97, decoded_andMatrixOutputs_andMatrixInput_6_97)
node decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_andMatrixOutputs_hi_lo_hi_97, decoded_andMatrixOutputs_hi_lo_lo_97)
node decoded_andMatrixOutputs_hi_hi_lo_97 = cat(decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_andMatrixOutputs_andMatrixInput_4_97)
node decoded_andMatrixOutputs_hi_hi_hi_hi_55 = cat(decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_andMatrixOutputs_andMatrixInput_1_98)
node decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_55, decoded_andMatrixOutputs_andMatrixInput_2_98)
node decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_andMatrixOutputs_hi_hi_hi_97, decoded_andMatrixOutputs_hi_hi_lo_97)
node decoded_andMatrixOutputs_hi_98 = cat(decoded_andMatrixOutputs_hi_hi_97, decoded_andMatrixOutputs_hi_lo_97)
node _decoded_andMatrixOutputs_T_98 = cat(decoded_andMatrixOutputs_hi_98, decoded_andMatrixOutputs_lo_97)
node decoded_andMatrixOutputs_25_2_1 = andr(_decoded_andMatrixOutputs_T_98)
node decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_invInputs_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_invInputs_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_invInputs_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_plaInput_1, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_invInputs_1, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_invInputs_1, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_invInputs_1, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_98 = bits(decoded_invInputs_1, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_98 = bits(decoded_invInputs_1, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_98 = bits(decoded_plaInput_1, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_61 = bits(decoded_plaInput_1, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_56 = bits(decoded_plaInput_1, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_61 = cat(decoded_andMatrixOutputs_andMatrixInput_15_61, decoded_andMatrixOutputs_andMatrixInput_16_56)
node decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_andMatrixOutputs_andMatrixInput_13_98, decoded_andMatrixOutputs_andMatrixInput_14_98)
node decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_andMatrixOutputs_lo_lo_hi_98, decoded_andMatrixOutputs_lo_lo_lo_61)
node decoded_andMatrixOutputs_lo_hi_lo_98 = cat(decoded_andMatrixOutputs_andMatrixInput_11_98, decoded_andMatrixOutputs_andMatrixInput_12_98)
node decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_andMatrixOutputs_andMatrixInput_10_98)
node decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_andMatrixOutputs_lo_hi_hi_98, decoded_andMatrixOutputs_lo_hi_lo_98)
node decoded_andMatrixOutputs_lo_98 = cat(decoded_andMatrixOutputs_lo_hi_98, decoded_andMatrixOutputs_lo_lo_98)
node decoded_andMatrixOutputs_hi_lo_lo_98 = cat(decoded_andMatrixOutputs_andMatrixInput_7_98, decoded_andMatrixOutputs_andMatrixInput_8_98)
node decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_andMatrixOutputs_andMatrixInput_5_98, decoded_andMatrixOutputs_andMatrixInput_6_98)
node decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_andMatrixOutputs_hi_lo_hi_98, decoded_andMatrixOutputs_hi_lo_lo_98)
node decoded_andMatrixOutputs_hi_hi_lo_98 = cat(decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_andMatrixOutputs_andMatrixInput_4_98)
node decoded_andMatrixOutputs_hi_hi_hi_hi_56 = cat(decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_andMatrixOutputs_andMatrixInput_1_99)
node decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_56, decoded_andMatrixOutputs_andMatrixInput_2_99)
node decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_andMatrixOutputs_hi_hi_hi_98, decoded_andMatrixOutputs_hi_hi_lo_98)
node decoded_andMatrixOutputs_hi_99 = cat(decoded_andMatrixOutputs_hi_hi_98, decoded_andMatrixOutputs_hi_lo_98)
node _decoded_andMatrixOutputs_T_99 = cat(decoded_andMatrixOutputs_hi_99, decoded_andMatrixOutputs_lo_98)
node decoded_andMatrixOutputs_48_2 = andr(_decoded_andMatrixOutputs_T_99)
node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_18_2_1, decoded_andMatrixOutputs_5_2_1)
node decoded_orMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_42_2_1, decoded_andMatrixOutputs_24_2_1)
node decoded_orMatrixOutputs_lo_lo_13 = cat(decoded_orMatrixOutputs_lo_lo_hi_8, decoded_orMatrixOutputs_lo_lo_lo_1)
node decoded_orMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_19_2_1, decoded_andMatrixOutputs_34_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_52_2, decoded_andMatrixOutputs_4_2_1)
node decoded_orMatrixOutputs_lo_hi_15 = cat(decoded_orMatrixOutputs_lo_hi_hi_13, decoded_orMatrixOutputs_lo_hi_lo_6)
node decoded_orMatrixOutputs_lo_25 = cat(decoded_orMatrixOutputs_lo_hi_15, decoded_orMatrixOutputs_lo_lo_13)
node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_31_2_1, decoded_andMatrixOutputs_10_2_1)
node decoded_orMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_46_2, decoded_andMatrixOutputs_2_2_1)
node decoded_orMatrixOutputs_hi_lo_13 = cat(decoded_orMatrixOutputs_hi_lo_hi_8, decoded_orMatrixOutputs_hi_lo_lo_1)
node decoded_orMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_55_2)
node decoded_orMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_25 = cat(decoded_orMatrixOutputs_hi_hi_hi_13, decoded_orMatrixOutputs_hi_hi_lo_6)
node decoded_orMatrixOutputs_hi_29 = cat(decoded_orMatrixOutputs_hi_hi_25, decoded_orMatrixOutputs_hi_lo_13)
node _decoded_orMatrixOutputs_T_56 = cat(decoded_orMatrixOutputs_hi_29, decoded_orMatrixOutputs_lo_25)
node _decoded_orMatrixOutputs_T_57 = orr(_decoded_orMatrixOutputs_T_56)
node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_18_2_1, decoded_andMatrixOutputs_5_2_1)
node decoded_orMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_42_2_1, decoded_andMatrixOutputs_24_2_1)
node decoded_orMatrixOutputs_lo_lo_14 = cat(decoded_orMatrixOutputs_lo_lo_hi_9, decoded_orMatrixOutputs_lo_lo_lo_2)
node decoded_orMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_19_2_1, decoded_andMatrixOutputs_34_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_52_2, decoded_andMatrixOutputs_4_2_1)
node decoded_orMatrixOutputs_lo_hi_16 = cat(decoded_orMatrixOutputs_lo_hi_hi_14, decoded_orMatrixOutputs_lo_hi_lo_7)
node decoded_orMatrixOutputs_lo_26 = cat(decoded_orMatrixOutputs_lo_hi_16, decoded_orMatrixOutputs_lo_lo_14)
node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_31_2_1, decoded_andMatrixOutputs_10_2_1)
node decoded_orMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_46_2, decoded_andMatrixOutputs_2_2_1)
node decoded_orMatrixOutputs_hi_lo_14 = cat(decoded_orMatrixOutputs_hi_lo_hi_9, decoded_orMatrixOutputs_hi_lo_lo_2)
node decoded_orMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_55_2)
node decoded_orMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_26 = cat(decoded_orMatrixOutputs_hi_hi_hi_14, decoded_orMatrixOutputs_hi_hi_lo_7)
node decoded_orMatrixOutputs_hi_30 = cat(decoded_orMatrixOutputs_hi_hi_26, decoded_orMatrixOutputs_hi_lo_14)
node _decoded_orMatrixOutputs_T_58 = cat(decoded_orMatrixOutputs_hi_30, decoded_orMatrixOutputs_lo_26)
node _decoded_orMatrixOutputs_T_59 = orr(_decoded_orMatrixOutputs_T_58)
node decoded_orMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_18_2_1, decoded_andMatrixOutputs_5_2_1)
node decoded_orMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_42_2_1, decoded_andMatrixOutputs_24_2_1)
node decoded_orMatrixOutputs_lo_lo_15 = cat(decoded_orMatrixOutputs_lo_lo_hi_10, decoded_orMatrixOutputs_lo_lo_lo_3)
node decoded_orMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_19_2_1, decoded_andMatrixOutputs_34_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_52_2, decoded_andMatrixOutputs_4_2_1)
node decoded_orMatrixOutputs_lo_hi_17 = cat(decoded_orMatrixOutputs_lo_hi_hi_15, decoded_orMatrixOutputs_lo_hi_lo_8)
node decoded_orMatrixOutputs_lo_27 = cat(decoded_orMatrixOutputs_lo_hi_17, decoded_orMatrixOutputs_lo_lo_15)
node decoded_orMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_31_2_1, decoded_andMatrixOutputs_10_2_1)
node decoded_orMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_46_2, decoded_andMatrixOutputs_2_2_1)
node decoded_orMatrixOutputs_hi_lo_15 = cat(decoded_orMatrixOutputs_hi_lo_hi_10, decoded_orMatrixOutputs_hi_lo_lo_3)
node decoded_orMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_55_2)
node decoded_orMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_27 = cat(decoded_orMatrixOutputs_hi_hi_hi_15, decoded_orMatrixOutputs_hi_hi_lo_8)
node decoded_orMatrixOutputs_hi_31 = cat(decoded_orMatrixOutputs_hi_hi_27, decoded_orMatrixOutputs_hi_lo_15)
node _decoded_orMatrixOutputs_T_60 = cat(decoded_orMatrixOutputs_hi_31, decoded_orMatrixOutputs_lo_27)
node _decoded_orMatrixOutputs_T_61 = orr(_decoded_orMatrixOutputs_T_60)
node decoded_orMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_34_2_1, decoded_andMatrixOutputs_45_2)
node decoded_orMatrixOutputs_lo_lo_16 = cat(decoded_orMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_35_2_1)
node decoded_orMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_4_2_1, decoded_andMatrixOutputs_19_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_10_2_1, decoded_andMatrixOutputs_52_2)
node decoded_orMatrixOutputs_lo_hi_18 = cat(decoded_orMatrixOutputs_lo_hi_hi_16, decoded_orMatrixOutputs_lo_hi_lo_9)
node decoded_orMatrixOutputs_lo_28 = cat(decoded_orMatrixOutputs_lo_hi_18, decoded_orMatrixOutputs_lo_lo_16)
node decoded_orMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_46_2, decoded_andMatrixOutputs_2_2_1)
node decoded_orMatrixOutputs_hi_lo_16 = cat(decoded_orMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_31_2_1)
node decoded_orMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_55_2)
node decoded_orMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_28 = cat(decoded_orMatrixOutputs_hi_hi_hi_16, decoded_orMatrixOutputs_hi_hi_lo_9)
node decoded_orMatrixOutputs_hi_32 = cat(decoded_orMatrixOutputs_hi_hi_28, decoded_orMatrixOutputs_hi_lo_16)
node _decoded_orMatrixOutputs_T_62 = cat(decoded_orMatrixOutputs_hi_32, decoded_orMatrixOutputs_lo_28)
node _decoded_orMatrixOutputs_T_63 = orr(_decoded_orMatrixOutputs_T_62)
node decoded_orMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_4_2_1, decoded_andMatrixOutputs_19_2_1)
node decoded_orMatrixOutputs_lo_lo_17 = cat(decoded_orMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_34_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_31_2_1, decoded_andMatrixOutputs_10_2_1)
node decoded_orMatrixOutputs_lo_hi_19 = cat(decoded_orMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_52_2)
node decoded_orMatrixOutputs_lo_29 = cat(decoded_orMatrixOutputs_lo_hi_19, decoded_orMatrixOutputs_lo_lo_17)
node decoded_orMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_55_2, decoded_andMatrixOutputs_46_2)
node decoded_orMatrixOutputs_hi_lo_17 = cat(decoded_orMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_2_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_29 = cat(decoded_orMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_9_2_1)
node decoded_orMatrixOutputs_hi_33 = cat(decoded_orMatrixOutputs_hi_hi_29, decoded_orMatrixOutputs_hi_lo_17)
node _decoded_orMatrixOutputs_T_64 = cat(decoded_orMatrixOutputs_hi_33, decoded_orMatrixOutputs_lo_29)
node _decoded_orMatrixOutputs_T_65 = orr(_decoded_orMatrixOutputs_T_64)
node decoded_orMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_4_2_1, decoded_andMatrixOutputs_19_2_1)
node decoded_orMatrixOutputs_lo_lo_18 = cat(decoded_orMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_32_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_33_2_1, decoded_andMatrixOutputs_10_2_1)
node decoded_orMatrixOutputs_lo_hi_20 = cat(decoded_orMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_52_2)
node decoded_orMatrixOutputs_lo_30 = cat(decoded_orMatrixOutputs_lo_hi_20, decoded_orMatrixOutputs_lo_lo_18)
node decoded_orMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_55_2, decoded_andMatrixOutputs_46_2)
node decoded_orMatrixOutputs_hi_lo_18 = cat(decoded_orMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_49_2)
node decoded_orMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_30 = cat(decoded_orMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_9_2_1)
node decoded_orMatrixOutputs_hi_34 = cat(decoded_orMatrixOutputs_hi_hi_30, decoded_orMatrixOutputs_hi_lo_18)
node _decoded_orMatrixOutputs_T_66 = cat(decoded_orMatrixOutputs_hi_34, decoded_orMatrixOutputs_lo_30)
node _decoded_orMatrixOutputs_T_67 = orr(_decoded_orMatrixOutputs_T_66)
node decoded_orMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_52_2, decoded_andMatrixOutputs_44_2)
node decoded_orMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_50_2, decoded_andMatrixOutputs_10_2_1)
node decoded_orMatrixOutputs_lo_31 = cat(decoded_orMatrixOutputs_lo_hi_21, decoded_orMatrixOutputs_lo_lo_19)
node decoded_orMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_9_2_1, decoded_andMatrixOutputs_55_2)
node decoded_orMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_51_2, decoded_andMatrixOutputs_1_2_1)
node decoded_orMatrixOutputs_hi_hi_31 = cat(decoded_orMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_20_2_1)
node decoded_orMatrixOutputs_hi_35 = cat(decoded_orMatrixOutputs_hi_hi_31, decoded_orMatrixOutputs_hi_lo_19)
node _decoded_orMatrixOutputs_T_68 = cat(decoded_orMatrixOutputs_hi_35, decoded_orMatrixOutputs_lo_31)
node _decoded_orMatrixOutputs_T_69 = orr(_decoded_orMatrixOutputs_T_68)
node _decoded_orMatrixOutputs_T_70 = cat(decoded_andMatrixOutputs_12_2_1, decoded_andMatrixOutputs_27_2_1)
node _decoded_orMatrixOutputs_T_71 = orr(_decoded_orMatrixOutputs_T_70)
node decoded_orMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_25_2_1, decoded_andMatrixOutputs_48_2)
node decoded_orMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_39_2_1, decoded_andMatrixOutputs_7_2_1)
node decoded_orMatrixOutputs_lo_lo_20 = cat(decoded_orMatrixOutputs_lo_lo_hi_14, decoded_orMatrixOutputs_lo_lo_lo_4)
node decoded_orMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_17_2_1, decoded_andMatrixOutputs_41_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_36_2_1)
node decoded_orMatrixOutputs_lo_hi_22 = cat(decoded_orMatrixOutputs_lo_hi_hi_19, decoded_orMatrixOutputs_lo_hi_lo_10)
node decoded_orMatrixOutputs_lo_32 = cat(decoded_orMatrixOutputs_lo_hi_22, decoded_orMatrixOutputs_lo_lo_20)
node decoded_orMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_30_2_1, decoded_andMatrixOutputs_22_2_1)
node decoded_orMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_29_2_1, decoded_andMatrixOutputs_53_2)
node decoded_orMatrixOutputs_hi_lo_20 = cat(decoded_orMatrixOutputs_hi_lo_hi_14, decoded_orMatrixOutputs_hi_lo_lo_4)
node decoded_orMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_37_2_1, decoded_andMatrixOutputs_13_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_32 = cat(decoded_orMatrixOutputs_hi_hi_hi_20, decoded_orMatrixOutputs_hi_hi_lo_10)
node decoded_orMatrixOutputs_hi_36 = cat(decoded_orMatrixOutputs_hi_hi_32, decoded_orMatrixOutputs_hi_lo_20)
node _decoded_orMatrixOutputs_T_72 = cat(decoded_orMatrixOutputs_hi_36, decoded_orMatrixOutputs_lo_32)
node _decoded_orMatrixOutputs_T_73 = orr(_decoded_orMatrixOutputs_T_72)
node decoded_orMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_25_2_1, decoded_andMatrixOutputs_48_2)
node decoded_orMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_39_2_1, decoded_andMatrixOutputs_7_2_1)
node decoded_orMatrixOutputs_lo_lo_21 = cat(decoded_orMatrixOutputs_lo_lo_hi_15, decoded_orMatrixOutputs_lo_lo_lo_5)
node decoded_orMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_17_2_1, decoded_andMatrixOutputs_41_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_36_2_1)
node decoded_orMatrixOutputs_lo_hi_23 = cat(decoded_orMatrixOutputs_lo_hi_hi_20, decoded_orMatrixOutputs_lo_hi_lo_11)
node decoded_orMatrixOutputs_lo_33 = cat(decoded_orMatrixOutputs_lo_hi_23, decoded_orMatrixOutputs_lo_lo_21)
node decoded_orMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_30_2_1, decoded_andMatrixOutputs_22_2_1)
node decoded_orMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_29_2_1, decoded_andMatrixOutputs_53_2)
node decoded_orMatrixOutputs_hi_lo_21 = cat(decoded_orMatrixOutputs_hi_lo_hi_15, decoded_orMatrixOutputs_hi_lo_lo_5)
node decoded_orMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_37_2_1, decoded_andMatrixOutputs_13_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_33 = cat(decoded_orMatrixOutputs_hi_hi_hi_21, decoded_orMatrixOutputs_hi_hi_lo_11)
node decoded_orMatrixOutputs_hi_37 = cat(decoded_orMatrixOutputs_hi_hi_33, decoded_orMatrixOutputs_hi_lo_21)
node _decoded_orMatrixOutputs_T_74 = cat(decoded_orMatrixOutputs_hi_37, decoded_orMatrixOutputs_lo_33)
node _decoded_orMatrixOutputs_T_75 = orr(_decoded_orMatrixOutputs_T_74)
node decoded_orMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_25_2_1, decoded_andMatrixOutputs_48_2)
node decoded_orMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_39_2_1, decoded_andMatrixOutputs_7_2_1)
node decoded_orMatrixOutputs_lo_lo_22 = cat(decoded_orMatrixOutputs_lo_lo_hi_16, decoded_orMatrixOutputs_lo_lo_lo_6)
node decoded_orMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_17_2_1, decoded_andMatrixOutputs_41_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_36_2_1)
node decoded_orMatrixOutputs_lo_hi_24 = cat(decoded_orMatrixOutputs_lo_hi_hi_21, decoded_orMatrixOutputs_lo_hi_lo_12)
node decoded_orMatrixOutputs_lo_34 = cat(decoded_orMatrixOutputs_lo_hi_24, decoded_orMatrixOutputs_lo_lo_22)
node decoded_orMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_30_2_1, decoded_andMatrixOutputs_22_2_1)
node decoded_orMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_29_2_1, decoded_andMatrixOutputs_53_2)
node decoded_orMatrixOutputs_hi_lo_22 = cat(decoded_orMatrixOutputs_hi_lo_hi_16, decoded_orMatrixOutputs_hi_lo_lo_6)
node decoded_orMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_37_2_1, decoded_andMatrixOutputs_13_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_34 = cat(decoded_orMatrixOutputs_hi_hi_hi_22, decoded_orMatrixOutputs_hi_hi_lo_12)
node decoded_orMatrixOutputs_hi_38 = cat(decoded_orMatrixOutputs_hi_hi_34, decoded_orMatrixOutputs_hi_lo_22)
node _decoded_orMatrixOutputs_T_76 = cat(decoded_orMatrixOutputs_hi_38, decoded_orMatrixOutputs_lo_34)
node _decoded_orMatrixOutputs_T_77 = orr(_decoded_orMatrixOutputs_T_76)
node decoded_orMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_41_2_1, decoded_andMatrixOutputs_14_2_1)
node decoded_orMatrixOutputs_lo_lo_23 = cat(decoded_orMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_21_2_1)
node decoded_orMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_36_2_1, decoded_andMatrixOutputs_17_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_22_2_1, decoded_andMatrixOutputs_0_2_1)
node decoded_orMatrixOutputs_lo_hi_25 = cat(decoded_orMatrixOutputs_lo_hi_hi_22, decoded_orMatrixOutputs_lo_hi_lo_13)
node decoded_orMatrixOutputs_lo_35 = cat(decoded_orMatrixOutputs_lo_hi_25, decoded_orMatrixOutputs_lo_lo_23)
node decoded_orMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_29_2_1, decoded_andMatrixOutputs_53_2)
node decoded_orMatrixOutputs_hi_lo_23 = cat(decoded_orMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_30_2_1)
node decoded_orMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_37_2_1, decoded_andMatrixOutputs_13_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_35 = cat(decoded_orMatrixOutputs_hi_hi_hi_23, decoded_orMatrixOutputs_hi_hi_lo_13)
node decoded_orMatrixOutputs_hi_39 = cat(decoded_orMatrixOutputs_hi_hi_35, decoded_orMatrixOutputs_hi_lo_23)
node _decoded_orMatrixOutputs_T_78 = cat(decoded_orMatrixOutputs_hi_39, decoded_orMatrixOutputs_lo_35)
node _decoded_orMatrixOutputs_T_79 = orr(_decoded_orMatrixOutputs_T_78)
node decoded_orMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_36_2_1, decoded_andMatrixOutputs_17_2_1)
node decoded_orMatrixOutputs_lo_lo_24 = cat(decoded_orMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_41_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_30_2_1, decoded_andMatrixOutputs_22_2_1)
node decoded_orMatrixOutputs_lo_hi_26 = cat(decoded_orMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_0_2_1)
node decoded_orMatrixOutputs_lo_36 = cat(decoded_orMatrixOutputs_lo_hi_26, decoded_orMatrixOutputs_lo_lo_24)
node decoded_orMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_13_2_1, decoded_andMatrixOutputs_29_2_1)
node decoded_orMatrixOutputs_hi_lo_24 = cat(decoded_orMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_53_2)
node decoded_orMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_36 = cat(decoded_orMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_37_2_1)
node decoded_orMatrixOutputs_hi_40 = cat(decoded_orMatrixOutputs_hi_hi_36, decoded_orMatrixOutputs_hi_lo_24)
node _decoded_orMatrixOutputs_T_80 = cat(decoded_orMatrixOutputs_hi_40, decoded_orMatrixOutputs_lo_36)
node _decoded_orMatrixOutputs_T_81 = orr(_decoded_orMatrixOutputs_T_80)
node decoded_orMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_36_2_1, decoded_andMatrixOutputs_17_2_1)
node decoded_orMatrixOutputs_lo_lo_25 = cat(decoded_orMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_41_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_16_2_1, decoded_andMatrixOutputs_22_2_1)
node decoded_orMatrixOutputs_lo_hi_27 = cat(decoded_orMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_0_2_1)
node decoded_orMatrixOutputs_lo_37 = cat(decoded_orMatrixOutputs_lo_hi_27, decoded_orMatrixOutputs_lo_lo_25)
node decoded_orMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_13_2_1, decoded_andMatrixOutputs_29_2_1)
node decoded_orMatrixOutputs_hi_lo_25 = cat(decoded_orMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_3_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_37 = cat(decoded_orMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_37_2_1)
node decoded_orMatrixOutputs_hi_41 = cat(decoded_orMatrixOutputs_hi_hi_37, decoded_orMatrixOutputs_hi_lo_25)
node _decoded_orMatrixOutputs_T_82 = cat(decoded_orMatrixOutputs_hi_41, decoded_orMatrixOutputs_lo_37)
node _decoded_orMatrixOutputs_T_83 = orr(_decoded_orMatrixOutputs_T_82)
node decoded_orMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_36_2_1)
node decoded_orMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_29_2_1, decoded_andMatrixOutputs_22_2_1)
node decoded_orMatrixOutputs_lo_38 = cat(decoded_orMatrixOutputs_lo_hi_28, decoded_orMatrixOutputs_lo_lo_26)
node decoded_orMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_37_2_1, decoded_andMatrixOutputs_13_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_43_2_1, decoded_andMatrixOutputs_38_2_1)
node decoded_orMatrixOutputs_hi_hi_38 = cat(decoded_orMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_6_2_1)
node decoded_orMatrixOutputs_hi_42 = cat(decoded_orMatrixOutputs_hi_hi_38, decoded_orMatrixOutputs_hi_lo_26)
node _decoded_orMatrixOutputs_T_84 = cat(decoded_orMatrixOutputs_hi_42, decoded_orMatrixOutputs_lo_38)
node _decoded_orMatrixOutputs_T_85 = orr(_decoded_orMatrixOutputs_T_84)
node _decoded_orMatrixOutputs_T_86 = orr(decoded_andMatrixOutputs_23_2_1)
node decoded_orMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_28_2_1, decoded_andMatrixOutputs_47_2)
node decoded_orMatrixOutputs_lo_hi_29 = cat(decoded_andMatrixOutputs_26_2_1, decoded_andMatrixOutputs_40_2_1)
node decoded_orMatrixOutputs_lo_39 = cat(decoded_orMatrixOutputs_lo_hi_29, decoded_orMatrixOutputs_lo_lo_27)
node decoded_orMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_8_2_1, decoded_andMatrixOutputs_15_2_1)
node decoded_orMatrixOutputs_hi_hi_39 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node decoded_orMatrixOutputs_hi_43 = cat(decoded_orMatrixOutputs_hi_hi_39, decoded_orMatrixOutputs_hi_lo_27)
node _decoded_orMatrixOutputs_T_87 = cat(decoded_orMatrixOutputs_hi_43, decoded_orMatrixOutputs_lo_39)
node _decoded_orMatrixOutputs_T_88 = orr(_decoded_orMatrixOutputs_T_87)
node decoded_orMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_28_2_1, decoded_andMatrixOutputs_47_2)
node decoded_orMatrixOutputs_lo_hi_30 = cat(decoded_andMatrixOutputs_26_2_1, decoded_andMatrixOutputs_40_2_1)
node decoded_orMatrixOutputs_lo_40 = cat(decoded_orMatrixOutputs_lo_hi_30, decoded_orMatrixOutputs_lo_lo_28)
node decoded_orMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_8_2_1, decoded_andMatrixOutputs_15_2_1)
node decoded_orMatrixOutputs_hi_hi_40 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node decoded_orMatrixOutputs_hi_44 = cat(decoded_orMatrixOutputs_hi_hi_40, decoded_orMatrixOutputs_hi_lo_28)
node _decoded_orMatrixOutputs_T_89 = cat(decoded_orMatrixOutputs_hi_44, decoded_orMatrixOutputs_lo_40)
node _decoded_orMatrixOutputs_T_90 = orr(_decoded_orMatrixOutputs_T_89)
node decoded_orMatrixOutputs_lo_lo_29 = cat(decoded_andMatrixOutputs_28_2_1, decoded_andMatrixOutputs_47_2)
node decoded_orMatrixOutputs_lo_hi_31 = cat(decoded_andMatrixOutputs_26_2_1, decoded_andMatrixOutputs_40_2_1)
node decoded_orMatrixOutputs_lo_41 = cat(decoded_orMatrixOutputs_lo_hi_31, decoded_orMatrixOutputs_lo_lo_29)
node decoded_orMatrixOutputs_hi_lo_29 = cat(decoded_andMatrixOutputs_8_2_1, decoded_andMatrixOutputs_15_2_1)
node decoded_orMatrixOutputs_hi_hi_41 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node decoded_orMatrixOutputs_hi_45 = cat(decoded_orMatrixOutputs_hi_hi_41, decoded_orMatrixOutputs_hi_lo_29)
node _decoded_orMatrixOutputs_T_91 = cat(decoded_orMatrixOutputs_hi_45, decoded_orMatrixOutputs_lo_41)
node _decoded_orMatrixOutputs_T_92 = orr(_decoded_orMatrixOutputs_T_91)
node decoded_orMatrixOutputs_lo_lo_30 = cat(decoded_andMatrixOutputs_28_2_1, decoded_andMatrixOutputs_47_2)
node decoded_orMatrixOutputs_lo_hi_32 = cat(decoded_andMatrixOutputs_26_2_1, decoded_andMatrixOutputs_40_2_1)
node decoded_orMatrixOutputs_lo_42 = cat(decoded_orMatrixOutputs_lo_hi_32, decoded_orMatrixOutputs_lo_lo_30)
node decoded_orMatrixOutputs_hi_lo_30 = cat(decoded_andMatrixOutputs_8_2_1, decoded_andMatrixOutputs_15_2_1)
node decoded_orMatrixOutputs_hi_hi_42 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node decoded_orMatrixOutputs_hi_46 = cat(decoded_orMatrixOutputs_hi_hi_42, decoded_orMatrixOutputs_hi_lo_30)
node _decoded_orMatrixOutputs_T_93 = cat(decoded_orMatrixOutputs_hi_46, decoded_orMatrixOutputs_lo_42)
node _decoded_orMatrixOutputs_T_94 = orr(_decoded_orMatrixOutputs_T_93)
node decoded_orMatrixOutputs_lo_hi_33 = cat(decoded_andMatrixOutputs_15_2_1, decoded_andMatrixOutputs_26_2_1)
node decoded_orMatrixOutputs_lo_43 = cat(decoded_orMatrixOutputs_lo_hi_33, decoded_andMatrixOutputs_40_2_1)
node decoded_orMatrixOutputs_hi_hi_43 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node decoded_orMatrixOutputs_hi_47 = cat(decoded_orMatrixOutputs_hi_hi_43, decoded_andMatrixOutputs_8_2_1)
node _decoded_orMatrixOutputs_T_95 = cat(decoded_orMatrixOutputs_hi_47, decoded_orMatrixOutputs_lo_43)
node _decoded_orMatrixOutputs_T_96 = orr(_decoded_orMatrixOutputs_T_95)
node decoded_orMatrixOutputs_lo_hi_34 = cat(decoded_andMatrixOutputs_15_2_1, decoded_andMatrixOutputs_26_2_1)
node decoded_orMatrixOutputs_lo_44 = cat(decoded_orMatrixOutputs_lo_hi_34, decoded_andMatrixOutputs_40_2_1)
node decoded_orMatrixOutputs_hi_hi_44 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node decoded_orMatrixOutputs_hi_48 = cat(decoded_orMatrixOutputs_hi_hi_44, decoded_andMatrixOutputs_8_2_1)
node _decoded_orMatrixOutputs_T_97 = cat(decoded_orMatrixOutputs_hi_48, decoded_orMatrixOutputs_lo_44)
node _decoded_orMatrixOutputs_T_98 = orr(_decoded_orMatrixOutputs_T_97)
node _decoded_orMatrixOutputs_T_99 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node _decoded_orMatrixOutputs_T_100 = orr(_decoded_orMatrixOutputs_T_99)
node _decoded_orMatrixOutputs_T_101 = cat(decoded_andMatrixOutputs_11_2_1, decoded_andMatrixOutputs_54_2)
node _decoded_orMatrixOutputs_T_102 = orr(_decoded_orMatrixOutputs_T_101)
node decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(_decoded_orMatrixOutputs_T_59, _decoded_orMatrixOutputs_T_57)
node decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_65, _decoded_orMatrixOutputs_T_63)
node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _decoded_orMatrixOutputs_T_61)
node decoded_orMatrixOutputs_lo_lo_lo_7 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_lo_1)
node decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_69, _decoded_orMatrixOutputs_T_67)
node decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, _decoded_orMatrixOutputs_T_71)
node decoded_orMatrixOutputs_lo_lo_hi_20 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, decoded_orMatrixOutputs_lo_lo_hi_lo_1)
node decoded_orMatrixOutputs_lo_lo_31 = cat(decoded_orMatrixOutputs_lo_lo_hi_20, decoded_orMatrixOutputs_lo_lo_lo_7)
node decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_lo_14 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, decoded_orMatrixOutputs_lo_hi_lo_lo_1)
node decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_73, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_79, _decoded_orMatrixOutputs_T_77)
node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, _decoded_orMatrixOutputs_T_75)
node decoded_orMatrixOutputs_lo_hi_hi_25 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoded_orMatrixOutputs_lo_hi_hi_lo_1)
node decoded_orMatrixOutputs_lo_hi_35 = cat(decoded_orMatrixOutputs_lo_hi_hi_25, decoded_orMatrixOutputs_lo_hi_lo_14)
node decoded_orMatrixOutputs_lo_45 = cat(decoded_orMatrixOutputs_lo_hi_35, decoded_orMatrixOutputs_lo_lo_31)
node decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(_decoded_orMatrixOutputs_T_83, _decoded_orMatrixOutputs_T_81)
node decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_86)
node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _decoded_orMatrixOutputs_T_85)
node decoded_orMatrixOutputs_hi_lo_lo_7 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_lo_1)
node decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_hi_20 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoded_orMatrixOutputs_hi_lo_hi_lo_1)
node decoded_orMatrixOutputs_hi_lo_31 = cat(decoded_orMatrixOutputs_hi_lo_hi_20, decoded_orMatrixOutputs_hi_lo_lo_7)
node decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_92, _decoded_orMatrixOutputs_T_90)
node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, _decoded_orMatrixOutputs_T_88)
node decoded_orMatrixOutputs_hi_hi_lo_14 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, decoded_orMatrixOutputs_hi_hi_lo_lo_1)
node decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_96, _decoded_orMatrixOutputs_T_94)
node decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_102, _decoded_orMatrixOutputs_T_100)
node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, _decoded_orMatrixOutputs_T_98)
node decoded_orMatrixOutputs_hi_hi_hi_27 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoded_orMatrixOutputs_hi_hi_hi_lo_1)
node decoded_orMatrixOutputs_hi_hi_45 = cat(decoded_orMatrixOutputs_hi_hi_hi_27, decoded_orMatrixOutputs_hi_hi_lo_14)
node decoded_orMatrixOutputs_hi_49 = cat(decoded_orMatrixOutputs_hi_hi_45, decoded_orMatrixOutputs_hi_lo_31)
node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_49, decoded_orMatrixOutputs_lo_45)
node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 0, 0)
node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 1, 1)
node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 2, 2)
node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 3, 3)
node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 4, 4)
node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 5, 5)
node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 6, 6)
node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 7, 7)
node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_1, 8, 8)
node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_1, 9, 9)
node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_1, 10, 10)
node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_1, 11, 11)
node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_1, 12, 12)
node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_1, 13, 13)
node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_1, 14, 14)
node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_1, 15, 15)
node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_1, 16, 16)
node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_1, 17, 17)
node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_1, 18, 18)
node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_1, 19, 19)
node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_1, 20, 20)
node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_1, 21, 21)
node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_1, 22, 22)
node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_1, 23, 23)
node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_1, 24, 24)
node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_1, 25, 25)
node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_1, 26, 26)
node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_1, 27, 27)
node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_1, 28, 28)
node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_1, 29, 29)
node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_1, 30, 30)
node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_1, 31, 31)
node _decoded_invMatrixOutputs_T_72 = bits(decoded_orMatrixOutputs_1, 32, 32)
node _decoded_invMatrixOutputs_T_73 = bits(decoded_orMatrixOutputs_1, 33, 33)
node _decoded_invMatrixOutputs_T_74 = bits(decoded_orMatrixOutputs_1, 34, 34)
node _decoded_invMatrixOutputs_T_75 = bits(decoded_orMatrixOutputs_1, 35, 35)
node _decoded_invMatrixOutputs_T_76 = bits(decoded_orMatrixOutputs_1, 36, 36)
node _decoded_invMatrixOutputs_T_77 = bits(decoded_orMatrixOutputs_1, 37, 37)
node _decoded_invMatrixOutputs_T_78 = bits(decoded_orMatrixOutputs_1, 38, 38)
node _decoded_invMatrixOutputs_T_79 = bits(decoded_orMatrixOutputs_1, 39, 39)
node decoded_invMatrixOutputs_lo_lo_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_41, _decoded_invMatrixOutputs_T_40)
node decoded_invMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43)
node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_hi_1, _decoded_invMatrixOutputs_T_42)
node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_lo_1)
node decoded_invMatrixOutputs_lo_lo_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_46, _decoded_invMatrixOutputs_T_45)
node decoded_invMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_49, _decoded_invMatrixOutputs_T_48)
node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_hi_1, _decoded_invMatrixOutputs_T_47)
node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, decoded_invMatrixOutputs_lo_lo_hi_lo_1)
node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1)
node decoded_invMatrixOutputs_lo_hi_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_51, _decoded_invMatrixOutputs_T_50)
node decoded_invMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_54, _decoded_invMatrixOutputs_T_53)
node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_hi_1, _decoded_invMatrixOutputs_T_52)
node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, decoded_invMatrixOutputs_lo_hi_lo_lo_1)
node decoded_invMatrixOutputs_lo_hi_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_56, _decoded_invMatrixOutputs_T_55)
node decoded_invMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58)
node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_hi_1, _decoded_invMatrixOutputs_T_57)
node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, decoded_invMatrixOutputs_lo_hi_hi_lo_1)
node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1)
node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1)
node decoded_invMatrixOutputs_hi_lo_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_61, _decoded_invMatrixOutputs_T_60)
node decoded_invMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_64, _decoded_invMatrixOutputs_T_63)
node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_hi_1, _decoded_invMatrixOutputs_T_62)
node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_lo_1)
node decoded_invMatrixOutputs_hi_lo_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_66, _decoded_invMatrixOutputs_T_65)
node decoded_invMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_69, _decoded_invMatrixOutputs_T_68)
node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_hi_1, _decoded_invMatrixOutputs_T_67)
node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, decoded_invMatrixOutputs_hi_lo_hi_lo_1)
node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1)
node decoded_invMatrixOutputs_hi_hi_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_71, _decoded_invMatrixOutputs_T_70)
node decoded_invMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_74, _decoded_invMatrixOutputs_T_73)
node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_hi_1, _decoded_invMatrixOutputs_T_72)
node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, decoded_invMatrixOutputs_hi_hi_lo_lo_1)
node decoded_invMatrixOutputs_hi_hi_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_76, _decoded_invMatrixOutputs_T_75)
node decoded_invMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_79, _decoded_invMatrixOutputs_T_78)
node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_hi_1, _decoded_invMatrixOutputs_T_77)
node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_hi_lo_1)
node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1)
node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1)
node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1)
connect decoded_plaOutput_1, decoded_invMatrixOutputs_1
connect decoded_plaInput_1, addr_1
node _decoded_T_80 = bits(decoded_plaOutput_1, 31, 0)
node _decoded_T_81 = shl(UInt<16>(0hffff), 16)
node _decoded_T_82 = xor(UInt<32>(0hffffffff), _decoded_T_81)
node _decoded_T_83 = shr(_decoded_T_80, 16)
node _decoded_T_84 = and(_decoded_T_83, _decoded_T_82)
node _decoded_T_85 = bits(_decoded_T_80, 15, 0)
node _decoded_T_86 = shl(_decoded_T_85, 16)
node _decoded_T_87 = not(_decoded_T_82)
node _decoded_T_88 = and(_decoded_T_86, _decoded_T_87)
node _decoded_T_89 = or(_decoded_T_84, _decoded_T_88)
node _decoded_T_90 = bits(_decoded_T_82, 23, 0)
node _decoded_T_91 = shl(_decoded_T_90, 8)
node _decoded_T_92 = xor(_decoded_T_82, _decoded_T_91)
node _decoded_T_93 = shr(_decoded_T_89, 8)
node _decoded_T_94 = and(_decoded_T_93, _decoded_T_92)
node _decoded_T_95 = bits(_decoded_T_89, 23, 0)
node _decoded_T_96 = shl(_decoded_T_95, 8)
node _decoded_T_97 = not(_decoded_T_92)
node _decoded_T_98 = and(_decoded_T_96, _decoded_T_97)
node _decoded_T_99 = or(_decoded_T_94, _decoded_T_98)
node _decoded_T_100 = bits(_decoded_T_92, 27, 0)
node _decoded_T_101 = shl(_decoded_T_100, 4)
node _decoded_T_102 = xor(_decoded_T_92, _decoded_T_101)
node _decoded_T_103 = shr(_decoded_T_99, 4)
node _decoded_T_104 = and(_decoded_T_103, _decoded_T_102)
node _decoded_T_105 = bits(_decoded_T_99, 27, 0)
node _decoded_T_106 = shl(_decoded_T_105, 4)
node _decoded_T_107 = not(_decoded_T_102)
node _decoded_T_108 = and(_decoded_T_106, _decoded_T_107)
node _decoded_T_109 = or(_decoded_T_104, _decoded_T_108)
node _decoded_T_110 = bits(_decoded_T_102, 29, 0)
node _decoded_T_111 = shl(_decoded_T_110, 2)
node _decoded_T_112 = xor(_decoded_T_102, _decoded_T_111)
node _decoded_T_113 = shr(_decoded_T_109, 2)
node _decoded_T_114 = and(_decoded_T_113, _decoded_T_112)
node _decoded_T_115 = bits(_decoded_T_109, 29, 0)
node _decoded_T_116 = shl(_decoded_T_115, 2)
node _decoded_T_117 = not(_decoded_T_112)
node _decoded_T_118 = and(_decoded_T_116, _decoded_T_117)
node _decoded_T_119 = or(_decoded_T_114, _decoded_T_118)
node _decoded_T_120 = bits(_decoded_T_112, 30, 0)
node _decoded_T_121 = shl(_decoded_T_120, 1)
node _decoded_T_122 = xor(_decoded_T_112, _decoded_T_121)
node _decoded_T_123 = shr(_decoded_T_119, 1)
node _decoded_T_124 = and(_decoded_T_123, _decoded_T_122)
node _decoded_T_125 = bits(_decoded_T_119, 30, 0)
node _decoded_T_126 = shl(_decoded_T_125, 1)
node _decoded_T_127 = not(_decoded_T_122)
node _decoded_T_128 = and(_decoded_T_126, _decoded_T_127)
node _decoded_T_129 = or(_decoded_T_124, _decoded_T_128)
node _decoded_T_130 = bits(decoded_plaOutput_1, 39, 32)
node _decoded_T_131 = shl(UInt<4>(0hf), 4)
node _decoded_T_132 = xor(UInt<8>(0hff), _decoded_T_131)
node _decoded_T_133 = shr(_decoded_T_130, 4)
node _decoded_T_134 = and(_decoded_T_133, _decoded_T_132)
node _decoded_T_135 = bits(_decoded_T_130, 3, 0)
node _decoded_T_136 = shl(_decoded_T_135, 4)
node _decoded_T_137 = not(_decoded_T_132)
node _decoded_T_138 = and(_decoded_T_136, _decoded_T_137)
node _decoded_T_139 = or(_decoded_T_134, _decoded_T_138)
node _decoded_T_140 = bits(_decoded_T_132, 5, 0)
node _decoded_T_141 = shl(_decoded_T_140, 2)
node _decoded_T_142 = xor(_decoded_T_132, _decoded_T_141)
node _decoded_T_143 = shr(_decoded_T_139, 2)
node _decoded_T_144 = and(_decoded_T_143, _decoded_T_142)
node _decoded_T_145 = bits(_decoded_T_139, 5, 0)
node _decoded_T_146 = shl(_decoded_T_145, 2)
node _decoded_T_147 = not(_decoded_T_142)
node _decoded_T_148 = and(_decoded_T_146, _decoded_T_147)
node _decoded_T_149 = or(_decoded_T_144, _decoded_T_148)
node _decoded_T_150 = bits(_decoded_T_142, 6, 0)
node _decoded_T_151 = shl(_decoded_T_150, 1)
node _decoded_T_152 = xor(_decoded_T_142, _decoded_T_151)
node _decoded_T_153 = shr(_decoded_T_149, 1)
node _decoded_T_154 = and(_decoded_T_153, _decoded_T_152)
node _decoded_T_155 = bits(_decoded_T_149, 6, 0)
node _decoded_T_156 = shl(_decoded_T_155, 1)
node _decoded_T_157 = not(_decoded_T_152)
node _decoded_T_158 = and(_decoded_T_156, _decoded_T_157)
node _decoded_T_159 = or(_decoded_T_154, _decoded_T_158)
node decoded_1 = cat(_decoded_T_129, _decoded_T_159)
node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0)
connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T
node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1)
connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T
node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2)
connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T
node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3)
connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T
node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4)
connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T
node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5)
connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T
node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6)
connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T
node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7)
connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T
node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 8, 8)
connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T
node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 9, 9)
connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T
node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 10, 10)
connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T
node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 11, 11)
connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T
node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 12, 12)
connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T
node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 13, 13)
connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T
node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 14, 14)
connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T
node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 15, 15)
connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T
node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 16, 16)
connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T
node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 17, 17)
connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T
node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 18, 18)
connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T
node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 19, 19)
connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T
node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 20, 20)
connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T
node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 21, 21)
connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T
node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 22, 22)
connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T
node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 23, 23)
connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T
node _io_resp_1_vc_sel_3_0_T = bits(decoded_1, 24, 24)
connect io.resp.`1`.vc_sel.`3`[0], _io_resp_1_vc_sel_3_0_T
node _io_resp_1_vc_sel_3_1_T = bits(decoded_1, 25, 25)
connect io.resp.`1`.vc_sel.`3`[1], _io_resp_1_vc_sel_3_1_T
node _io_resp_1_vc_sel_3_2_T = bits(decoded_1, 26, 26)
connect io.resp.`1`.vc_sel.`3`[2], _io_resp_1_vc_sel_3_2_T
node _io_resp_1_vc_sel_3_3_T = bits(decoded_1, 27, 27)
connect io.resp.`1`.vc_sel.`3`[3], _io_resp_1_vc_sel_3_3_T
node _io_resp_1_vc_sel_3_4_T = bits(decoded_1, 28, 28)
connect io.resp.`1`.vc_sel.`3`[4], _io_resp_1_vc_sel_3_4_T
node _io_resp_1_vc_sel_3_5_T = bits(decoded_1, 29, 29)
connect io.resp.`1`.vc_sel.`3`[5], _io_resp_1_vc_sel_3_5_T
node _io_resp_1_vc_sel_3_6_T = bits(decoded_1, 30, 30)
connect io.resp.`1`.vc_sel.`3`[6], _io_resp_1_vc_sel_3_6_T
node _io_resp_1_vc_sel_3_7_T = bits(decoded_1, 31, 31)
connect io.resp.`1`.vc_sel.`3`[7], _io_resp_1_vc_sel_3_7_T
node _io_resp_1_vc_sel_4_0_T = bits(decoded_1, 32, 32)
connect io.resp.`1`.vc_sel.`4`[0], _io_resp_1_vc_sel_4_0_T
node _io_resp_1_vc_sel_4_1_T = bits(decoded_1, 33, 33)
connect io.resp.`1`.vc_sel.`4`[1], _io_resp_1_vc_sel_4_1_T
node _io_resp_1_vc_sel_4_2_T = bits(decoded_1, 34, 34)
connect io.resp.`1`.vc_sel.`4`[2], _io_resp_1_vc_sel_4_2_T
node _io_resp_1_vc_sel_4_3_T = bits(decoded_1, 35, 35)
connect io.resp.`1`.vc_sel.`4`[3], _io_resp_1_vc_sel_4_3_T
node _io_resp_1_vc_sel_4_4_T = bits(decoded_1, 36, 36)
connect io.resp.`1`.vc_sel.`4`[4], _io_resp_1_vc_sel_4_4_T
node _io_resp_1_vc_sel_4_5_T = bits(decoded_1, 37, 37)
connect io.resp.`1`.vc_sel.`4`[5], _io_resp_1_vc_sel_4_5_T
node _io_resp_1_vc_sel_4_6_T = bits(decoded_1, 38, 38)
connect io.resp.`1`.vc_sel.`4`[6], _io_resp_1_vc_sel_4_6_T
node _io_resp_1_vc_sel_4_7_T = bits(decoded_1, 39, 39)
connect io.resp.`1`.vc_sel.`4`[7], _io_resp_1_vc_sel_4_7_T
connect io.req.`2`.ready, UInt<1>(0h1)
node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id)
node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node)
node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id)
node _addr_T_2 = cat(addr_hi_2, addr_lo_2)
node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2)
wire decoded_plaInput_2 : UInt<20>
node decoded_invInputs_2 = not(decoded_plaInput_2)
wire decoded_plaOutput_2 : UInt<40>
node decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_99 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_99 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_99 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_andMatrixOutputs_andMatrixInput_12_99, decoded_andMatrixOutputs_andMatrixInput_13_99)
node decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_andMatrixOutputs_lo_lo_hi_99, decoded_andMatrixOutputs_andMatrixInput_14_99)
node decoded_andMatrixOutputs_lo_hi_lo_99 = cat(decoded_andMatrixOutputs_andMatrixInput_10_99, decoded_andMatrixOutputs_andMatrixInput_11_99)
node decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_andMatrixOutputs_andMatrixInput_8_99, decoded_andMatrixOutputs_andMatrixInput_9_99)
node decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_andMatrixOutputs_lo_hi_hi_99, decoded_andMatrixOutputs_lo_hi_lo_99)
node decoded_andMatrixOutputs_lo_99 = cat(decoded_andMatrixOutputs_lo_hi_99, decoded_andMatrixOutputs_lo_lo_99)
node decoded_andMatrixOutputs_hi_lo_lo_99 = cat(decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_andMatrixOutputs_andMatrixInput_7_99)
node decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_andMatrixOutputs_andMatrixInput_4_99, decoded_andMatrixOutputs_andMatrixInput_5_99)
node decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_andMatrixOutputs_hi_lo_hi_99, decoded_andMatrixOutputs_hi_lo_lo_99)
node decoded_andMatrixOutputs_hi_hi_lo_99 = cat(decoded_andMatrixOutputs_andMatrixInput_2_100, decoded_andMatrixOutputs_andMatrixInput_3_99)
node decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_andMatrixOutputs_andMatrixInput_1_100)
node decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_andMatrixOutputs_hi_hi_hi_99, decoded_andMatrixOutputs_hi_hi_lo_99)
node decoded_andMatrixOutputs_hi_100 = cat(decoded_andMatrixOutputs_hi_hi_99, decoded_andMatrixOutputs_hi_lo_99)
node _decoded_andMatrixOutputs_T_100 = cat(decoded_andMatrixOutputs_hi_100, decoded_andMatrixOutputs_lo_99)
node decoded_andMatrixOutputs_19_2_2 = andr(_decoded_andMatrixOutputs_T_100)
node decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_100 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_100 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_100 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_andMatrixOutputs_andMatrixInput_12_100, decoded_andMatrixOutputs_andMatrixInput_13_100)
node decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_andMatrixOutputs_lo_lo_hi_100, decoded_andMatrixOutputs_andMatrixInput_14_100)
node decoded_andMatrixOutputs_lo_hi_lo_100 = cat(decoded_andMatrixOutputs_andMatrixInput_10_100, decoded_andMatrixOutputs_andMatrixInput_11_100)
node decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_andMatrixOutputs_andMatrixInput_8_100, decoded_andMatrixOutputs_andMatrixInput_9_100)
node decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_andMatrixOutputs_lo_hi_hi_100, decoded_andMatrixOutputs_lo_hi_lo_100)
node decoded_andMatrixOutputs_lo_100 = cat(decoded_andMatrixOutputs_lo_hi_100, decoded_andMatrixOutputs_lo_lo_100)
node decoded_andMatrixOutputs_hi_lo_lo_100 = cat(decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_andMatrixOutputs_andMatrixInput_7_100)
node decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_andMatrixOutputs_andMatrixInput_4_100, decoded_andMatrixOutputs_andMatrixInput_5_100)
node decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_andMatrixOutputs_hi_lo_hi_100, decoded_andMatrixOutputs_hi_lo_lo_100)
node decoded_andMatrixOutputs_hi_hi_lo_100 = cat(decoded_andMatrixOutputs_andMatrixInput_2_101, decoded_andMatrixOutputs_andMatrixInput_3_100)
node decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_andMatrixOutputs_andMatrixInput_1_101)
node decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_andMatrixOutputs_hi_hi_hi_100, decoded_andMatrixOutputs_hi_hi_lo_100)
node decoded_andMatrixOutputs_hi_101 = cat(decoded_andMatrixOutputs_hi_hi_100, decoded_andMatrixOutputs_hi_lo_100)
node _decoded_andMatrixOutputs_T_101 = cat(decoded_andMatrixOutputs_hi_101, decoded_andMatrixOutputs_lo_100)
node decoded_andMatrixOutputs_21_2_2 = andr(_decoded_andMatrixOutputs_T_101)
node decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_101 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_101 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_101 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_andMatrixOutputs_andMatrixInput_12_101, decoded_andMatrixOutputs_andMatrixInput_13_101)
node decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_andMatrixOutputs_lo_lo_hi_101, decoded_andMatrixOutputs_andMatrixInput_14_101)
node decoded_andMatrixOutputs_lo_hi_lo_101 = cat(decoded_andMatrixOutputs_andMatrixInput_10_101, decoded_andMatrixOutputs_andMatrixInput_11_101)
node decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_andMatrixOutputs_andMatrixInput_8_101, decoded_andMatrixOutputs_andMatrixInput_9_101)
node decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_andMatrixOutputs_lo_hi_hi_101, decoded_andMatrixOutputs_lo_hi_lo_101)
node decoded_andMatrixOutputs_lo_101 = cat(decoded_andMatrixOutputs_lo_hi_101, decoded_andMatrixOutputs_lo_lo_101)
node decoded_andMatrixOutputs_hi_lo_lo_101 = cat(decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_andMatrixOutputs_andMatrixInput_7_101)
node decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_andMatrixOutputs_andMatrixInput_4_101, decoded_andMatrixOutputs_andMatrixInput_5_101)
node decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_andMatrixOutputs_hi_lo_hi_101, decoded_andMatrixOutputs_hi_lo_lo_101)
node decoded_andMatrixOutputs_hi_hi_lo_101 = cat(decoded_andMatrixOutputs_andMatrixInput_2_102, decoded_andMatrixOutputs_andMatrixInput_3_101)
node decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_andMatrixOutputs_andMatrixInput_1_102)
node decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_andMatrixOutputs_hi_hi_hi_101, decoded_andMatrixOutputs_hi_hi_lo_101)
node decoded_andMatrixOutputs_hi_102 = cat(decoded_andMatrixOutputs_hi_hi_101, decoded_andMatrixOutputs_hi_lo_101)
node _decoded_andMatrixOutputs_T_102 = cat(decoded_andMatrixOutputs_hi_102, decoded_andMatrixOutputs_lo_101)
node decoded_andMatrixOutputs_10_2_2 = andr(_decoded_andMatrixOutputs_T_102)
node decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_102 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_102 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_102 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_andMatrixOutputs_andMatrixInput_12_102, decoded_andMatrixOutputs_andMatrixInput_13_102)
node decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_andMatrixOutputs_lo_lo_hi_102, decoded_andMatrixOutputs_andMatrixInput_14_102)
node decoded_andMatrixOutputs_lo_hi_lo_102 = cat(decoded_andMatrixOutputs_andMatrixInput_10_102, decoded_andMatrixOutputs_andMatrixInput_11_102)
node decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_andMatrixOutputs_andMatrixInput_8_102, decoded_andMatrixOutputs_andMatrixInput_9_102)
node decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_andMatrixOutputs_lo_hi_hi_102, decoded_andMatrixOutputs_lo_hi_lo_102)
node decoded_andMatrixOutputs_lo_102 = cat(decoded_andMatrixOutputs_lo_hi_102, decoded_andMatrixOutputs_lo_lo_102)
node decoded_andMatrixOutputs_hi_lo_lo_102 = cat(decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_andMatrixOutputs_andMatrixInput_7_102)
node decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_andMatrixOutputs_andMatrixInput_4_102, decoded_andMatrixOutputs_andMatrixInput_5_102)
node decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_andMatrixOutputs_hi_lo_hi_102, decoded_andMatrixOutputs_hi_lo_lo_102)
node decoded_andMatrixOutputs_hi_hi_lo_102 = cat(decoded_andMatrixOutputs_andMatrixInput_2_103, decoded_andMatrixOutputs_andMatrixInput_3_102)
node decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_andMatrixOutputs_andMatrixInput_1_103)
node decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_andMatrixOutputs_hi_hi_hi_102, decoded_andMatrixOutputs_hi_hi_lo_102)
node decoded_andMatrixOutputs_hi_103 = cat(decoded_andMatrixOutputs_hi_hi_102, decoded_andMatrixOutputs_hi_lo_102)
node _decoded_andMatrixOutputs_T_103 = cat(decoded_andMatrixOutputs_hi_103, decoded_andMatrixOutputs_lo_102)
node decoded_andMatrixOutputs_60_2 = andr(_decoded_andMatrixOutputs_T_103)
node decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_andMatrixOutputs_andMatrixInput_7_103, decoded_andMatrixOutputs_andMatrixInput_8_103)
node decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_andMatrixOutputs_andMatrixInput_5_103, decoded_andMatrixOutputs_andMatrixInput_6_103)
node decoded_andMatrixOutputs_lo_103 = cat(decoded_andMatrixOutputs_lo_hi_103, decoded_andMatrixOutputs_lo_lo_103)
node decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_andMatrixOutputs_andMatrixInput_4_103)
node decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_andMatrixOutputs_andMatrixInput_1_104)
node decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_andMatrixOutputs_hi_hi_hi_103, decoded_andMatrixOutputs_andMatrixInput_2_104)
node decoded_andMatrixOutputs_hi_104 = cat(decoded_andMatrixOutputs_hi_hi_103, decoded_andMatrixOutputs_hi_lo_103)
node _decoded_andMatrixOutputs_T_104 = cat(decoded_andMatrixOutputs_hi_104, decoded_andMatrixOutputs_lo_103)
node decoded_andMatrixOutputs_27_2_2 = andr(_decoded_andMatrixOutputs_T_104)
node decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_103 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_103 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_103 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_andMatrixOutputs_andMatrixInput_12_103, decoded_andMatrixOutputs_andMatrixInput_13_103)
node decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_andMatrixOutputs_lo_lo_hi_103, decoded_andMatrixOutputs_andMatrixInput_14_103)
node decoded_andMatrixOutputs_lo_hi_lo_103 = cat(decoded_andMatrixOutputs_andMatrixInput_10_103, decoded_andMatrixOutputs_andMatrixInput_11_103)
node decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_andMatrixOutputs_andMatrixInput_8_104, decoded_andMatrixOutputs_andMatrixInput_9_103)
node decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_andMatrixOutputs_lo_hi_hi_103, decoded_andMatrixOutputs_lo_hi_lo_103)
node decoded_andMatrixOutputs_lo_104 = cat(decoded_andMatrixOutputs_lo_hi_104, decoded_andMatrixOutputs_lo_lo_104)
node decoded_andMatrixOutputs_hi_lo_lo_103 = cat(decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_andMatrixOutputs_andMatrixInput_7_104)
node decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_andMatrixOutputs_andMatrixInput_4_104, decoded_andMatrixOutputs_andMatrixInput_5_104)
node decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_andMatrixOutputs_hi_lo_hi_103, decoded_andMatrixOutputs_hi_lo_lo_103)
node decoded_andMatrixOutputs_hi_hi_lo_103 = cat(decoded_andMatrixOutputs_andMatrixInput_2_105, decoded_andMatrixOutputs_andMatrixInput_3_104)
node decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_andMatrixOutputs_andMatrixInput_1_105)
node decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_andMatrixOutputs_hi_hi_hi_104, decoded_andMatrixOutputs_hi_hi_lo_103)
node decoded_andMatrixOutputs_hi_105 = cat(decoded_andMatrixOutputs_hi_hi_104, decoded_andMatrixOutputs_hi_lo_104)
node _decoded_andMatrixOutputs_T_105 = cat(decoded_andMatrixOutputs_hi_105, decoded_andMatrixOutputs_lo_104)
node decoded_andMatrixOutputs_66_2 = andr(_decoded_andMatrixOutputs_T_105)
node decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_104 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_104 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_104 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_andMatrixOutputs_andMatrixInput_12_104, decoded_andMatrixOutputs_andMatrixInput_13_104)
node decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_andMatrixOutputs_lo_lo_hi_104, decoded_andMatrixOutputs_andMatrixInput_14_104)
node decoded_andMatrixOutputs_lo_hi_lo_104 = cat(decoded_andMatrixOutputs_andMatrixInput_10_104, decoded_andMatrixOutputs_andMatrixInput_11_104)
node decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_andMatrixOutputs_andMatrixInput_8_105, decoded_andMatrixOutputs_andMatrixInput_9_104)
node decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_andMatrixOutputs_lo_hi_hi_104, decoded_andMatrixOutputs_lo_hi_lo_104)
node decoded_andMatrixOutputs_lo_105 = cat(decoded_andMatrixOutputs_lo_hi_105, decoded_andMatrixOutputs_lo_lo_105)
node decoded_andMatrixOutputs_hi_lo_lo_104 = cat(decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_andMatrixOutputs_andMatrixInput_7_105)
node decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_andMatrixOutputs_andMatrixInput_4_105, decoded_andMatrixOutputs_andMatrixInput_5_105)
node decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_andMatrixOutputs_hi_lo_hi_104, decoded_andMatrixOutputs_hi_lo_lo_104)
node decoded_andMatrixOutputs_hi_hi_lo_104 = cat(decoded_andMatrixOutputs_andMatrixInput_2_106, decoded_andMatrixOutputs_andMatrixInput_3_105)
node decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_andMatrixOutputs_andMatrixInput_1_106)
node decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_andMatrixOutputs_hi_hi_hi_105, decoded_andMatrixOutputs_hi_hi_lo_104)
node decoded_andMatrixOutputs_hi_106 = cat(decoded_andMatrixOutputs_hi_hi_105, decoded_andMatrixOutputs_hi_lo_105)
node _decoded_andMatrixOutputs_T_106 = cat(decoded_andMatrixOutputs_hi_106, decoded_andMatrixOutputs_lo_105)
node decoded_andMatrixOutputs_55_2_1 = andr(_decoded_andMatrixOutputs_T_106)
node decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_105 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_105 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_105 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_62 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_62 = cat(decoded_andMatrixOutputs_andMatrixInput_14_105, decoded_andMatrixOutputs_andMatrixInput_15_62)
node decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_andMatrixOutputs_andMatrixInput_12_105, decoded_andMatrixOutputs_andMatrixInput_13_105)
node decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_andMatrixOutputs_lo_lo_hi_105, decoded_andMatrixOutputs_lo_lo_lo_62)
node decoded_andMatrixOutputs_lo_hi_lo_105 = cat(decoded_andMatrixOutputs_andMatrixInput_10_105, decoded_andMatrixOutputs_andMatrixInput_11_105)
node decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_andMatrixOutputs_andMatrixInput_8_106, decoded_andMatrixOutputs_andMatrixInput_9_105)
node decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_andMatrixOutputs_lo_hi_hi_105, decoded_andMatrixOutputs_lo_hi_lo_105)
node decoded_andMatrixOutputs_lo_106 = cat(decoded_andMatrixOutputs_lo_hi_106, decoded_andMatrixOutputs_lo_lo_106)
node decoded_andMatrixOutputs_hi_lo_lo_105 = cat(decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_andMatrixOutputs_andMatrixInput_7_106)
node decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_andMatrixOutputs_andMatrixInput_4_106, decoded_andMatrixOutputs_andMatrixInput_5_106)
node decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_andMatrixOutputs_hi_lo_hi_105, decoded_andMatrixOutputs_hi_lo_lo_105)
node decoded_andMatrixOutputs_hi_hi_lo_105 = cat(decoded_andMatrixOutputs_andMatrixInput_2_107, decoded_andMatrixOutputs_andMatrixInput_3_106)
node decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_andMatrixOutputs_andMatrixInput_1_107)
node decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_andMatrixOutputs_hi_hi_hi_106, decoded_andMatrixOutputs_hi_hi_lo_105)
node decoded_andMatrixOutputs_hi_107 = cat(decoded_andMatrixOutputs_hi_hi_106, decoded_andMatrixOutputs_hi_lo_106)
node _decoded_andMatrixOutputs_T_107 = cat(decoded_andMatrixOutputs_hi_107, decoded_andMatrixOutputs_lo_106)
node decoded_andMatrixOutputs_73_2 = andr(_decoded_andMatrixOutputs_T_107)
node decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_106 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_106 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_106 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_63 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_63 = cat(decoded_andMatrixOutputs_andMatrixInput_14_106, decoded_andMatrixOutputs_andMatrixInput_15_63)
node decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_andMatrixOutputs_andMatrixInput_12_106, decoded_andMatrixOutputs_andMatrixInput_13_106)
node decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_andMatrixOutputs_lo_lo_hi_106, decoded_andMatrixOutputs_lo_lo_lo_63)
node decoded_andMatrixOutputs_lo_hi_lo_106 = cat(decoded_andMatrixOutputs_andMatrixInput_10_106, decoded_andMatrixOutputs_andMatrixInput_11_106)
node decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_andMatrixOutputs_andMatrixInput_8_107, decoded_andMatrixOutputs_andMatrixInput_9_106)
node decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_andMatrixOutputs_lo_hi_hi_106, decoded_andMatrixOutputs_lo_hi_lo_106)
node decoded_andMatrixOutputs_lo_107 = cat(decoded_andMatrixOutputs_lo_hi_107, decoded_andMatrixOutputs_lo_lo_107)
node decoded_andMatrixOutputs_hi_lo_lo_106 = cat(decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_andMatrixOutputs_andMatrixInput_7_107)
node decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_andMatrixOutputs_andMatrixInput_4_107, decoded_andMatrixOutputs_andMatrixInput_5_107)
node decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_andMatrixOutputs_hi_lo_hi_106, decoded_andMatrixOutputs_hi_lo_lo_106)
node decoded_andMatrixOutputs_hi_hi_lo_106 = cat(decoded_andMatrixOutputs_andMatrixInput_2_108, decoded_andMatrixOutputs_andMatrixInput_3_107)
node decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_andMatrixOutputs_andMatrixInput_1_108)
node decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_andMatrixOutputs_hi_hi_hi_107, decoded_andMatrixOutputs_hi_hi_lo_106)
node decoded_andMatrixOutputs_hi_108 = cat(decoded_andMatrixOutputs_hi_hi_107, decoded_andMatrixOutputs_hi_lo_107)
node _decoded_andMatrixOutputs_T_108 = cat(decoded_andMatrixOutputs_hi_108, decoded_andMatrixOutputs_lo_107)
node decoded_andMatrixOutputs_20_2_2 = andr(_decoded_andMatrixOutputs_T_108)
node decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_107 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_107 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_107 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_64 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_64 = cat(decoded_andMatrixOutputs_andMatrixInput_14_107, decoded_andMatrixOutputs_andMatrixInput_15_64)
node decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_andMatrixOutputs_andMatrixInput_12_107, decoded_andMatrixOutputs_andMatrixInput_13_107)
node decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_andMatrixOutputs_lo_lo_hi_107, decoded_andMatrixOutputs_lo_lo_lo_64)
node decoded_andMatrixOutputs_lo_hi_lo_107 = cat(decoded_andMatrixOutputs_andMatrixInput_10_107, decoded_andMatrixOutputs_andMatrixInput_11_107)
node decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_andMatrixOutputs_andMatrixInput_8_108, decoded_andMatrixOutputs_andMatrixInput_9_107)
node decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_andMatrixOutputs_lo_hi_hi_107, decoded_andMatrixOutputs_lo_hi_lo_107)
node decoded_andMatrixOutputs_lo_108 = cat(decoded_andMatrixOutputs_lo_hi_108, decoded_andMatrixOutputs_lo_lo_108)
node decoded_andMatrixOutputs_hi_lo_lo_107 = cat(decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_andMatrixOutputs_andMatrixInput_7_108)
node decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_andMatrixOutputs_andMatrixInput_4_108, decoded_andMatrixOutputs_andMatrixInput_5_108)
node decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_andMatrixOutputs_hi_lo_hi_107, decoded_andMatrixOutputs_hi_lo_lo_107)
node decoded_andMatrixOutputs_hi_hi_lo_107 = cat(decoded_andMatrixOutputs_andMatrixInput_2_109, decoded_andMatrixOutputs_andMatrixInput_3_108)
node decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_andMatrixOutputs_andMatrixInput_1_109)
node decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_andMatrixOutputs_hi_hi_hi_108, decoded_andMatrixOutputs_hi_hi_lo_107)
node decoded_andMatrixOutputs_hi_109 = cat(decoded_andMatrixOutputs_hi_hi_108, decoded_andMatrixOutputs_hi_lo_108)
node _decoded_andMatrixOutputs_T_109 = cat(decoded_andMatrixOutputs_hi_109, decoded_andMatrixOutputs_lo_108)
node decoded_andMatrixOutputs_33_2_2 = andr(_decoded_andMatrixOutputs_T_109)
node decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_108 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_108 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_108 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_65 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_65 = cat(decoded_andMatrixOutputs_andMatrixInput_14_108, decoded_andMatrixOutputs_andMatrixInput_15_65)
node decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_andMatrixOutputs_andMatrixInput_12_108, decoded_andMatrixOutputs_andMatrixInput_13_108)
node decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_andMatrixOutputs_lo_lo_hi_108, decoded_andMatrixOutputs_lo_lo_lo_65)
node decoded_andMatrixOutputs_lo_hi_lo_108 = cat(decoded_andMatrixOutputs_andMatrixInput_10_108, decoded_andMatrixOutputs_andMatrixInput_11_108)
node decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_andMatrixOutputs_andMatrixInput_8_109, decoded_andMatrixOutputs_andMatrixInput_9_108)
node decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_andMatrixOutputs_lo_hi_hi_108, decoded_andMatrixOutputs_lo_hi_lo_108)
node decoded_andMatrixOutputs_lo_109 = cat(decoded_andMatrixOutputs_lo_hi_109, decoded_andMatrixOutputs_lo_lo_109)
node decoded_andMatrixOutputs_hi_lo_lo_108 = cat(decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_andMatrixOutputs_andMatrixInput_7_109)
node decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_andMatrixOutputs_andMatrixInput_4_109, decoded_andMatrixOutputs_andMatrixInput_5_109)
node decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_andMatrixOutputs_hi_lo_hi_108, decoded_andMatrixOutputs_hi_lo_lo_108)
node decoded_andMatrixOutputs_hi_hi_lo_108 = cat(decoded_andMatrixOutputs_andMatrixInput_2_110, decoded_andMatrixOutputs_andMatrixInput_3_109)
node decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_andMatrixOutputs_andMatrixInput_1_110)
node decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_andMatrixOutputs_hi_hi_hi_109, decoded_andMatrixOutputs_hi_hi_lo_108)
node decoded_andMatrixOutputs_hi_110 = cat(decoded_andMatrixOutputs_hi_hi_109, decoded_andMatrixOutputs_hi_lo_109)
node _decoded_andMatrixOutputs_T_110 = cat(decoded_andMatrixOutputs_hi_110, decoded_andMatrixOutputs_lo_109)
node decoded_andMatrixOutputs_45_2_1 = andr(_decoded_andMatrixOutputs_T_110)
node decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_109 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_109 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_109 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_66 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_66 = cat(decoded_andMatrixOutputs_andMatrixInput_14_109, decoded_andMatrixOutputs_andMatrixInput_15_66)
node decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_andMatrixOutputs_andMatrixInput_12_109, decoded_andMatrixOutputs_andMatrixInput_13_109)
node decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_andMatrixOutputs_lo_lo_hi_109, decoded_andMatrixOutputs_lo_lo_lo_66)
node decoded_andMatrixOutputs_lo_hi_lo_109 = cat(decoded_andMatrixOutputs_andMatrixInput_10_109, decoded_andMatrixOutputs_andMatrixInput_11_109)
node decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_andMatrixOutputs_andMatrixInput_8_110, decoded_andMatrixOutputs_andMatrixInput_9_109)
node decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_andMatrixOutputs_lo_hi_hi_109, decoded_andMatrixOutputs_lo_hi_lo_109)
node decoded_andMatrixOutputs_lo_110 = cat(decoded_andMatrixOutputs_lo_hi_110, decoded_andMatrixOutputs_lo_lo_110)
node decoded_andMatrixOutputs_hi_lo_lo_109 = cat(decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_andMatrixOutputs_andMatrixInput_7_110)
node decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_andMatrixOutputs_andMatrixInput_4_110, decoded_andMatrixOutputs_andMatrixInput_5_110)
node decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_andMatrixOutputs_hi_lo_hi_109, decoded_andMatrixOutputs_hi_lo_lo_109)
node decoded_andMatrixOutputs_hi_hi_lo_109 = cat(decoded_andMatrixOutputs_andMatrixInput_2_111, decoded_andMatrixOutputs_andMatrixInput_3_110)
node decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_andMatrixOutputs_andMatrixInput_1_111)
node decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_andMatrixOutputs_hi_hi_hi_110, decoded_andMatrixOutputs_hi_hi_lo_109)
node decoded_andMatrixOutputs_hi_111 = cat(decoded_andMatrixOutputs_hi_hi_110, decoded_andMatrixOutputs_hi_lo_110)
node _decoded_andMatrixOutputs_T_111 = cat(decoded_andMatrixOutputs_hi_111, decoded_andMatrixOutputs_lo_110)
node decoded_andMatrixOutputs_63_2 = andr(_decoded_andMatrixOutputs_T_111)
node decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_110 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_110 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_110 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_67 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_67 = cat(decoded_andMatrixOutputs_andMatrixInput_14_110, decoded_andMatrixOutputs_andMatrixInput_15_67)
node decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_andMatrixOutputs_andMatrixInput_12_110, decoded_andMatrixOutputs_andMatrixInput_13_110)
node decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_andMatrixOutputs_lo_lo_hi_110, decoded_andMatrixOutputs_lo_lo_lo_67)
node decoded_andMatrixOutputs_lo_hi_lo_110 = cat(decoded_andMatrixOutputs_andMatrixInput_10_110, decoded_andMatrixOutputs_andMatrixInput_11_110)
node decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_andMatrixOutputs_andMatrixInput_8_111, decoded_andMatrixOutputs_andMatrixInput_9_110)
node decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_andMatrixOutputs_lo_hi_hi_110, decoded_andMatrixOutputs_lo_hi_lo_110)
node decoded_andMatrixOutputs_lo_111 = cat(decoded_andMatrixOutputs_lo_hi_111, decoded_andMatrixOutputs_lo_lo_111)
node decoded_andMatrixOutputs_hi_lo_lo_110 = cat(decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_andMatrixOutputs_andMatrixInput_7_111)
node decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_andMatrixOutputs_andMatrixInput_4_111, decoded_andMatrixOutputs_andMatrixInput_5_111)
node decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_andMatrixOutputs_hi_lo_hi_110, decoded_andMatrixOutputs_hi_lo_lo_110)
node decoded_andMatrixOutputs_hi_hi_lo_110 = cat(decoded_andMatrixOutputs_andMatrixInput_2_112, decoded_andMatrixOutputs_andMatrixInput_3_111)
node decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_andMatrixOutputs_andMatrixInput_1_112)
node decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_andMatrixOutputs_hi_hi_hi_111, decoded_andMatrixOutputs_hi_hi_lo_110)
node decoded_andMatrixOutputs_hi_112 = cat(decoded_andMatrixOutputs_hi_hi_111, decoded_andMatrixOutputs_hi_lo_111)
node _decoded_andMatrixOutputs_T_112 = cat(decoded_andMatrixOutputs_hi_112, decoded_andMatrixOutputs_lo_111)
node decoded_andMatrixOutputs_42_2_2 = andr(_decoded_andMatrixOutputs_T_112)
node decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_111 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_111 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_111 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_andMatrixOutputs_andMatrixInput_12_111, decoded_andMatrixOutputs_andMatrixInput_13_111)
node decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_andMatrixOutputs_lo_lo_hi_111, decoded_andMatrixOutputs_andMatrixInput_14_111)
node decoded_andMatrixOutputs_lo_hi_lo_111 = cat(decoded_andMatrixOutputs_andMatrixInput_10_111, decoded_andMatrixOutputs_andMatrixInput_11_111)
node decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_andMatrixOutputs_andMatrixInput_8_112, decoded_andMatrixOutputs_andMatrixInput_9_111)
node decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_andMatrixOutputs_lo_hi_hi_111, decoded_andMatrixOutputs_lo_hi_lo_111)
node decoded_andMatrixOutputs_lo_112 = cat(decoded_andMatrixOutputs_lo_hi_112, decoded_andMatrixOutputs_lo_lo_112)
node decoded_andMatrixOutputs_hi_lo_lo_111 = cat(decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_andMatrixOutputs_andMatrixInput_7_112)
node decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_andMatrixOutputs_andMatrixInput_4_112, decoded_andMatrixOutputs_andMatrixInput_5_112)
node decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_andMatrixOutputs_hi_lo_hi_111, decoded_andMatrixOutputs_hi_lo_lo_111)
node decoded_andMatrixOutputs_hi_hi_lo_111 = cat(decoded_andMatrixOutputs_andMatrixInput_2_113, decoded_andMatrixOutputs_andMatrixInput_3_112)
node decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_andMatrixOutputs_andMatrixInput_1_113)
node decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_andMatrixOutputs_hi_hi_hi_112, decoded_andMatrixOutputs_hi_hi_lo_111)
node decoded_andMatrixOutputs_hi_113 = cat(decoded_andMatrixOutputs_hi_hi_112, decoded_andMatrixOutputs_hi_lo_112)
node _decoded_andMatrixOutputs_T_113 = cat(decoded_andMatrixOutputs_hi_113, decoded_andMatrixOutputs_lo_112)
node decoded_andMatrixOutputs_11_2_2 = andr(_decoded_andMatrixOutputs_T_113)
node decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_112 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_112 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_112 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_andMatrixOutputs_andMatrixInput_12_112, decoded_andMatrixOutputs_andMatrixInput_13_112)
node decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_andMatrixOutputs_lo_lo_hi_112, decoded_andMatrixOutputs_andMatrixInput_14_112)
node decoded_andMatrixOutputs_lo_hi_lo_112 = cat(decoded_andMatrixOutputs_andMatrixInput_10_112, decoded_andMatrixOutputs_andMatrixInput_11_112)
node decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_andMatrixOutputs_andMatrixInput_8_113, decoded_andMatrixOutputs_andMatrixInput_9_112)
node decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_andMatrixOutputs_lo_hi_hi_112, decoded_andMatrixOutputs_lo_hi_lo_112)
node decoded_andMatrixOutputs_lo_113 = cat(decoded_andMatrixOutputs_lo_hi_113, decoded_andMatrixOutputs_lo_lo_113)
node decoded_andMatrixOutputs_hi_lo_lo_112 = cat(decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_andMatrixOutputs_andMatrixInput_7_113)
node decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_andMatrixOutputs_andMatrixInput_4_113, decoded_andMatrixOutputs_andMatrixInput_5_113)
node decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_andMatrixOutputs_hi_lo_hi_112, decoded_andMatrixOutputs_hi_lo_lo_112)
node decoded_andMatrixOutputs_hi_hi_lo_112 = cat(decoded_andMatrixOutputs_andMatrixInput_2_114, decoded_andMatrixOutputs_andMatrixInput_3_113)
node decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_andMatrixOutputs_andMatrixInput_1_114)
node decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_andMatrixOutputs_hi_hi_hi_113, decoded_andMatrixOutputs_hi_hi_lo_112)
node decoded_andMatrixOutputs_hi_114 = cat(decoded_andMatrixOutputs_hi_hi_113, decoded_andMatrixOutputs_hi_lo_113)
node _decoded_andMatrixOutputs_T_114 = cat(decoded_andMatrixOutputs_hi_114, decoded_andMatrixOutputs_lo_113)
node decoded_andMatrixOutputs_24_2_2 = andr(_decoded_andMatrixOutputs_T_114)
node decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_113 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_113 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_113 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_68 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_68 = cat(decoded_andMatrixOutputs_andMatrixInput_14_113, decoded_andMatrixOutputs_andMatrixInput_15_68)
node decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_andMatrixOutputs_andMatrixInput_12_113, decoded_andMatrixOutputs_andMatrixInput_13_113)
node decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_andMatrixOutputs_lo_lo_hi_113, decoded_andMatrixOutputs_lo_lo_lo_68)
node decoded_andMatrixOutputs_lo_hi_lo_113 = cat(decoded_andMatrixOutputs_andMatrixInput_10_113, decoded_andMatrixOutputs_andMatrixInput_11_113)
node decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_andMatrixOutputs_andMatrixInput_8_114, decoded_andMatrixOutputs_andMatrixInput_9_113)
node decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_andMatrixOutputs_lo_hi_hi_113, decoded_andMatrixOutputs_lo_hi_lo_113)
node decoded_andMatrixOutputs_lo_114 = cat(decoded_andMatrixOutputs_lo_hi_114, decoded_andMatrixOutputs_lo_lo_114)
node decoded_andMatrixOutputs_hi_lo_lo_113 = cat(decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_andMatrixOutputs_andMatrixInput_7_114)
node decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_andMatrixOutputs_andMatrixInput_4_114, decoded_andMatrixOutputs_andMatrixInput_5_114)
node decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_andMatrixOutputs_hi_lo_hi_113, decoded_andMatrixOutputs_hi_lo_lo_113)
node decoded_andMatrixOutputs_hi_hi_lo_113 = cat(decoded_andMatrixOutputs_andMatrixInput_2_115, decoded_andMatrixOutputs_andMatrixInput_3_114)
node decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_andMatrixOutputs_andMatrixInput_1_115)
node decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_andMatrixOutputs_hi_hi_hi_114, decoded_andMatrixOutputs_hi_hi_lo_113)
node decoded_andMatrixOutputs_hi_115 = cat(decoded_andMatrixOutputs_hi_hi_114, decoded_andMatrixOutputs_hi_lo_114)
node _decoded_andMatrixOutputs_T_115 = cat(decoded_andMatrixOutputs_hi_115, decoded_andMatrixOutputs_lo_114)
node decoded_andMatrixOutputs_17_2_2 = andr(_decoded_andMatrixOutputs_T_115)
node decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_114 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_114 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_114 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_69 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_69 = cat(decoded_andMatrixOutputs_andMatrixInput_14_114, decoded_andMatrixOutputs_andMatrixInput_15_69)
node decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_andMatrixOutputs_andMatrixInput_12_114, decoded_andMatrixOutputs_andMatrixInput_13_114)
node decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_andMatrixOutputs_lo_lo_hi_114, decoded_andMatrixOutputs_lo_lo_lo_69)
node decoded_andMatrixOutputs_lo_hi_lo_114 = cat(decoded_andMatrixOutputs_andMatrixInput_10_114, decoded_andMatrixOutputs_andMatrixInput_11_114)
node decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_andMatrixOutputs_andMatrixInput_8_115, decoded_andMatrixOutputs_andMatrixInput_9_114)
node decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_andMatrixOutputs_lo_hi_hi_114, decoded_andMatrixOutputs_lo_hi_lo_114)
node decoded_andMatrixOutputs_lo_115 = cat(decoded_andMatrixOutputs_lo_hi_115, decoded_andMatrixOutputs_lo_lo_115)
node decoded_andMatrixOutputs_hi_lo_lo_114 = cat(decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_andMatrixOutputs_andMatrixInput_7_115)
node decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_andMatrixOutputs_andMatrixInput_4_115, decoded_andMatrixOutputs_andMatrixInput_5_115)
node decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_andMatrixOutputs_hi_lo_hi_114, decoded_andMatrixOutputs_hi_lo_lo_114)
node decoded_andMatrixOutputs_hi_hi_lo_114 = cat(decoded_andMatrixOutputs_andMatrixInput_2_116, decoded_andMatrixOutputs_andMatrixInput_3_115)
node decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_andMatrixOutputs_andMatrixInput_1_116)
node decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_andMatrixOutputs_hi_hi_hi_115, decoded_andMatrixOutputs_hi_hi_lo_114)
node decoded_andMatrixOutputs_hi_116 = cat(decoded_andMatrixOutputs_hi_hi_115, decoded_andMatrixOutputs_hi_lo_115)
node _decoded_andMatrixOutputs_T_116 = cat(decoded_andMatrixOutputs_hi_116, decoded_andMatrixOutputs_lo_115)
node decoded_andMatrixOutputs_71_2 = andr(_decoded_andMatrixOutputs_T_116)
node decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_115 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_115 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_115 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_70 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_70 = cat(decoded_andMatrixOutputs_andMatrixInput_14_115, decoded_andMatrixOutputs_andMatrixInput_15_70)
node decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_andMatrixOutputs_andMatrixInput_12_115, decoded_andMatrixOutputs_andMatrixInput_13_115)
node decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_andMatrixOutputs_lo_lo_hi_115, decoded_andMatrixOutputs_lo_lo_lo_70)
node decoded_andMatrixOutputs_lo_hi_lo_115 = cat(decoded_andMatrixOutputs_andMatrixInput_10_115, decoded_andMatrixOutputs_andMatrixInput_11_115)
node decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_andMatrixOutputs_andMatrixInput_8_116, decoded_andMatrixOutputs_andMatrixInput_9_115)
node decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_andMatrixOutputs_lo_hi_hi_115, decoded_andMatrixOutputs_lo_hi_lo_115)
node decoded_andMatrixOutputs_lo_116 = cat(decoded_andMatrixOutputs_lo_hi_116, decoded_andMatrixOutputs_lo_lo_116)
node decoded_andMatrixOutputs_hi_lo_lo_115 = cat(decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_andMatrixOutputs_andMatrixInput_7_116)
node decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_andMatrixOutputs_andMatrixInput_4_116, decoded_andMatrixOutputs_andMatrixInput_5_116)
node decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_andMatrixOutputs_hi_lo_hi_115, decoded_andMatrixOutputs_hi_lo_lo_115)
node decoded_andMatrixOutputs_hi_hi_lo_115 = cat(decoded_andMatrixOutputs_andMatrixInput_2_117, decoded_andMatrixOutputs_andMatrixInput_3_116)
node decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_andMatrixOutputs_andMatrixInput_1_117)
node decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_andMatrixOutputs_hi_hi_hi_116, decoded_andMatrixOutputs_hi_hi_lo_115)
node decoded_andMatrixOutputs_hi_117 = cat(decoded_andMatrixOutputs_hi_hi_116, decoded_andMatrixOutputs_hi_lo_116)
node _decoded_andMatrixOutputs_T_117 = cat(decoded_andMatrixOutputs_hi_117, decoded_andMatrixOutputs_lo_116)
node decoded_andMatrixOutputs_46_2_1 = andr(_decoded_andMatrixOutputs_T_117)
node decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_plaInput_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_116 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_116 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_116 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_71 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_71 = cat(decoded_andMatrixOutputs_andMatrixInput_14_116, decoded_andMatrixOutputs_andMatrixInput_15_71)
node decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_andMatrixOutputs_andMatrixInput_12_116, decoded_andMatrixOutputs_andMatrixInput_13_116)
node decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_andMatrixOutputs_lo_lo_hi_116, decoded_andMatrixOutputs_lo_lo_lo_71)
node decoded_andMatrixOutputs_lo_hi_lo_116 = cat(decoded_andMatrixOutputs_andMatrixInput_10_116, decoded_andMatrixOutputs_andMatrixInput_11_116)
node decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_andMatrixOutputs_andMatrixInput_8_117, decoded_andMatrixOutputs_andMatrixInput_9_116)
node decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_andMatrixOutputs_lo_hi_hi_116, decoded_andMatrixOutputs_lo_hi_lo_116)
node decoded_andMatrixOutputs_lo_117 = cat(decoded_andMatrixOutputs_lo_hi_117, decoded_andMatrixOutputs_lo_lo_117)
node decoded_andMatrixOutputs_hi_lo_lo_116 = cat(decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_andMatrixOutputs_andMatrixInput_7_117)
node decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_andMatrixOutputs_andMatrixInput_4_117, decoded_andMatrixOutputs_andMatrixInput_5_117)
node decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_andMatrixOutputs_hi_lo_hi_116, decoded_andMatrixOutputs_hi_lo_lo_116)
node decoded_andMatrixOutputs_hi_hi_lo_116 = cat(decoded_andMatrixOutputs_andMatrixInput_2_118, decoded_andMatrixOutputs_andMatrixInput_3_117)
node decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_andMatrixOutputs_andMatrixInput_1_118)
node decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_andMatrixOutputs_hi_hi_hi_117, decoded_andMatrixOutputs_hi_hi_lo_116)
node decoded_andMatrixOutputs_hi_118 = cat(decoded_andMatrixOutputs_hi_hi_117, decoded_andMatrixOutputs_hi_lo_117)
node _decoded_andMatrixOutputs_T_118 = cat(decoded_andMatrixOutputs_hi_118, decoded_andMatrixOutputs_lo_117)
node decoded_andMatrixOutputs_23_2_2 = andr(_decoded_andMatrixOutputs_T_118)
node decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_117 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_117 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_117 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_72 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_72 = cat(decoded_andMatrixOutputs_andMatrixInput_14_117, decoded_andMatrixOutputs_andMatrixInput_15_72)
node decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_andMatrixOutputs_andMatrixInput_12_117, decoded_andMatrixOutputs_andMatrixInput_13_117)
node decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_andMatrixOutputs_lo_lo_hi_117, decoded_andMatrixOutputs_lo_lo_lo_72)
node decoded_andMatrixOutputs_lo_hi_lo_117 = cat(decoded_andMatrixOutputs_andMatrixInput_10_117, decoded_andMatrixOutputs_andMatrixInput_11_117)
node decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_andMatrixOutputs_andMatrixInput_8_118, decoded_andMatrixOutputs_andMatrixInput_9_117)
node decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_andMatrixOutputs_lo_hi_hi_117, decoded_andMatrixOutputs_lo_hi_lo_117)
node decoded_andMatrixOutputs_lo_118 = cat(decoded_andMatrixOutputs_lo_hi_118, decoded_andMatrixOutputs_lo_lo_118)
node decoded_andMatrixOutputs_hi_lo_lo_117 = cat(decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_andMatrixOutputs_andMatrixInput_7_118)
node decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_andMatrixOutputs_andMatrixInput_4_118, decoded_andMatrixOutputs_andMatrixInput_5_118)
node decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_andMatrixOutputs_hi_lo_hi_117, decoded_andMatrixOutputs_hi_lo_lo_117)
node decoded_andMatrixOutputs_hi_hi_lo_117 = cat(decoded_andMatrixOutputs_andMatrixInput_2_119, decoded_andMatrixOutputs_andMatrixInput_3_118)
node decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_andMatrixOutputs_andMatrixInput_1_119)
node decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_andMatrixOutputs_hi_hi_hi_118, decoded_andMatrixOutputs_hi_hi_lo_117)
node decoded_andMatrixOutputs_hi_119 = cat(decoded_andMatrixOutputs_hi_hi_118, decoded_andMatrixOutputs_hi_lo_118)
node _decoded_andMatrixOutputs_T_119 = cat(decoded_andMatrixOutputs_hi_119, decoded_andMatrixOutputs_lo_118)
node decoded_andMatrixOutputs_61_2 = andr(_decoded_andMatrixOutputs_T_119)
node decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_118 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_118 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_118 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_73 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_73 = cat(decoded_andMatrixOutputs_andMatrixInput_14_118, decoded_andMatrixOutputs_andMatrixInput_15_73)
node decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_andMatrixOutputs_andMatrixInput_12_118, decoded_andMatrixOutputs_andMatrixInput_13_118)
node decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_andMatrixOutputs_lo_lo_hi_118, decoded_andMatrixOutputs_lo_lo_lo_73)
node decoded_andMatrixOutputs_lo_hi_lo_118 = cat(decoded_andMatrixOutputs_andMatrixInput_10_118, decoded_andMatrixOutputs_andMatrixInput_11_118)
node decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_andMatrixOutputs_andMatrixInput_8_119, decoded_andMatrixOutputs_andMatrixInput_9_118)
node decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_andMatrixOutputs_lo_hi_hi_118, decoded_andMatrixOutputs_lo_hi_lo_118)
node decoded_andMatrixOutputs_lo_119 = cat(decoded_andMatrixOutputs_lo_hi_119, decoded_andMatrixOutputs_lo_lo_119)
node decoded_andMatrixOutputs_hi_lo_lo_118 = cat(decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_andMatrixOutputs_andMatrixInput_7_119)
node decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_andMatrixOutputs_andMatrixInput_4_119, decoded_andMatrixOutputs_andMatrixInput_5_119)
node decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_andMatrixOutputs_hi_lo_hi_118, decoded_andMatrixOutputs_hi_lo_lo_118)
node decoded_andMatrixOutputs_hi_hi_lo_118 = cat(decoded_andMatrixOutputs_andMatrixInput_2_120, decoded_andMatrixOutputs_andMatrixInput_3_119)
node decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_andMatrixOutputs_andMatrixInput_1_120)
node decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_andMatrixOutputs_hi_hi_hi_119, decoded_andMatrixOutputs_hi_hi_lo_118)
node decoded_andMatrixOutputs_hi_120 = cat(decoded_andMatrixOutputs_hi_hi_119, decoded_andMatrixOutputs_hi_lo_119)
node _decoded_andMatrixOutputs_T_120 = cat(decoded_andMatrixOutputs_hi_120, decoded_andMatrixOutputs_lo_119)
node decoded_andMatrixOutputs_56_2 = andr(_decoded_andMatrixOutputs_T_120)
node decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_119 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_119 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_119 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_74 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_74 = cat(decoded_andMatrixOutputs_andMatrixInput_14_119, decoded_andMatrixOutputs_andMatrixInput_15_74)
node decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_andMatrixOutputs_andMatrixInput_12_119, decoded_andMatrixOutputs_andMatrixInput_13_119)
node decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_andMatrixOutputs_lo_lo_hi_119, decoded_andMatrixOutputs_lo_lo_lo_74)
node decoded_andMatrixOutputs_lo_hi_lo_119 = cat(decoded_andMatrixOutputs_andMatrixInput_10_119, decoded_andMatrixOutputs_andMatrixInput_11_119)
node decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_andMatrixOutputs_andMatrixInput_8_120, decoded_andMatrixOutputs_andMatrixInput_9_119)
node decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_andMatrixOutputs_lo_hi_hi_119, decoded_andMatrixOutputs_lo_hi_lo_119)
node decoded_andMatrixOutputs_lo_120 = cat(decoded_andMatrixOutputs_lo_hi_120, decoded_andMatrixOutputs_lo_lo_120)
node decoded_andMatrixOutputs_hi_lo_lo_119 = cat(decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_andMatrixOutputs_andMatrixInput_7_120)
node decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_andMatrixOutputs_andMatrixInput_4_120, decoded_andMatrixOutputs_andMatrixInput_5_120)
node decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_andMatrixOutputs_hi_lo_hi_119, decoded_andMatrixOutputs_hi_lo_lo_119)
node decoded_andMatrixOutputs_hi_hi_lo_119 = cat(decoded_andMatrixOutputs_andMatrixInput_2_121, decoded_andMatrixOutputs_andMatrixInput_3_120)
node decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_andMatrixOutputs_andMatrixInput_1_121)
node decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_andMatrixOutputs_hi_hi_hi_120, decoded_andMatrixOutputs_hi_hi_lo_119)
node decoded_andMatrixOutputs_hi_121 = cat(decoded_andMatrixOutputs_hi_hi_120, decoded_andMatrixOutputs_hi_lo_120)
node _decoded_andMatrixOutputs_T_121 = cat(decoded_andMatrixOutputs_hi_121, decoded_andMatrixOutputs_lo_120)
node decoded_andMatrixOutputs_70_2 = andr(_decoded_andMatrixOutputs_T_121)
node decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_120 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_120 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_120 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_andMatrixOutputs_andMatrixInput_12_120, decoded_andMatrixOutputs_andMatrixInput_13_120)
node decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_andMatrixOutputs_lo_lo_hi_120, decoded_andMatrixOutputs_andMatrixInput_14_120)
node decoded_andMatrixOutputs_lo_hi_lo_120 = cat(decoded_andMatrixOutputs_andMatrixInput_10_120, decoded_andMatrixOutputs_andMatrixInput_11_120)
node decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_andMatrixOutputs_andMatrixInput_8_121, decoded_andMatrixOutputs_andMatrixInput_9_120)
node decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_andMatrixOutputs_lo_hi_hi_120, decoded_andMatrixOutputs_lo_hi_lo_120)
node decoded_andMatrixOutputs_lo_121 = cat(decoded_andMatrixOutputs_lo_hi_121, decoded_andMatrixOutputs_lo_lo_121)
node decoded_andMatrixOutputs_hi_lo_lo_120 = cat(decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_andMatrixOutputs_andMatrixInput_7_121)
node decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_andMatrixOutputs_andMatrixInput_4_121, decoded_andMatrixOutputs_andMatrixInput_5_121)
node decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_andMatrixOutputs_hi_lo_hi_120, decoded_andMatrixOutputs_hi_lo_lo_120)
node decoded_andMatrixOutputs_hi_hi_lo_120 = cat(decoded_andMatrixOutputs_andMatrixInput_2_122, decoded_andMatrixOutputs_andMatrixInput_3_121)
node decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_andMatrixOutputs_andMatrixInput_1_122)
node decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_andMatrixOutputs_hi_hi_hi_121, decoded_andMatrixOutputs_hi_hi_lo_120)
node decoded_andMatrixOutputs_hi_122 = cat(decoded_andMatrixOutputs_hi_hi_121, decoded_andMatrixOutputs_hi_lo_121)
node _decoded_andMatrixOutputs_T_122 = cat(decoded_andMatrixOutputs_hi_122, decoded_andMatrixOutputs_lo_121)
node decoded_andMatrixOutputs_13_2_2 = andr(_decoded_andMatrixOutputs_T_122)
node decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_121 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_121 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_121 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_andMatrixOutputs_andMatrixInput_12_121, decoded_andMatrixOutputs_andMatrixInput_13_121)
node decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_andMatrixOutputs_lo_lo_hi_121, decoded_andMatrixOutputs_andMatrixInput_14_121)
node decoded_andMatrixOutputs_lo_hi_lo_121 = cat(decoded_andMatrixOutputs_andMatrixInput_10_121, decoded_andMatrixOutputs_andMatrixInput_11_121)
node decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_andMatrixOutputs_andMatrixInput_8_122, decoded_andMatrixOutputs_andMatrixInput_9_121)
node decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_andMatrixOutputs_lo_hi_hi_121, decoded_andMatrixOutputs_lo_hi_lo_121)
node decoded_andMatrixOutputs_lo_122 = cat(decoded_andMatrixOutputs_lo_hi_122, decoded_andMatrixOutputs_lo_lo_122)
node decoded_andMatrixOutputs_hi_lo_lo_121 = cat(decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_andMatrixOutputs_andMatrixInput_7_122)
node decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_andMatrixOutputs_andMatrixInput_4_122, decoded_andMatrixOutputs_andMatrixInput_5_122)
node decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_andMatrixOutputs_hi_lo_hi_121, decoded_andMatrixOutputs_hi_lo_lo_121)
node decoded_andMatrixOutputs_hi_hi_lo_121 = cat(decoded_andMatrixOutputs_andMatrixInput_2_123, decoded_andMatrixOutputs_andMatrixInput_3_122)
node decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_andMatrixOutputs_andMatrixInput_1_123)
node decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_andMatrixOutputs_hi_hi_hi_122, decoded_andMatrixOutputs_hi_hi_lo_121)
node decoded_andMatrixOutputs_hi_123 = cat(decoded_andMatrixOutputs_hi_hi_122, decoded_andMatrixOutputs_hi_lo_122)
node _decoded_andMatrixOutputs_T_123 = cat(decoded_andMatrixOutputs_hi_123, decoded_andMatrixOutputs_lo_122)
node decoded_andMatrixOutputs_65_2 = andr(_decoded_andMatrixOutputs_T_123)
node decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_122 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_122 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_122 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_andMatrixOutputs_andMatrixInput_12_122, decoded_andMatrixOutputs_andMatrixInput_13_122)
node decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_andMatrixOutputs_lo_lo_hi_122, decoded_andMatrixOutputs_andMatrixInput_14_122)
node decoded_andMatrixOutputs_lo_hi_lo_122 = cat(decoded_andMatrixOutputs_andMatrixInput_10_122, decoded_andMatrixOutputs_andMatrixInput_11_122)
node decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_andMatrixOutputs_andMatrixInput_8_123, decoded_andMatrixOutputs_andMatrixInput_9_122)
node decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_andMatrixOutputs_lo_hi_hi_122, decoded_andMatrixOutputs_lo_hi_lo_122)
node decoded_andMatrixOutputs_lo_123 = cat(decoded_andMatrixOutputs_lo_hi_123, decoded_andMatrixOutputs_lo_lo_123)
node decoded_andMatrixOutputs_hi_lo_lo_122 = cat(decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_andMatrixOutputs_andMatrixInput_7_123)
node decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_andMatrixOutputs_andMatrixInput_4_123, decoded_andMatrixOutputs_andMatrixInput_5_123)
node decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_andMatrixOutputs_hi_lo_hi_122, decoded_andMatrixOutputs_hi_lo_lo_122)
node decoded_andMatrixOutputs_hi_hi_lo_122 = cat(decoded_andMatrixOutputs_andMatrixInput_2_124, decoded_andMatrixOutputs_andMatrixInput_3_123)
node decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_andMatrixOutputs_andMatrixInput_1_124)
node decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_andMatrixOutputs_hi_hi_hi_123, decoded_andMatrixOutputs_hi_hi_lo_122)
node decoded_andMatrixOutputs_hi_124 = cat(decoded_andMatrixOutputs_hi_hi_123, decoded_andMatrixOutputs_hi_lo_123)
node _decoded_andMatrixOutputs_T_124 = cat(decoded_andMatrixOutputs_hi_124, decoded_andMatrixOutputs_lo_123)
node decoded_andMatrixOutputs_22_2_2 = andr(_decoded_andMatrixOutputs_T_124)
node decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_123 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_123 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_123 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_andMatrixOutputs_andMatrixInput_12_123, decoded_andMatrixOutputs_andMatrixInput_13_123)
node decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_andMatrixOutputs_lo_lo_hi_123, decoded_andMatrixOutputs_andMatrixInput_14_123)
node decoded_andMatrixOutputs_lo_hi_lo_123 = cat(decoded_andMatrixOutputs_andMatrixInput_10_123, decoded_andMatrixOutputs_andMatrixInput_11_123)
node decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_andMatrixOutputs_andMatrixInput_8_124, decoded_andMatrixOutputs_andMatrixInput_9_123)
node decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_andMatrixOutputs_lo_hi_hi_123, decoded_andMatrixOutputs_lo_hi_lo_123)
node decoded_andMatrixOutputs_lo_124 = cat(decoded_andMatrixOutputs_lo_hi_124, decoded_andMatrixOutputs_lo_lo_124)
node decoded_andMatrixOutputs_hi_lo_lo_123 = cat(decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_andMatrixOutputs_andMatrixInput_7_124)
node decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_andMatrixOutputs_andMatrixInput_4_124, decoded_andMatrixOutputs_andMatrixInput_5_124)
node decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_andMatrixOutputs_hi_lo_hi_123, decoded_andMatrixOutputs_hi_lo_lo_123)
node decoded_andMatrixOutputs_hi_hi_lo_123 = cat(decoded_andMatrixOutputs_andMatrixInput_2_125, decoded_andMatrixOutputs_andMatrixInput_3_124)
node decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_andMatrixOutputs_andMatrixInput_1_125)
node decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_andMatrixOutputs_hi_hi_hi_124, decoded_andMatrixOutputs_hi_hi_lo_123)
node decoded_andMatrixOutputs_hi_125 = cat(decoded_andMatrixOutputs_hi_hi_124, decoded_andMatrixOutputs_hi_lo_124)
node _decoded_andMatrixOutputs_T_125 = cat(decoded_andMatrixOutputs_hi_125, decoded_andMatrixOutputs_lo_124)
node decoded_andMatrixOutputs_14_2_2 = andr(_decoded_andMatrixOutputs_T_125)
node decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_andMatrixOutputs_andMatrixInput_7_125, decoded_andMatrixOutputs_andMatrixInput_8_125)
node decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_andMatrixOutputs_andMatrixInput_5_125, decoded_andMatrixOutputs_andMatrixInput_6_125)
node decoded_andMatrixOutputs_lo_125 = cat(decoded_andMatrixOutputs_lo_hi_125, decoded_andMatrixOutputs_lo_lo_125)
node decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_andMatrixOutputs_andMatrixInput_4_125)
node decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_andMatrixOutputs_andMatrixInput_1_126)
node decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_andMatrixOutputs_hi_hi_hi_125, decoded_andMatrixOutputs_andMatrixInput_2_126)
node decoded_andMatrixOutputs_hi_126 = cat(decoded_andMatrixOutputs_hi_hi_125, decoded_andMatrixOutputs_hi_lo_125)
node _decoded_andMatrixOutputs_T_126 = cat(decoded_andMatrixOutputs_hi_126, decoded_andMatrixOutputs_lo_125)
node decoded_andMatrixOutputs_44_2_1 = andr(_decoded_andMatrixOutputs_T_126)
node decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_124 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_124 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_124 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_andMatrixOutputs_andMatrixInput_12_124, decoded_andMatrixOutputs_andMatrixInput_13_124)
node decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_andMatrixOutputs_lo_lo_hi_124, decoded_andMatrixOutputs_andMatrixInput_14_124)
node decoded_andMatrixOutputs_lo_hi_lo_124 = cat(decoded_andMatrixOutputs_andMatrixInput_10_124, decoded_andMatrixOutputs_andMatrixInput_11_124)
node decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_andMatrixOutputs_andMatrixInput_8_126, decoded_andMatrixOutputs_andMatrixInput_9_124)
node decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_andMatrixOutputs_lo_hi_hi_124, decoded_andMatrixOutputs_lo_hi_lo_124)
node decoded_andMatrixOutputs_lo_126 = cat(decoded_andMatrixOutputs_lo_hi_126, decoded_andMatrixOutputs_lo_lo_126)
node decoded_andMatrixOutputs_hi_lo_lo_124 = cat(decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_andMatrixOutputs_andMatrixInput_7_126)
node decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_andMatrixOutputs_andMatrixInput_4_126, decoded_andMatrixOutputs_andMatrixInput_5_126)
node decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_andMatrixOutputs_hi_lo_hi_124, decoded_andMatrixOutputs_hi_lo_lo_124)
node decoded_andMatrixOutputs_hi_hi_lo_124 = cat(decoded_andMatrixOutputs_andMatrixInput_2_127, decoded_andMatrixOutputs_andMatrixInput_3_126)
node decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_andMatrixOutputs_andMatrixInput_1_127)
node decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_andMatrixOutputs_hi_hi_hi_126, decoded_andMatrixOutputs_hi_hi_lo_124)
node decoded_andMatrixOutputs_hi_127 = cat(decoded_andMatrixOutputs_hi_hi_126, decoded_andMatrixOutputs_hi_lo_126)
node _decoded_andMatrixOutputs_T_127 = cat(decoded_andMatrixOutputs_hi_127, decoded_andMatrixOutputs_lo_126)
node decoded_andMatrixOutputs_49_2_1 = andr(_decoded_andMatrixOutputs_T_127)
node decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_125 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_125 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_125 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_andMatrixOutputs_andMatrixInput_12_125, decoded_andMatrixOutputs_andMatrixInput_13_125)
node decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_andMatrixOutputs_lo_lo_hi_125, decoded_andMatrixOutputs_andMatrixInput_14_125)
node decoded_andMatrixOutputs_lo_hi_lo_125 = cat(decoded_andMatrixOutputs_andMatrixInput_10_125, decoded_andMatrixOutputs_andMatrixInput_11_125)
node decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_andMatrixOutputs_andMatrixInput_8_127, decoded_andMatrixOutputs_andMatrixInput_9_125)
node decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_andMatrixOutputs_lo_hi_hi_125, decoded_andMatrixOutputs_lo_hi_lo_125)
node decoded_andMatrixOutputs_lo_127 = cat(decoded_andMatrixOutputs_lo_hi_127, decoded_andMatrixOutputs_lo_lo_127)
node decoded_andMatrixOutputs_hi_lo_lo_125 = cat(decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_andMatrixOutputs_andMatrixInput_7_127)
node decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_andMatrixOutputs_andMatrixInput_4_127, decoded_andMatrixOutputs_andMatrixInput_5_127)
node decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_andMatrixOutputs_hi_lo_hi_125, decoded_andMatrixOutputs_hi_lo_lo_125)
node decoded_andMatrixOutputs_hi_hi_lo_125 = cat(decoded_andMatrixOutputs_andMatrixInput_2_128, decoded_andMatrixOutputs_andMatrixInput_3_127)
node decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_andMatrixOutputs_andMatrixInput_1_128)
node decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_andMatrixOutputs_hi_hi_hi_127, decoded_andMatrixOutputs_hi_hi_lo_125)
node decoded_andMatrixOutputs_hi_128 = cat(decoded_andMatrixOutputs_hi_hi_127, decoded_andMatrixOutputs_hi_lo_127)
node _decoded_andMatrixOutputs_T_128 = cat(decoded_andMatrixOutputs_hi_128, decoded_andMatrixOutputs_lo_127)
node decoded_andMatrixOutputs_4_2_2 = andr(_decoded_andMatrixOutputs_T_128)
node decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_126 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_126 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_126 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_75 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_75 = cat(decoded_andMatrixOutputs_andMatrixInput_14_126, decoded_andMatrixOutputs_andMatrixInput_15_75)
node decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_andMatrixOutputs_andMatrixInput_12_126, decoded_andMatrixOutputs_andMatrixInput_13_126)
node decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_andMatrixOutputs_lo_lo_hi_126, decoded_andMatrixOutputs_lo_lo_lo_75)
node decoded_andMatrixOutputs_lo_hi_lo_126 = cat(decoded_andMatrixOutputs_andMatrixInput_10_126, decoded_andMatrixOutputs_andMatrixInput_11_126)
node decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_andMatrixOutputs_andMatrixInput_8_128, decoded_andMatrixOutputs_andMatrixInput_9_126)
node decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_andMatrixOutputs_lo_hi_hi_126, decoded_andMatrixOutputs_lo_hi_lo_126)
node decoded_andMatrixOutputs_lo_128 = cat(decoded_andMatrixOutputs_lo_hi_128, decoded_andMatrixOutputs_lo_lo_128)
node decoded_andMatrixOutputs_hi_lo_lo_126 = cat(decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_andMatrixOutputs_andMatrixInput_7_128)
node decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_andMatrixOutputs_andMatrixInput_4_128, decoded_andMatrixOutputs_andMatrixInput_5_128)
node decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_andMatrixOutputs_hi_lo_hi_126, decoded_andMatrixOutputs_hi_lo_lo_126)
node decoded_andMatrixOutputs_hi_hi_lo_126 = cat(decoded_andMatrixOutputs_andMatrixInput_2_129, decoded_andMatrixOutputs_andMatrixInput_3_128)
node decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_andMatrixOutputs_andMatrixInput_1_129)
node decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_andMatrixOutputs_hi_hi_hi_128, decoded_andMatrixOutputs_hi_hi_lo_126)
node decoded_andMatrixOutputs_hi_129 = cat(decoded_andMatrixOutputs_hi_hi_128, decoded_andMatrixOutputs_hi_lo_128)
node _decoded_andMatrixOutputs_T_129 = cat(decoded_andMatrixOutputs_hi_129, decoded_andMatrixOutputs_lo_128)
node decoded_andMatrixOutputs_8_2_2 = andr(_decoded_andMatrixOutputs_T_129)
node decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_127 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_127 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_127 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_76 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_76 = cat(decoded_andMatrixOutputs_andMatrixInput_14_127, decoded_andMatrixOutputs_andMatrixInput_15_76)
node decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_andMatrixOutputs_andMatrixInput_12_127, decoded_andMatrixOutputs_andMatrixInput_13_127)
node decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_andMatrixOutputs_lo_lo_hi_127, decoded_andMatrixOutputs_lo_lo_lo_76)
node decoded_andMatrixOutputs_lo_hi_lo_127 = cat(decoded_andMatrixOutputs_andMatrixInput_10_127, decoded_andMatrixOutputs_andMatrixInput_11_127)
node decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_andMatrixOutputs_andMatrixInput_8_129, decoded_andMatrixOutputs_andMatrixInput_9_127)
node decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_andMatrixOutputs_lo_hi_hi_127, decoded_andMatrixOutputs_lo_hi_lo_127)
node decoded_andMatrixOutputs_lo_129 = cat(decoded_andMatrixOutputs_lo_hi_129, decoded_andMatrixOutputs_lo_lo_129)
node decoded_andMatrixOutputs_hi_lo_lo_127 = cat(decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_andMatrixOutputs_andMatrixInput_7_129)
node decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_andMatrixOutputs_andMatrixInput_4_129, decoded_andMatrixOutputs_andMatrixInput_5_129)
node decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_andMatrixOutputs_hi_lo_hi_127, decoded_andMatrixOutputs_hi_lo_lo_127)
node decoded_andMatrixOutputs_hi_hi_lo_127 = cat(decoded_andMatrixOutputs_andMatrixInput_2_130, decoded_andMatrixOutputs_andMatrixInput_3_129)
node decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_andMatrixOutputs_andMatrixInput_1_130)
node decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_andMatrixOutputs_hi_hi_hi_129, decoded_andMatrixOutputs_hi_hi_lo_127)
node decoded_andMatrixOutputs_hi_130 = cat(decoded_andMatrixOutputs_hi_hi_129, decoded_andMatrixOutputs_hi_lo_129)
node _decoded_andMatrixOutputs_T_130 = cat(decoded_andMatrixOutputs_hi_130, decoded_andMatrixOutputs_lo_129)
node decoded_andMatrixOutputs_36_2_2 = andr(_decoded_andMatrixOutputs_T_130)
node decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_128 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_128 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_128 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_77 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_77 = cat(decoded_andMatrixOutputs_andMatrixInput_14_128, decoded_andMatrixOutputs_andMatrixInput_15_77)
node decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_andMatrixOutputs_andMatrixInput_12_128, decoded_andMatrixOutputs_andMatrixInput_13_128)
node decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_andMatrixOutputs_lo_lo_hi_128, decoded_andMatrixOutputs_lo_lo_lo_77)
node decoded_andMatrixOutputs_lo_hi_lo_128 = cat(decoded_andMatrixOutputs_andMatrixInput_10_128, decoded_andMatrixOutputs_andMatrixInput_11_128)
node decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_andMatrixOutputs_andMatrixInput_8_130, decoded_andMatrixOutputs_andMatrixInput_9_128)
node decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_andMatrixOutputs_lo_hi_hi_128, decoded_andMatrixOutputs_lo_hi_lo_128)
node decoded_andMatrixOutputs_lo_130 = cat(decoded_andMatrixOutputs_lo_hi_130, decoded_andMatrixOutputs_lo_lo_130)
node decoded_andMatrixOutputs_hi_lo_lo_128 = cat(decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_andMatrixOutputs_andMatrixInput_7_130)
node decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_andMatrixOutputs_andMatrixInput_4_130, decoded_andMatrixOutputs_andMatrixInput_5_130)
node decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_andMatrixOutputs_hi_lo_hi_128, decoded_andMatrixOutputs_hi_lo_lo_128)
node decoded_andMatrixOutputs_hi_hi_lo_128 = cat(decoded_andMatrixOutputs_andMatrixInput_2_131, decoded_andMatrixOutputs_andMatrixInput_3_130)
node decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_andMatrixOutputs_andMatrixInput_1_131)
node decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_andMatrixOutputs_hi_hi_hi_130, decoded_andMatrixOutputs_hi_hi_lo_128)
node decoded_andMatrixOutputs_hi_131 = cat(decoded_andMatrixOutputs_hi_hi_130, decoded_andMatrixOutputs_hi_lo_130)
node _decoded_andMatrixOutputs_T_131 = cat(decoded_andMatrixOutputs_hi_131, decoded_andMatrixOutputs_lo_130)
node decoded_andMatrixOutputs_58_2 = andr(_decoded_andMatrixOutputs_T_131)
node decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_129 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_129 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_129 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_78 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_78 = cat(decoded_andMatrixOutputs_andMatrixInput_14_129, decoded_andMatrixOutputs_andMatrixInput_15_78)
node decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_andMatrixOutputs_andMatrixInput_12_129, decoded_andMatrixOutputs_andMatrixInput_13_129)
node decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_andMatrixOutputs_lo_lo_hi_129, decoded_andMatrixOutputs_lo_lo_lo_78)
node decoded_andMatrixOutputs_lo_hi_lo_129 = cat(decoded_andMatrixOutputs_andMatrixInput_10_129, decoded_andMatrixOutputs_andMatrixInput_11_129)
node decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_andMatrixOutputs_andMatrixInput_8_131, decoded_andMatrixOutputs_andMatrixInput_9_129)
node decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_andMatrixOutputs_lo_hi_hi_129, decoded_andMatrixOutputs_lo_hi_lo_129)
node decoded_andMatrixOutputs_lo_131 = cat(decoded_andMatrixOutputs_lo_hi_131, decoded_andMatrixOutputs_lo_lo_131)
node decoded_andMatrixOutputs_hi_lo_lo_129 = cat(decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_andMatrixOutputs_andMatrixInput_7_131)
node decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_andMatrixOutputs_andMatrixInput_4_131, decoded_andMatrixOutputs_andMatrixInput_5_131)
node decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_andMatrixOutputs_hi_lo_hi_129, decoded_andMatrixOutputs_hi_lo_lo_129)
node decoded_andMatrixOutputs_hi_hi_lo_129 = cat(decoded_andMatrixOutputs_andMatrixInput_2_132, decoded_andMatrixOutputs_andMatrixInput_3_131)
node decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_andMatrixOutputs_andMatrixInput_1_132)
node decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_andMatrixOutputs_hi_hi_hi_131, decoded_andMatrixOutputs_hi_hi_lo_129)
node decoded_andMatrixOutputs_hi_132 = cat(decoded_andMatrixOutputs_hi_hi_131, decoded_andMatrixOutputs_hi_lo_131)
node _decoded_andMatrixOutputs_T_132 = cat(decoded_andMatrixOutputs_hi_132, decoded_andMatrixOutputs_lo_131)
node decoded_andMatrixOutputs_53_2_1 = andr(_decoded_andMatrixOutputs_T_132)
node decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_130 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_130 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_130 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_79 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_79 = cat(decoded_andMatrixOutputs_andMatrixInput_14_130, decoded_andMatrixOutputs_andMatrixInput_15_79)
node decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_andMatrixOutputs_andMatrixInput_12_130, decoded_andMatrixOutputs_andMatrixInput_13_130)
node decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_andMatrixOutputs_lo_lo_hi_130, decoded_andMatrixOutputs_lo_lo_lo_79)
node decoded_andMatrixOutputs_lo_hi_lo_130 = cat(decoded_andMatrixOutputs_andMatrixInput_10_130, decoded_andMatrixOutputs_andMatrixInput_11_130)
node decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_andMatrixOutputs_andMatrixInput_8_132, decoded_andMatrixOutputs_andMatrixInput_9_130)
node decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_andMatrixOutputs_lo_hi_hi_130, decoded_andMatrixOutputs_lo_hi_lo_130)
node decoded_andMatrixOutputs_lo_132 = cat(decoded_andMatrixOutputs_lo_hi_132, decoded_andMatrixOutputs_lo_lo_132)
node decoded_andMatrixOutputs_hi_lo_lo_130 = cat(decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_andMatrixOutputs_andMatrixInput_7_132)
node decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_andMatrixOutputs_andMatrixInput_4_132, decoded_andMatrixOutputs_andMatrixInput_5_132)
node decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_andMatrixOutputs_hi_lo_hi_130, decoded_andMatrixOutputs_hi_lo_lo_130)
node decoded_andMatrixOutputs_hi_hi_lo_130 = cat(decoded_andMatrixOutputs_andMatrixInput_2_133, decoded_andMatrixOutputs_andMatrixInput_3_132)
node decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_andMatrixOutputs_andMatrixInput_1_133)
node decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_andMatrixOutputs_hi_hi_hi_132, decoded_andMatrixOutputs_hi_hi_lo_130)
node decoded_andMatrixOutputs_hi_133 = cat(decoded_andMatrixOutputs_hi_hi_132, decoded_andMatrixOutputs_hi_lo_132)
node _decoded_andMatrixOutputs_T_133 = cat(decoded_andMatrixOutputs_hi_133, decoded_andMatrixOutputs_lo_132)
node decoded_andMatrixOutputs_2_2_2 = andr(_decoded_andMatrixOutputs_T_133)
node decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_131 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_131 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_131 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_80 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_80 = cat(decoded_andMatrixOutputs_andMatrixInput_14_131, decoded_andMatrixOutputs_andMatrixInput_15_80)
node decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_andMatrixOutputs_andMatrixInput_12_131, decoded_andMatrixOutputs_andMatrixInput_13_131)
node decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_andMatrixOutputs_lo_lo_hi_131, decoded_andMatrixOutputs_lo_lo_lo_80)
node decoded_andMatrixOutputs_lo_hi_lo_131 = cat(decoded_andMatrixOutputs_andMatrixInput_10_131, decoded_andMatrixOutputs_andMatrixInput_11_131)
node decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_andMatrixOutputs_andMatrixInput_8_133, decoded_andMatrixOutputs_andMatrixInput_9_131)
node decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_andMatrixOutputs_lo_hi_hi_131, decoded_andMatrixOutputs_lo_hi_lo_131)
node decoded_andMatrixOutputs_lo_133 = cat(decoded_andMatrixOutputs_lo_hi_133, decoded_andMatrixOutputs_lo_lo_133)
node decoded_andMatrixOutputs_hi_lo_lo_131 = cat(decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_andMatrixOutputs_andMatrixInput_7_133)
node decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_andMatrixOutputs_andMatrixInput_4_133, decoded_andMatrixOutputs_andMatrixInput_5_133)
node decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_andMatrixOutputs_hi_lo_hi_131, decoded_andMatrixOutputs_hi_lo_lo_131)
node decoded_andMatrixOutputs_hi_hi_lo_131 = cat(decoded_andMatrixOutputs_andMatrixInput_2_134, decoded_andMatrixOutputs_andMatrixInput_3_133)
node decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_andMatrixOutputs_andMatrixInput_1_134)
node decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_andMatrixOutputs_hi_hi_hi_133, decoded_andMatrixOutputs_hi_hi_lo_131)
node decoded_andMatrixOutputs_hi_134 = cat(decoded_andMatrixOutputs_hi_hi_133, decoded_andMatrixOutputs_hi_lo_133)
node _decoded_andMatrixOutputs_T_134 = cat(decoded_andMatrixOutputs_hi_134, decoded_andMatrixOutputs_lo_133)
node decoded_andMatrixOutputs_38_2_2 = andr(_decoded_andMatrixOutputs_T_134)
node decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_132 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_132 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_132 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_132 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_132 = cat(decoded_andMatrixOutputs_andMatrixInput_12_132, decoded_andMatrixOutputs_andMatrixInput_13_132)
node decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_andMatrixOutputs_lo_lo_hi_132, decoded_andMatrixOutputs_andMatrixInput_14_132)
node decoded_andMatrixOutputs_lo_hi_lo_132 = cat(decoded_andMatrixOutputs_andMatrixInput_10_132, decoded_andMatrixOutputs_andMatrixInput_11_132)
node decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_andMatrixOutputs_andMatrixInput_8_134, decoded_andMatrixOutputs_andMatrixInput_9_132)
node decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_andMatrixOutputs_lo_hi_hi_132, decoded_andMatrixOutputs_lo_hi_lo_132)
node decoded_andMatrixOutputs_lo_134 = cat(decoded_andMatrixOutputs_lo_hi_134, decoded_andMatrixOutputs_lo_lo_134)
node decoded_andMatrixOutputs_hi_lo_lo_132 = cat(decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_andMatrixOutputs_andMatrixInput_7_134)
node decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_andMatrixOutputs_andMatrixInput_4_134, decoded_andMatrixOutputs_andMatrixInput_5_134)
node decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_andMatrixOutputs_hi_lo_hi_132, decoded_andMatrixOutputs_hi_lo_lo_132)
node decoded_andMatrixOutputs_hi_hi_lo_132 = cat(decoded_andMatrixOutputs_andMatrixInput_2_135, decoded_andMatrixOutputs_andMatrixInput_3_134)
node decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_andMatrixOutputs_andMatrixInput_1_135)
node decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_andMatrixOutputs_hi_hi_hi_134, decoded_andMatrixOutputs_hi_hi_lo_132)
node decoded_andMatrixOutputs_hi_135 = cat(decoded_andMatrixOutputs_hi_hi_134, decoded_andMatrixOutputs_hi_lo_134)
node _decoded_andMatrixOutputs_T_135 = cat(decoded_andMatrixOutputs_hi_135, decoded_andMatrixOutputs_lo_134)
node decoded_andMatrixOutputs_15_2_2 = andr(_decoded_andMatrixOutputs_T_135)
node decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_plaInput_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_plaInput_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_133 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_133 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_133 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_133 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_133 = cat(decoded_andMatrixOutputs_andMatrixInput_12_133, decoded_andMatrixOutputs_andMatrixInput_13_133)
node decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_andMatrixOutputs_lo_lo_hi_133, decoded_andMatrixOutputs_andMatrixInput_14_133)
node decoded_andMatrixOutputs_lo_hi_lo_133 = cat(decoded_andMatrixOutputs_andMatrixInput_10_133, decoded_andMatrixOutputs_andMatrixInput_11_133)
node decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_andMatrixOutputs_andMatrixInput_8_135, decoded_andMatrixOutputs_andMatrixInput_9_133)
node decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_andMatrixOutputs_lo_hi_hi_133, decoded_andMatrixOutputs_lo_hi_lo_133)
node decoded_andMatrixOutputs_lo_135 = cat(decoded_andMatrixOutputs_lo_hi_135, decoded_andMatrixOutputs_lo_lo_135)
node decoded_andMatrixOutputs_hi_lo_lo_133 = cat(decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_andMatrixOutputs_andMatrixInput_7_135)
node decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_andMatrixOutputs_andMatrixInput_4_135, decoded_andMatrixOutputs_andMatrixInput_5_135)
node decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_andMatrixOutputs_hi_lo_hi_133, decoded_andMatrixOutputs_hi_lo_lo_133)
node decoded_andMatrixOutputs_hi_hi_lo_133 = cat(decoded_andMatrixOutputs_andMatrixInput_2_136, decoded_andMatrixOutputs_andMatrixInput_3_135)
node decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_andMatrixOutputs_andMatrixInput_1_136)
node decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_andMatrixOutputs_hi_hi_hi_135, decoded_andMatrixOutputs_hi_hi_lo_133)
node decoded_andMatrixOutputs_hi_136 = cat(decoded_andMatrixOutputs_hi_hi_135, decoded_andMatrixOutputs_hi_lo_135)
node _decoded_andMatrixOutputs_T_136 = cat(decoded_andMatrixOutputs_hi_136, decoded_andMatrixOutputs_lo_135)
node decoded_andMatrixOutputs_25_2_2 = andr(_decoded_andMatrixOutputs_T_136)
node decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_134 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_134 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_134 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_134 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_81 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_81 = cat(decoded_andMatrixOutputs_andMatrixInput_14_134, decoded_andMatrixOutputs_andMatrixInput_15_81)
node decoded_andMatrixOutputs_lo_lo_hi_134 = cat(decoded_andMatrixOutputs_andMatrixInput_12_134, decoded_andMatrixOutputs_andMatrixInput_13_134)
node decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_andMatrixOutputs_lo_lo_hi_134, decoded_andMatrixOutputs_lo_lo_lo_81)
node decoded_andMatrixOutputs_lo_hi_lo_134 = cat(decoded_andMatrixOutputs_andMatrixInput_10_134, decoded_andMatrixOutputs_andMatrixInput_11_134)
node decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_andMatrixOutputs_andMatrixInput_8_136, decoded_andMatrixOutputs_andMatrixInput_9_134)
node decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_andMatrixOutputs_lo_hi_hi_134, decoded_andMatrixOutputs_lo_hi_lo_134)
node decoded_andMatrixOutputs_lo_136 = cat(decoded_andMatrixOutputs_lo_hi_136, decoded_andMatrixOutputs_lo_lo_136)
node decoded_andMatrixOutputs_hi_lo_lo_134 = cat(decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_andMatrixOutputs_andMatrixInput_7_136)
node decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_andMatrixOutputs_andMatrixInput_4_136, decoded_andMatrixOutputs_andMatrixInput_5_136)
node decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_andMatrixOutputs_hi_lo_hi_134, decoded_andMatrixOutputs_hi_lo_lo_134)
node decoded_andMatrixOutputs_hi_hi_lo_134 = cat(decoded_andMatrixOutputs_andMatrixInput_2_137, decoded_andMatrixOutputs_andMatrixInput_3_136)
node decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_andMatrixOutputs_andMatrixInput_1_137)
node decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_andMatrixOutputs_hi_hi_hi_136, decoded_andMatrixOutputs_hi_hi_lo_134)
node decoded_andMatrixOutputs_hi_137 = cat(decoded_andMatrixOutputs_hi_hi_136, decoded_andMatrixOutputs_hi_lo_136)
node _decoded_andMatrixOutputs_T_137 = cat(decoded_andMatrixOutputs_hi_137, decoded_andMatrixOutputs_lo_136)
node decoded_andMatrixOutputs_32_2_2 = andr(_decoded_andMatrixOutputs_T_137)
node decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_135 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_135 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_135 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_135 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_82 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_82 = cat(decoded_andMatrixOutputs_andMatrixInput_14_135, decoded_andMatrixOutputs_andMatrixInput_15_82)
node decoded_andMatrixOutputs_lo_lo_hi_135 = cat(decoded_andMatrixOutputs_andMatrixInput_12_135, decoded_andMatrixOutputs_andMatrixInput_13_135)
node decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_andMatrixOutputs_lo_lo_hi_135, decoded_andMatrixOutputs_lo_lo_lo_82)
node decoded_andMatrixOutputs_lo_hi_lo_135 = cat(decoded_andMatrixOutputs_andMatrixInput_10_135, decoded_andMatrixOutputs_andMatrixInput_11_135)
node decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_andMatrixOutputs_andMatrixInput_8_137, decoded_andMatrixOutputs_andMatrixInput_9_135)
node decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_andMatrixOutputs_lo_hi_hi_135, decoded_andMatrixOutputs_lo_hi_lo_135)
node decoded_andMatrixOutputs_lo_137 = cat(decoded_andMatrixOutputs_lo_hi_137, decoded_andMatrixOutputs_lo_lo_137)
node decoded_andMatrixOutputs_hi_lo_lo_135 = cat(decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_andMatrixOutputs_andMatrixInput_7_137)
node decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_andMatrixOutputs_andMatrixInput_4_137, decoded_andMatrixOutputs_andMatrixInput_5_137)
node decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_andMatrixOutputs_hi_lo_hi_135, decoded_andMatrixOutputs_hi_lo_lo_135)
node decoded_andMatrixOutputs_hi_hi_lo_135 = cat(decoded_andMatrixOutputs_andMatrixInput_2_138, decoded_andMatrixOutputs_andMatrixInput_3_137)
node decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_andMatrixOutputs_andMatrixInput_1_138)
node decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_andMatrixOutputs_hi_hi_hi_137, decoded_andMatrixOutputs_hi_hi_lo_135)
node decoded_andMatrixOutputs_hi_138 = cat(decoded_andMatrixOutputs_hi_hi_137, decoded_andMatrixOutputs_hi_lo_137)
node _decoded_andMatrixOutputs_T_138 = cat(decoded_andMatrixOutputs_hi_138, decoded_andMatrixOutputs_lo_137)
node decoded_andMatrixOutputs_54_2_1 = andr(_decoded_andMatrixOutputs_T_138)
node decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_136 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_136 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_136 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_136 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_83 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_83 = cat(decoded_andMatrixOutputs_andMatrixInput_14_136, decoded_andMatrixOutputs_andMatrixInput_15_83)
node decoded_andMatrixOutputs_lo_lo_hi_136 = cat(decoded_andMatrixOutputs_andMatrixInput_12_136, decoded_andMatrixOutputs_andMatrixInput_13_136)
node decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_andMatrixOutputs_lo_lo_hi_136, decoded_andMatrixOutputs_lo_lo_lo_83)
node decoded_andMatrixOutputs_lo_hi_lo_136 = cat(decoded_andMatrixOutputs_andMatrixInput_10_136, decoded_andMatrixOutputs_andMatrixInput_11_136)
node decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_andMatrixOutputs_andMatrixInput_8_138, decoded_andMatrixOutputs_andMatrixInput_9_136)
node decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_andMatrixOutputs_lo_hi_hi_136, decoded_andMatrixOutputs_lo_hi_lo_136)
node decoded_andMatrixOutputs_lo_138 = cat(decoded_andMatrixOutputs_lo_hi_138, decoded_andMatrixOutputs_lo_lo_138)
node decoded_andMatrixOutputs_hi_lo_lo_136 = cat(decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_andMatrixOutputs_andMatrixInput_7_138)
node decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_andMatrixOutputs_andMatrixInput_4_138, decoded_andMatrixOutputs_andMatrixInput_5_138)
node decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_andMatrixOutputs_hi_lo_hi_136, decoded_andMatrixOutputs_hi_lo_lo_136)
node decoded_andMatrixOutputs_hi_hi_lo_136 = cat(decoded_andMatrixOutputs_andMatrixInput_2_139, decoded_andMatrixOutputs_andMatrixInput_3_138)
node decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_andMatrixOutputs_andMatrixInput_1_139)
node decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_andMatrixOutputs_hi_hi_hi_138, decoded_andMatrixOutputs_hi_hi_lo_136)
node decoded_andMatrixOutputs_hi_139 = cat(decoded_andMatrixOutputs_hi_hi_138, decoded_andMatrixOutputs_hi_lo_138)
node _decoded_andMatrixOutputs_T_139 = cat(decoded_andMatrixOutputs_hi_139, decoded_andMatrixOutputs_lo_138)
node decoded_andMatrixOutputs_7_2_2 = andr(_decoded_andMatrixOutputs_T_139)
node decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_plaInput_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_137 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_137 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_137 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_137 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_84 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_84 = cat(decoded_andMatrixOutputs_andMatrixInput_14_137, decoded_andMatrixOutputs_andMatrixInput_15_84)
node decoded_andMatrixOutputs_lo_lo_hi_137 = cat(decoded_andMatrixOutputs_andMatrixInput_12_137, decoded_andMatrixOutputs_andMatrixInput_13_137)
node decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_andMatrixOutputs_lo_lo_hi_137, decoded_andMatrixOutputs_lo_lo_lo_84)
node decoded_andMatrixOutputs_lo_hi_lo_137 = cat(decoded_andMatrixOutputs_andMatrixInput_10_137, decoded_andMatrixOutputs_andMatrixInput_11_137)
node decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_andMatrixOutputs_andMatrixInput_8_139, decoded_andMatrixOutputs_andMatrixInput_9_137)
node decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_andMatrixOutputs_lo_hi_hi_137, decoded_andMatrixOutputs_lo_hi_lo_137)
node decoded_andMatrixOutputs_lo_139 = cat(decoded_andMatrixOutputs_lo_hi_139, decoded_andMatrixOutputs_lo_lo_139)
node decoded_andMatrixOutputs_hi_lo_lo_137 = cat(decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_andMatrixOutputs_andMatrixInput_7_139)
node decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_andMatrixOutputs_andMatrixInput_4_139, decoded_andMatrixOutputs_andMatrixInput_5_139)
node decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_andMatrixOutputs_hi_lo_hi_137, decoded_andMatrixOutputs_hi_lo_lo_137)
node decoded_andMatrixOutputs_hi_hi_lo_137 = cat(decoded_andMatrixOutputs_andMatrixInput_2_140, decoded_andMatrixOutputs_andMatrixInput_3_139)
node decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_andMatrixOutputs_andMatrixInput_1_140)
node decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_andMatrixOutputs_hi_hi_hi_139, decoded_andMatrixOutputs_hi_hi_lo_137)
node decoded_andMatrixOutputs_hi_140 = cat(decoded_andMatrixOutputs_hi_hi_139, decoded_andMatrixOutputs_hi_lo_139)
node _decoded_andMatrixOutputs_T_140 = cat(decoded_andMatrixOutputs_hi_140, decoded_andMatrixOutputs_lo_139)
node decoded_andMatrixOutputs_34_2_2 = andr(_decoded_andMatrixOutputs_T_140)
node decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_138 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_138 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_138 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_138 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_85 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_85 = cat(decoded_andMatrixOutputs_andMatrixInput_14_138, decoded_andMatrixOutputs_andMatrixInput_15_85)
node decoded_andMatrixOutputs_lo_lo_hi_138 = cat(decoded_andMatrixOutputs_andMatrixInput_12_138, decoded_andMatrixOutputs_andMatrixInput_13_138)
node decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_andMatrixOutputs_lo_lo_hi_138, decoded_andMatrixOutputs_lo_lo_lo_85)
node decoded_andMatrixOutputs_lo_hi_lo_138 = cat(decoded_andMatrixOutputs_andMatrixInput_10_138, decoded_andMatrixOutputs_andMatrixInput_11_138)
node decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_andMatrixOutputs_andMatrixInput_8_140, decoded_andMatrixOutputs_andMatrixInput_9_138)
node decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_andMatrixOutputs_lo_hi_hi_138, decoded_andMatrixOutputs_lo_hi_lo_138)
node decoded_andMatrixOutputs_lo_140 = cat(decoded_andMatrixOutputs_lo_hi_140, decoded_andMatrixOutputs_lo_lo_140)
node decoded_andMatrixOutputs_hi_lo_lo_138 = cat(decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_andMatrixOutputs_andMatrixInput_7_140)
node decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_andMatrixOutputs_andMatrixInput_4_140, decoded_andMatrixOutputs_andMatrixInput_5_140)
node decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_andMatrixOutputs_hi_lo_hi_138, decoded_andMatrixOutputs_hi_lo_lo_138)
node decoded_andMatrixOutputs_hi_hi_lo_138 = cat(decoded_andMatrixOutputs_andMatrixInput_2_141, decoded_andMatrixOutputs_andMatrixInput_3_140)
node decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_andMatrixOutputs_andMatrixInput_1_141)
node decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_andMatrixOutputs_hi_hi_hi_140, decoded_andMatrixOutputs_hi_hi_lo_138)
node decoded_andMatrixOutputs_hi_141 = cat(decoded_andMatrixOutputs_hi_hi_140, decoded_andMatrixOutputs_hi_lo_140)
node _decoded_andMatrixOutputs_T_141 = cat(decoded_andMatrixOutputs_hi_141, decoded_andMatrixOutputs_lo_140)
node decoded_andMatrixOutputs_12_2_2 = andr(_decoded_andMatrixOutputs_T_141)
node decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_139 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_139 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_139 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_139 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_86 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_86 = cat(decoded_andMatrixOutputs_andMatrixInput_14_139, decoded_andMatrixOutputs_andMatrixInput_15_86)
node decoded_andMatrixOutputs_lo_lo_hi_139 = cat(decoded_andMatrixOutputs_andMatrixInput_12_139, decoded_andMatrixOutputs_andMatrixInput_13_139)
node decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_andMatrixOutputs_lo_lo_hi_139, decoded_andMatrixOutputs_lo_lo_lo_86)
node decoded_andMatrixOutputs_lo_hi_lo_139 = cat(decoded_andMatrixOutputs_andMatrixInput_10_139, decoded_andMatrixOutputs_andMatrixInput_11_139)
node decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_andMatrixOutputs_andMatrixInput_8_141, decoded_andMatrixOutputs_andMatrixInput_9_139)
node decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_andMatrixOutputs_lo_hi_hi_139, decoded_andMatrixOutputs_lo_hi_lo_139)
node decoded_andMatrixOutputs_lo_141 = cat(decoded_andMatrixOutputs_lo_hi_141, decoded_andMatrixOutputs_lo_lo_141)
node decoded_andMatrixOutputs_hi_lo_lo_139 = cat(decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_andMatrixOutputs_andMatrixInput_7_141)
node decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_andMatrixOutputs_andMatrixInput_4_141, decoded_andMatrixOutputs_andMatrixInput_5_141)
node decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_andMatrixOutputs_hi_lo_hi_139, decoded_andMatrixOutputs_hi_lo_lo_139)
node decoded_andMatrixOutputs_hi_hi_lo_139 = cat(decoded_andMatrixOutputs_andMatrixInput_2_142, decoded_andMatrixOutputs_andMatrixInput_3_141)
node decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_andMatrixOutputs_andMatrixInput_1_142)
node decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_andMatrixOutputs_hi_hi_hi_141, decoded_andMatrixOutputs_hi_hi_lo_139)
node decoded_andMatrixOutputs_hi_142 = cat(decoded_andMatrixOutputs_hi_hi_141, decoded_andMatrixOutputs_hi_lo_141)
node _decoded_andMatrixOutputs_T_142 = cat(decoded_andMatrixOutputs_hi_142, decoded_andMatrixOutputs_lo_141)
node decoded_andMatrixOutputs_50_2_1 = andr(_decoded_andMatrixOutputs_T_142)
node decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_140 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_140 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_140 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_140 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_87 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_87 = cat(decoded_andMatrixOutputs_andMatrixInput_14_140, decoded_andMatrixOutputs_andMatrixInput_15_87)
node decoded_andMatrixOutputs_lo_lo_hi_140 = cat(decoded_andMatrixOutputs_andMatrixInput_12_140, decoded_andMatrixOutputs_andMatrixInput_13_140)
node decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_andMatrixOutputs_lo_lo_hi_140, decoded_andMatrixOutputs_lo_lo_lo_87)
node decoded_andMatrixOutputs_lo_hi_lo_140 = cat(decoded_andMatrixOutputs_andMatrixInput_10_140, decoded_andMatrixOutputs_andMatrixInput_11_140)
node decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_andMatrixOutputs_andMatrixInput_8_142, decoded_andMatrixOutputs_andMatrixInput_9_140)
node decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_andMatrixOutputs_lo_hi_hi_140, decoded_andMatrixOutputs_lo_hi_lo_140)
node decoded_andMatrixOutputs_lo_142 = cat(decoded_andMatrixOutputs_lo_hi_142, decoded_andMatrixOutputs_lo_lo_142)
node decoded_andMatrixOutputs_hi_lo_lo_140 = cat(decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_andMatrixOutputs_andMatrixInput_7_142)
node decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_andMatrixOutputs_andMatrixInput_4_142, decoded_andMatrixOutputs_andMatrixInput_5_142)
node decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_andMatrixOutputs_hi_lo_hi_140, decoded_andMatrixOutputs_hi_lo_lo_140)
node decoded_andMatrixOutputs_hi_hi_lo_140 = cat(decoded_andMatrixOutputs_andMatrixInput_2_143, decoded_andMatrixOutputs_andMatrixInput_3_142)
node decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_andMatrixOutputs_andMatrixInput_1_143)
node decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_andMatrixOutputs_hi_hi_hi_142, decoded_andMatrixOutputs_hi_hi_lo_140)
node decoded_andMatrixOutputs_hi_143 = cat(decoded_andMatrixOutputs_hi_hi_142, decoded_andMatrixOutputs_hi_lo_142)
node _decoded_andMatrixOutputs_T_143 = cat(decoded_andMatrixOutputs_hi_143, decoded_andMatrixOutputs_lo_142)
node decoded_andMatrixOutputs_5_2_2 = andr(_decoded_andMatrixOutputs_T_143)
node decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_141 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_141 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_141 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_141 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_141 = cat(decoded_andMatrixOutputs_andMatrixInput_12_141, decoded_andMatrixOutputs_andMatrixInput_13_141)
node decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_andMatrixOutputs_lo_lo_hi_141, decoded_andMatrixOutputs_andMatrixInput_14_141)
node decoded_andMatrixOutputs_lo_hi_lo_141 = cat(decoded_andMatrixOutputs_andMatrixInput_10_141, decoded_andMatrixOutputs_andMatrixInput_11_141)
node decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_andMatrixOutputs_andMatrixInput_8_143, decoded_andMatrixOutputs_andMatrixInput_9_141)
node decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_andMatrixOutputs_lo_hi_hi_141, decoded_andMatrixOutputs_lo_hi_lo_141)
node decoded_andMatrixOutputs_lo_143 = cat(decoded_andMatrixOutputs_lo_hi_143, decoded_andMatrixOutputs_lo_lo_143)
node decoded_andMatrixOutputs_hi_lo_lo_141 = cat(decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_andMatrixOutputs_andMatrixInput_7_143)
node decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_andMatrixOutputs_andMatrixInput_4_143, decoded_andMatrixOutputs_andMatrixInput_5_143)
node decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_andMatrixOutputs_hi_lo_hi_141, decoded_andMatrixOutputs_hi_lo_lo_141)
node decoded_andMatrixOutputs_hi_hi_lo_141 = cat(decoded_andMatrixOutputs_andMatrixInput_2_144, decoded_andMatrixOutputs_andMatrixInput_3_143)
node decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_andMatrixOutputs_andMatrixInput_1_144)
node decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_andMatrixOutputs_hi_hi_hi_143, decoded_andMatrixOutputs_hi_hi_lo_141)
node decoded_andMatrixOutputs_hi_144 = cat(decoded_andMatrixOutputs_hi_hi_143, decoded_andMatrixOutputs_hi_lo_143)
node _decoded_andMatrixOutputs_T_144 = cat(decoded_andMatrixOutputs_hi_144, decoded_andMatrixOutputs_lo_143)
node decoded_andMatrixOutputs_30_2_2 = andr(_decoded_andMatrixOutputs_T_144)
node decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_142 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_142 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_142 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_142 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_142 = cat(decoded_andMatrixOutputs_andMatrixInput_12_142, decoded_andMatrixOutputs_andMatrixInput_13_142)
node decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_andMatrixOutputs_lo_lo_hi_142, decoded_andMatrixOutputs_andMatrixInput_14_142)
node decoded_andMatrixOutputs_lo_hi_lo_142 = cat(decoded_andMatrixOutputs_andMatrixInput_10_142, decoded_andMatrixOutputs_andMatrixInput_11_142)
node decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_andMatrixOutputs_andMatrixInput_8_144, decoded_andMatrixOutputs_andMatrixInput_9_142)
node decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_andMatrixOutputs_lo_hi_hi_142, decoded_andMatrixOutputs_lo_hi_lo_142)
node decoded_andMatrixOutputs_lo_144 = cat(decoded_andMatrixOutputs_lo_hi_144, decoded_andMatrixOutputs_lo_lo_144)
node decoded_andMatrixOutputs_hi_lo_lo_142 = cat(decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_andMatrixOutputs_andMatrixInput_7_144)
node decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_andMatrixOutputs_andMatrixInput_4_144, decoded_andMatrixOutputs_andMatrixInput_5_144)
node decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_andMatrixOutputs_hi_lo_hi_142, decoded_andMatrixOutputs_hi_lo_lo_142)
node decoded_andMatrixOutputs_hi_hi_lo_142 = cat(decoded_andMatrixOutputs_andMatrixInput_2_145, decoded_andMatrixOutputs_andMatrixInput_3_144)
node decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_andMatrixOutputs_andMatrixInput_1_145)
node decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_andMatrixOutputs_hi_hi_hi_144, decoded_andMatrixOutputs_hi_hi_lo_142)
node decoded_andMatrixOutputs_hi_145 = cat(decoded_andMatrixOutputs_hi_hi_144, decoded_andMatrixOutputs_hi_lo_144)
node _decoded_andMatrixOutputs_T_145 = cat(decoded_andMatrixOutputs_hi_145, decoded_andMatrixOutputs_lo_144)
node decoded_andMatrixOutputs_26_2_2 = andr(_decoded_andMatrixOutputs_T_145)
node decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_143 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_143 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_143 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_143 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_143 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_143 = cat(decoded_andMatrixOutputs_andMatrixInput_12_143, decoded_andMatrixOutputs_andMatrixInput_13_143)
node decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_andMatrixOutputs_lo_lo_hi_143, decoded_andMatrixOutputs_andMatrixInput_14_143)
node decoded_andMatrixOutputs_lo_hi_lo_143 = cat(decoded_andMatrixOutputs_andMatrixInput_10_143, decoded_andMatrixOutputs_andMatrixInput_11_143)
node decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_andMatrixOutputs_andMatrixInput_8_145, decoded_andMatrixOutputs_andMatrixInput_9_143)
node decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_andMatrixOutputs_lo_hi_hi_143, decoded_andMatrixOutputs_lo_hi_lo_143)
node decoded_andMatrixOutputs_lo_145 = cat(decoded_andMatrixOutputs_lo_hi_145, decoded_andMatrixOutputs_lo_lo_145)
node decoded_andMatrixOutputs_hi_lo_lo_143 = cat(decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_andMatrixOutputs_andMatrixInput_7_145)
node decoded_andMatrixOutputs_hi_lo_hi_143 = cat(decoded_andMatrixOutputs_andMatrixInput_4_145, decoded_andMatrixOutputs_andMatrixInput_5_145)
node decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_andMatrixOutputs_hi_lo_hi_143, decoded_andMatrixOutputs_hi_lo_lo_143)
node decoded_andMatrixOutputs_hi_hi_lo_143 = cat(decoded_andMatrixOutputs_andMatrixInput_2_146, decoded_andMatrixOutputs_andMatrixInput_3_145)
node decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_andMatrixOutputs_andMatrixInput_1_146)
node decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_andMatrixOutputs_hi_hi_hi_145, decoded_andMatrixOutputs_hi_hi_lo_143)
node decoded_andMatrixOutputs_hi_146 = cat(decoded_andMatrixOutputs_hi_hi_145, decoded_andMatrixOutputs_hi_lo_145)
node _decoded_andMatrixOutputs_T_146 = cat(decoded_andMatrixOutputs_hi_146, decoded_andMatrixOutputs_lo_145)
node decoded_andMatrixOutputs_67_2 = andr(_decoded_andMatrixOutputs_T_146)
node decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_plaInput_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_144 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_144 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_144 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_144 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_144 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_144 = cat(decoded_andMatrixOutputs_andMatrixInput_12_144, decoded_andMatrixOutputs_andMatrixInput_13_144)
node decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_andMatrixOutputs_lo_lo_hi_144, decoded_andMatrixOutputs_andMatrixInput_14_144)
node decoded_andMatrixOutputs_lo_hi_lo_144 = cat(decoded_andMatrixOutputs_andMatrixInput_10_144, decoded_andMatrixOutputs_andMatrixInput_11_144)
node decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_andMatrixOutputs_andMatrixInput_8_146, decoded_andMatrixOutputs_andMatrixInput_9_144)
node decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_andMatrixOutputs_lo_hi_hi_144, decoded_andMatrixOutputs_lo_hi_lo_144)
node decoded_andMatrixOutputs_lo_146 = cat(decoded_andMatrixOutputs_lo_hi_146, decoded_andMatrixOutputs_lo_lo_146)
node decoded_andMatrixOutputs_hi_lo_lo_144 = cat(decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_andMatrixOutputs_andMatrixInput_7_146)
node decoded_andMatrixOutputs_hi_lo_hi_144 = cat(decoded_andMatrixOutputs_andMatrixInput_4_146, decoded_andMatrixOutputs_andMatrixInput_5_146)
node decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_andMatrixOutputs_hi_lo_hi_144, decoded_andMatrixOutputs_hi_lo_lo_144)
node decoded_andMatrixOutputs_hi_hi_lo_144 = cat(decoded_andMatrixOutputs_andMatrixInput_2_147, decoded_andMatrixOutputs_andMatrixInput_3_146)
node decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_andMatrixOutputs_andMatrixInput_1_147)
node decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_andMatrixOutputs_hi_hi_hi_146, decoded_andMatrixOutputs_hi_hi_lo_144)
node decoded_andMatrixOutputs_hi_147 = cat(decoded_andMatrixOutputs_hi_hi_146, decoded_andMatrixOutputs_hi_lo_146)
node _decoded_andMatrixOutputs_T_147 = cat(decoded_andMatrixOutputs_hi_147, decoded_andMatrixOutputs_lo_146)
node decoded_andMatrixOutputs_47_2_1 = andr(_decoded_andMatrixOutputs_T_147)
node decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_plaInput_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_andMatrixOutputs_andMatrixInput_7_147, decoded_andMatrixOutputs_andMatrixInput_8_147)
node decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_andMatrixOutputs_andMatrixInput_5_147, decoded_andMatrixOutputs_andMatrixInput_6_147)
node decoded_andMatrixOutputs_lo_147 = cat(decoded_andMatrixOutputs_lo_hi_147, decoded_andMatrixOutputs_lo_lo_147)
node decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_andMatrixOutputs_andMatrixInput_4_147)
node decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_andMatrixOutputs_andMatrixInput_1_148)
node decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_andMatrixOutputs_hi_hi_hi_147, decoded_andMatrixOutputs_andMatrixInput_2_148)
node decoded_andMatrixOutputs_hi_148 = cat(decoded_andMatrixOutputs_hi_hi_147, decoded_andMatrixOutputs_hi_lo_147)
node _decoded_andMatrixOutputs_T_148 = cat(decoded_andMatrixOutputs_hi_148, decoded_andMatrixOutputs_lo_147)
node decoded_andMatrixOutputs_6_2_2 = andr(_decoded_andMatrixOutputs_T_148)
node decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_148 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_145 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_145 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_145 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_145 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_145 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_88 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_88 = cat(decoded_andMatrixOutputs_andMatrixInput_14_145, decoded_andMatrixOutputs_andMatrixInput_15_88)
node decoded_andMatrixOutputs_lo_lo_hi_145 = cat(decoded_andMatrixOutputs_andMatrixInput_12_145, decoded_andMatrixOutputs_andMatrixInput_13_145)
node decoded_andMatrixOutputs_lo_lo_148 = cat(decoded_andMatrixOutputs_lo_lo_hi_145, decoded_andMatrixOutputs_lo_lo_lo_88)
node decoded_andMatrixOutputs_lo_hi_lo_145 = cat(decoded_andMatrixOutputs_andMatrixInput_10_145, decoded_andMatrixOutputs_andMatrixInput_11_145)
node decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_andMatrixOutputs_andMatrixInput_8_148, decoded_andMatrixOutputs_andMatrixInput_9_145)
node decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_andMatrixOutputs_lo_hi_hi_145, decoded_andMatrixOutputs_lo_hi_lo_145)
node decoded_andMatrixOutputs_lo_148 = cat(decoded_andMatrixOutputs_lo_hi_148, decoded_andMatrixOutputs_lo_lo_148)
node decoded_andMatrixOutputs_hi_lo_lo_145 = cat(decoded_andMatrixOutputs_andMatrixInput_6_148, decoded_andMatrixOutputs_andMatrixInput_7_148)
node decoded_andMatrixOutputs_hi_lo_hi_145 = cat(decoded_andMatrixOutputs_andMatrixInput_4_148, decoded_andMatrixOutputs_andMatrixInput_5_148)
node decoded_andMatrixOutputs_hi_lo_148 = cat(decoded_andMatrixOutputs_hi_lo_hi_145, decoded_andMatrixOutputs_hi_lo_lo_145)
node decoded_andMatrixOutputs_hi_hi_lo_145 = cat(decoded_andMatrixOutputs_andMatrixInput_2_149, decoded_andMatrixOutputs_andMatrixInput_3_148)
node decoded_andMatrixOutputs_hi_hi_hi_148 = cat(decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_andMatrixOutputs_andMatrixInput_1_149)
node decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_andMatrixOutputs_hi_hi_hi_148, decoded_andMatrixOutputs_hi_hi_lo_145)
node decoded_andMatrixOutputs_hi_149 = cat(decoded_andMatrixOutputs_hi_hi_148, decoded_andMatrixOutputs_hi_lo_148)
node _decoded_andMatrixOutputs_T_149 = cat(decoded_andMatrixOutputs_hi_149, decoded_andMatrixOutputs_lo_148)
node decoded_andMatrixOutputs_18_2_2 = andr(_decoded_andMatrixOutputs_T_149)
node decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_149 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_146 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_146 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_146 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_146 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_146 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_146 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_89 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_89 = cat(decoded_andMatrixOutputs_andMatrixInput_14_146, decoded_andMatrixOutputs_andMatrixInput_15_89)
node decoded_andMatrixOutputs_lo_lo_hi_146 = cat(decoded_andMatrixOutputs_andMatrixInput_12_146, decoded_andMatrixOutputs_andMatrixInput_13_146)
node decoded_andMatrixOutputs_lo_lo_149 = cat(decoded_andMatrixOutputs_lo_lo_hi_146, decoded_andMatrixOutputs_lo_lo_lo_89)
node decoded_andMatrixOutputs_lo_hi_lo_146 = cat(decoded_andMatrixOutputs_andMatrixInput_10_146, decoded_andMatrixOutputs_andMatrixInput_11_146)
node decoded_andMatrixOutputs_lo_hi_hi_146 = cat(decoded_andMatrixOutputs_andMatrixInput_8_149, decoded_andMatrixOutputs_andMatrixInput_9_146)
node decoded_andMatrixOutputs_lo_hi_149 = cat(decoded_andMatrixOutputs_lo_hi_hi_146, decoded_andMatrixOutputs_lo_hi_lo_146)
node decoded_andMatrixOutputs_lo_149 = cat(decoded_andMatrixOutputs_lo_hi_149, decoded_andMatrixOutputs_lo_lo_149)
node decoded_andMatrixOutputs_hi_lo_lo_146 = cat(decoded_andMatrixOutputs_andMatrixInput_6_149, decoded_andMatrixOutputs_andMatrixInput_7_149)
node decoded_andMatrixOutputs_hi_lo_hi_146 = cat(decoded_andMatrixOutputs_andMatrixInput_4_149, decoded_andMatrixOutputs_andMatrixInput_5_149)
node decoded_andMatrixOutputs_hi_lo_149 = cat(decoded_andMatrixOutputs_hi_lo_hi_146, decoded_andMatrixOutputs_hi_lo_lo_146)
node decoded_andMatrixOutputs_hi_hi_lo_146 = cat(decoded_andMatrixOutputs_andMatrixInput_2_150, decoded_andMatrixOutputs_andMatrixInput_3_149)
node decoded_andMatrixOutputs_hi_hi_hi_149 = cat(decoded_andMatrixOutputs_andMatrixInput_0_150, decoded_andMatrixOutputs_andMatrixInput_1_150)
node decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_andMatrixOutputs_hi_hi_hi_149, decoded_andMatrixOutputs_hi_hi_lo_146)
node decoded_andMatrixOutputs_hi_150 = cat(decoded_andMatrixOutputs_hi_hi_149, decoded_andMatrixOutputs_hi_lo_149)
node _decoded_andMatrixOutputs_T_150 = cat(decoded_andMatrixOutputs_hi_150, decoded_andMatrixOutputs_lo_149)
node decoded_andMatrixOutputs_37_2_2 = andr(_decoded_andMatrixOutputs_T_150)
node decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_150 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_147 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_147 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_147 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_147 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_147 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_147 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_90 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_90 = cat(decoded_andMatrixOutputs_andMatrixInput_14_147, decoded_andMatrixOutputs_andMatrixInput_15_90)
node decoded_andMatrixOutputs_lo_lo_hi_147 = cat(decoded_andMatrixOutputs_andMatrixInput_12_147, decoded_andMatrixOutputs_andMatrixInput_13_147)
node decoded_andMatrixOutputs_lo_lo_150 = cat(decoded_andMatrixOutputs_lo_lo_hi_147, decoded_andMatrixOutputs_lo_lo_lo_90)
node decoded_andMatrixOutputs_lo_hi_lo_147 = cat(decoded_andMatrixOutputs_andMatrixInput_10_147, decoded_andMatrixOutputs_andMatrixInput_11_147)
node decoded_andMatrixOutputs_lo_hi_hi_147 = cat(decoded_andMatrixOutputs_andMatrixInput_8_150, decoded_andMatrixOutputs_andMatrixInput_9_147)
node decoded_andMatrixOutputs_lo_hi_150 = cat(decoded_andMatrixOutputs_lo_hi_hi_147, decoded_andMatrixOutputs_lo_hi_lo_147)
node decoded_andMatrixOutputs_lo_150 = cat(decoded_andMatrixOutputs_lo_hi_150, decoded_andMatrixOutputs_lo_lo_150)
node decoded_andMatrixOutputs_hi_lo_lo_147 = cat(decoded_andMatrixOutputs_andMatrixInput_6_150, decoded_andMatrixOutputs_andMatrixInput_7_150)
node decoded_andMatrixOutputs_hi_lo_hi_147 = cat(decoded_andMatrixOutputs_andMatrixInput_4_150, decoded_andMatrixOutputs_andMatrixInput_5_150)
node decoded_andMatrixOutputs_hi_lo_150 = cat(decoded_andMatrixOutputs_hi_lo_hi_147, decoded_andMatrixOutputs_hi_lo_lo_147)
node decoded_andMatrixOutputs_hi_hi_lo_147 = cat(decoded_andMatrixOutputs_andMatrixInput_2_151, decoded_andMatrixOutputs_andMatrixInput_3_150)
node decoded_andMatrixOutputs_hi_hi_hi_150 = cat(decoded_andMatrixOutputs_andMatrixInput_0_151, decoded_andMatrixOutputs_andMatrixInput_1_151)
node decoded_andMatrixOutputs_hi_hi_150 = cat(decoded_andMatrixOutputs_hi_hi_hi_150, decoded_andMatrixOutputs_hi_hi_lo_147)
node decoded_andMatrixOutputs_hi_151 = cat(decoded_andMatrixOutputs_hi_hi_150, decoded_andMatrixOutputs_hi_lo_150)
node _decoded_andMatrixOutputs_T_151 = cat(decoded_andMatrixOutputs_hi_151, decoded_andMatrixOutputs_lo_150)
node decoded_andMatrixOutputs_43_2_2 = andr(_decoded_andMatrixOutputs_T_151)
node decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(decoded_plaInput_2, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_151 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_148 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_148 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_148 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_148 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_148 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_148 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_91 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_91 = cat(decoded_andMatrixOutputs_andMatrixInput_14_148, decoded_andMatrixOutputs_andMatrixInput_15_91)
node decoded_andMatrixOutputs_lo_lo_hi_148 = cat(decoded_andMatrixOutputs_andMatrixInput_12_148, decoded_andMatrixOutputs_andMatrixInput_13_148)
node decoded_andMatrixOutputs_lo_lo_151 = cat(decoded_andMatrixOutputs_lo_lo_hi_148, decoded_andMatrixOutputs_lo_lo_lo_91)
node decoded_andMatrixOutputs_lo_hi_lo_148 = cat(decoded_andMatrixOutputs_andMatrixInput_10_148, decoded_andMatrixOutputs_andMatrixInput_11_148)
node decoded_andMatrixOutputs_lo_hi_hi_148 = cat(decoded_andMatrixOutputs_andMatrixInput_8_151, decoded_andMatrixOutputs_andMatrixInput_9_148)
node decoded_andMatrixOutputs_lo_hi_151 = cat(decoded_andMatrixOutputs_lo_hi_hi_148, decoded_andMatrixOutputs_lo_hi_lo_148)
node decoded_andMatrixOutputs_lo_151 = cat(decoded_andMatrixOutputs_lo_hi_151, decoded_andMatrixOutputs_lo_lo_151)
node decoded_andMatrixOutputs_hi_lo_lo_148 = cat(decoded_andMatrixOutputs_andMatrixInput_6_151, decoded_andMatrixOutputs_andMatrixInput_7_151)
node decoded_andMatrixOutputs_hi_lo_hi_148 = cat(decoded_andMatrixOutputs_andMatrixInput_4_151, decoded_andMatrixOutputs_andMatrixInput_5_151)
node decoded_andMatrixOutputs_hi_lo_151 = cat(decoded_andMatrixOutputs_hi_lo_hi_148, decoded_andMatrixOutputs_hi_lo_lo_148)
node decoded_andMatrixOutputs_hi_hi_lo_148 = cat(decoded_andMatrixOutputs_andMatrixInput_2_152, decoded_andMatrixOutputs_andMatrixInput_3_151)
node decoded_andMatrixOutputs_hi_hi_hi_151 = cat(decoded_andMatrixOutputs_andMatrixInput_0_152, decoded_andMatrixOutputs_andMatrixInput_1_152)
node decoded_andMatrixOutputs_hi_hi_151 = cat(decoded_andMatrixOutputs_hi_hi_hi_151, decoded_andMatrixOutputs_hi_hi_lo_148)
node decoded_andMatrixOutputs_hi_152 = cat(decoded_andMatrixOutputs_hi_hi_151, decoded_andMatrixOutputs_hi_lo_151)
node _decoded_andMatrixOutputs_T_152 = cat(decoded_andMatrixOutputs_hi_152, decoded_andMatrixOutputs_lo_151)
node decoded_andMatrixOutputs_39_2_2 = andr(_decoded_andMatrixOutputs_T_152)
node decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_152 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_149 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_149 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_149 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_149 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_149 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_149 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_92 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_92 = cat(decoded_andMatrixOutputs_andMatrixInput_14_149, decoded_andMatrixOutputs_andMatrixInput_15_92)
node decoded_andMatrixOutputs_lo_lo_hi_149 = cat(decoded_andMatrixOutputs_andMatrixInput_12_149, decoded_andMatrixOutputs_andMatrixInput_13_149)
node decoded_andMatrixOutputs_lo_lo_152 = cat(decoded_andMatrixOutputs_lo_lo_hi_149, decoded_andMatrixOutputs_lo_lo_lo_92)
node decoded_andMatrixOutputs_lo_hi_lo_149 = cat(decoded_andMatrixOutputs_andMatrixInput_10_149, decoded_andMatrixOutputs_andMatrixInput_11_149)
node decoded_andMatrixOutputs_lo_hi_hi_149 = cat(decoded_andMatrixOutputs_andMatrixInput_8_152, decoded_andMatrixOutputs_andMatrixInput_9_149)
node decoded_andMatrixOutputs_lo_hi_152 = cat(decoded_andMatrixOutputs_lo_hi_hi_149, decoded_andMatrixOutputs_lo_hi_lo_149)
node decoded_andMatrixOutputs_lo_152 = cat(decoded_andMatrixOutputs_lo_hi_152, decoded_andMatrixOutputs_lo_lo_152)
node decoded_andMatrixOutputs_hi_lo_lo_149 = cat(decoded_andMatrixOutputs_andMatrixInput_6_152, decoded_andMatrixOutputs_andMatrixInput_7_152)
node decoded_andMatrixOutputs_hi_lo_hi_149 = cat(decoded_andMatrixOutputs_andMatrixInput_4_152, decoded_andMatrixOutputs_andMatrixInput_5_152)
node decoded_andMatrixOutputs_hi_lo_152 = cat(decoded_andMatrixOutputs_hi_lo_hi_149, decoded_andMatrixOutputs_hi_lo_lo_149)
node decoded_andMatrixOutputs_hi_hi_lo_149 = cat(decoded_andMatrixOutputs_andMatrixInput_2_153, decoded_andMatrixOutputs_andMatrixInput_3_152)
node decoded_andMatrixOutputs_hi_hi_hi_152 = cat(decoded_andMatrixOutputs_andMatrixInput_0_153, decoded_andMatrixOutputs_andMatrixInput_1_153)
node decoded_andMatrixOutputs_hi_hi_152 = cat(decoded_andMatrixOutputs_hi_hi_hi_152, decoded_andMatrixOutputs_hi_hi_lo_149)
node decoded_andMatrixOutputs_hi_153 = cat(decoded_andMatrixOutputs_hi_hi_152, decoded_andMatrixOutputs_hi_lo_152)
node _decoded_andMatrixOutputs_T_153 = cat(decoded_andMatrixOutputs_hi_153, decoded_andMatrixOutputs_lo_152)
node decoded_andMatrixOutputs_51_2_1 = andr(_decoded_andMatrixOutputs_T_153)
node decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_153 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_150 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_150 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_150 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_150 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_150 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_150 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_93 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_93 = cat(decoded_andMatrixOutputs_andMatrixInput_14_150, decoded_andMatrixOutputs_andMatrixInput_15_93)
node decoded_andMatrixOutputs_lo_lo_hi_150 = cat(decoded_andMatrixOutputs_andMatrixInput_12_150, decoded_andMatrixOutputs_andMatrixInput_13_150)
node decoded_andMatrixOutputs_lo_lo_153 = cat(decoded_andMatrixOutputs_lo_lo_hi_150, decoded_andMatrixOutputs_lo_lo_lo_93)
node decoded_andMatrixOutputs_lo_hi_lo_150 = cat(decoded_andMatrixOutputs_andMatrixInput_10_150, decoded_andMatrixOutputs_andMatrixInput_11_150)
node decoded_andMatrixOutputs_lo_hi_hi_150 = cat(decoded_andMatrixOutputs_andMatrixInput_8_153, decoded_andMatrixOutputs_andMatrixInput_9_150)
node decoded_andMatrixOutputs_lo_hi_153 = cat(decoded_andMatrixOutputs_lo_hi_hi_150, decoded_andMatrixOutputs_lo_hi_lo_150)
node decoded_andMatrixOutputs_lo_153 = cat(decoded_andMatrixOutputs_lo_hi_153, decoded_andMatrixOutputs_lo_lo_153)
node decoded_andMatrixOutputs_hi_lo_lo_150 = cat(decoded_andMatrixOutputs_andMatrixInput_6_153, decoded_andMatrixOutputs_andMatrixInput_7_153)
node decoded_andMatrixOutputs_hi_lo_hi_150 = cat(decoded_andMatrixOutputs_andMatrixInput_4_153, decoded_andMatrixOutputs_andMatrixInput_5_153)
node decoded_andMatrixOutputs_hi_lo_153 = cat(decoded_andMatrixOutputs_hi_lo_hi_150, decoded_andMatrixOutputs_hi_lo_lo_150)
node decoded_andMatrixOutputs_hi_hi_lo_150 = cat(decoded_andMatrixOutputs_andMatrixInput_2_154, decoded_andMatrixOutputs_andMatrixInput_3_153)
node decoded_andMatrixOutputs_hi_hi_hi_153 = cat(decoded_andMatrixOutputs_andMatrixInput_0_154, decoded_andMatrixOutputs_andMatrixInput_1_154)
node decoded_andMatrixOutputs_hi_hi_153 = cat(decoded_andMatrixOutputs_hi_hi_hi_153, decoded_andMatrixOutputs_hi_hi_lo_150)
node decoded_andMatrixOutputs_hi_154 = cat(decoded_andMatrixOutputs_hi_hi_153, decoded_andMatrixOutputs_hi_lo_153)
node _decoded_andMatrixOutputs_T_154 = cat(decoded_andMatrixOutputs_hi_154, decoded_andMatrixOutputs_lo_153)
node decoded_andMatrixOutputs_9_2_2 = andr(_decoded_andMatrixOutputs_T_154)
node decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_154 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_151 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_151 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_151 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_151 = bits(decoded_plaInput_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_151 = bits(decoded_plaInput_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_151 = bits(decoded_invInputs_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_94 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_94 = cat(decoded_andMatrixOutputs_andMatrixInput_14_151, decoded_andMatrixOutputs_andMatrixInput_15_94)
node decoded_andMatrixOutputs_lo_lo_hi_151 = cat(decoded_andMatrixOutputs_andMatrixInput_12_151, decoded_andMatrixOutputs_andMatrixInput_13_151)
node decoded_andMatrixOutputs_lo_lo_154 = cat(decoded_andMatrixOutputs_lo_lo_hi_151, decoded_andMatrixOutputs_lo_lo_lo_94)
node decoded_andMatrixOutputs_lo_hi_lo_151 = cat(decoded_andMatrixOutputs_andMatrixInput_10_151, decoded_andMatrixOutputs_andMatrixInput_11_151)
node decoded_andMatrixOutputs_lo_hi_hi_151 = cat(decoded_andMatrixOutputs_andMatrixInput_8_154, decoded_andMatrixOutputs_andMatrixInput_9_151)
node decoded_andMatrixOutputs_lo_hi_154 = cat(decoded_andMatrixOutputs_lo_hi_hi_151, decoded_andMatrixOutputs_lo_hi_lo_151)
node decoded_andMatrixOutputs_lo_154 = cat(decoded_andMatrixOutputs_lo_hi_154, decoded_andMatrixOutputs_lo_lo_154)
node decoded_andMatrixOutputs_hi_lo_lo_151 = cat(decoded_andMatrixOutputs_andMatrixInput_6_154, decoded_andMatrixOutputs_andMatrixInput_7_154)
node decoded_andMatrixOutputs_hi_lo_hi_151 = cat(decoded_andMatrixOutputs_andMatrixInput_4_154, decoded_andMatrixOutputs_andMatrixInput_5_154)
node decoded_andMatrixOutputs_hi_lo_154 = cat(decoded_andMatrixOutputs_hi_lo_hi_151, decoded_andMatrixOutputs_hi_lo_lo_151)
node decoded_andMatrixOutputs_hi_hi_lo_151 = cat(decoded_andMatrixOutputs_andMatrixInput_2_155, decoded_andMatrixOutputs_andMatrixInput_3_154)
node decoded_andMatrixOutputs_hi_hi_hi_154 = cat(decoded_andMatrixOutputs_andMatrixInput_0_155, decoded_andMatrixOutputs_andMatrixInput_1_155)
node decoded_andMatrixOutputs_hi_hi_154 = cat(decoded_andMatrixOutputs_hi_hi_hi_154, decoded_andMatrixOutputs_hi_hi_lo_151)
node decoded_andMatrixOutputs_hi_155 = cat(decoded_andMatrixOutputs_hi_hi_154, decoded_andMatrixOutputs_hi_lo_154)
node _decoded_andMatrixOutputs_T_155 = cat(decoded_andMatrixOutputs_hi_155, decoded_andMatrixOutputs_lo_154)
node decoded_andMatrixOutputs_35_2_2 = andr(_decoded_andMatrixOutputs_T_155)
node decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_155 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_152 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_152 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_152 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_152 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_152 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_152 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_152 = cat(decoded_andMatrixOutputs_andMatrixInput_12_152, decoded_andMatrixOutputs_andMatrixInput_13_152)
node decoded_andMatrixOutputs_lo_lo_155 = cat(decoded_andMatrixOutputs_lo_lo_hi_152, decoded_andMatrixOutputs_andMatrixInput_14_152)
node decoded_andMatrixOutputs_lo_hi_lo_152 = cat(decoded_andMatrixOutputs_andMatrixInput_10_152, decoded_andMatrixOutputs_andMatrixInput_11_152)
node decoded_andMatrixOutputs_lo_hi_hi_152 = cat(decoded_andMatrixOutputs_andMatrixInput_8_155, decoded_andMatrixOutputs_andMatrixInput_9_152)
node decoded_andMatrixOutputs_lo_hi_155 = cat(decoded_andMatrixOutputs_lo_hi_hi_152, decoded_andMatrixOutputs_lo_hi_lo_152)
node decoded_andMatrixOutputs_lo_155 = cat(decoded_andMatrixOutputs_lo_hi_155, decoded_andMatrixOutputs_lo_lo_155)
node decoded_andMatrixOutputs_hi_lo_lo_152 = cat(decoded_andMatrixOutputs_andMatrixInput_6_155, decoded_andMatrixOutputs_andMatrixInput_7_155)
node decoded_andMatrixOutputs_hi_lo_hi_152 = cat(decoded_andMatrixOutputs_andMatrixInput_4_155, decoded_andMatrixOutputs_andMatrixInput_5_155)
node decoded_andMatrixOutputs_hi_lo_155 = cat(decoded_andMatrixOutputs_hi_lo_hi_152, decoded_andMatrixOutputs_hi_lo_lo_152)
node decoded_andMatrixOutputs_hi_hi_lo_152 = cat(decoded_andMatrixOutputs_andMatrixInput_2_156, decoded_andMatrixOutputs_andMatrixInput_3_155)
node decoded_andMatrixOutputs_hi_hi_hi_155 = cat(decoded_andMatrixOutputs_andMatrixInput_0_156, decoded_andMatrixOutputs_andMatrixInput_1_156)
node decoded_andMatrixOutputs_hi_hi_155 = cat(decoded_andMatrixOutputs_hi_hi_hi_155, decoded_andMatrixOutputs_hi_hi_lo_152)
node decoded_andMatrixOutputs_hi_156 = cat(decoded_andMatrixOutputs_hi_hi_155, decoded_andMatrixOutputs_hi_lo_155)
node _decoded_andMatrixOutputs_T_156 = cat(decoded_andMatrixOutputs_hi_156, decoded_andMatrixOutputs_lo_155)
node decoded_andMatrixOutputs_3_2_2 = andr(_decoded_andMatrixOutputs_T_156)
node decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_156 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_153 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_153 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_153 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_153 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_153 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_153 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_153 = cat(decoded_andMatrixOutputs_andMatrixInput_12_153, decoded_andMatrixOutputs_andMatrixInput_13_153)
node decoded_andMatrixOutputs_lo_lo_156 = cat(decoded_andMatrixOutputs_lo_lo_hi_153, decoded_andMatrixOutputs_andMatrixInput_14_153)
node decoded_andMatrixOutputs_lo_hi_lo_153 = cat(decoded_andMatrixOutputs_andMatrixInput_10_153, decoded_andMatrixOutputs_andMatrixInput_11_153)
node decoded_andMatrixOutputs_lo_hi_hi_153 = cat(decoded_andMatrixOutputs_andMatrixInput_8_156, decoded_andMatrixOutputs_andMatrixInput_9_153)
node decoded_andMatrixOutputs_lo_hi_156 = cat(decoded_andMatrixOutputs_lo_hi_hi_153, decoded_andMatrixOutputs_lo_hi_lo_153)
node decoded_andMatrixOutputs_lo_156 = cat(decoded_andMatrixOutputs_lo_hi_156, decoded_andMatrixOutputs_lo_lo_156)
node decoded_andMatrixOutputs_hi_lo_lo_153 = cat(decoded_andMatrixOutputs_andMatrixInput_6_156, decoded_andMatrixOutputs_andMatrixInput_7_156)
node decoded_andMatrixOutputs_hi_lo_hi_153 = cat(decoded_andMatrixOutputs_andMatrixInput_4_156, decoded_andMatrixOutputs_andMatrixInput_5_156)
node decoded_andMatrixOutputs_hi_lo_156 = cat(decoded_andMatrixOutputs_hi_lo_hi_153, decoded_andMatrixOutputs_hi_lo_lo_153)
node decoded_andMatrixOutputs_hi_hi_lo_153 = cat(decoded_andMatrixOutputs_andMatrixInput_2_157, decoded_andMatrixOutputs_andMatrixInput_3_156)
node decoded_andMatrixOutputs_hi_hi_hi_156 = cat(decoded_andMatrixOutputs_andMatrixInput_0_157, decoded_andMatrixOutputs_andMatrixInput_1_157)
node decoded_andMatrixOutputs_hi_hi_156 = cat(decoded_andMatrixOutputs_hi_hi_hi_156, decoded_andMatrixOutputs_hi_hi_lo_153)
node decoded_andMatrixOutputs_hi_157 = cat(decoded_andMatrixOutputs_hi_hi_156, decoded_andMatrixOutputs_hi_lo_156)
node _decoded_andMatrixOutputs_T_157 = cat(decoded_andMatrixOutputs_hi_157, decoded_andMatrixOutputs_lo_156)
node decoded_andMatrixOutputs_59_2 = andr(_decoded_andMatrixOutputs_T_157)
node decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_157 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_154 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_154 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_154 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_154 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_154 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_154 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_154 = cat(decoded_andMatrixOutputs_andMatrixInput_12_154, decoded_andMatrixOutputs_andMatrixInput_13_154)
node decoded_andMatrixOutputs_lo_lo_157 = cat(decoded_andMatrixOutputs_lo_lo_hi_154, decoded_andMatrixOutputs_andMatrixInput_14_154)
node decoded_andMatrixOutputs_lo_hi_lo_154 = cat(decoded_andMatrixOutputs_andMatrixInput_10_154, decoded_andMatrixOutputs_andMatrixInput_11_154)
node decoded_andMatrixOutputs_lo_hi_hi_154 = cat(decoded_andMatrixOutputs_andMatrixInput_8_157, decoded_andMatrixOutputs_andMatrixInput_9_154)
node decoded_andMatrixOutputs_lo_hi_157 = cat(decoded_andMatrixOutputs_lo_hi_hi_154, decoded_andMatrixOutputs_lo_hi_lo_154)
node decoded_andMatrixOutputs_lo_157 = cat(decoded_andMatrixOutputs_lo_hi_157, decoded_andMatrixOutputs_lo_lo_157)
node decoded_andMatrixOutputs_hi_lo_lo_154 = cat(decoded_andMatrixOutputs_andMatrixInput_6_157, decoded_andMatrixOutputs_andMatrixInput_7_157)
node decoded_andMatrixOutputs_hi_lo_hi_154 = cat(decoded_andMatrixOutputs_andMatrixInput_4_157, decoded_andMatrixOutputs_andMatrixInput_5_157)
node decoded_andMatrixOutputs_hi_lo_157 = cat(decoded_andMatrixOutputs_hi_lo_hi_154, decoded_andMatrixOutputs_hi_lo_lo_154)
node decoded_andMatrixOutputs_hi_hi_lo_154 = cat(decoded_andMatrixOutputs_andMatrixInput_2_158, decoded_andMatrixOutputs_andMatrixInput_3_157)
node decoded_andMatrixOutputs_hi_hi_hi_157 = cat(decoded_andMatrixOutputs_andMatrixInput_0_158, decoded_andMatrixOutputs_andMatrixInput_1_158)
node decoded_andMatrixOutputs_hi_hi_157 = cat(decoded_andMatrixOutputs_hi_hi_hi_157, decoded_andMatrixOutputs_hi_hi_lo_154)
node decoded_andMatrixOutputs_hi_158 = cat(decoded_andMatrixOutputs_hi_hi_157, decoded_andMatrixOutputs_hi_lo_157)
node _decoded_andMatrixOutputs_T_158 = cat(decoded_andMatrixOutputs_hi_158, decoded_andMatrixOutputs_lo_157)
node decoded_andMatrixOutputs_62_2 = andr(_decoded_andMatrixOutputs_T_158)
node decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_158 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_155 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_155 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_155 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_155 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_155 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_155 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_155 = cat(decoded_andMatrixOutputs_andMatrixInput_12_155, decoded_andMatrixOutputs_andMatrixInput_13_155)
node decoded_andMatrixOutputs_lo_lo_158 = cat(decoded_andMatrixOutputs_lo_lo_hi_155, decoded_andMatrixOutputs_andMatrixInput_14_155)
node decoded_andMatrixOutputs_lo_hi_lo_155 = cat(decoded_andMatrixOutputs_andMatrixInput_10_155, decoded_andMatrixOutputs_andMatrixInput_11_155)
node decoded_andMatrixOutputs_lo_hi_hi_155 = cat(decoded_andMatrixOutputs_andMatrixInput_8_158, decoded_andMatrixOutputs_andMatrixInput_9_155)
node decoded_andMatrixOutputs_lo_hi_158 = cat(decoded_andMatrixOutputs_lo_hi_hi_155, decoded_andMatrixOutputs_lo_hi_lo_155)
node decoded_andMatrixOutputs_lo_158 = cat(decoded_andMatrixOutputs_lo_hi_158, decoded_andMatrixOutputs_lo_lo_158)
node decoded_andMatrixOutputs_hi_lo_lo_155 = cat(decoded_andMatrixOutputs_andMatrixInput_6_158, decoded_andMatrixOutputs_andMatrixInput_7_158)
node decoded_andMatrixOutputs_hi_lo_hi_155 = cat(decoded_andMatrixOutputs_andMatrixInput_4_158, decoded_andMatrixOutputs_andMatrixInput_5_158)
node decoded_andMatrixOutputs_hi_lo_158 = cat(decoded_andMatrixOutputs_hi_lo_hi_155, decoded_andMatrixOutputs_hi_lo_lo_155)
node decoded_andMatrixOutputs_hi_hi_lo_155 = cat(decoded_andMatrixOutputs_andMatrixInput_2_159, decoded_andMatrixOutputs_andMatrixInput_3_158)
node decoded_andMatrixOutputs_hi_hi_hi_158 = cat(decoded_andMatrixOutputs_andMatrixInput_0_159, decoded_andMatrixOutputs_andMatrixInput_1_159)
node decoded_andMatrixOutputs_hi_hi_158 = cat(decoded_andMatrixOutputs_hi_hi_hi_158, decoded_andMatrixOutputs_hi_hi_lo_155)
node decoded_andMatrixOutputs_hi_159 = cat(decoded_andMatrixOutputs_hi_hi_158, decoded_andMatrixOutputs_hi_lo_158)
node _decoded_andMatrixOutputs_T_159 = cat(decoded_andMatrixOutputs_hi_159, decoded_andMatrixOutputs_lo_158)
node decoded_andMatrixOutputs_72_2 = andr(_decoded_andMatrixOutputs_T_159)
node decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(decoded_invInputs_2, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_159 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_159 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_156 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_156 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_156 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_156 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_156 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_156 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_156 = cat(decoded_andMatrixOutputs_andMatrixInput_12_156, decoded_andMatrixOutputs_andMatrixInput_13_156)
node decoded_andMatrixOutputs_lo_lo_159 = cat(decoded_andMatrixOutputs_lo_lo_hi_156, decoded_andMatrixOutputs_andMatrixInput_14_156)
node decoded_andMatrixOutputs_lo_hi_lo_156 = cat(decoded_andMatrixOutputs_andMatrixInput_10_156, decoded_andMatrixOutputs_andMatrixInput_11_156)
node decoded_andMatrixOutputs_lo_hi_hi_156 = cat(decoded_andMatrixOutputs_andMatrixInput_8_159, decoded_andMatrixOutputs_andMatrixInput_9_156)
node decoded_andMatrixOutputs_lo_hi_159 = cat(decoded_andMatrixOutputs_lo_hi_hi_156, decoded_andMatrixOutputs_lo_hi_lo_156)
node decoded_andMatrixOutputs_lo_159 = cat(decoded_andMatrixOutputs_lo_hi_159, decoded_andMatrixOutputs_lo_lo_159)
node decoded_andMatrixOutputs_hi_lo_lo_156 = cat(decoded_andMatrixOutputs_andMatrixInput_6_159, decoded_andMatrixOutputs_andMatrixInput_7_159)
node decoded_andMatrixOutputs_hi_lo_hi_156 = cat(decoded_andMatrixOutputs_andMatrixInput_4_159, decoded_andMatrixOutputs_andMatrixInput_5_159)
node decoded_andMatrixOutputs_hi_lo_159 = cat(decoded_andMatrixOutputs_hi_lo_hi_156, decoded_andMatrixOutputs_hi_lo_lo_156)
node decoded_andMatrixOutputs_hi_hi_lo_156 = cat(decoded_andMatrixOutputs_andMatrixInput_2_160, decoded_andMatrixOutputs_andMatrixInput_3_159)
node decoded_andMatrixOutputs_hi_hi_hi_159 = cat(decoded_andMatrixOutputs_andMatrixInput_0_160, decoded_andMatrixOutputs_andMatrixInput_1_160)
node decoded_andMatrixOutputs_hi_hi_159 = cat(decoded_andMatrixOutputs_hi_hi_hi_159, decoded_andMatrixOutputs_hi_hi_lo_156)
node decoded_andMatrixOutputs_hi_160 = cat(decoded_andMatrixOutputs_hi_hi_159, decoded_andMatrixOutputs_hi_lo_159)
node _decoded_andMatrixOutputs_T_160 = cat(decoded_andMatrixOutputs_hi_160, decoded_andMatrixOutputs_lo_159)
node decoded_andMatrixOutputs_41_2_2 = andr(_decoded_andMatrixOutputs_T_160)
node decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_160 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_160 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_157 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_157 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_157 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_157 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_157 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_157 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_95 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_95 = cat(decoded_andMatrixOutputs_andMatrixInput_14_157, decoded_andMatrixOutputs_andMatrixInput_15_95)
node decoded_andMatrixOutputs_lo_lo_hi_157 = cat(decoded_andMatrixOutputs_andMatrixInput_12_157, decoded_andMatrixOutputs_andMatrixInput_13_157)
node decoded_andMatrixOutputs_lo_lo_160 = cat(decoded_andMatrixOutputs_lo_lo_hi_157, decoded_andMatrixOutputs_lo_lo_lo_95)
node decoded_andMatrixOutputs_lo_hi_lo_157 = cat(decoded_andMatrixOutputs_andMatrixInput_10_157, decoded_andMatrixOutputs_andMatrixInput_11_157)
node decoded_andMatrixOutputs_lo_hi_hi_157 = cat(decoded_andMatrixOutputs_andMatrixInput_8_160, decoded_andMatrixOutputs_andMatrixInput_9_157)
node decoded_andMatrixOutputs_lo_hi_160 = cat(decoded_andMatrixOutputs_lo_hi_hi_157, decoded_andMatrixOutputs_lo_hi_lo_157)
node decoded_andMatrixOutputs_lo_160 = cat(decoded_andMatrixOutputs_lo_hi_160, decoded_andMatrixOutputs_lo_lo_160)
node decoded_andMatrixOutputs_hi_lo_lo_157 = cat(decoded_andMatrixOutputs_andMatrixInput_6_160, decoded_andMatrixOutputs_andMatrixInput_7_160)
node decoded_andMatrixOutputs_hi_lo_hi_157 = cat(decoded_andMatrixOutputs_andMatrixInput_4_160, decoded_andMatrixOutputs_andMatrixInput_5_160)
node decoded_andMatrixOutputs_hi_lo_160 = cat(decoded_andMatrixOutputs_hi_lo_hi_157, decoded_andMatrixOutputs_hi_lo_lo_157)
node decoded_andMatrixOutputs_hi_hi_lo_157 = cat(decoded_andMatrixOutputs_andMatrixInput_2_161, decoded_andMatrixOutputs_andMatrixInput_3_160)
node decoded_andMatrixOutputs_hi_hi_hi_160 = cat(decoded_andMatrixOutputs_andMatrixInput_0_161, decoded_andMatrixOutputs_andMatrixInput_1_161)
node decoded_andMatrixOutputs_hi_hi_160 = cat(decoded_andMatrixOutputs_hi_hi_hi_160, decoded_andMatrixOutputs_hi_hi_lo_157)
node decoded_andMatrixOutputs_hi_161 = cat(decoded_andMatrixOutputs_hi_hi_160, decoded_andMatrixOutputs_hi_lo_160)
node _decoded_andMatrixOutputs_T_161 = cat(decoded_andMatrixOutputs_hi_161, decoded_andMatrixOutputs_lo_160)
node decoded_andMatrixOutputs_52_2_1 = andr(_decoded_andMatrixOutputs_T_161)
node decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_161 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_161 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_158 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_158 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_158 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_158 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_158 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_158 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_96 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_96 = cat(decoded_andMatrixOutputs_andMatrixInput_14_158, decoded_andMatrixOutputs_andMatrixInput_15_96)
node decoded_andMatrixOutputs_lo_lo_hi_158 = cat(decoded_andMatrixOutputs_andMatrixInput_12_158, decoded_andMatrixOutputs_andMatrixInput_13_158)
node decoded_andMatrixOutputs_lo_lo_161 = cat(decoded_andMatrixOutputs_lo_lo_hi_158, decoded_andMatrixOutputs_lo_lo_lo_96)
node decoded_andMatrixOutputs_lo_hi_lo_158 = cat(decoded_andMatrixOutputs_andMatrixInput_10_158, decoded_andMatrixOutputs_andMatrixInput_11_158)
node decoded_andMatrixOutputs_lo_hi_hi_158 = cat(decoded_andMatrixOutputs_andMatrixInput_8_161, decoded_andMatrixOutputs_andMatrixInput_9_158)
node decoded_andMatrixOutputs_lo_hi_161 = cat(decoded_andMatrixOutputs_lo_hi_hi_158, decoded_andMatrixOutputs_lo_hi_lo_158)
node decoded_andMatrixOutputs_lo_161 = cat(decoded_andMatrixOutputs_lo_hi_161, decoded_andMatrixOutputs_lo_lo_161)
node decoded_andMatrixOutputs_hi_lo_lo_158 = cat(decoded_andMatrixOutputs_andMatrixInput_6_161, decoded_andMatrixOutputs_andMatrixInput_7_161)
node decoded_andMatrixOutputs_hi_lo_hi_158 = cat(decoded_andMatrixOutputs_andMatrixInput_4_161, decoded_andMatrixOutputs_andMatrixInput_5_161)
node decoded_andMatrixOutputs_hi_lo_161 = cat(decoded_andMatrixOutputs_hi_lo_hi_158, decoded_andMatrixOutputs_hi_lo_lo_158)
node decoded_andMatrixOutputs_hi_hi_lo_158 = cat(decoded_andMatrixOutputs_andMatrixInput_2_162, decoded_andMatrixOutputs_andMatrixInput_3_161)
node decoded_andMatrixOutputs_hi_hi_hi_161 = cat(decoded_andMatrixOutputs_andMatrixInput_0_162, decoded_andMatrixOutputs_andMatrixInput_1_162)
node decoded_andMatrixOutputs_hi_hi_161 = cat(decoded_andMatrixOutputs_hi_hi_hi_161, decoded_andMatrixOutputs_hi_hi_lo_158)
node decoded_andMatrixOutputs_hi_162 = cat(decoded_andMatrixOutputs_hi_hi_161, decoded_andMatrixOutputs_hi_lo_161)
node _decoded_andMatrixOutputs_T_162 = cat(decoded_andMatrixOutputs_hi_162, decoded_andMatrixOutputs_lo_161)
node decoded_andMatrixOutputs_31_2_2 = andr(_decoded_andMatrixOutputs_T_162)
node decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_162 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_162 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_159 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_159 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_159 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_159 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_159 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_159 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_97 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_97 = cat(decoded_andMatrixOutputs_andMatrixInput_14_159, decoded_andMatrixOutputs_andMatrixInput_15_97)
node decoded_andMatrixOutputs_lo_lo_hi_159 = cat(decoded_andMatrixOutputs_andMatrixInput_12_159, decoded_andMatrixOutputs_andMatrixInput_13_159)
node decoded_andMatrixOutputs_lo_lo_162 = cat(decoded_andMatrixOutputs_lo_lo_hi_159, decoded_andMatrixOutputs_lo_lo_lo_97)
node decoded_andMatrixOutputs_lo_hi_lo_159 = cat(decoded_andMatrixOutputs_andMatrixInput_10_159, decoded_andMatrixOutputs_andMatrixInput_11_159)
node decoded_andMatrixOutputs_lo_hi_hi_159 = cat(decoded_andMatrixOutputs_andMatrixInput_8_162, decoded_andMatrixOutputs_andMatrixInput_9_159)
node decoded_andMatrixOutputs_lo_hi_162 = cat(decoded_andMatrixOutputs_lo_hi_hi_159, decoded_andMatrixOutputs_lo_hi_lo_159)
node decoded_andMatrixOutputs_lo_162 = cat(decoded_andMatrixOutputs_lo_hi_162, decoded_andMatrixOutputs_lo_lo_162)
node decoded_andMatrixOutputs_hi_lo_lo_159 = cat(decoded_andMatrixOutputs_andMatrixInput_6_162, decoded_andMatrixOutputs_andMatrixInput_7_162)
node decoded_andMatrixOutputs_hi_lo_hi_159 = cat(decoded_andMatrixOutputs_andMatrixInput_4_162, decoded_andMatrixOutputs_andMatrixInput_5_162)
node decoded_andMatrixOutputs_hi_lo_162 = cat(decoded_andMatrixOutputs_hi_lo_hi_159, decoded_andMatrixOutputs_hi_lo_lo_159)
node decoded_andMatrixOutputs_hi_hi_lo_159 = cat(decoded_andMatrixOutputs_andMatrixInput_2_163, decoded_andMatrixOutputs_andMatrixInput_3_162)
node decoded_andMatrixOutputs_hi_hi_hi_162 = cat(decoded_andMatrixOutputs_andMatrixInput_0_163, decoded_andMatrixOutputs_andMatrixInput_1_163)
node decoded_andMatrixOutputs_hi_hi_162 = cat(decoded_andMatrixOutputs_hi_hi_hi_162, decoded_andMatrixOutputs_hi_hi_lo_159)
node decoded_andMatrixOutputs_hi_163 = cat(decoded_andMatrixOutputs_hi_hi_162, decoded_andMatrixOutputs_hi_lo_162)
node _decoded_andMatrixOutputs_T_163 = cat(decoded_andMatrixOutputs_hi_163, decoded_andMatrixOutputs_lo_162)
node decoded_andMatrixOutputs_48_2_1 = andr(_decoded_andMatrixOutputs_T_163)
node decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(decoded_plaInput_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_163 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_163 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_160 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_160 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_160 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_160 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_160 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_160 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_98 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_98 = cat(decoded_andMatrixOutputs_andMatrixInput_14_160, decoded_andMatrixOutputs_andMatrixInput_15_98)
node decoded_andMatrixOutputs_lo_lo_hi_160 = cat(decoded_andMatrixOutputs_andMatrixInput_12_160, decoded_andMatrixOutputs_andMatrixInput_13_160)
node decoded_andMatrixOutputs_lo_lo_163 = cat(decoded_andMatrixOutputs_lo_lo_hi_160, decoded_andMatrixOutputs_lo_lo_lo_98)
node decoded_andMatrixOutputs_lo_hi_lo_160 = cat(decoded_andMatrixOutputs_andMatrixInput_10_160, decoded_andMatrixOutputs_andMatrixInput_11_160)
node decoded_andMatrixOutputs_lo_hi_hi_160 = cat(decoded_andMatrixOutputs_andMatrixInput_8_163, decoded_andMatrixOutputs_andMatrixInput_9_160)
node decoded_andMatrixOutputs_lo_hi_163 = cat(decoded_andMatrixOutputs_lo_hi_hi_160, decoded_andMatrixOutputs_lo_hi_lo_160)
node decoded_andMatrixOutputs_lo_163 = cat(decoded_andMatrixOutputs_lo_hi_163, decoded_andMatrixOutputs_lo_lo_163)
node decoded_andMatrixOutputs_hi_lo_lo_160 = cat(decoded_andMatrixOutputs_andMatrixInput_6_163, decoded_andMatrixOutputs_andMatrixInput_7_163)
node decoded_andMatrixOutputs_hi_lo_hi_160 = cat(decoded_andMatrixOutputs_andMatrixInput_4_163, decoded_andMatrixOutputs_andMatrixInput_5_163)
node decoded_andMatrixOutputs_hi_lo_163 = cat(decoded_andMatrixOutputs_hi_lo_hi_160, decoded_andMatrixOutputs_hi_lo_lo_160)
node decoded_andMatrixOutputs_hi_hi_lo_160 = cat(decoded_andMatrixOutputs_andMatrixInput_2_164, decoded_andMatrixOutputs_andMatrixInput_3_163)
node decoded_andMatrixOutputs_hi_hi_hi_163 = cat(decoded_andMatrixOutputs_andMatrixInput_0_164, decoded_andMatrixOutputs_andMatrixInput_1_164)
node decoded_andMatrixOutputs_hi_hi_163 = cat(decoded_andMatrixOutputs_hi_hi_hi_163, decoded_andMatrixOutputs_hi_hi_lo_160)
node decoded_andMatrixOutputs_hi_164 = cat(decoded_andMatrixOutputs_hi_hi_163, decoded_andMatrixOutputs_hi_lo_163)
node _decoded_andMatrixOutputs_T_164 = cat(decoded_andMatrixOutputs_hi_164, decoded_andMatrixOutputs_lo_163)
node decoded_andMatrixOutputs_69_2 = andr(_decoded_andMatrixOutputs_T_164)
node decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_164 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_164 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_161 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_161 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_161 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_161 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_161 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_161 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_161 = cat(decoded_andMatrixOutputs_andMatrixInput_12_161, decoded_andMatrixOutputs_andMatrixInput_13_161)
node decoded_andMatrixOutputs_lo_lo_164 = cat(decoded_andMatrixOutputs_lo_lo_hi_161, decoded_andMatrixOutputs_andMatrixInput_14_161)
node decoded_andMatrixOutputs_lo_hi_lo_161 = cat(decoded_andMatrixOutputs_andMatrixInput_10_161, decoded_andMatrixOutputs_andMatrixInput_11_161)
node decoded_andMatrixOutputs_lo_hi_hi_161 = cat(decoded_andMatrixOutputs_andMatrixInput_8_164, decoded_andMatrixOutputs_andMatrixInput_9_161)
node decoded_andMatrixOutputs_lo_hi_164 = cat(decoded_andMatrixOutputs_lo_hi_hi_161, decoded_andMatrixOutputs_lo_hi_lo_161)
node decoded_andMatrixOutputs_lo_164 = cat(decoded_andMatrixOutputs_lo_hi_164, decoded_andMatrixOutputs_lo_lo_164)
node decoded_andMatrixOutputs_hi_lo_lo_161 = cat(decoded_andMatrixOutputs_andMatrixInput_6_164, decoded_andMatrixOutputs_andMatrixInput_7_164)
node decoded_andMatrixOutputs_hi_lo_hi_161 = cat(decoded_andMatrixOutputs_andMatrixInput_4_164, decoded_andMatrixOutputs_andMatrixInput_5_164)
node decoded_andMatrixOutputs_hi_lo_164 = cat(decoded_andMatrixOutputs_hi_lo_hi_161, decoded_andMatrixOutputs_hi_lo_lo_161)
node decoded_andMatrixOutputs_hi_hi_lo_161 = cat(decoded_andMatrixOutputs_andMatrixInput_2_165, decoded_andMatrixOutputs_andMatrixInput_3_164)
node decoded_andMatrixOutputs_hi_hi_hi_164 = cat(decoded_andMatrixOutputs_andMatrixInput_0_165, decoded_andMatrixOutputs_andMatrixInput_1_165)
node decoded_andMatrixOutputs_hi_hi_164 = cat(decoded_andMatrixOutputs_hi_hi_hi_164, decoded_andMatrixOutputs_hi_hi_lo_161)
node decoded_andMatrixOutputs_hi_165 = cat(decoded_andMatrixOutputs_hi_hi_164, decoded_andMatrixOutputs_hi_lo_164)
node _decoded_andMatrixOutputs_T_165 = cat(decoded_andMatrixOutputs_hi_165, decoded_andMatrixOutputs_lo_164)
node decoded_andMatrixOutputs_29_2_2 = andr(_decoded_andMatrixOutputs_T_165)
node decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_165 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_165 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_162 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_162 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_162 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_162 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_162 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_162 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_162 = cat(decoded_andMatrixOutputs_andMatrixInput_12_162, decoded_andMatrixOutputs_andMatrixInput_13_162)
node decoded_andMatrixOutputs_lo_lo_165 = cat(decoded_andMatrixOutputs_lo_lo_hi_162, decoded_andMatrixOutputs_andMatrixInput_14_162)
node decoded_andMatrixOutputs_lo_hi_lo_162 = cat(decoded_andMatrixOutputs_andMatrixInput_10_162, decoded_andMatrixOutputs_andMatrixInput_11_162)
node decoded_andMatrixOutputs_lo_hi_hi_162 = cat(decoded_andMatrixOutputs_andMatrixInput_8_165, decoded_andMatrixOutputs_andMatrixInput_9_162)
node decoded_andMatrixOutputs_lo_hi_165 = cat(decoded_andMatrixOutputs_lo_hi_hi_162, decoded_andMatrixOutputs_lo_hi_lo_162)
node decoded_andMatrixOutputs_lo_165 = cat(decoded_andMatrixOutputs_lo_hi_165, decoded_andMatrixOutputs_lo_lo_165)
node decoded_andMatrixOutputs_hi_lo_lo_162 = cat(decoded_andMatrixOutputs_andMatrixInput_6_165, decoded_andMatrixOutputs_andMatrixInput_7_165)
node decoded_andMatrixOutputs_hi_lo_hi_162 = cat(decoded_andMatrixOutputs_andMatrixInput_4_165, decoded_andMatrixOutputs_andMatrixInput_5_165)
node decoded_andMatrixOutputs_hi_lo_165 = cat(decoded_andMatrixOutputs_hi_lo_hi_162, decoded_andMatrixOutputs_hi_lo_lo_162)
node decoded_andMatrixOutputs_hi_hi_lo_162 = cat(decoded_andMatrixOutputs_andMatrixInput_2_166, decoded_andMatrixOutputs_andMatrixInput_3_165)
node decoded_andMatrixOutputs_hi_hi_hi_165 = cat(decoded_andMatrixOutputs_andMatrixInput_0_166, decoded_andMatrixOutputs_andMatrixInput_1_166)
node decoded_andMatrixOutputs_hi_hi_165 = cat(decoded_andMatrixOutputs_hi_hi_hi_165, decoded_andMatrixOutputs_hi_hi_lo_162)
node decoded_andMatrixOutputs_hi_166 = cat(decoded_andMatrixOutputs_hi_hi_165, decoded_andMatrixOutputs_hi_lo_165)
node _decoded_andMatrixOutputs_T_166 = cat(decoded_andMatrixOutputs_hi_166, decoded_andMatrixOutputs_lo_165)
node decoded_andMatrixOutputs_28_2_2 = andr(_decoded_andMatrixOutputs_T_166)
node decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_166 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_166 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_166 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_163 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_163 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_163 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_163 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_163 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_163 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_99 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_99 = cat(decoded_andMatrixOutputs_andMatrixInput_14_163, decoded_andMatrixOutputs_andMatrixInput_15_99)
node decoded_andMatrixOutputs_lo_lo_hi_163 = cat(decoded_andMatrixOutputs_andMatrixInput_12_163, decoded_andMatrixOutputs_andMatrixInput_13_163)
node decoded_andMatrixOutputs_lo_lo_166 = cat(decoded_andMatrixOutputs_lo_lo_hi_163, decoded_andMatrixOutputs_lo_lo_lo_99)
node decoded_andMatrixOutputs_lo_hi_lo_163 = cat(decoded_andMatrixOutputs_andMatrixInput_10_163, decoded_andMatrixOutputs_andMatrixInput_11_163)
node decoded_andMatrixOutputs_lo_hi_hi_163 = cat(decoded_andMatrixOutputs_andMatrixInput_8_166, decoded_andMatrixOutputs_andMatrixInput_9_163)
node decoded_andMatrixOutputs_lo_hi_166 = cat(decoded_andMatrixOutputs_lo_hi_hi_163, decoded_andMatrixOutputs_lo_hi_lo_163)
node decoded_andMatrixOutputs_lo_166 = cat(decoded_andMatrixOutputs_lo_hi_166, decoded_andMatrixOutputs_lo_lo_166)
node decoded_andMatrixOutputs_hi_lo_lo_163 = cat(decoded_andMatrixOutputs_andMatrixInput_6_166, decoded_andMatrixOutputs_andMatrixInput_7_166)
node decoded_andMatrixOutputs_hi_lo_hi_163 = cat(decoded_andMatrixOutputs_andMatrixInput_4_166, decoded_andMatrixOutputs_andMatrixInput_5_166)
node decoded_andMatrixOutputs_hi_lo_166 = cat(decoded_andMatrixOutputs_hi_lo_hi_163, decoded_andMatrixOutputs_hi_lo_lo_163)
node decoded_andMatrixOutputs_hi_hi_lo_163 = cat(decoded_andMatrixOutputs_andMatrixInput_2_167, decoded_andMatrixOutputs_andMatrixInput_3_166)
node decoded_andMatrixOutputs_hi_hi_hi_166 = cat(decoded_andMatrixOutputs_andMatrixInput_0_167, decoded_andMatrixOutputs_andMatrixInput_1_167)
node decoded_andMatrixOutputs_hi_hi_166 = cat(decoded_andMatrixOutputs_hi_hi_hi_166, decoded_andMatrixOutputs_hi_hi_lo_163)
node decoded_andMatrixOutputs_hi_167 = cat(decoded_andMatrixOutputs_hi_hi_166, decoded_andMatrixOutputs_hi_lo_166)
node _decoded_andMatrixOutputs_T_167 = cat(decoded_andMatrixOutputs_hi_167, decoded_andMatrixOutputs_lo_166)
node decoded_andMatrixOutputs_74_2 = andr(_decoded_andMatrixOutputs_T_167)
node decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_167 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_167 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_167 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_164 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_164 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_164 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_164 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_164 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_164 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_100 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_100 = cat(decoded_andMatrixOutputs_andMatrixInput_14_164, decoded_andMatrixOutputs_andMatrixInput_15_100)
node decoded_andMatrixOutputs_lo_lo_hi_164 = cat(decoded_andMatrixOutputs_andMatrixInput_12_164, decoded_andMatrixOutputs_andMatrixInput_13_164)
node decoded_andMatrixOutputs_lo_lo_167 = cat(decoded_andMatrixOutputs_lo_lo_hi_164, decoded_andMatrixOutputs_lo_lo_lo_100)
node decoded_andMatrixOutputs_lo_hi_lo_164 = cat(decoded_andMatrixOutputs_andMatrixInput_10_164, decoded_andMatrixOutputs_andMatrixInput_11_164)
node decoded_andMatrixOutputs_lo_hi_hi_164 = cat(decoded_andMatrixOutputs_andMatrixInput_8_167, decoded_andMatrixOutputs_andMatrixInput_9_164)
node decoded_andMatrixOutputs_lo_hi_167 = cat(decoded_andMatrixOutputs_lo_hi_hi_164, decoded_andMatrixOutputs_lo_hi_lo_164)
node decoded_andMatrixOutputs_lo_167 = cat(decoded_andMatrixOutputs_lo_hi_167, decoded_andMatrixOutputs_lo_lo_167)
node decoded_andMatrixOutputs_hi_lo_lo_164 = cat(decoded_andMatrixOutputs_andMatrixInput_6_167, decoded_andMatrixOutputs_andMatrixInput_7_167)
node decoded_andMatrixOutputs_hi_lo_hi_164 = cat(decoded_andMatrixOutputs_andMatrixInput_4_167, decoded_andMatrixOutputs_andMatrixInput_5_167)
node decoded_andMatrixOutputs_hi_lo_167 = cat(decoded_andMatrixOutputs_hi_lo_hi_164, decoded_andMatrixOutputs_hi_lo_lo_164)
node decoded_andMatrixOutputs_hi_hi_lo_164 = cat(decoded_andMatrixOutputs_andMatrixInput_2_168, decoded_andMatrixOutputs_andMatrixInput_3_167)
node decoded_andMatrixOutputs_hi_hi_hi_167 = cat(decoded_andMatrixOutputs_andMatrixInput_0_168, decoded_andMatrixOutputs_andMatrixInput_1_168)
node decoded_andMatrixOutputs_hi_hi_167 = cat(decoded_andMatrixOutputs_hi_hi_hi_167, decoded_andMatrixOutputs_hi_hi_lo_164)
node decoded_andMatrixOutputs_hi_168 = cat(decoded_andMatrixOutputs_hi_hi_167, decoded_andMatrixOutputs_hi_lo_167)
node _decoded_andMatrixOutputs_T_168 = cat(decoded_andMatrixOutputs_hi_168, decoded_andMatrixOutputs_lo_167)
node decoded_andMatrixOutputs_57_2 = andr(_decoded_andMatrixOutputs_T_168)
node decoded_andMatrixOutputs_andMatrixInput_0_169 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_169 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_169 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_168 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_168 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_168 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_168 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_165 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_165 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_165 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_165 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_165 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_165 = bits(decoded_plaInput_2, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_101 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_101 = cat(decoded_andMatrixOutputs_andMatrixInput_14_165, decoded_andMatrixOutputs_andMatrixInput_15_101)
node decoded_andMatrixOutputs_lo_lo_hi_165 = cat(decoded_andMatrixOutputs_andMatrixInput_12_165, decoded_andMatrixOutputs_andMatrixInput_13_165)
node decoded_andMatrixOutputs_lo_lo_168 = cat(decoded_andMatrixOutputs_lo_lo_hi_165, decoded_andMatrixOutputs_lo_lo_lo_101)
node decoded_andMatrixOutputs_lo_hi_lo_165 = cat(decoded_andMatrixOutputs_andMatrixInput_10_165, decoded_andMatrixOutputs_andMatrixInput_11_165)
node decoded_andMatrixOutputs_lo_hi_hi_165 = cat(decoded_andMatrixOutputs_andMatrixInput_8_168, decoded_andMatrixOutputs_andMatrixInput_9_165)
node decoded_andMatrixOutputs_lo_hi_168 = cat(decoded_andMatrixOutputs_lo_hi_hi_165, decoded_andMatrixOutputs_lo_hi_lo_165)
node decoded_andMatrixOutputs_lo_168 = cat(decoded_andMatrixOutputs_lo_hi_168, decoded_andMatrixOutputs_lo_lo_168)
node decoded_andMatrixOutputs_hi_lo_lo_165 = cat(decoded_andMatrixOutputs_andMatrixInput_6_168, decoded_andMatrixOutputs_andMatrixInput_7_168)
node decoded_andMatrixOutputs_hi_lo_hi_165 = cat(decoded_andMatrixOutputs_andMatrixInput_4_168, decoded_andMatrixOutputs_andMatrixInput_5_168)
node decoded_andMatrixOutputs_hi_lo_168 = cat(decoded_andMatrixOutputs_hi_lo_hi_165, decoded_andMatrixOutputs_hi_lo_lo_165)
node decoded_andMatrixOutputs_hi_hi_lo_165 = cat(decoded_andMatrixOutputs_andMatrixInput_2_169, decoded_andMatrixOutputs_andMatrixInput_3_168)
node decoded_andMatrixOutputs_hi_hi_hi_168 = cat(decoded_andMatrixOutputs_andMatrixInput_0_169, decoded_andMatrixOutputs_andMatrixInput_1_169)
node decoded_andMatrixOutputs_hi_hi_168 = cat(decoded_andMatrixOutputs_hi_hi_hi_168, decoded_andMatrixOutputs_hi_hi_lo_165)
node decoded_andMatrixOutputs_hi_169 = cat(decoded_andMatrixOutputs_hi_hi_168, decoded_andMatrixOutputs_hi_lo_168)
node _decoded_andMatrixOutputs_T_169 = cat(decoded_andMatrixOutputs_hi_169, decoded_andMatrixOutputs_lo_168)
node decoded_andMatrixOutputs_40_2_2 = andr(_decoded_andMatrixOutputs_T_169)
node decoded_andMatrixOutputs_andMatrixInput_0_170 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_170 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_170 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_169 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_169 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_169 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_169 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_169 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_169 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_166 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_166 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_166 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_166 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_166 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_14_166 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_166 = cat(decoded_andMatrixOutputs_andMatrixInput_12_166, decoded_andMatrixOutputs_andMatrixInput_13_166)
node decoded_andMatrixOutputs_lo_lo_169 = cat(decoded_andMatrixOutputs_lo_lo_hi_166, decoded_andMatrixOutputs_andMatrixInput_14_166)
node decoded_andMatrixOutputs_lo_hi_lo_166 = cat(decoded_andMatrixOutputs_andMatrixInput_10_166, decoded_andMatrixOutputs_andMatrixInput_11_166)
node decoded_andMatrixOutputs_lo_hi_hi_166 = cat(decoded_andMatrixOutputs_andMatrixInput_8_169, decoded_andMatrixOutputs_andMatrixInput_9_166)
node decoded_andMatrixOutputs_lo_hi_169 = cat(decoded_andMatrixOutputs_lo_hi_hi_166, decoded_andMatrixOutputs_lo_hi_lo_166)
node decoded_andMatrixOutputs_lo_169 = cat(decoded_andMatrixOutputs_lo_hi_169, decoded_andMatrixOutputs_lo_lo_169)
node decoded_andMatrixOutputs_hi_lo_lo_166 = cat(decoded_andMatrixOutputs_andMatrixInput_6_169, decoded_andMatrixOutputs_andMatrixInput_7_169)
node decoded_andMatrixOutputs_hi_lo_hi_166 = cat(decoded_andMatrixOutputs_andMatrixInput_4_169, decoded_andMatrixOutputs_andMatrixInput_5_169)
node decoded_andMatrixOutputs_hi_lo_169 = cat(decoded_andMatrixOutputs_hi_lo_hi_166, decoded_andMatrixOutputs_hi_lo_lo_166)
node decoded_andMatrixOutputs_hi_hi_lo_166 = cat(decoded_andMatrixOutputs_andMatrixInput_2_170, decoded_andMatrixOutputs_andMatrixInput_3_169)
node decoded_andMatrixOutputs_hi_hi_hi_169 = cat(decoded_andMatrixOutputs_andMatrixInput_0_170, decoded_andMatrixOutputs_andMatrixInput_1_170)
node decoded_andMatrixOutputs_hi_hi_169 = cat(decoded_andMatrixOutputs_hi_hi_hi_169, decoded_andMatrixOutputs_hi_hi_lo_166)
node decoded_andMatrixOutputs_hi_170 = cat(decoded_andMatrixOutputs_hi_hi_169, decoded_andMatrixOutputs_hi_lo_169)
node _decoded_andMatrixOutputs_T_170 = cat(decoded_andMatrixOutputs_hi_170, decoded_andMatrixOutputs_lo_169)
node decoded_andMatrixOutputs_64_2 = andr(_decoded_andMatrixOutputs_T_170)
node decoded_andMatrixOutputs_andMatrixInput_0_171 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_171 = bits(decoded_invInputs_2, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_171 = bits(decoded_plaInput_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_170 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_170 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_170 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_170 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_170 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_170 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_167 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_167 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_167 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_167 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_167 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_14_167 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_167 = cat(decoded_andMatrixOutputs_andMatrixInput_12_167, decoded_andMatrixOutputs_andMatrixInput_13_167)
node decoded_andMatrixOutputs_lo_lo_170 = cat(decoded_andMatrixOutputs_lo_lo_hi_167, decoded_andMatrixOutputs_andMatrixInput_14_167)
node decoded_andMatrixOutputs_lo_hi_lo_167 = cat(decoded_andMatrixOutputs_andMatrixInput_10_167, decoded_andMatrixOutputs_andMatrixInput_11_167)
node decoded_andMatrixOutputs_lo_hi_hi_167 = cat(decoded_andMatrixOutputs_andMatrixInput_8_170, decoded_andMatrixOutputs_andMatrixInput_9_167)
node decoded_andMatrixOutputs_lo_hi_170 = cat(decoded_andMatrixOutputs_lo_hi_hi_167, decoded_andMatrixOutputs_lo_hi_lo_167)
node decoded_andMatrixOutputs_lo_170 = cat(decoded_andMatrixOutputs_lo_hi_170, decoded_andMatrixOutputs_lo_lo_170)
node decoded_andMatrixOutputs_hi_lo_lo_167 = cat(decoded_andMatrixOutputs_andMatrixInput_6_170, decoded_andMatrixOutputs_andMatrixInput_7_170)
node decoded_andMatrixOutputs_hi_lo_hi_167 = cat(decoded_andMatrixOutputs_andMatrixInput_4_170, decoded_andMatrixOutputs_andMatrixInput_5_170)
node decoded_andMatrixOutputs_hi_lo_170 = cat(decoded_andMatrixOutputs_hi_lo_hi_167, decoded_andMatrixOutputs_hi_lo_lo_167)
node decoded_andMatrixOutputs_hi_hi_lo_167 = cat(decoded_andMatrixOutputs_andMatrixInput_2_171, decoded_andMatrixOutputs_andMatrixInput_3_170)
node decoded_andMatrixOutputs_hi_hi_hi_170 = cat(decoded_andMatrixOutputs_andMatrixInput_0_171, decoded_andMatrixOutputs_andMatrixInput_1_171)
node decoded_andMatrixOutputs_hi_hi_170 = cat(decoded_andMatrixOutputs_hi_hi_hi_170, decoded_andMatrixOutputs_hi_hi_lo_167)
node decoded_andMatrixOutputs_hi_171 = cat(decoded_andMatrixOutputs_hi_hi_170, decoded_andMatrixOutputs_hi_lo_170)
node _decoded_andMatrixOutputs_T_171 = cat(decoded_andMatrixOutputs_hi_171, decoded_andMatrixOutputs_lo_170)
node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_171)
node decoded_andMatrixOutputs_andMatrixInput_0_172 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_172 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_172 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_171 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_171 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_171 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_171 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_171 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_171 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_168 = bits(decoded_invInputs_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_168 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_168 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_168 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_168 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_168 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_15_102 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_102 = cat(decoded_andMatrixOutputs_andMatrixInput_14_168, decoded_andMatrixOutputs_andMatrixInput_15_102)
node decoded_andMatrixOutputs_lo_lo_hi_168 = cat(decoded_andMatrixOutputs_andMatrixInput_12_168, decoded_andMatrixOutputs_andMatrixInput_13_168)
node decoded_andMatrixOutputs_lo_lo_171 = cat(decoded_andMatrixOutputs_lo_lo_hi_168, decoded_andMatrixOutputs_lo_lo_lo_102)
node decoded_andMatrixOutputs_lo_hi_lo_168 = cat(decoded_andMatrixOutputs_andMatrixInput_10_168, decoded_andMatrixOutputs_andMatrixInput_11_168)
node decoded_andMatrixOutputs_lo_hi_hi_168 = cat(decoded_andMatrixOutputs_andMatrixInput_8_171, decoded_andMatrixOutputs_andMatrixInput_9_168)
node decoded_andMatrixOutputs_lo_hi_171 = cat(decoded_andMatrixOutputs_lo_hi_hi_168, decoded_andMatrixOutputs_lo_hi_lo_168)
node decoded_andMatrixOutputs_lo_171 = cat(decoded_andMatrixOutputs_lo_hi_171, decoded_andMatrixOutputs_lo_lo_171)
node decoded_andMatrixOutputs_hi_lo_lo_168 = cat(decoded_andMatrixOutputs_andMatrixInput_6_171, decoded_andMatrixOutputs_andMatrixInput_7_171)
node decoded_andMatrixOutputs_hi_lo_hi_168 = cat(decoded_andMatrixOutputs_andMatrixInput_4_171, decoded_andMatrixOutputs_andMatrixInput_5_171)
node decoded_andMatrixOutputs_hi_lo_171 = cat(decoded_andMatrixOutputs_hi_lo_hi_168, decoded_andMatrixOutputs_hi_lo_lo_168)
node decoded_andMatrixOutputs_hi_hi_lo_168 = cat(decoded_andMatrixOutputs_andMatrixInput_2_172, decoded_andMatrixOutputs_andMatrixInput_3_171)
node decoded_andMatrixOutputs_hi_hi_hi_171 = cat(decoded_andMatrixOutputs_andMatrixInput_0_172, decoded_andMatrixOutputs_andMatrixInput_1_172)
node decoded_andMatrixOutputs_hi_hi_171 = cat(decoded_andMatrixOutputs_hi_hi_hi_171, decoded_andMatrixOutputs_hi_hi_lo_168)
node decoded_andMatrixOutputs_hi_172 = cat(decoded_andMatrixOutputs_hi_hi_171, decoded_andMatrixOutputs_hi_lo_171)
node _decoded_andMatrixOutputs_T_172 = cat(decoded_andMatrixOutputs_hi_172, decoded_andMatrixOutputs_lo_171)
node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_172)
node decoded_andMatrixOutputs_andMatrixInput_0_173 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_173 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_173 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_172 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_172 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_172 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_172 = bits(decoded_invInputs_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_172 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_172 = bits(decoded_invInputs_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_169 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_169 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_169 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_169 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_169 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_169 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_15_103 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_103 = cat(decoded_andMatrixOutputs_andMatrixInput_14_169, decoded_andMatrixOutputs_andMatrixInput_15_103)
node decoded_andMatrixOutputs_lo_lo_hi_169 = cat(decoded_andMatrixOutputs_andMatrixInput_12_169, decoded_andMatrixOutputs_andMatrixInput_13_169)
node decoded_andMatrixOutputs_lo_lo_172 = cat(decoded_andMatrixOutputs_lo_lo_hi_169, decoded_andMatrixOutputs_lo_lo_lo_103)
node decoded_andMatrixOutputs_lo_hi_lo_169 = cat(decoded_andMatrixOutputs_andMatrixInput_10_169, decoded_andMatrixOutputs_andMatrixInput_11_169)
node decoded_andMatrixOutputs_lo_hi_hi_169 = cat(decoded_andMatrixOutputs_andMatrixInput_8_172, decoded_andMatrixOutputs_andMatrixInput_9_169)
node decoded_andMatrixOutputs_lo_hi_172 = cat(decoded_andMatrixOutputs_lo_hi_hi_169, decoded_andMatrixOutputs_lo_hi_lo_169)
node decoded_andMatrixOutputs_lo_172 = cat(decoded_andMatrixOutputs_lo_hi_172, decoded_andMatrixOutputs_lo_lo_172)
node decoded_andMatrixOutputs_hi_lo_lo_169 = cat(decoded_andMatrixOutputs_andMatrixInput_6_172, decoded_andMatrixOutputs_andMatrixInput_7_172)
node decoded_andMatrixOutputs_hi_lo_hi_169 = cat(decoded_andMatrixOutputs_andMatrixInput_4_172, decoded_andMatrixOutputs_andMatrixInput_5_172)
node decoded_andMatrixOutputs_hi_lo_172 = cat(decoded_andMatrixOutputs_hi_lo_hi_169, decoded_andMatrixOutputs_hi_lo_lo_169)
node decoded_andMatrixOutputs_hi_hi_lo_169 = cat(decoded_andMatrixOutputs_andMatrixInput_2_173, decoded_andMatrixOutputs_andMatrixInput_3_172)
node decoded_andMatrixOutputs_hi_hi_hi_172 = cat(decoded_andMatrixOutputs_andMatrixInput_0_173, decoded_andMatrixOutputs_andMatrixInput_1_173)
node decoded_andMatrixOutputs_hi_hi_172 = cat(decoded_andMatrixOutputs_hi_hi_hi_172, decoded_andMatrixOutputs_hi_hi_lo_169)
node decoded_andMatrixOutputs_hi_173 = cat(decoded_andMatrixOutputs_hi_hi_172, decoded_andMatrixOutputs_hi_lo_172)
node _decoded_andMatrixOutputs_T_173 = cat(decoded_andMatrixOutputs_hi_173, decoded_andMatrixOutputs_lo_172)
node decoded_andMatrixOutputs_16_2_2 = andr(_decoded_andMatrixOutputs_T_173)
node decoded_andMatrixOutputs_andMatrixInput_0_174 = bits(decoded_invInputs_2, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_174 = bits(decoded_invInputs_2, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_174 = bits(decoded_invInputs_2, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_173 = bits(decoded_invInputs_2, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_173 = bits(decoded_invInputs_2, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_173 = bits(decoded_invInputs_2, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_173 = bits(decoded_plaInput_2, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_173 = bits(decoded_invInputs_2, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_173 = bits(decoded_plaInput_2, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_170 = bits(decoded_plaInput_2, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_170 = bits(decoded_invInputs_2, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_170 = bits(decoded_invInputs_2, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_170 = bits(decoded_invInputs_2, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_170 = bits(decoded_plaInput_2, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_170 = bits(decoded_plaInput_2, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_15_104 = bits(decoded_plaInput_2, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_104 = cat(decoded_andMatrixOutputs_andMatrixInput_14_170, decoded_andMatrixOutputs_andMatrixInput_15_104)
node decoded_andMatrixOutputs_lo_lo_hi_170 = cat(decoded_andMatrixOutputs_andMatrixInput_12_170, decoded_andMatrixOutputs_andMatrixInput_13_170)
node decoded_andMatrixOutputs_lo_lo_173 = cat(decoded_andMatrixOutputs_lo_lo_hi_170, decoded_andMatrixOutputs_lo_lo_lo_104)
node decoded_andMatrixOutputs_lo_hi_lo_170 = cat(decoded_andMatrixOutputs_andMatrixInput_10_170, decoded_andMatrixOutputs_andMatrixInput_11_170)
node decoded_andMatrixOutputs_lo_hi_hi_170 = cat(decoded_andMatrixOutputs_andMatrixInput_8_173, decoded_andMatrixOutputs_andMatrixInput_9_170)
node decoded_andMatrixOutputs_lo_hi_173 = cat(decoded_andMatrixOutputs_lo_hi_hi_170, decoded_andMatrixOutputs_lo_hi_lo_170)
node decoded_andMatrixOutputs_lo_173 = cat(decoded_andMatrixOutputs_lo_hi_173, decoded_andMatrixOutputs_lo_lo_173)
node decoded_andMatrixOutputs_hi_lo_lo_170 = cat(decoded_andMatrixOutputs_andMatrixInput_6_173, decoded_andMatrixOutputs_andMatrixInput_7_173)
node decoded_andMatrixOutputs_hi_lo_hi_170 = cat(decoded_andMatrixOutputs_andMatrixInput_4_173, decoded_andMatrixOutputs_andMatrixInput_5_173)
node decoded_andMatrixOutputs_hi_lo_173 = cat(decoded_andMatrixOutputs_hi_lo_hi_170, decoded_andMatrixOutputs_hi_lo_lo_170)
node decoded_andMatrixOutputs_hi_hi_lo_170 = cat(decoded_andMatrixOutputs_andMatrixInput_2_174, decoded_andMatrixOutputs_andMatrixInput_3_173)
node decoded_andMatrixOutputs_hi_hi_hi_173 = cat(decoded_andMatrixOutputs_andMatrixInput_0_174, decoded_andMatrixOutputs_andMatrixInput_1_174)
node decoded_andMatrixOutputs_hi_hi_173 = cat(decoded_andMatrixOutputs_hi_hi_hi_173, decoded_andMatrixOutputs_hi_hi_lo_170)
node decoded_andMatrixOutputs_hi_174 = cat(decoded_andMatrixOutputs_hi_hi_173, decoded_andMatrixOutputs_hi_lo_173)
node _decoded_andMatrixOutputs_T_174 = cat(decoded_andMatrixOutputs_hi_174, decoded_andMatrixOutputs_lo_173)
node decoded_andMatrixOutputs_68_2 = andr(_decoded_andMatrixOutputs_T_174)
node decoded_orMatrixOutputs_lo_lo_lo_8 = cat(decoded_andMatrixOutputs_64_2, decoded_andMatrixOutputs_0_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_29_2_2, decoded_andMatrixOutputs_28_2_2)
node decoded_orMatrixOutputs_lo_lo_32 = cat(decoded_orMatrixOutputs_lo_lo_hi_21, decoded_orMatrixOutputs_lo_lo_lo_8)
node decoded_orMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_47_2_1, decoded_andMatrixOutputs_39_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_26 = cat(decoded_andMatrixOutputs_34_2_2, decoded_andMatrixOutputs_26_2_2)
node decoded_orMatrixOutputs_lo_hi_36 = cat(decoded_orMatrixOutputs_lo_hi_hi_26, decoded_orMatrixOutputs_lo_hi_lo_15)
node decoded_orMatrixOutputs_lo_46 = cat(decoded_orMatrixOutputs_lo_hi_36, decoded_orMatrixOutputs_lo_lo_32)
node decoded_orMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_15_2_2, decoded_andMatrixOutputs_25_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_49_2_1, decoded_andMatrixOutputs_4_2_2)
node decoded_orMatrixOutputs_hi_lo_32 = cat(decoded_orMatrixOutputs_hi_lo_hi_21, decoded_orMatrixOutputs_hi_lo_lo_8)
node decoded_orMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_24_2_2, decoded_andMatrixOutputs_23_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_28 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_11_2_2)
node decoded_orMatrixOutputs_hi_hi_46 = cat(decoded_orMatrixOutputs_hi_hi_hi_28, decoded_orMatrixOutputs_hi_hi_lo_15)
node decoded_orMatrixOutputs_hi_50 = cat(decoded_orMatrixOutputs_hi_hi_46, decoded_orMatrixOutputs_hi_lo_32)
node _decoded_orMatrixOutputs_T_103 = cat(decoded_orMatrixOutputs_hi_50, decoded_orMatrixOutputs_lo_46)
node _decoded_orMatrixOutputs_T_104 = orr(_decoded_orMatrixOutputs_T_103)
node decoded_orMatrixOutputs_lo_lo_lo_9 = cat(decoded_andMatrixOutputs_64_2, decoded_andMatrixOutputs_0_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_29_2_2, decoded_andMatrixOutputs_28_2_2)
node decoded_orMatrixOutputs_lo_lo_33 = cat(decoded_orMatrixOutputs_lo_lo_hi_22, decoded_orMatrixOutputs_lo_lo_lo_9)
node decoded_orMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_47_2_1, decoded_andMatrixOutputs_39_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_27 = cat(decoded_andMatrixOutputs_34_2_2, decoded_andMatrixOutputs_26_2_2)
node decoded_orMatrixOutputs_lo_hi_37 = cat(decoded_orMatrixOutputs_lo_hi_hi_27, decoded_orMatrixOutputs_lo_hi_lo_16)
node decoded_orMatrixOutputs_lo_47 = cat(decoded_orMatrixOutputs_lo_hi_37, decoded_orMatrixOutputs_lo_lo_33)
node decoded_orMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_15_2_2, decoded_andMatrixOutputs_25_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_49_2_1, decoded_andMatrixOutputs_4_2_2)
node decoded_orMatrixOutputs_hi_lo_33 = cat(decoded_orMatrixOutputs_hi_lo_hi_22, decoded_orMatrixOutputs_hi_lo_lo_9)
node decoded_orMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_24_2_2, decoded_andMatrixOutputs_23_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_29 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_11_2_2)
node decoded_orMatrixOutputs_hi_hi_47 = cat(decoded_orMatrixOutputs_hi_hi_hi_29, decoded_orMatrixOutputs_hi_hi_lo_16)
node decoded_orMatrixOutputs_hi_51 = cat(decoded_orMatrixOutputs_hi_hi_47, decoded_orMatrixOutputs_hi_lo_33)
node _decoded_orMatrixOutputs_T_105 = cat(decoded_orMatrixOutputs_hi_51, decoded_orMatrixOutputs_lo_47)
node _decoded_orMatrixOutputs_T_106 = orr(_decoded_orMatrixOutputs_T_105)
node decoded_orMatrixOutputs_lo_lo_lo_10 = cat(decoded_andMatrixOutputs_64_2, decoded_andMatrixOutputs_0_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_29_2_2, decoded_andMatrixOutputs_28_2_2)
node decoded_orMatrixOutputs_lo_lo_34 = cat(decoded_orMatrixOutputs_lo_lo_hi_23, decoded_orMatrixOutputs_lo_lo_lo_10)
node decoded_orMatrixOutputs_lo_hi_lo_17 = cat(decoded_andMatrixOutputs_47_2_1, decoded_andMatrixOutputs_39_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_28 = cat(decoded_andMatrixOutputs_34_2_2, decoded_andMatrixOutputs_26_2_2)
node decoded_orMatrixOutputs_lo_hi_38 = cat(decoded_orMatrixOutputs_lo_hi_hi_28, decoded_orMatrixOutputs_lo_hi_lo_17)
node decoded_orMatrixOutputs_lo_48 = cat(decoded_orMatrixOutputs_lo_hi_38, decoded_orMatrixOutputs_lo_lo_34)
node decoded_orMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_15_2_2, decoded_andMatrixOutputs_25_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_49_2_1, decoded_andMatrixOutputs_4_2_2)
node decoded_orMatrixOutputs_hi_lo_34 = cat(decoded_orMatrixOutputs_hi_lo_hi_23, decoded_orMatrixOutputs_hi_lo_lo_10)
node decoded_orMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_24_2_2, decoded_andMatrixOutputs_23_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_30 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_4, decoded_andMatrixOutputs_11_2_2)
node decoded_orMatrixOutputs_hi_hi_48 = cat(decoded_orMatrixOutputs_hi_hi_hi_30, decoded_orMatrixOutputs_hi_hi_lo_17)
node decoded_orMatrixOutputs_hi_52 = cat(decoded_orMatrixOutputs_hi_hi_48, decoded_orMatrixOutputs_hi_lo_34)
node _decoded_orMatrixOutputs_T_107 = cat(decoded_orMatrixOutputs_hi_52, decoded_orMatrixOutputs_lo_48)
node _decoded_orMatrixOutputs_T_108 = orr(_decoded_orMatrixOutputs_T_107)
node decoded_orMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_39_2_2, decoded_andMatrixOutputs_72_2)
node decoded_orMatrixOutputs_lo_lo_35 = cat(decoded_orMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_41_2_2)
node decoded_orMatrixOutputs_lo_hi_lo_18 = cat(decoded_andMatrixOutputs_26_2_2, decoded_andMatrixOutputs_47_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_29 = cat(decoded_andMatrixOutputs_25_2_2, decoded_andMatrixOutputs_34_2_2)
node decoded_orMatrixOutputs_lo_hi_39 = cat(decoded_orMatrixOutputs_lo_hi_hi_29, decoded_orMatrixOutputs_lo_hi_lo_18)
node decoded_orMatrixOutputs_lo_49 = cat(decoded_orMatrixOutputs_lo_hi_39, decoded_orMatrixOutputs_lo_lo_35)
node decoded_orMatrixOutputs_hi_lo_lo_11 = cat(decoded_andMatrixOutputs_4_2_2, decoded_andMatrixOutputs_15_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_23_2_2, decoded_andMatrixOutputs_49_2_1)
node decoded_orMatrixOutputs_hi_lo_35 = cat(decoded_orMatrixOutputs_hi_lo_hi_24, decoded_orMatrixOutputs_hi_lo_lo_11)
node decoded_orMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_11_2_2, decoded_andMatrixOutputs_24_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_49 = cat(decoded_orMatrixOutputs_hi_hi_hi_31, decoded_orMatrixOutputs_hi_hi_lo_18)
node decoded_orMatrixOutputs_hi_53 = cat(decoded_orMatrixOutputs_hi_hi_49, decoded_orMatrixOutputs_hi_lo_35)
node _decoded_orMatrixOutputs_T_109 = cat(decoded_orMatrixOutputs_hi_53, decoded_orMatrixOutputs_lo_49)
node _decoded_orMatrixOutputs_T_110 = orr(_decoded_orMatrixOutputs_T_109)
node decoded_orMatrixOutputs_lo_lo_hi_25 = cat(decoded_andMatrixOutputs_26_2_2, decoded_andMatrixOutputs_47_2_1)
node decoded_orMatrixOutputs_lo_lo_36 = cat(decoded_orMatrixOutputs_lo_lo_hi_25, decoded_andMatrixOutputs_51_2_1)
node decoded_orMatrixOutputs_lo_hi_lo_19 = cat(decoded_andMatrixOutputs_25_2_2, decoded_andMatrixOutputs_34_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_30 = cat(decoded_andMatrixOutputs_53_2_1, decoded_andMatrixOutputs_15_2_2)
node decoded_orMatrixOutputs_lo_hi_40 = cat(decoded_orMatrixOutputs_lo_hi_hi_30, decoded_orMatrixOutputs_lo_hi_lo_19)
node decoded_orMatrixOutputs_lo_50 = cat(decoded_orMatrixOutputs_lo_hi_40, decoded_orMatrixOutputs_lo_lo_36)
node decoded_orMatrixOutputs_hi_lo_hi_25 = cat(decoded_andMatrixOutputs_23_2_2, decoded_andMatrixOutputs_49_2_1)
node decoded_orMatrixOutputs_hi_lo_36 = cat(decoded_orMatrixOutputs_hi_lo_hi_25, decoded_andMatrixOutputs_4_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_19 = cat(decoded_andMatrixOutputs_11_2_2, decoded_andMatrixOutputs_24_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_50 = cat(decoded_orMatrixOutputs_hi_hi_hi_32, decoded_orMatrixOutputs_hi_hi_lo_19)
node decoded_orMatrixOutputs_hi_54 = cat(decoded_orMatrixOutputs_hi_hi_50, decoded_orMatrixOutputs_hi_lo_36)
node _decoded_orMatrixOutputs_T_111 = cat(decoded_orMatrixOutputs_hi_54, decoded_orMatrixOutputs_lo_50)
node _decoded_orMatrixOutputs_T_112 = orr(_decoded_orMatrixOutputs_T_111)
node decoded_orMatrixOutputs_lo_lo_hi_26 = cat(decoded_andMatrixOutputs_34_2_2, decoded_andMatrixOutputs_26_2_2)
node decoded_orMatrixOutputs_lo_lo_37 = cat(decoded_orMatrixOutputs_lo_lo_hi_26, decoded_andMatrixOutputs_47_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_31 = cat(decoded_andMatrixOutputs_14_2_2, decoded_andMatrixOutputs_15_2_2)
node decoded_orMatrixOutputs_lo_hi_41 = cat(decoded_orMatrixOutputs_lo_hi_hi_31, decoded_andMatrixOutputs_25_2_2)
node decoded_orMatrixOutputs_lo_51 = cat(decoded_orMatrixOutputs_lo_hi_41, decoded_orMatrixOutputs_lo_lo_37)
node decoded_orMatrixOutputs_hi_lo_hi_26 = cat(decoded_andMatrixOutputs_24_2_2, decoded_andMatrixOutputs_23_2_2)
node decoded_orMatrixOutputs_hi_lo_37 = cat(decoded_orMatrixOutputs_hi_lo_hi_26, decoded_andMatrixOutputs_65_2)
node decoded_orMatrixOutputs_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_51 = cat(decoded_orMatrixOutputs_hi_hi_hi_33, decoded_andMatrixOutputs_11_2_2)
node decoded_orMatrixOutputs_hi_55 = cat(decoded_orMatrixOutputs_hi_hi_51, decoded_orMatrixOutputs_hi_lo_37)
node _decoded_orMatrixOutputs_T_113 = cat(decoded_orMatrixOutputs_hi_55, decoded_orMatrixOutputs_lo_51)
node _decoded_orMatrixOutputs_T_114 = orr(_decoded_orMatrixOutputs_T_113)
node decoded_orMatrixOutputs_lo_lo_38 = cat(decoded_andMatrixOutputs_25_2_2, decoded_andMatrixOutputs_12_2_2)
node decoded_orMatrixOutputs_lo_hi_42 = cat(decoded_andMatrixOutputs_61_2, decoded_andMatrixOutputs_15_2_2)
node decoded_orMatrixOutputs_lo_52 = cat(decoded_orMatrixOutputs_lo_hi_42, decoded_orMatrixOutputs_lo_lo_38)
node decoded_orMatrixOutputs_hi_lo_38 = cat(decoded_andMatrixOutputs_11_2_2, decoded_andMatrixOutputs_24_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_66_2, decoded_andMatrixOutputs_55_2_1)
node decoded_orMatrixOutputs_hi_hi_52 = cat(decoded_orMatrixOutputs_hi_hi_hi_34, decoded_andMatrixOutputs_45_2_1)
node decoded_orMatrixOutputs_hi_56 = cat(decoded_orMatrixOutputs_hi_hi_52, decoded_orMatrixOutputs_hi_lo_38)
node _decoded_orMatrixOutputs_T_115 = cat(decoded_orMatrixOutputs_hi_56, decoded_orMatrixOutputs_lo_52)
node _decoded_orMatrixOutputs_T_116 = orr(_decoded_orMatrixOutputs_T_115)
node _decoded_orMatrixOutputs_T_117 = cat(decoded_andMatrixOutputs_21_2_2, decoded_andMatrixOutputs_60_2)
node _decoded_orMatrixOutputs_T_118 = orr(_decoded_orMatrixOutputs_T_117)
node decoded_orMatrixOutputs_lo_lo_hi_27 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_16_2_2)
node decoded_orMatrixOutputs_lo_lo_39 = cat(decoded_orMatrixOutputs_lo_lo_hi_27, decoded_andMatrixOutputs_68_2)
node decoded_orMatrixOutputs_lo_hi_lo_20 = cat(decoded_andMatrixOutputs_57_2, decoded_andMatrixOutputs_40_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_32 = cat(decoded_andMatrixOutputs_35_2_2, decoded_andMatrixOutputs_74_2)
node decoded_orMatrixOutputs_lo_hi_43 = cat(decoded_orMatrixOutputs_lo_hi_hi_32, decoded_orMatrixOutputs_lo_hi_lo_20)
node decoded_orMatrixOutputs_lo_53 = cat(decoded_orMatrixOutputs_lo_hi_43, decoded_orMatrixOutputs_lo_lo_39)
node decoded_orMatrixOutputs_hi_lo_lo_12 = cat(decoded_andMatrixOutputs_37_2_2, decoded_andMatrixOutputs_43_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_27 = cat(decoded_andMatrixOutputs_7_2_2, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_hi_lo_39 = cat(decoded_orMatrixOutputs_hi_lo_hi_27, decoded_orMatrixOutputs_hi_lo_lo_12)
node decoded_orMatrixOutputs_hi_hi_lo_20 = cat(decoded_andMatrixOutputs_70_2, decoded_andMatrixOutputs_54_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_35 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_hi_53 = cat(decoded_orMatrixOutputs_hi_hi_hi_35, decoded_orMatrixOutputs_hi_hi_lo_20)
node decoded_orMatrixOutputs_hi_57 = cat(decoded_orMatrixOutputs_hi_hi_53, decoded_orMatrixOutputs_hi_lo_39)
node _decoded_orMatrixOutputs_T_119 = cat(decoded_orMatrixOutputs_hi_57, decoded_orMatrixOutputs_lo_53)
node _decoded_orMatrixOutputs_T_120 = orr(_decoded_orMatrixOutputs_T_119)
node decoded_orMatrixOutputs_lo_lo_hi_28 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_16_2_2)
node decoded_orMatrixOutputs_lo_lo_40 = cat(decoded_orMatrixOutputs_lo_lo_hi_28, decoded_andMatrixOutputs_68_2)
node decoded_orMatrixOutputs_lo_hi_lo_21 = cat(decoded_andMatrixOutputs_57_2, decoded_andMatrixOutputs_40_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_33 = cat(decoded_andMatrixOutputs_35_2_2, decoded_andMatrixOutputs_74_2)
node decoded_orMatrixOutputs_lo_hi_44 = cat(decoded_orMatrixOutputs_lo_hi_hi_33, decoded_orMatrixOutputs_lo_hi_lo_21)
node decoded_orMatrixOutputs_lo_54 = cat(decoded_orMatrixOutputs_lo_hi_44, decoded_orMatrixOutputs_lo_lo_40)
node decoded_orMatrixOutputs_hi_lo_lo_13 = cat(decoded_andMatrixOutputs_37_2_2, decoded_andMatrixOutputs_43_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_28 = cat(decoded_andMatrixOutputs_7_2_2, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_hi_lo_40 = cat(decoded_orMatrixOutputs_hi_lo_hi_28, decoded_orMatrixOutputs_hi_lo_lo_13)
node decoded_orMatrixOutputs_hi_hi_lo_21 = cat(decoded_andMatrixOutputs_70_2, decoded_andMatrixOutputs_54_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_36 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_hi_54 = cat(decoded_orMatrixOutputs_hi_hi_hi_36, decoded_orMatrixOutputs_hi_hi_lo_21)
node decoded_orMatrixOutputs_hi_58 = cat(decoded_orMatrixOutputs_hi_hi_54, decoded_orMatrixOutputs_hi_lo_40)
node _decoded_orMatrixOutputs_T_121 = cat(decoded_orMatrixOutputs_hi_58, decoded_orMatrixOutputs_lo_54)
node _decoded_orMatrixOutputs_T_122 = orr(_decoded_orMatrixOutputs_T_121)
node decoded_orMatrixOutputs_lo_lo_hi_29 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_16_2_2)
node decoded_orMatrixOutputs_lo_lo_41 = cat(decoded_orMatrixOutputs_lo_lo_hi_29, decoded_andMatrixOutputs_68_2)
node decoded_orMatrixOutputs_lo_hi_lo_22 = cat(decoded_andMatrixOutputs_57_2, decoded_andMatrixOutputs_40_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_34 = cat(decoded_andMatrixOutputs_35_2_2, decoded_andMatrixOutputs_74_2)
node decoded_orMatrixOutputs_lo_hi_45 = cat(decoded_orMatrixOutputs_lo_hi_hi_34, decoded_orMatrixOutputs_lo_hi_lo_22)
node decoded_orMatrixOutputs_lo_55 = cat(decoded_orMatrixOutputs_lo_hi_45, decoded_orMatrixOutputs_lo_lo_41)
node decoded_orMatrixOutputs_hi_lo_lo_14 = cat(decoded_andMatrixOutputs_37_2_2, decoded_andMatrixOutputs_43_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_29 = cat(decoded_andMatrixOutputs_7_2_2, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_hi_lo_41 = cat(decoded_orMatrixOutputs_hi_lo_hi_29, decoded_orMatrixOutputs_hi_lo_lo_14)
node decoded_orMatrixOutputs_hi_hi_lo_22 = cat(decoded_andMatrixOutputs_70_2, decoded_andMatrixOutputs_54_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_37 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_hi_55 = cat(decoded_orMatrixOutputs_hi_hi_hi_37, decoded_orMatrixOutputs_hi_hi_lo_22)
node decoded_orMatrixOutputs_hi_59 = cat(decoded_orMatrixOutputs_hi_hi_55, decoded_orMatrixOutputs_hi_lo_41)
node _decoded_orMatrixOutputs_T_123 = cat(decoded_orMatrixOutputs_hi_59, decoded_orMatrixOutputs_lo_55)
node _decoded_orMatrixOutputs_T_124 = orr(_decoded_orMatrixOutputs_T_123)
node decoded_orMatrixOutputs_lo_lo_hi_30 = cat(decoded_andMatrixOutputs_52_2_1, decoded_andMatrixOutputs_31_2_2)
node decoded_orMatrixOutputs_lo_lo_42 = cat(decoded_orMatrixOutputs_lo_lo_hi_30, decoded_andMatrixOutputs_48_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_35 = cat(decoded_andMatrixOutputs_37_2_2, decoded_andMatrixOutputs_43_2_2)
node decoded_orMatrixOutputs_lo_hi_46 = cat(decoded_orMatrixOutputs_lo_hi_hi_35, decoded_andMatrixOutputs_35_2_2)
node decoded_orMatrixOutputs_lo_56 = cat(decoded_orMatrixOutputs_lo_hi_46, decoded_orMatrixOutputs_lo_lo_42)
node decoded_orMatrixOutputs_hi_lo_hi_30 = cat(decoded_andMatrixOutputs_54_2_1, decoded_andMatrixOutputs_7_2_2)
node decoded_orMatrixOutputs_hi_lo_42 = cat(decoded_orMatrixOutputs_hi_lo_hi_30, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_38 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_hi_56 = cat(decoded_orMatrixOutputs_hi_hi_hi_38, decoded_andMatrixOutputs_70_2)
node decoded_orMatrixOutputs_hi_60 = cat(decoded_orMatrixOutputs_hi_hi_56, decoded_orMatrixOutputs_hi_lo_42)
node _decoded_orMatrixOutputs_T_125 = cat(decoded_orMatrixOutputs_hi_60, decoded_orMatrixOutputs_lo_56)
node _decoded_orMatrixOutputs_T_126 = orr(_decoded_orMatrixOutputs_T_125)
node decoded_orMatrixOutputs_lo_lo_hi_31 = cat(decoded_andMatrixOutputs_37_2_2, decoded_andMatrixOutputs_43_2_2)
node decoded_orMatrixOutputs_lo_lo_43 = cat(decoded_orMatrixOutputs_lo_lo_hi_31, decoded_andMatrixOutputs_35_2_2)
node decoded_orMatrixOutputs_lo_hi_hi_36 = cat(decoded_andMatrixOutputs_54_2_1, decoded_andMatrixOutputs_7_2_2)
node decoded_orMatrixOutputs_lo_hi_47 = cat(decoded_orMatrixOutputs_lo_hi_hi_36, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_lo_57 = cat(decoded_orMatrixOutputs_lo_hi_47, decoded_orMatrixOutputs_lo_lo_43)
node decoded_orMatrixOutputs_hi_lo_hi_31 = cat(decoded_andMatrixOutputs_36_2_2, decoded_andMatrixOutputs_58_2)
node decoded_orMatrixOutputs_hi_lo_43 = cat(decoded_orMatrixOutputs_hi_lo_hi_31, decoded_andMatrixOutputs_38_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_39 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_hi_57 = cat(decoded_orMatrixOutputs_hi_hi_hi_39, decoded_andMatrixOutputs_70_2)
node decoded_orMatrixOutputs_hi_61 = cat(decoded_orMatrixOutputs_hi_hi_57, decoded_orMatrixOutputs_hi_lo_43)
node _decoded_orMatrixOutputs_T_127 = cat(decoded_orMatrixOutputs_hi_61, decoded_orMatrixOutputs_lo_57)
node _decoded_orMatrixOutputs_T_128 = orr(_decoded_orMatrixOutputs_T_127)
node decoded_orMatrixOutputs_lo_hi_48 = cat(decoded_andMatrixOutputs_54_2_1, decoded_andMatrixOutputs_7_2_2)
node decoded_orMatrixOutputs_lo_58 = cat(decoded_orMatrixOutputs_lo_hi_48, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_hi_hi_58 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_62 = cat(decoded_orMatrixOutputs_hi_hi_58, decoded_andMatrixOutputs_70_2)
node _decoded_orMatrixOutputs_T_129 = cat(decoded_orMatrixOutputs_hi_62, decoded_orMatrixOutputs_lo_58)
node _decoded_orMatrixOutputs_T_130 = orr(_decoded_orMatrixOutputs_T_129)
node decoded_orMatrixOutputs_lo_lo_44 = cat(decoded_andMatrixOutputs_7_2_2, decoded_andMatrixOutputs_5_2_2)
node decoded_orMatrixOutputs_lo_hi_49 = cat(decoded_andMatrixOutputs_70_2, decoded_andMatrixOutputs_54_2_1)
node decoded_orMatrixOutputs_lo_59 = cat(decoded_orMatrixOutputs_lo_hi_49, decoded_orMatrixOutputs_lo_lo_44)
node decoded_orMatrixOutputs_hi_lo_44 = cat(decoded_andMatrixOutputs_71_2, decoded_andMatrixOutputs_46_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_40 = cat(decoded_andMatrixOutputs_20_2_2, decoded_andMatrixOutputs_33_2_2)
node decoded_orMatrixOutputs_hi_hi_59 = cat(decoded_orMatrixOutputs_hi_hi_hi_40, decoded_andMatrixOutputs_42_2_2)
node decoded_orMatrixOutputs_hi_63 = cat(decoded_orMatrixOutputs_hi_hi_59, decoded_orMatrixOutputs_hi_lo_44)
node _decoded_orMatrixOutputs_T_131 = cat(decoded_orMatrixOutputs_hi_63, decoded_orMatrixOutputs_lo_59)
node _decoded_orMatrixOutputs_T_132 = orr(_decoded_orMatrixOutputs_T_131)
node decoded_orMatrixOutputs_lo_lo_hi_32 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_16_2_2)
node decoded_orMatrixOutputs_lo_lo_45 = cat(decoded_orMatrixOutputs_lo_lo_hi_32, decoded_andMatrixOutputs_68_2)
node decoded_orMatrixOutputs_lo_hi_hi_37 = cat(decoded_andMatrixOutputs_74_2, decoded_andMatrixOutputs_57_2)
node decoded_orMatrixOutputs_lo_hi_50 = cat(decoded_orMatrixOutputs_lo_hi_hi_37, decoded_andMatrixOutputs_40_2_2)
node decoded_orMatrixOutputs_lo_60 = cat(decoded_orMatrixOutputs_lo_hi_50, decoded_orMatrixOutputs_lo_lo_45)
node decoded_orMatrixOutputs_hi_lo_hi_32 = cat(decoded_andMatrixOutputs_50_2_1, decoded_andMatrixOutputs_18_2_2)
node decoded_orMatrixOutputs_hi_lo_45 = cat(decoded_orMatrixOutputs_hi_lo_hi_32, decoded_andMatrixOutputs_9_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_41 = cat(decoded_andMatrixOutputs_17_2_2, decoded_andMatrixOutputs_56_2)
node decoded_orMatrixOutputs_hi_hi_60 = cat(decoded_orMatrixOutputs_hi_hi_hi_41, decoded_andMatrixOutputs_32_2_2)
node decoded_orMatrixOutputs_hi_64 = cat(decoded_orMatrixOutputs_hi_hi_60, decoded_orMatrixOutputs_hi_lo_45)
node _decoded_orMatrixOutputs_T_133 = cat(decoded_orMatrixOutputs_hi_64, decoded_orMatrixOutputs_lo_60)
node _decoded_orMatrixOutputs_T_134 = orr(_decoded_orMatrixOutputs_T_133)
node decoded_orMatrixOutputs_lo_lo_hi_33 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_16_2_2)
node decoded_orMatrixOutputs_lo_lo_46 = cat(decoded_orMatrixOutputs_lo_lo_hi_33, decoded_andMatrixOutputs_68_2)
node decoded_orMatrixOutputs_lo_hi_hi_38 = cat(decoded_andMatrixOutputs_74_2, decoded_andMatrixOutputs_57_2)
node decoded_orMatrixOutputs_lo_hi_51 = cat(decoded_orMatrixOutputs_lo_hi_hi_38, decoded_andMatrixOutputs_40_2_2)
node decoded_orMatrixOutputs_lo_61 = cat(decoded_orMatrixOutputs_lo_hi_51, decoded_orMatrixOutputs_lo_lo_46)
node decoded_orMatrixOutputs_hi_lo_hi_33 = cat(decoded_andMatrixOutputs_50_2_1, decoded_andMatrixOutputs_18_2_2)
node decoded_orMatrixOutputs_hi_lo_46 = cat(decoded_orMatrixOutputs_hi_lo_hi_33, decoded_andMatrixOutputs_9_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_42 = cat(decoded_andMatrixOutputs_17_2_2, decoded_andMatrixOutputs_56_2)
node decoded_orMatrixOutputs_hi_hi_61 = cat(decoded_orMatrixOutputs_hi_hi_hi_42, decoded_andMatrixOutputs_32_2_2)
node decoded_orMatrixOutputs_hi_65 = cat(decoded_orMatrixOutputs_hi_hi_61, decoded_orMatrixOutputs_hi_lo_46)
node _decoded_orMatrixOutputs_T_135 = cat(decoded_orMatrixOutputs_hi_65, decoded_orMatrixOutputs_lo_61)
node _decoded_orMatrixOutputs_T_136 = orr(_decoded_orMatrixOutputs_T_135)
node decoded_orMatrixOutputs_lo_lo_hi_34 = cat(decoded_andMatrixOutputs_1_2_2, decoded_andMatrixOutputs_16_2_2)
node decoded_orMatrixOutputs_lo_lo_47 = cat(decoded_orMatrixOutputs_lo_lo_hi_34, decoded_andMatrixOutputs_68_2)
node decoded_orMatrixOutputs_lo_hi_hi_39 = cat(decoded_andMatrixOutputs_74_2, decoded_andMatrixOutputs_57_2)
node decoded_orMatrixOutputs_lo_hi_52 = cat(decoded_orMatrixOutputs_lo_hi_hi_39, decoded_andMatrixOutputs_40_2_2)
node decoded_orMatrixOutputs_lo_62 = cat(decoded_orMatrixOutputs_lo_hi_52, decoded_orMatrixOutputs_lo_lo_47)
node decoded_orMatrixOutputs_hi_lo_hi_34 = cat(decoded_andMatrixOutputs_50_2_1, decoded_andMatrixOutputs_18_2_2)
node decoded_orMatrixOutputs_hi_lo_47 = cat(decoded_orMatrixOutputs_hi_lo_hi_34, decoded_andMatrixOutputs_9_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_43 = cat(decoded_andMatrixOutputs_17_2_2, decoded_andMatrixOutputs_56_2)
node decoded_orMatrixOutputs_hi_hi_62 = cat(decoded_orMatrixOutputs_hi_hi_hi_43, decoded_andMatrixOutputs_32_2_2)
node decoded_orMatrixOutputs_hi_66 = cat(decoded_orMatrixOutputs_hi_hi_62, decoded_orMatrixOutputs_hi_lo_47)
node _decoded_orMatrixOutputs_T_137 = cat(decoded_orMatrixOutputs_hi_66, decoded_orMatrixOutputs_lo_62)
node _decoded_orMatrixOutputs_T_138 = orr(_decoded_orMatrixOutputs_T_137)
node decoded_orMatrixOutputs_lo_hi_53 = cat(decoded_andMatrixOutputs_50_2_1, decoded_andMatrixOutputs_18_2_2)
node decoded_orMatrixOutputs_lo_63 = cat(decoded_orMatrixOutputs_lo_hi_53, decoded_andMatrixOutputs_9_2_2)
node decoded_orMatrixOutputs_hi_hi_63 = cat(decoded_andMatrixOutputs_17_2_2, decoded_andMatrixOutputs_56_2)
node decoded_orMatrixOutputs_hi_67 = cat(decoded_orMatrixOutputs_hi_hi_63, decoded_andMatrixOutputs_32_2_2)
node _decoded_orMatrixOutputs_T_139 = cat(decoded_orMatrixOutputs_hi_67, decoded_orMatrixOutputs_lo_63)
node _decoded_orMatrixOutputs_T_140 = orr(_decoded_orMatrixOutputs_T_139)
node decoded_orMatrixOutputs_lo_lo_48 = cat(decoded_andMatrixOutputs_18_2_2, decoded_andMatrixOutputs_9_2_2)
node decoded_orMatrixOutputs_lo_hi_54 = cat(decoded_andMatrixOutputs_32_2_2, decoded_andMatrixOutputs_50_2_1)
node decoded_orMatrixOutputs_lo_64 = cat(decoded_orMatrixOutputs_lo_hi_54, decoded_orMatrixOutputs_lo_lo_48)
node decoded_orMatrixOutputs_hi_lo_48 = cat(decoded_andMatrixOutputs_8_2_2, decoded_andMatrixOutputs_2_2_2)
node decoded_orMatrixOutputs_hi_hi_64 = cat(decoded_andMatrixOutputs_17_2_2, decoded_andMatrixOutputs_56_2)
node decoded_orMatrixOutputs_hi_68 = cat(decoded_orMatrixOutputs_hi_hi_64, decoded_orMatrixOutputs_hi_lo_48)
node _decoded_orMatrixOutputs_T_141 = cat(decoded_orMatrixOutputs_hi_68, decoded_orMatrixOutputs_lo_64)
node _decoded_orMatrixOutputs_T_142 = orr(_decoded_orMatrixOutputs_T_141)
node decoded_orMatrixOutputs_lo_65 = cat(decoded_andMatrixOutputs_32_2_2, decoded_andMatrixOutputs_50_2_1)
node decoded_orMatrixOutputs_hi_69 = cat(decoded_andMatrixOutputs_17_2_2, decoded_andMatrixOutputs_56_2)
node _decoded_orMatrixOutputs_T_143 = cat(decoded_orMatrixOutputs_hi_69, decoded_orMatrixOutputs_lo_65)
node _decoded_orMatrixOutputs_T_144 = orr(_decoded_orMatrixOutputs_T_143)
node decoded_orMatrixOutputs_lo_hi_55 = cat(decoded_andMatrixOutputs_56_2, decoded_andMatrixOutputs_32_2_2)
node decoded_orMatrixOutputs_lo_66 = cat(decoded_orMatrixOutputs_lo_hi_55, decoded_andMatrixOutputs_50_2_1)
node decoded_orMatrixOutputs_hi_hi_65 = cat(decoded_andMatrixOutputs_73_2, decoded_andMatrixOutputs_63_2)
node decoded_orMatrixOutputs_hi_70 = cat(decoded_orMatrixOutputs_hi_hi_65, decoded_andMatrixOutputs_17_2_2)
node _decoded_orMatrixOutputs_T_145 = cat(decoded_orMatrixOutputs_hi_70, decoded_orMatrixOutputs_lo_66)
node _decoded_orMatrixOutputs_T_146 = orr(_decoded_orMatrixOutputs_T_145)
node decoded_orMatrixOutputs_lo_lo_hi_35 = cat(decoded_andMatrixOutputs_59_2, decoded_andMatrixOutputs_62_2)
node decoded_orMatrixOutputs_lo_lo_49 = cat(decoded_orMatrixOutputs_lo_lo_hi_35, decoded_andMatrixOutputs_69_2)
node decoded_orMatrixOutputs_lo_hi_hi_40 = cat(decoded_andMatrixOutputs_67_2, decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_hi_56 = cat(decoded_orMatrixOutputs_lo_hi_hi_40, decoded_andMatrixOutputs_3_2_2)
node decoded_orMatrixOutputs_lo_67 = cat(decoded_orMatrixOutputs_lo_hi_56, decoded_orMatrixOutputs_lo_lo_49)
node decoded_orMatrixOutputs_hi_lo_hi_35 = cat(decoded_andMatrixOutputs_22_2_2, decoded_andMatrixOutputs_44_2_1)
node decoded_orMatrixOutputs_hi_lo_49 = cat(decoded_orMatrixOutputs_hi_lo_hi_35, decoded_andMatrixOutputs_30_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_23 = cat(decoded_andMatrixOutputs_27_2_2, decoded_andMatrixOutputs_13_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_44 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node decoded_orMatrixOutputs_hi_hi_66 = cat(decoded_orMatrixOutputs_hi_hi_hi_44, decoded_orMatrixOutputs_hi_hi_lo_23)
node decoded_orMatrixOutputs_hi_71 = cat(decoded_orMatrixOutputs_hi_hi_66, decoded_orMatrixOutputs_hi_lo_49)
node _decoded_orMatrixOutputs_T_147 = cat(decoded_orMatrixOutputs_hi_71, decoded_orMatrixOutputs_lo_67)
node _decoded_orMatrixOutputs_T_148 = orr(_decoded_orMatrixOutputs_T_147)
node decoded_orMatrixOutputs_lo_lo_hi_36 = cat(decoded_andMatrixOutputs_59_2, decoded_andMatrixOutputs_62_2)
node decoded_orMatrixOutputs_lo_lo_50 = cat(decoded_orMatrixOutputs_lo_lo_hi_36, decoded_andMatrixOutputs_69_2)
node decoded_orMatrixOutputs_lo_hi_hi_41 = cat(decoded_andMatrixOutputs_67_2, decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_hi_57 = cat(decoded_orMatrixOutputs_lo_hi_hi_41, decoded_andMatrixOutputs_3_2_2)
node decoded_orMatrixOutputs_lo_68 = cat(decoded_orMatrixOutputs_lo_hi_57, decoded_orMatrixOutputs_lo_lo_50)
node decoded_orMatrixOutputs_hi_lo_hi_36 = cat(decoded_andMatrixOutputs_22_2_2, decoded_andMatrixOutputs_44_2_1)
node decoded_orMatrixOutputs_hi_lo_50 = cat(decoded_orMatrixOutputs_hi_lo_hi_36, decoded_andMatrixOutputs_30_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_24 = cat(decoded_andMatrixOutputs_27_2_2, decoded_andMatrixOutputs_13_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_45 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node decoded_orMatrixOutputs_hi_hi_67 = cat(decoded_orMatrixOutputs_hi_hi_hi_45, decoded_orMatrixOutputs_hi_hi_lo_24)
node decoded_orMatrixOutputs_hi_72 = cat(decoded_orMatrixOutputs_hi_hi_67, decoded_orMatrixOutputs_hi_lo_50)
node _decoded_orMatrixOutputs_T_149 = cat(decoded_orMatrixOutputs_hi_72, decoded_orMatrixOutputs_lo_68)
node _decoded_orMatrixOutputs_T_150 = orr(_decoded_orMatrixOutputs_T_149)
node decoded_orMatrixOutputs_lo_lo_hi_37 = cat(decoded_andMatrixOutputs_59_2, decoded_andMatrixOutputs_62_2)
node decoded_orMatrixOutputs_lo_lo_51 = cat(decoded_orMatrixOutputs_lo_lo_hi_37, decoded_andMatrixOutputs_69_2)
node decoded_orMatrixOutputs_lo_hi_hi_42 = cat(decoded_andMatrixOutputs_67_2, decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_hi_58 = cat(decoded_orMatrixOutputs_lo_hi_hi_42, decoded_andMatrixOutputs_3_2_2)
node decoded_orMatrixOutputs_lo_69 = cat(decoded_orMatrixOutputs_lo_hi_58, decoded_orMatrixOutputs_lo_lo_51)
node decoded_orMatrixOutputs_hi_lo_hi_37 = cat(decoded_andMatrixOutputs_22_2_2, decoded_andMatrixOutputs_44_2_1)
node decoded_orMatrixOutputs_hi_lo_51 = cat(decoded_orMatrixOutputs_hi_lo_hi_37, decoded_andMatrixOutputs_30_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_25 = cat(decoded_andMatrixOutputs_27_2_2, decoded_andMatrixOutputs_13_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_46 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node decoded_orMatrixOutputs_hi_hi_68 = cat(decoded_orMatrixOutputs_hi_hi_hi_46, decoded_orMatrixOutputs_hi_hi_lo_25)
node decoded_orMatrixOutputs_hi_73 = cat(decoded_orMatrixOutputs_hi_hi_68, decoded_orMatrixOutputs_hi_lo_51)
node _decoded_orMatrixOutputs_T_151 = cat(decoded_orMatrixOutputs_hi_73, decoded_orMatrixOutputs_lo_69)
node _decoded_orMatrixOutputs_T_152 = orr(_decoded_orMatrixOutputs_T_151)
node decoded_orMatrixOutputs_lo_lo_hi_38 = cat(decoded_andMatrixOutputs_59_2, decoded_andMatrixOutputs_62_2)
node decoded_orMatrixOutputs_lo_lo_52 = cat(decoded_orMatrixOutputs_lo_lo_hi_38, decoded_andMatrixOutputs_69_2)
node decoded_orMatrixOutputs_lo_hi_hi_43 = cat(decoded_andMatrixOutputs_67_2, decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_hi_59 = cat(decoded_orMatrixOutputs_lo_hi_hi_43, decoded_andMatrixOutputs_3_2_2)
node decoded_orMatrixOutputs_lo_70 = cat(decoded_orMatrixOutputs_lo_hi_59, decoded_orMatrixOutputs_lo_lo_52)
node decoded_orMatrixOutputs_hi_lo_hi_38 = cat(decoded_andMatrixOutputs_22_2_2, decoded_andMatrixOutputs_44_2_1)
node decoded_orMatrixOutputs_hi_lo_52 = cat(decoded_orMatrixOutputs_hi_lo_hi_38, decoded_andMatrixOutputs_30_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_26 = cat(decoded_andMatrixOutputs_27_2_2, decoded_andMatrixOutputs_13_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_47 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node decoded_orMatrixOutputs_hi_hi_69 = cat(decoded_orMatrixOutputs_hi_hi_hi_47, decoded_orMatrixOutputs_hi_hi_lo_26)
node decoded_orMatrixOutputs_hi_74 = cat(decoded_orMatrixOutputs_hi_hi_69, decoded_orMatrixOutputs_hi_lo_52)
node _decoded_orMatrixOutputs_T_153 = cat(decoded_orMatrixOutputs_hi_74, decoded_orMatrixOutputs_lo_70)
node _decoded_orMatrixOutputs_T_154 = orr(_decoded_orMatrixOutputs_T_153)
node decoded_orMatrixOutputs_lo_lo_53 = cat(decoded_andMatrixOutputs_67_2, decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_hi_60 = cat(decoded_andMatrixOutputs_44_2_1, decoded_andMatrixOutputs_30_2_2)
node decoded_orMatrixOutputs_lo_71 = cat(decoded_orMatrixOutputs_lo_hi_60, decoded_orMatrixOutputs_lo_lo_53)
node decoded_orMatrixOutputs_hi_lo_53 = cat(decoded_andMatrixOutputs_13_2_2, decoded_andMatrixOutputs_22_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_48 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node decoded_orMatrixOutputs_hi_hi_70 = cat(decoded_orMatrixOutputs_hi_hi_hi_48, decoded_andMatrixOutputs_27_2_2)
node decoded_orMatrixOutputs_hi_75 = cat(decoded_orMatrixOutputs_hi_hi_70, decoded_orMatrixOutputs_hi_lo_53)
node _decoded_orMatrixOutputs_T_155 = cat(decoded_orMatrixOutputs_hi_75, decoded_orMatrixOutputs_lo_71)
node _decoded_orMatrixOutputs_T_156 = orr(_decoded_orMatrixOutputs_T_155)
node decoded_orMatrixOutputs_lo_lo_54 = cat(decoded_andMatrixOutputs_67_2, decoded_andMatrixOutputs_6_2_2)
node decoded_orMatrixOutputs_lo_hi_61 = cat(decoded_andMatrixOutputs_44_2_1, decoded_andMatrixOutputs_30_2_2)
node decoded_orMatrixOutputs_lo_72 = cat(decoded_orMatrixOutputs_lo_hi_61, decoded_orMatrixOutputs_lo_lo_54)
node decoded_orMatrixOutputs_hi_lo_54 = cat(decoded_andMatrixOutputs_13_2_2, decoded_andMatrixOutputs_22_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_49 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node decoded_orMatrixOutputs_hi_hi_71 = cat(decoded_orMatrixOutputs_hi_hi_hi_49, decoded_andMatrixOutputs_27_2_2)
node decoded_orMatrixOutputs_hi_76 = cat(decoded_orMatrixOutputs_hi_hi_71, decoded_orMatrixOutputs_hi_lo_54)
node _decoded_orMatrixOutputs_T_157 = cat(decoded_orMatrixOutputs_hi_76, decoded_orMatrixOutputs_lo_72)
node _decoded_orMatrixOutputs_T_158 = orr(_decoded_orMatrixOutputs_T_157)
node decoded_orMatrixOutputs_hi_77 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node _decoded_orMatrixOutputs_T_159 = cat(decoded_orMatrixOutputs_hi_77, decoded_andMatrixOutputs_27_2_2)
node _decoded_orMatrixOutputs_T_160 = orr(_decoded_orMatrixOutputs_T_159)
node decoded_orMatrixOutputs_hi_78 = cat(decoded_andMatrixOutputs_19_2_2, decoded_andMatrixOutputs_10_2_2)
node _decoded_orMatrixOutputs_T_161 = cat(decoded_orMatrixOutputs_hi_78, decoded_andMatrixOutputs_27_2_2)
node _decoded_orMatrixOutputs_T_162 = orr(_decoded_orMatrixOutputs_T_161)
node decoded_orMatrixOutputs_lo_lo_lo_lo_2 = cat(_decoded_orMatrixOutputs_T_106, _decoded_orMatrixOutputs_T_104)
node decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_112, _decoded_orMatrixOutputs_T_110)
node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, _decoded_orMatrixOutputs_T_108)
node decoded_orMatrixOutputs_lo_lo_lo_11 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_lo_2)
node decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_116, _decoded_orMatrixOutputs_T_114)
node decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_122, _decoded_orMatrixOutputs_T_120)
node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, _decoded_orMatrixOutputs_T_118)
node decoded_orMatrixOutputs_lo_lo_hi_39 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, decoded_orMatrixOutputs_lo_lo_hi_lo_2)
node decoded_orMatrixOutputs_lo_lo_55 = cat(decoded_orMatrixOutputs_lo_lo_hi_39, decoded_orMatrixOutputs_lo_lo_lo_11)
node decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(_decoded_orMatrixOutputs_T_126, _decoded_orMatrixOutputs_T_124)
node decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_132, _decoded_orMatrixOutputs_T_130)
node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, _decoded_orMatrixOutputs_T_128)
node decoded_orMatrixOutputs_lo_hi_lo_23 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, decoded_orMatrixOutputs_lo_hi_lo_lo_2)
node decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_44 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, decoded_orMatrixOutputs_lo_hi_hi_lo_2)
node decoded_orMatrixOutputs_lo_hi_62 = cat(decoded_orMatrixOutputs_lo_hi_hi_44, decoded_orMatrixOutputs_lo_hi_lo_23)
node decoded_orMatrixOutputs_lo_73 = cat(decoded_orMatrixOutputs_lo_hi_62, decoded_orMatrixOutputs_lo_lo_55)
node decoded_orMatrixOutputs_hi_lo_lo_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_134, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_lo_15 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_lo_2)
node decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_138, _decoded_orMatrixOutputs_T_136)
node decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_144, _decoded_orMatrixOutputs_T_142)
node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, _decoded_orMatrixOutputs_T_140)
node decoded_orMatrixOutputs_hi_lo_hi_39 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, decoded_orMatrixOutputs_hi_lo_hi_lo_2)
node decoded_orMatrixOutputs_hi_lo_55 = cat(decoded_orMatrixOutputs_hi_lo_hi_39, decoded_orMatrixOutputs_hi_lo_lo_15)
node decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_146)
node decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_152, _decoded_orMatrixOutputs_T_150)
node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, _decoded_orMatrixOutputs_T_148)
node decoded_orMatrixOutputs_hi_hi_lo_27 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, decoded_orMatrixOutputs_hi_hi_lo_lo_2)
node decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_156, _decoded_orMatrixOutputs_T_154)
node decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_162, _decoded_orMatrixOutputs_T_160)
node decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, _decoded_orMatrixOutputs_T_158)
node decoded_orMatrixOutputs_hi_hi_hi_50 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_5, decoded_orMatrixOutputs_hi_hi_hi_lo_2)
node decoded_orMatrixOutputs_hi_hi_72 = cat(decoded_orMatrixOutputs_hi_hi_hi_50, decoded_orMatrixOutputs_hi_hi_lo_27)
node decoded_orMatrixOutputs_hi_79 = cat(decoded_orMatrixOutputs_hi_hi_72, decoded_orMatrixOutputs_hi_lo_55)
node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_79, decoded_orMatrixOutputs_lo_73)
node _decoded_invMatrixOutputs_T_80 = bits(decoded_orMatrixOutputs_2, 0, 0)
node _decoded_invMatrixOutputs_T_81 = bits(decoded_orMatrixOutputs_2, 1, 1)
node _decoded_invMatrixOutputs_T_82 = bits(decoded_orMatrixOutputs_2, 2, 2)
node _decoded_invMatrixOutputs_T_83 = bits(decoded_orMatrixOutputs_2, 3, 3)
node _decoded_invMatrixOutputs_T_84 = bits(decoded_orMatrixOutputs_2, 4, 4)
node _decoded_invMatrixOutputs_T_85 = bits(decoded_orMatrixOutputs_2, 5, 5)
node _decoded_invMatrixOutputs_T_86 = bits(decoded_orMatrixOutputs_2, 6, 6)
node _decoded_invMatrixOutputs_T_87 = bits(decoded_orMatrixOutputs_2, 7, 7)
node _decoded_invMatrixOutputs_T_88 = bits(decoded_orMatrixOutputs_2, 8, 8)
node _decoded_invMatrixOutputs_T_89 = bits(decoded_orMatrixOutputs_2, 9, 9)
node _decoded_invMatrixOutputs_T_90 = bits(decoded_orMatrixOutputs_2, 10, 10)
node _decoded_invMatrixOutputs_T_91 = bits(decoded_orMatrixOutputs_2, 11, 11)
node _decoded_invMatrixOutputs_T_92 = bits(decoded_orMatrixOutputs_2, 12, 12)
node _decoded_invMatrixOutputs_T_93 = bits(decoded_orMatrixOutputs_2, 13, 13)
node _decoded_invMatrixOutputs_T_94 = bits(decoded_orMatrixOutputs_2, 14, 14)
node _decoded_invMatrixOutputs_T_95 = bits(decoded_orMatrixOutputs_2, 15, 15)
node _decoded_invMatrixOutputs_T_96 = bits(decoded_orMatrixOutputs_2, 16, 16)
node _decoded_invMatrixOutputs_T_97 = bits(decoded_orMatrixOutputs_2, 17, 17)
node _decoded_invMatrixOutputs_T_98 = bits(decoded_orMatrixOutputs_2, 18, 18)
node _decoded_invMatrixOutputs_T_99 = bits(decoded_orMatrixOutputs_2, 19, 19)
node _decoded_invMatrixOutputs_T_100 = bits(decoded_orMatrixOutputs_2, 20, 20)
node _decoded_invMatrixOutputs_T_101 = bits(decoded_orMatrixOutputs_2, 21, 21)
node _decoded_invMatrixOutputs_T_102 = bits(decoded_orMatrixOutputs_2, 22, 22)
node _decoded_invMatrixOutputs_T_103 = bits(decoded_orMatrixOutputs_2, 23, 23)
node _decoded_invMatrixOutputs_T_104 = bits(decoded_orMatrixOutputs_2, 24, 24)
node _decoded_invMatrixOutputs_T_105 = bits(decoded_orMatrixOutputs_2, 25, 25)
node _decoded_invMatrixOutputs_T_106 = bits(decoded_orMatrixOutputs_2, 26, 26)
node _decoded_invMatrixOutputs_T_107 = bits(decoded_orMatrixOutputs_2, 27, 27)
node _decoded_invMatrixOutputs_T_108 = bits(decoded_orMatrixOutputs_2, 28, 28)
node _decoded_invMatrixOutputs_T_109 = bits(decoded_orMatrixOutputs_2, 29, 29)
node _decoded_invMatrixOutputs_T_110 = bits(decoded_orMatrixOutputs_2, 30, 30)
node _decoded_invMatrixOutputs_T_111 = bits(decoded_orMatrixOutputs_2, 31, 31)
node _decoded_invMatrixOutputs_T_112 = bits(decoded_orMatrixOutputs_2, 32, 32)
node _decoded_invMatrixOutputs_T_113 = bits(decoded_orMatrixOutputs_2, 33, 33)
node _decoded_invMatrixOutputs_T_114 = bits(decoded_orMatrixOutputs_2, 34, 34)
node _decoded_invMatrixOutputs_T_115 = bits(decoded_orMatrixOutputs_2, 35, 35)
node _decoded_invMatrixOutputs_T_116 = bits(decoded_orMatrixOutputs_2, 36, 36)
node _decoded_invMatrixOutputs_T_117 = bits(decoded_orMatrixOutputs_2, 37, 37)
node _decoded_invMatrixOutputs_T_118 = bits(decoded_orMatrixOutputs_2, 38, 38)
node _decoded_invMatrixOutputs_T_119 = bits(decoded_orMatrixOutputs_2, 39, 39)
node decoded_invMatrixOutputs_lo_lo_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_81, _decoded_invMatrixOutputs_T_80)
node decoded_invMatrixOutputs_lo_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_84, _decoded_invMatrixOutputs_T_83)
node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_hi_2, _decoded_invMatrixOutputs_T_82)
node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_lo_2)
node decoded_invMatrixOutputs_lo_lo_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_86, _decoded_invMatrixOutputs_T_85)
node decoded_invMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_89, _decoded_invMatrixOutputs_T_88)
node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_hi_2, _decoded_invMatrixOutputs_T_87)
node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, decoded_invMatrixOutputs_lo_lo_hi_lo_2)
node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2)
node decoded_invMatrixOutputs_lo_hi_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_91, _decoded_invMatrixOutputs_T_90)
node decoded_invMatrixOutputs_lo_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_94, _decoded_invMatrixOutputs_T_93)
node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_hi_2, _decoded_invMatrixOutputs_T_92)
node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, decoded_invMatrixOutputs_lo_hi_lo_lo_2)
node decoded_invMatrixOutputs_lo_hi_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_96, _decoded_invMatrixOutputs_T_95)
node decoded_invMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_99, _decoded_invMatrixOutputs_T_98)
node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_hi_2, _decoded_invMatrixOutputs_T_97)
node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, decoded_invMatrixOutputs_lo_hi_hi_lo_2)
node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2)
node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2)
node decoded_invMatrixOutputs_hi_lo_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_101, _decoded_invMatrixOutputs_T_100)
node decoded_invMatrixOutputs_hi_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_104, _decoded_invMatrixOutputs_T_103)
node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_hi_2, _decoded_invMatrixOutputs_T_102)
node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_lo_2)
node decoded_invMatrixOutputs_hi_lo_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_106, _decoded_invMatrixOutputs_T_105)
node decoded_invMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_109, _decoded_invMatrixOutputs_T_108)
node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_hi_2, _decoded_invMatrixOutputs_T_107)
node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, decoded_invMatrixOutputs_hi_lo_hi_lo_2)
node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2)
node decoded_invMatrixOutputs_hi_hi_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_111, _decoded_invMatrixOutputs_T_110)
node decoded_invMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_114, _decoded_invMatrixOutputs_T_113)
node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_hi_2, _decoded_invMatrixOutputs_T_112)
node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, decoded_invMatrixOutputs_hi_hi_lo_lo_2)
node decoded_invMatrixOutputs_hi_hi_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_116, _decoded_invMatrixOutputs_T_115)
node decoded_invMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_119, _decoded_invMatrixOutputs_T_118)
node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_hi_2, _decoded_invMatrixOutputs_T_117)
node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_hi_lo_2)
node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2)
node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2)
node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2)
connect decoded_plaOutput_2, decoded_invMatrixOutputs_2
connect decoded_plaInput_2, addr_2
node _decoded_T_160 = bits(decoded_plaOutput_2, 31, 0)
node _decoded_T_161 = shl(UInt<16>(0hffff), 16)
node _decoded_T_162 = xor(UInt<32>(0hffffffff), _decoded_T_161)
node _decoded_T_163 = shr(_decoded_T_160, 16)
node _decoded_T_164 = and(_decoded_T_163, _decoded_T_162)
node _decoded_T_165 = bits(_decoded_T_160, 15, 0)
node _decoded_T_166 = shl(_decoded_T_165, 16)
node _decoded_T_167 = not(_decoded_T_162)
node _decoded_T_168 = and(_decoded_T_166, _decoded_T_167)
node _decoded_T_169 = or(_decoded_T_164, _decoded_T_168)
node _decoded_T_170 = bits(_decoded_T_162, 23, 0)
node _decoded_T_171 = shl(_decoded_T_170, 8)
node _decoded_T_172 = xor(_decoded_T_162, _decoded_T_171)
node _decoded_T_173 = shr(_decoded_T_169, 8)
node _decoded_T_174 = and(_decoded_T_173, _decoded_T_172)
node _decoded_T_175 = bits(_decoded_T_169, 23, 0)
node _decoded_T_176 = shl(_decoded_T_175, 8)
node _decoded_T_177 = not(_decoded_T_172)
node _decoded_T_178 = and(_decoded_T_176, _decoded_T_177)
node _decoded_T_179 = or(_decoded_T_174, _decoded_T_178)
node _decoded_T_180 = bits(_decoded_T_172, 27, 0)
node _decoded_T_181 = shl(_decoded_T_180, 4)
node _decoded_T_182 = xor(_decoded_T_172, _decoded_T_181)
node _decoded_T_183 = shr(_decoded_T_179, 4)
node _decoded_T_184 = and(_decoded_T_183, _decoded_T_182)
node _decoded_T_185 = bits(_decoded_T_179, 27, 0)
node _decoded_T_186 = shl(_decoded_T_185, 4)
node _decoded_T_187 = not(_decoded_T_182)
node _decoded_T_188 = and(_decoded_T_186, _decoded_T_187)
node _decoded_T_189 = or(_decoded_T_184, _decoded_T_188)
node _decoded_T_190 = bits(_decoded_T_182, 29, 0)
node _decoded_T_191 = shl(_decoded_T_190, 2)
node _decoded_T_192 = xor(_decoded_T_182, _decoded_T_191)
node _decoded_T_193 = shr(_decoded_T_189, 2)
node _decoded_T_194 = and(_decoded_T_193, _decoded_T_192)
node _decoded_T_195 = bits(_decoded_T_189, 29, 0)
node _decoded_T_196 = shl(_decoded_T_195, 2)
node _decoded_T_197 = not(_decoded_T_192)
node _decoded_T_198 = and(_decoded_T_196, _decoded_T_197)
node _decoded_T_199 = or(_decoded_T_194, _decoded_T_198)
node _decoded_T_200 = bits(_decoded_T_192, 30, 0)
node _decoded_T_201 = shl(_decoded_T_200, 1)
node _decoded_T_202 = xor(_decoded_T_192, _decoded_T_201)
node _decoded_T_203 = shr(_decoded_T_199, 1)
node _decoded_T_204 = and(_decoded_T_203, _decoded_T_202)
node _decoded_T_205 = bits(_decoded_T_199, 30, 0)
node _decoded_T_206 = shl(_decoded_T_205, 1)
node _decoded_T_207 = not(_decoded_T_202)
node _decoded_T_208 = and(_decoded_T_206, _decoded_T_207)
node _decoded_T_209 = or(_decoded_T_204, _decoded_T_208)
node _decoded_T_210 = bits(decoded_plaOutput_2, 39, 32)
node _decoded_T_211 = shl(UInt<4>(0hf), 4)
node _decoded_T_212 = xor(UInt<8>(0hff), _decoded_T_211)
node _decoded_T_213 = shr(_decoded_T_210, 4)
node _decoded_T_214 = and(_decoded_T_213, _decoded_T_212)
node _decoded_T_215 = bits(_decoded_T_210, 3, 0)
node _decoded_T_216 = shl(_decoded_T_215, 4)
node _decoded_T_217 = not(_decoded_T_212)
node _decoded_T_218 = and(_decoded_T_216, _decoded_T_217)
node _decoded_T_219 = or(_decoded_T_214, _decoded_T_218)
node _decoded_T_220 = bits(_decoded_T_212, 5, 0)
node _decoded_T_221 = shl(_decoded_T_220, 2)
node _decoded_T_222 = xor(_decoded_T_212, _decoded_T_221)
node _decoded_T_223 = shr(_decoded_T_219, 2)
node _decoded_T_224 = and(_decoded_T_223, _decoded_T_222)
node _decoded_T_225 = bits(_decoded_T_219, 5, 0)
node _decoded_T_226 = shl(_decoded_T_225, 2)
node _decoded_T_227 = not(_decoded_T_222)
node _decoded_T_228 = and(_decoded_T_226, _decoded_T_227)
node _decoded_T_229 = or(_decoded_T_224, _decoded_T_228)
node _decoded_T_230 = bits(_decoded_T_222, 6, 0)
node _decoded_T_231 = shl(_decoded_T_230, 1)
node _decoded_T_232 = xor(_decoded_T_222, _decoded_T_231)
node _decoded_T_233 = shr(_decoded_T_229, 1)
node _decoded_T_234 = and(_decoded_T_233, _decoded_T_232)
node _decoded_T_235 = bits(_decoded_T_229, 6, 0)
node _decoded_T_236 = shl(_decoded_T_235, 1)
node _decoded_T_237 = not(_decoded_T_232)
node _decoded_T_238 = and(_decoded_T_236, _decoded_T_237)
node _decoded_T_239 = or(_decoded_T_234, _decoded_T_238)
node decoded_2 = cat(_decoded_T_209, _decoded_T_239)
node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0)
connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T
node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1)
connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T
node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2)
connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T
node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3)
connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T
node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4)
connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T
node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5)
connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T
node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6)
connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T
node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7)
connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T
node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 8, 8)
connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T
node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 9, 9)
connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T
node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 10, 10)
connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T
node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 11, 11)
connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T
node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 12, 12)
connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T
node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 13, 13)
connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T
node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 14, 14)
connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T
node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 15, 15)
connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T
node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 16, 16)
connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T
node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 17, 17)
connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T
node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 18, 18)
connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T
node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 19, 19)
connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T
node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 20, 20)
connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T
node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 21, 21)
connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T
node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 22, 22)
connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T
node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 23, 23)
connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T
node _io_resp_2_vc_sel_3_0_T = bits(decoded_2, 24, 24)
connect io.resp.`2`.vc_sel.`3`[0], _io_resp_2_vc_sel_3_0_T
node _io_resp_2_vc_sel_3_1_T = bits(decoded_2, 25, 25)
connect io.resp.`2`.vc_sel.`3`[1], _io_resp_2_vc_sel_3_1_T
node _io_resp_2_vc_sel_3_2_T = bits(decoded_2, 26, 26)
connect io.resp.`2`.vc_sel.`3`[2], _io_resp_2_vc_sel_3_2_T
node _io_resp_2_vc_sel_3_3_T = bits(decoded_2, 27, 27)
connect io.resp.`2`.vc_sel.`3`[3], _io_resp_2_vc_sel_3_3_T
node _io_resp_2_vc_sel_3_4_T = bits(decoded_2, 28, 28)
connect io.resp.`2`.vc_sel.`3`[4], _io_resp_2_vc_sel_3_4_T
node _io_resp_2_vc_sel_3_5_T = bits(decoded_2, 29, 29)
connect io.resp.`2`.vc_sel.`3`[5], _io_resp_2_vc_sel_3_5_T
node _io_resp_2_vc_sel_3_6_T = bits(decoded_2, 30, 30)
connect io.resp.`2`.vc_sel.`3`[6], _io_resp_2_vc_sel_3_6_T
node _io_resp_2_vc_sel_3_7_T = bits(decoded_2, 31, 31)
connect io.resp.`2`.vc_sel.`3`[7], _io_resp_2_vc_sel_3_7_T
node _io_resp_2_vc_sel_4_0_T = bits(decoded_2, 32, 32)
connect io.resp.`2`.vc_sel.`4`[0], _io_resp_2_vc_sel_4_0_T
node _io_resp_2_vc_sel_4_1_T = bits(decoded_2, 33, 33)
connect io.resp.`2`.vc_sel.`4`[1], _io_resp_2_vc_sel_4_1_T
node _io_resp_2_vc_sel_4_2_T = bits(decoded_2, 34, 34)
connect io.resp.`2`.vc_sel.`4`[2], _io_resp_2_vc_sel_4_2_T
node _io_resp_2_vc_sel_4_3_T = bits(decoded_2, 35, 35)
connect io.resp.`2`.vc_sel.`4`[3], _io_resp_2_vc_sel_4_3_T
node _io_resp_2_vc_sel_4_4_T = bits(decoded_2, 36, 36)
connect io.resp.`2`.vc_sel.`4`[4], _io_resp_2_vc_sel_4_4_T
node _io_resp_2_vc_sel_4_5_T = bits(decoded_2, 37, 37)
connect io.resp.`2`.vc_sel.`4`[5], _io_resp_2_vc_sel_4_5_T
node _io_resp_2_vc_sel_4_6_T = bits(decoded_2, 38, 38)
connect io.resp.`2`.vc_sel.`4`[6], _io_resp_2_vc_sel_4_6_T
node _io_resp_2_vc_sel_4_7_T = bits(decoded_2, 39, 39)
connect io.resp.`2`.vc_sel.`4`[7], _io_resp_2_vc_sel_4_7_T
connect io.req.`3`.ready, UInt<1>(0h1)
node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id)
node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node)
node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id)
node _addr_T_3 = cat(addr_hi_3, addr_lo_3)
node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3)
wire decoded_plaInput_3 : UInt<20>
node decoded_invInputs_3 = not(decoded_plaInput_3)
wire decoded_plaOutput_3 : UInt<40>
node decoded_andMatrixOutputs_andMatrixInput_0_175 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_175 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_175 = bits(decoded_plaInput_3, 2, 2)
node decoded_andMatrixOutputs_hi_175 = cat(decoded_andMatrixOutputs_andMatrixInput_0_175, decoded_andMatrixOutputs_andMatrixInput_1_175)
node _decoded_andMatrixOutputs_T_175 = cat(decoded_andMatrixOutputs_hi_175, decoded_andMatrixOutputs_andMatrixInput_2_175)
node decoded_andMatrixOutputs_26_2_3 = andr(_decoded_andMatrixOutputs_T_175)
node decoded_andMatrixOutputs_andMatrixInput_0_176 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_176 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_176 = bits(decoded_invInputs_3, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_174 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_174 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_174 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_174 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_174 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_174 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_171 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_171 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_171 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_171 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_171 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_171 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_171 = cat(decoded_andMatrixOutputs_andMatrixInput_12_171, decoded_andMatrixOutputs_andMatrixInput_13_171)
node decoded_andMatrixOutputs_lo_lo_174 = cat(decoded_andMatrixOutputs_lo_lo_hi_171, decoded_andMatrixOutputs_andMatrixInput_14_171)
node decoded_andMatrixOutputs_lo_hi_lo_171 = cat(decoded_andMatrixOutputs_andMatrixInput_10_171, decoded_andMatrixOutputs_andMatrixInput_11_171)
node decoded_andMatrixOutputs_lo_hi_hi_171 = cat(decoded_andMatrixOutputs_andMatrixInput_8_174, decoded_andMatrixOutputs_andMatrixInput_9_171)
node decoded_andMatrixOutputs_lo_hi_174 = cat(decoded_andMatrixOutputs_lo_hi_hi_171, decoded_andMatrixOutputs_lo_hi_lo_171)
node decoded_andMatrixOutputs_lo_174 = cat(decoded_andMatrixOutputs_lo_hi_174, decoded_andMatrixOutputs_lo_lo_174)
node decoded_andMatrixOutputs_hi_lo_lo_171 = cat(decoded_andMatrixOutputs_andMatrixInput_6_174, decoded_andMatrixOutputs_andMatrixInput_7_174)
node decoded_andMatrixOutputs_hi_lo_hi_171 = cat(decoded_andMatrixOutputs_andMatrixInput_4_174, decoded_andMatrixOutputs_andMatrixInput_5_174)
node decoded_andMatrixOutputs_hi_lo_174 = cat(decoded_andMatrixOutputs_hi_lo_hi_171, decoded_andMatrixOutputs_hi_lo_lo_171)
node decoded_andMatrixOutputs_hi_hi_lo_171 = cat(decoded_andMatrixOutputs_andMatrixInput_2_176, decoded_andMatrixOutputs_andMatrixInput_3_174)
node decoded_andMatrixOutputs_hi_hi_hi_174 = cat(decoded_andMatrixOutputs_andMatrixInput_0_176, decoded_andMatrixOutputs_andMatrixInput_1_176)
node decoded_andMatrixOutputs_hi_hi_174 = cat(decoded_andMatrixOutputs_hi_hi_hi_174, decoded_andMatrixOutputs_hi_hi_lo_171)
node decoded_andMatrixOutputs_hi_176 = cat(decoded_andMatrixOutputs_hi_hi_174, decoded_andMatrixOutputs_hi_lo_174)
node _decoded_andMatrixOutputs_T_176 = cat(decoded_andMatrixOutputs_hi_176, decoded_andMatrixOutputs_lo_174)
node decoded_andMatrixOutputs_13_2_3 = andr(_decoded_andMatrixOutputs_T_176)
node decoded_andMatrixOutputs_andMatrixInput_0_177 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_177 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_177 = bits(decoded_invInputs_3, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_175 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_175 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_175 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_175 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_175 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_175 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_172 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_172 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_172 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_172 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_172 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_172 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_lo_lo_hi_172 = cat(decoded_andMatrixOutputs_andMatrixInput_12_172, decoded_andMatrixOutputs_andMatrixInput_13_172)
node decoded_andMatrixOutputs_lo_lo_175 = cat(decoded_andMatrixOutputs_lo_lo_hi_172, decoded_andMatrixOutputs_andMatrixInput_14_172)
node decoded_andMatrixOutputs_lo_hi_lo_172 = cat(decoded_andMatrixOutputs_andMatrixInput_10_172, decoded_andMatrixOutputs_andMatrixInput_11_172)
node decoded_andMatrixOutputs_lo_hi_hi_172 = cat(decoded_andMatrixOutputs_andMatrixInput_8_175, decoded_andMatrixOutputs_andMatrixInput_9_172)
node decoded_andMatrixOutputs_lo_hi_175 = cat(decoded_andMatrixOutputs_lo_hi_hi_172, decoded_andMatrixOutputs_lo_hi_lo_172)
node decoded_andMatrixOutputs_lo_175 = cat(decoded_andMatrixOutputs_lo_hi_175, decoded_andMatrixOutputs_lo_lo_175)
node decoded_andMatrixOutputs_hi_lo_lo_172 = cat(decoded_andMatrixOutputs_andMatrixInput_6_175, decoded_andMatrixOutputs_andMatrixInput_7_175)
node decoded_andMatrixOutputs_hi_lo_hi_172 = cat(decoded_andMatrixOutputs_andMatrixInput_4_175, decoded_andMatrixOutputs_andMatrixInput_5_175)
node decoded_andMatrixOutputs_hi_lo_175 = cat(decoded_andMatrixOutputs_hi_lo_hi_172, decoded_andMatrixOutputs_hi_lo_lo_172)
node decoded_andMatrixOutputs_hi_hi_lo_172 = cat(decoded_andMatrixOutputs_andMatrixInput_2_177, decoded_andMatrixOutputs_andMatrixInput_3_175)
node decoded_andMatrixOutputs_hi_hi_hi_175 = cat(decoded_andMatrixOutputs_andMatrixInput_0_177, decoded_andMatrixOutputs_andMatrixInput_1_177)
node decoded_andMatrixOutputs_hi_hi_175 = cat(decoded_andMatrixOutputs_hi_hi_hi_175, decoded_andMatrixOutputs_hi_hi_lo_172)
node decoded_andMatrixOutputs_hi_177 = cat(decoded_andMatrixOutputs_hi_hi_175, decoded_andMatrixOutputs_hi_lo_175)
node _decoded_andMatrixOutputs_T_177 = cat(decoded_andMatrixOutputs_hi_177, decoded_andMatrixOutputs_lo_175)
node decoded_andMatrixOutputs_21_2_3 = andr(_decoded_andMatrixOutputs_T_177)
node decoded_andMatrixOutputs_andMatrixInput_0_178 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_178 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_178 = bits(decoded_invInputs_3, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_176 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_4_176 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_5_176 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_6_176 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_7_176 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_lo_lo_176 = cat(decoded_andMatrixOutputs_andMatrixInput_6_176, decoded_andMatrixOutputs_andMatrixInput_7_176)
node decoded_andMatrixOutputs_lo_hi_176 = cat(decoded_andMatrixOutputs_andMatrixInput_4_176, decoded_andMatrixOutputs_andMatrixInput_5_176)
node decoded_andMatrixOutputs_lo_176 = cat(decoded_andMatrixOutputs_lo_hi_176, decoded_andMatrixOutputs_lo_lo_176)
node decoded_andMatrixOutputs_hi_lo_176 = cat(decoded_andMatrixOutputs_andMatrixInput_2_178, decoded_andMatrixOutputs_andMatrixInput_3_176)
node decoded_andMatrixOutputs_hi_hi_176 = cat(decoded_andMatrixOutputs_andMatrixInput_0_178, decoded_andMatrixOutputs_andMatrixInput_1_178)
node decoded_andMatrixOutputs_hi_178 = cat(decoded_andMatrixOutputs_hi_hi_176, decoded_andMatrixOutputs_hi_lo_176)
node _decoded_andMatrixOutputs_T_178 = cat(decoded_andMatrixOutputs_hi_178, decoded_andMatrixOutputs_lo_176)
node decoded_andMatrixOutputs_46_2_2 = andr(_decoded_andMatrixOutputs_T_178)
node decoded_andMatrixOutputs_andMatrixInput_0_179 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_179 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_179 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_177 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_177 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_177 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_177 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_177 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_176 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_173 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_173 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_173 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_173 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_173 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_173 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_105 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_57 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_105 = cat(decoded_andMatrixOutputs_andMatrixInput_15_105, decoded_andMatrixOutputs_andMatrixInput_16_57)
node decoded_andMatrixOutputs_lo_lo_hi_173 = cat(decoded_andMatrixOutputs_andMatrixInput_13_173, decoded_andMatrixOutputs_andMatrixInput_14_173)
node decoded_andMatrixOutputs_lo_lo_177 = cat(decoded_andMatrixOutputs_lo_lo_hi_173, decoded_andMatrixOutputs_lo_lo_lo_105)
node decoded_andMatrixOutputs_lo_hi_lo_173 = cat(decoded_andMatrixOutputs_andMatrixInput_11_173, decoded_andMatrixOutputs_andMatrixInput_12_173)
node decoded_andMatrixOutputs_lo_hi_hi_173 = cat(decoded_andMatrixOutputs_andMatrixInput_9_173, decoded_andMatrixOutputs_andMatrixInput_10_173)
node decoded_andMatrixOutputs_lo_hi_177 = cat(decoded_andMatrixOutputs_lo_hi_hi_173, decoded_andMatrixOutputs_lo_hi_lo_173)
node decoded_andMatrixOutputs_lo_177 = cat(decoded_andMatrixOutputs_lo_hi_177, decoded_andMatrixOutputs_lo_lo_177)
node decoded_andMatrixOutputs_hi_lo_lo_173 = cat(decoded_andMatrixOutputs_andMatrixInput_7_177, decoded_andMatrixOutputs_andMatrixInput_8_176)
node decoded_andMatrixOutputs_hi_lo_hi_173 = cat(decoded_andMatrixOutputs_andMatrixInput_5_177, decoded_andMatrixOutputs_andMatrixInput_6_177)
node decoded_andMatrixOutputs_hi_lo_177 = cat(decoded_andMatrixOutputs_hi_lo_hi_173, decoded_andMatrixOutputs_hi_lo_lo_173)
node decoded_andMatrixOutputs_hi_hi_lo_173 = cat(decoded_andMatrixOutputs_andMatrixInput_3_177, decoded_andMatrixOutputs_andMatrixInput_4_177)
node decoded_andMatrixOutputs_hi_hi_hi_hi_57 = cat(decoded_andMatrixOutputs_andMatrixInput_0_179, decoded_andMatrixOutputs_andMatrixInput_1_179)
node decoded_andMatrixOutputs_hi_hi_hi_176 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_57, decoded_andMatrixOutputs_andMatrixInput_2_179)
node decoded_andMatrixOutputs_hi_hi_177 = cat(decoded_andMatrixOutputs_hi_hi_hi_176, decoded_andMatrixOutputs_hi_hi_lo_173)
node decoded_andMatrixOutputs_hi_179 = cat(decoded_andMatrixOutputs_hi_hi_177, decoded_andMatrixOutputs_hi_lo_177)
node _decoded_andMatrixOutputs_T_179 = cat(decoded_andMatrixOutputs_hi_179, decoded_andMatrixOutputs_lo_177)
node decoded_andMatrixOutputs_20_2_3 = andr(_decoded_andMatrixOutputs_T_179)
node decoded_andMatrixOutputs_andMatrixInput_0_180 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_180 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_180 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_178 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_178 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_178 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_178 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_178 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_177 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_174 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_174 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_174 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_174 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_174 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_174 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_174 = cat(decoded_andMatrixOutputs_andMatrixInput_12_174, decoded_andMatrixOutputs_andMatrixInput_13_174)
node decoded_andMatrixOutputs_lo_lo_178 = cat(decoded_andMatrixOutputs_lo_lo_hi_174, decoded_andMatrixOutputs_andMatrixInput_14_174)
node decoded_andMatrixOutputs_lo_hi_lo_174 = cat(decoded_andMatrixOutputs_andMatrixInput_10_174, decoded_andMatrixOutputs_andMatrixInput_11_174)
node decoded_andMatrixOutputs_lo_hi_hi_174 = cat(decoded_andMatrixOutputs_andMatrixInput_8_177, decoded_andMatrixOutputs_andMatrixInput_9_174)
node decoded_andMatrixOutputs_lo_hi_178 = cat(decoded_andMatrixOutputs_lo_hi_hi_174, decoded_andMatrixOutputs_lo_hi_lo_174)
node decoded_andMatrixOutputs_lo_178 = cat(decoded_andMatrixOutputs_lo_hi_178, decoded_andMatrixOutputs_lo_lo_178)
node decoded_andMatrixOutputs_hi_lo_lo_174 = cat(decoded_andMatrixOutputs_andMatrixInput_6_178, decoded_andMatrixOutputs_andMatrixInput_7_178)
node decoded_andMatrixOutputs_hi_lo_hi_174 = cat(decoded_andMatrixOutputs_andMatrixInput_4_178, decoded_andMatrixOutputs_andMatrixInput_5_178)
node decoded_andMatrixOutputs_hi_lo_178 = cat(decoded_andMatrixOutputs_hi_lo_hi_174, decoded_andMatrixOutputs_hi_lo_lo_174)
node decoded_andMatrixOutputs_hi_hi_lo_174 = cat(decoded_andMatrixOutputs_andMatrixInput_2_180, decoded_andMatrixOutputs_andMatrixInput_3_178)
node decoded_andMatrixOutputs_hi_hi_hi_177 = cat(decoded_andMatrixOutputs_andMatrixInput_0_180, decoded_andMatrixOutputs_andMatrixInput_1_180)
node decoded_andMatrixOutputs_hi_hi_178 = cat(decoded_andMatrixOutputs_hi_hi_hi_177, decoded_andMatrixOutputs_hi_hi_lo_174)
node decoded_andMatrixOutputs_hi_180 = cat(decoded_andMatrixOutputs_hi_hi_178, decoded_andMatrixOutputs_hi_lo_178)
node _decoded_andMatrixOutputs_T_180 = cat(decoded_andMatrixOutputs_hi_180, decoded_andMatrixOutputs_lo_178)
node decoded_andMatrixOutputs_30_2_3 = andr(_decoded_andMatrixOutputs_T_180)
node decoded_andMatrixOutputs_andMatrixInput_0_181 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_181 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_181 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_179 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_179 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_179 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_179 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_179 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_178 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_175 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_175 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_175 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_175 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_175 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_175 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_106 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_58 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_106 = cat(decoded_andMatrixOutputs_andMatrixInput_15_106, decoded_andMatrixOutputs_andMatrixInput_16_58)
node decoded_andMatrixOutputs_lo_lo_hi_175 = cat(decoded_andMatrixOutputs_andMatrixInput_13_175, decoded_andMatrixOutputs_andMatrixInput_14_175)
node decoded_andMatrixOutputs_lo_lo_179 = cat(decoded_andMatrixOutputs_lo_lo_hi_175, decoded_andMatrixOutputs_lo_lo_lo_106)
node decoded_andMatrixOutputs_lo_hi_lo_175 = cat(decoded_andMatrixOutputs_andMatrixInput_11_175, decoded_andMatrixOutputs_andMatrixInput_12_175)
node decoded_andMatrixOutputs_lo_hi_hi_175 = cat(decoded_andMatrixOutputs_andMatrixInput_9_175, decoded_andMatrixOutputs_andMatrixInput_10_175)
node decoded_andMatrixOutputs_lo_hi_179 = cat(decoded_andMatrixOutputs_lo_hi_hi_175, decoded_andMatrixOutputs_lo_hi_lo_175)
node decoded_andMatrixOutputs_lo_179 = cat(decoded_andMatrixOutputs_lo_hi_179, decoded_andMatrixOutputs_lo_lo_179)
node decoded_andMatrixOutputs_hi_lo_lo_175 = cat(decoded_andMatrixOutputs_andMatrixInput_7_179, decoded_andMatrixOutputs_andMatrixInput_8_178)
node decoded_andMatrixOutputs_hi_lo_hi_175 = cat(decoded_andMatrixOutputs_andMatrixInput_5_179, decoded_andMatrixOutputs_andMatrixInput_6_179)
node decoded_andMatrixOutputs_hi_lo_179 = cat(decoded_andMatrixOutputs_hi_lo_hi_175, decoded_andMatrixOutputs_hi_lo_lo_175)
node decoded_andMatrixOutputs_hi_hi_lo_175 = cat(decoded_andMatrixOutputs_andMatrixInput_3_179, decoded_andMatrixOutputs_andMatrixInput_4_179)
node decoded_andMatrixOutputs_hi_hi_hi_hi_58 = cat(decoded_andMatrixOutputs_andMatrixInput_0_181, decoded_andMatrixOutputs_andMatrixInput_1_181)
node decoded_andMatrixOutputs_hi_hi_hi_178 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_58, decoded_andMatrixOutputs_andMatrixInput_2_181)
node decoded_andMatrixOutputs_hi_hi_179 = cat(decoded_andMatrixOutputs_hi_hi_hi_178, decoded_andMatrixOutputs_hi_hi_lo_175)
node decoded_andMatrixOutputs_hi_181 = cat(decoded_andMatrixOutputs_hi_hi_179, decoded_andMatrixOutputs_hi_lo_179)
node _decoded_andMatrixOutputs_T_181 = cat(decoded_andMatrixOutputs_hi_181, decoded_andMatrixOutputs_lo_179)
node decoded_andMatrixOutputs_15_2_3 = andr(_decoded_andMatrixOutputs_T_181)
node decoded_andMatrixOutputs_andMatrixInput_0_182 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_182 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_182 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_180 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_180 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_180 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_180 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_180 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_179 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_176 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_176 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_176 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_176 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_176 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_176 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_107 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_59 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_107 = cat(decoded_andMatrixOutputs_andMatrixInput_15_107, decoded_andMatrixOutputs_andMatrixInput_16_59)
node decoded_andMatrixOutputs_lo_lo_hi_176 = cat(decoded_andMatrixOutputs_andMatrixInput_13_176, decoded_andMatrixOutputs_andMatrixInput_14_176)
node decoded_andMatrixOutputs_lo_lo_180 = cat(decoded_andMatrixOutputs_lo_lo_hi_176, decoded_andMatrixOutputs_lo_lo_lo_107)
node decoded_andMatrixOutputs_lo_hi_lo_176 = cat(decoded_andMatrixOutputs_andMatrixInput_11_176, decoded_andMatrixOutputs_andMatrixInput_12_176)
node decoded_andMatrixOutputs_lo_hi_hi_176 = cat(decoded_andMatrixOutputs_andMatrixInput_9_176, decoded_andMatrixOutputs_andMatrixInput_10_176)
node decoded_andMatrixOutputs_lo_hi_180 = cat(decoded_andMatrixOutputs_lo_hi_hi_176, decoded_andMatrixOutputs_lo_hi_lo_176)
node decoded_andMatrixOutputs_lo_180 = cat(decoded_andMatrixOutputs_lo_hi_180, decoded_andMatrixOutputs_lo_lo_180)
node decoded_andMatrixOutputs_hi_lo_lo_176 = cat(decoded_andMatrixOutputs_andMatrixInput_7_180, decoded_andMatrixOutputs_andMatrixInput_8_179)
node decoded_andMatrixOutputs_hi_lo_hi_176 = cat(decoded_andMatrixOutputs_andMatrixInput_5_180, decoded_andMatrixOutputs_andMatrixInput_6_180)
node decoded_andMatrixOutputs_hi_lo_180 = cat(decoded_andMatrixOutputs_hi_lo_hi_176, decoded_andMatrixOutputs_hi_lo_lo_176)
node decoded_andMatrixOutputs_hi_hi_lo_176 = cat(decoded_andMatrixOutputs_andMatrixInput_3_180, decoded_andMatrixOutputs_andMatrixInput_4_180)
node decoded_andMatrixOutputs_hi_hi_hi_hi_59 = cat(decoded_andMatrixOutputs_andMatrixInput_0_182, decoded_andMatrixOutputs_andMatrixInput_1_182)
node decoded_andMatrixOutputs_hi_hi_hi_179 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_59, decoded_andMatrixOutputs_andMatrixInput_2_182)
node decoded_andMatrixOutputs_hi_hi_180 = cat(decoded_andMatrixOutputs_hi_hi_hi_179, decoded_andMatrixOutputs_hi_hi_lo_176)
node decoded_andMatrixOutputs_hi_182 = cat(decoded_andMatrixOutputs_hi_hi_180, decoded_andMatrixOutputs_hi_lo_180)
node _decoded_andMatrixOutputs_T_182 = cat(decoded_andMatrixOutputs_hi_182, decoded_andMatrixOutputs_lo_180)
node decoded_andMatrixOutputs_35_2_3 = andr(_decoded_andMatrixOutputs_T_182)
node decoded_andMatrixOutputs_andMatrixInput_0_183 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_183 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_183 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_181 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_181 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_181 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_181 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_181 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_180 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_177 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_177 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_177 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_177 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_177 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_177 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_lo_lo_hi_177 = cat(decoded_andMatrixOutputs_andMatrixInput_12_177, decoded_andMatrixOutputs_andMatrixInput_13_177)
node decoded_andMatrixOutputs_lo_lo_181 = cat(decoded_andMatrixOutputs_lo_lo_hi_177, decoded_andMatrixOutputs_andMatrixInput_14_177)
node decoded_andMatrixOutputs_lo_hi_lo_177 = cat(decoded_andMatrixOutputs_andMatrixInput_10_177, decoded_andMatrixOutputs_andMatrixInput_11_177)
node decoded_andMatrixOutputs_lo_hi_hi_177 = cat(decoded_andMatrixOutputs_andMatrixInput_8_180, decoded_andMatrixOutputs_andMatrixInput_9_177)
node decoded_andMatrixOutputs_lo_hi_181 = cat(decoded_andMatrixOutputs_lo_hi_hi_177, decoded_andMatrixOutputs_lo_hi_lo_177)
node decoded_andMatrixOutputs_lo_181 = cat(decoded_andMatrixOutputs_lo_hi_181, decoded_andMatrixOutputs_lo_lo_181)
node decoded_andMatrixOutputs_hi_lo_lo_177 = cat(decoded_andMatrixOutputs_andMatrixInput_6_181, decoded_andMatrixOutputs_andMatrixInput_7_181)
node decoded_andMatrixOutputs_hi_lo_hi_177 = cat(decoded_andMatrixOutputs_andMatrixInput_4_181, decoded_andMatrixOutputs_andMatrixInput_5_181)
node decoded_andMatrixOutputs_hi_lo_181 = cat(decoded_andMatrixOutputs_hi_lo_hi_177, decoded_andMatrixOutputs_hi_lo_lo_177)
node decoded_andMatrixOutputs_hi_hi_lo_177 = cat(decoded_andMatrixOutputs_andMatrixInput_2_183, decoded_andMatrixOutputs_andMatrixInput_3_181)
node decoded_andMatrixOutputs_hi_hi_hi_180 = cat(decoded_andMatrixOutputs_andMatrixInput_0_183, decoded_andMatrixOutputs_andMatrixInput_1_183)
node decoded_andMatrixOutputs_hi_hi_181 = cat(decoded_andMatrixOutputs_hi_hi_hi_180, decoded_andMatrixOutputs_hi_hi_lo_177)
node decoded_andMatrixOutputs_hi_183 = cat(decoded_andMatrixOutputs_hi_hi_181, decoded_andMatrixOutputs_hi_lo_181)
node _decoded_andMatrixOutputs_T_183 = cat(decoded_andMatrixOutputs_hi_183, decoded_andMatrixOutputs_lo_181)
node decoded_andMatrixOutputs_12_2_3 = andr(_decoded_andMatrixOutputs_T_183)
node decoded_andMatrixOutputs_andMatrixInput_0_184 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_184 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_184 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_182 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_182 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_182 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_182 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_182 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_181 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_178 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_178 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_178 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_178 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_178 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_178 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_108 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_60 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_108 = cat(decoded_andMatrixOutputs_andMatrixInput_15_108, decoded_andMatrixOutputs_andMatrixInput_16_60)
node decoded_andMatrixOutputs_lo_lo_hi_178 = cat(decoded_andMatrixOutputs_andMatrixInput_13_178, decoded_andMatrixOutputs_andMatrixInput_14_178)
node decoded_andMatrixOutputs_lo_lo_182 = cat(decoded_andMatrixOutputs_lo_lo_hi_178, decoded_andMatrixOutputs_lo_lo_lo_108)
node decoded_andMatrixOutputs_lo_hi_lo_178 = cat(decoded_andMatrixOutputs_andMatrixInput_11_178, decoded_andMatrixOutputs_andMatrixInput_12_178)
node decoded_andMatrixOutputs_lo_hi_hi_178 = cat(decoded_andMatrixOutputs_andMatrixInput_9_178, decoded_andMatrixOutputs_andMatrixInput_10_178)
node decoded_andMatrixOutputs_lo_hi_182 = cat(decoded_andMatrixOutputs_lo_hi_hi_178, decoded_andMatrixOutputs_lo_hi_lo_178)
node decoded_andMatrixOutputs_lo_182 = cat(decoded_andMatrixOutputs_lo_hi_182, decoded_andMatrixOutputs_lo_lo_182)
node decoded_andMatrixOutputs_hi_lo_lo_178 = cat(decoded_andMatrixOutputs_andMatrixInput_7_182, decoded_andMatrixOutputs_andMatrixInput_8_181)
node decoded_andMatrixOutputs_hi_lo_hi_178 = cat(decoded_andMatrixOutputs_andMatrixInput_5_182, decoded_andMatrixOutputs_andMatrixInput_6_182)
node decoded_andMatrixOutputs_hi_lo_182 = cat(decoded_andMatrixOutputs_hi_lo_hi_178, decoded_andMatrixOutputs_hi_lo_lo_178)
node decoded_andMatrixOutputs_hi_hi_lo_178 = cat(decoded_andMatrixOutputs_andMatrixInput_3_182, decoded_andMatrixOutputs_andMatrixInput_4_182)
node decoded_andMatrixOutputs_hi_hi_hi_hi_60 = cat(decoded_andMatrixOutputs_andMatrixInput_0_184, decoded_andMatrixOutputs_andMatrixInput_1_184)
node decoded_andMatrixOutputs_hi_hi_hi_181 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_60, decoded_andMatrixOutputs_andMatrixInput_2_184)
node decoded_andMatrixOutputs_hi_hi_182 = cat(decoded_andMatrixOutputs_hi_hi_hi_181, decoded_andMatrixOutputs_hi_hi_lo_178)
node decoded_andMatrixOutputs_hi_184 = cat(decoded_andMatrixOutputs_hi_hi_182, decoded_andMatrixOutputs_hi_lo_182)
node _decoded_andMatrixOutputs_T_184 = cat(decoded_andMatrixOutputs_hi_184, decoded_andMatrixOutputs_lo_182)
node decoded_andMatrixOutputs_1_2_3 = andr(_decoded_andMatrixOutputs_T_184)
node decoded_andMatrixOutputs_andMatrixInput_0_185 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_185 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_185 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_183 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_183 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_183 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_183 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_183 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_182 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_179 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_179 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_179 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_179 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_179 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_179 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_109 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_61 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_109 = cat(decoded_andMatrixOutputs_andMatrixInput_15_109, decoded_andMatrixOutputs_andMatrixInput_16_61)
node decoded_andMatrixOutputs_lo_lo_hi_179 = cat(decoded_andMatrixOutputs_andMatrixInput_13_179, decoded_andMatrixOutputs_andMatrixInput_14_179)
node decoded_andMatrixOutputs_lo_lo_183 = cat(decoded_andMatrixOutputs_lo_lo_hi_179, decoded_andMatrixOutputs_lo_lo_lo_109)
node decoded_andMatrixOutputs_lo_hi_lo_179 = cat(decoded_andMatrixOutputs_andMatrixInput_11_179, decoded_andMatrixOutputs_andMatrixInput_12_179)
node decoded_andMatrixOutputs_lo_hi_hi_179 = cat(decoded_andMatrixOutputs_andMatrixInput_9_179, decoded_andMatrixOutputs_andMatrixInput_10_179)
node decoded_andMatrixOutputs_lo_hi_183 = cat(decoded_andMatrixOutputs_lo_hi_hi_179, decoded_andMatrixOutputs_lo_hi_lo_179)
node decoded_andMatrixOutputs_lo_183 = cat(decoded_andMatrixOutputs_lo_hi_183, decoded_andMatrixOutputs_lo_lo_183)
node decoded_andMatrixOutputs_hi_lo_lo_179 = cat(decoded_andMatrixOutputs_andMatrixInput_7_183, decoded_andMatrixOutputs_andMatrixInput_8_182)
node decoded_andMatrixOutputs_hi_lo_hi_179 = cat(decoded_andMatrixOutputs_andMatrixInput_5_183, decoded_andMatrixOutputs_andMatrixInput_6_183)
node decoded_andMatrixOutputs_hi_lo_183 = cat(decoded_andMatrixOutputs_hi_lo_hi_179, decoded_andMatrixOutputs_hi_lo_lo_179)
node decoded_andMatrixOutputs_hi_hi_lo_179 = cat(decoded_andMatrixOutputs_andMatrixInput_3_183, decoded_andMatrixOutputs_andMatrixInput_4_183)
node decoded_andMatrixOutputs_hi_hi_hi_hi_61 = cat(decoded_andMatrixOutputs_andMatrixInput_0_185, decoded_andMatrixOutputs_andMatrixInput_1_185)
node decoded_andMatrixOutputs_hi_hi_hi_182 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_61, decoded_andMatrixOutputs_andMatrixInput_2_185)
node decoded_andMatrixOutputs_hi_hi_183 = cat(decoded_andMatrixOutputs_hi_hi_hi_182, decoded_andMatrixOutputs_hi_hi_lo_179)
node decoded_andMatrixOutputs_hi_185 = cat(decoded_andMatrixOutputs_hi_hi_183, decoded_andMatrixOutputs_hi_lo_183)
node _decoded_andMatrixOutputs_T_185 = cat(decoded_andMatrixOutputs_hi_185, decoded_andMatrixOutputs_lo_183)
node decoded_andMatrixOutputs_22_2_3 = andr(_decoded_andMatrixOutputs_T_185)
node decoded_andMatrixOutputs_andMatrixInput_0_186 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_186 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_186 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_184 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_184 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_184 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_184 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_184 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_183 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_180 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_180 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_180 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_180 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_180 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_180 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_180 = cat(decoded_andMatrixOutputs_andMatrixInput_12_180, decoded_andMatrixOutputs_andMatrixInput_13_180)
node decoded_andMatrixOutputs_lo_lo_184 = cat(decoded_andMatrixOutputs_lo_lo_hi_180, decoded_andMatrixOutputs_andMatrixInput_14_180)
node decoded_andMatrixOutputs_lo_hi_lo_180 = cat(decoded_andMatrixOutputs_andMatrixInput_10_180, decoded_andMatrixOutputs_andMatrixInput_11_180)
node decoded_andMatrixOutputs_lo_hi_hi_180 = cat(decoded_andMatrixOutputs_andMatrixInput_8_183, decoded_andMatrixOutputs_andMatrixInput_9_180)
node decoded_andMatrixOutputs_lo_hi_184 = cat(decoded_andMatrixOutputs_lo_hi_hi_180, decoded_andMatrixOutputs_lo_hi_lo_180)
node decoded_andMatrixOutputs_lo_184 = cat(decoded_andMatrixOutputs_lo_hi_184, decoded_andMatrixOutputs_lo_lo_184)
node decoded_andMatrixOutputs_hi_lo_lo_180 = cat(decoded_andMatrixOutputs_andMatrixInput_6_184, decoded_andMatrixOutputs_andMatrixInput_7_184)
node decoded_andMatrixOutputs_hi_lo_hi_180 = cat(decoded_andMatrixOutputs_andMatrixInput_4_184, decoded_andMatrixOutputs_andMatrixInput_5_184)
node decoded_andMatrixOutputs_hi_lo_184 = cat(decoded_andMatrixOutputs_hi_lo_hi_180, decoded_andMatrixOutputs_hi_lo_lo_180)
node decoded_andMatrixOutputs_hi_hi_lo_180 = cat(decoded_andMatrixOutputs_andMatrixInput_2_186, decoded_andMatrixOutputs_andMatrixInput_3_184)
node decoded_andMatrixOutputs_hi_hi_hi_183 = cat(decoded_andMatrixOutputs_andMatrixInput_0_186, decoded_andMatrixOutputs_andMatrixInput_1_186)
node decoded_andMatrixOutputs_hi_hi_184 = cat(decoded_andMatrixOutputs_hi_hi_hi_183, decoded_andMatrixOutputs_hi_hi_lo_180)
node decoded_andMatrixOutputs_hi_186 = cat(decoded_andMatrixOutputs_hi_hi_184, decoded_andMatrixOutputs_hi_lo_184)
node _decoded_andMatrixOutputs_T_186 = cat(decoded_andMatrixOutputs_hi_186, decoded_andMatrixOutputs_lo_184)
node decoded_andMatrixOutputs_7_2_3 = andr(_decoded_andMatrixOutputs_T_186)
node decoded_andMatrixOutputs_andMatrixInput_0_187 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_187 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_187 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_185 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_185 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_185 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_185 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_185 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_184 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_181 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_181 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_181 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_181 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_181 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_181 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_110 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_62 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_110 = cat(decoded_andMatrixOutputs_andMatrixInput_15_110, decoded_andMatrixOutputs_andMatrixInput_16_62)
node decoded_andMatrixOutputs_lo_lo_hi_181 = cat(decoded_andMatrixOutputs_andMatrixInput_13_181, decoded_andMatrixOutputs_andMatrixInput_14_181)
node decoded_andMatrixOutputs_lo_lo_185 = cat(decoded_andMatrixOutputs_lo_lo_hi_181, decoded_andMatrixOutputs_lo_lo_lo_110)
node decoded_andMatrixOutputs_lo_hi_lo_181 = cat(decoded_andMatrixOutputs_andMatrixInput_11_181, decoded_andMatrixOutputs_andMatrixInput_12_181)
node decoded_andMatrixOutputs_lo_hi_hi_181 = cat(decoded_andMatrixOutputs_andMatrixInput_9_181, decoded_andMatrixOutputs_andMatrixInput_10_181)
node decoded_andMatrixOutputs_lo_hi_185 = cat(decoded_andMatrixOutputs_lo_hi_hi_181, decoded_andMatrixOutputs_lo_hi_lo_181)
node decoded_andMatrixOutputs_lo_185 = cat(decoded_andMatrixOutputs_lo_hi_185, decoded_andMatrixOutputs_lo_lo_185)
node decoded_andMatrixOutputs_hi_lo_lo_181 = cat(decoded_andMatrixOutputs_andMatrixInput_7_185, decoded_andMatrixOutputs_andMatrixInput_8_184)
node decoded_andMatrixOutputs_hi_lo_hi_181 = cat(decoded_andMatrixOutputs_andMatrixInput_5_185, decoded_andMatrixOutputs_andMatrixInput_6_185)
node decoded_andMatrixOutputs_hi_lo_185 = cat(decoded_andMatrixOutputs_hi_lo_hi_181, decoded_andMatrixOutputs_hi_lo_lo_181)
node decoded_andMatrixOutputs_hi_hi_lo_181 = cat(decoded_andMatrixOutputs_andMatrixInput_3_185, decoded_andMatrixOutputs_andMatrixInput_4_185)
node decoded_andMatrixOutputs_hi_hi_hi_hi_62 = cat(decoded_andMatrixOutputs_andMatrixInput_0_187, decoded_andMatrixOutputs_andMatrixInput_1_187)
node decoded_andMatrixOutputs_hi_hi_hi_184 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_62, decoded_andMatrixOutputs_andMatrixInput_2_187)
node decoded_andMatrixOutputs_hi_hi_185 = cat(decoded_andMatrixOutputs_hi_hi_hi_184, decoded_andMatrixOutputs_hi_hi_lo_181)
node decoded_andMatrixOutputs_hi_187 = cat(decoded_andMatrixOutputs_hi_hi_185, decoded_andMatrixOutputs_hi_lo_185)
node _decoded_andMatrixOutputs_T_187 = cat(decoded_andMatrixOutputs_hi_187, decoded_andMatrixOutputs_lo_185)
node decoded_andMatrixOutputs_53_2_2 = andr(_decoded_andMatrixOutputs_T_187)
node decoded_andMatrixOutputs_andMatrixInput_0_188 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_188 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_188 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_186 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_186 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_186 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_186 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_186 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_185 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_182 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_182 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_182 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_182 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_182 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_182 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_111 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_63 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_111 = cat(decoded_andMatrixOutputs_andMatrixInput_15_111, decoded_andMatrixOutputs_andMatrixInput_16_63)
node decoded_andMatrixOutputs_lo_lo_hi_182 = cat(decoded_andMatrixOutputs_andMatrixInput_13_182, decoded_andMatrixOutputs_andMatrixInput_14_182)
node decoded_andMatrixOutputs_lo_lo_186 = cat(decoded_andMatrixOutputs_lo_lo_hi_182, decoded_andMatrixOutputs_lo_lo_lo_111)
node decoded_andMatrixOutputs_lo_hi_lo_182 = cat(decoded_andMatrixOutputs_andMatrixInput_11_182, decoded_andMatrixOutputs_andMatrixInput_12_182)
node decoded_andMatrixOutputs_lo_hi_hi_182 = cat(decoded_andMatrixOutputs_andMatrixInput_9_182, decoded_andMatrixOutputs_andMatrixInput_10_182)
node decoded_andMatrixOutputs_lo_hi_186 = cat(decoded_andMatrixOutputs_lo_hi_hi_182, decoded_andMatrixOutputs_lo_hi_lo_182)
node decoded_andMatrixOutputs_lo_186 = cat(decoded_andMatrixOutputs_lo_hi_186, decoded_andMatrixOutputs_lo_lo_186)
node decoded_andMatrixOutputs_hi_lo_lo_182 = cat(decoded_andMatrixOutputs_andMatrixInput_7_186, decoded_andMatrixOutputs_andMatrixInput_8_185)
node decoded_andMatrixOutputs_hi_lo_hi_182 = cat(decoded_andMatrixOutputs_andMatrixInput_5_186, decoded_andMatrixOutputs_andMatrixInput_6_186)
node decoded_andMatrixOutputs_hi_lo_186 = cat(decoded_andMatrixOutputs_hi_lo_hi_182, decoded_andMatrixOutputs_hi_lo_lo_182)
node decoded_andMatrixOutputs_hi_hi_lo_182 = cat(decoded_andMatrixOutputs_andMatrixInput_3_186, decoded_andMatrixOutputs_andMatrixInput_4_186)
node decoded_andMatrixOutputs_hi_hi_hi_hi_63 = cat(decoded_andMatrixOutputs_andMatrixInput_0_188, decoded_andMatrixOutputs_andMatrixInput_1_188)
node decoded_andMatrixOutputs_hi_hi_hi_185 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_63, decoded_andMatrixOutputs_andMatrixInput_2_188)
node decoded_andMatrixOutputs_hi_hi_186 = cat(decoded_andMatrixOutputs_hi_hi_hi_185, decoded_andMatrixOutputs_hi_hi_lo_182)
node decoded_andMatrixOutputs_hi_188 = cat(decoded_andMatrixOutputs_hi_hi_186, decoded_andMatrixOutputs_hi_lo_186)
node _decoded_andMatrixOutputs_T_188 = cat(decoded_andMatrixOutputs_hi_188, decoded_andMatrixOutputs_lo_186)
node decoded_andMatrixOutputs_5_2_3 = andr(_decoded_andMatrixOutputs_T_188)
node decoded_andMatrixOutputs_andMatrixInput_0_189 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_189 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_189 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_187 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_187 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_187 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_187 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_187 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_186 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_183 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_183 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_183 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_183 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_183 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_183 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_183 = cat(decoded_andMatrixOutputs_andMatrixInput_12_183, decoded_andMatrixOutputs_andMatrixInput_13_183)
node decoded_andMatrixOutputs_lo_lo_187 = cat(decoded_andMatrixOutputs_lo_lo_hi_183, decoded_andMatrixOutputs_andMatrixInput_14_183)
node decoded_andMatrixOutputs_lo_hi_lo_183 = cat(decoded_andMatrixOutputs_andMatrixInput_10_183, decoded_andMatrixOutputs_andMatrixInput_11_183)
node decoded_andMatrixOutputs_lo_hi_hi_183 = cat(decoded_andMatrixOutputs_andMatrixInput_8_186, decoded_andMatrixOutputs_andMatrixInput_9_183)
node decoded_andMatrixOutputs_lo_hi_187 = cat(decoded_andMatrixOutputs_lo_hi_hi_183, decoded_andMatrixOutputs_lo_hi_lo_183)
node decoded_andMatrixOutputs_lo_187 = cat(decoded_andMatrixOutputs_lo_hi_187, decoded_andMatrixOutputs_lo_lo_187)
node decoded_andMatrixOutputs_hi_lo_lo_183 = cat(decoded_andMatrixOutputs_andMatrixInput_6_187, decoded_andMatrixOutputs_andMatrixInput_7_187)
node decoded_andMatrixOutputs_hi_lo_hi_183 = cat(decoded_andMatrixOutputs_andMatrixInput_4_187, decoded_andMatrixOutputs_andMatrixInput_5_187)
node decoded_andMatrixOutputs_hi_lo_187 = cat(decoded_andMatrixOutputs_hi_lo_hi_183, decoded_andMatrixOutputs_hi_lo_lo_183)
node decoded_andMatrixOutputs_hi_hi_lo_183 = cat(decoded_andMatrixOutputs_andMatrixInput_2_189, decoded_andMatrixOutputs_andMatrixInput_3_187)
node decoded_andMatrixOutputs_hi_hi_hi_186 = cat(decoded_andMatrixOutputs_andMatrixInput_0_189, decoded_andMatrixOutputs_andMatrixInput_1_189)
node decoded_andMatrixOutputs_hi_hi_187 = cat(decoded_andMatrixOutputs_hi_hi_hi_186, decoded_andMatrixOutputs_hi_hi_lo_183)
node decoded_andMatrixOutputs_hi_189 = cat(decoded_andMatrixOutputs_hi_hi_187, decoded_andMatrixOutputs_hi_lo_187)
node _decoded_andMatrixOutputs_T_189 = cat(decoded_andMatrixOutputs_hi_189, decoded_andMatrixOutputs_lo_187)
node decoded_andMatrixOutputs_2_2_3 = andr(_decoded_andMatrixOutputs_T_189)
node decoded_andMatrixOutputs_andMatrixInput_0_190 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_190 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_190 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_188 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_188 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_188 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_188 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_188 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_187 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_184 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_184 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_184 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_184 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_184 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_184 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_184 = cat(decoded_andMatrixOutputs_andMatrixInput_12_184, decoded_andMatrixOutputs_andMatrixInput_13_184)
node decoded_andMatrixOutputs_lo_lo_188 = cat(decoded_andMatrixOutputs_lo_lo_hi_184, decoded_andMatrixOutputs_andMatrixInput_14_184)
node decoded_andMatrixOutputs_lo_hi_lo_184 = cat(decoded_andMatrixOutputs_andMatrixInput_10_184, decoded_andMatrixOutputs_andMatrixInput_11_184)
node decoded_andMatrixOutputs_lo_hi_hi_184 = cat(decoded_andMatrixOutputs_andMatrixInput_8_187, decoded_andMatrixOutputs_andMatrixInput_9_184)
node decoded_andMatrixOutputs_lo_hi_188 = cat(decoded_andMatrixOutputs_lo_hi_hi_184, decoded_andMatrixOutputs_lo_hi_lo_184)
node decoded_andMatrixOutputs_lo_188 = cat(decoded_andMatrixOutputs_lo_hi_188, decoded_andMatrixOutputs_lo_lo_188)
node decoded_andMatrixOutputs_hi_lo_lo_184 = cat(decoded_andMatrixOutputs_andMatrixInput_6_188, decoded_andMatrixOutputs_andMatrixInput_7_188)
node decoded_andMatrixOutputs_hi_lo_hi_184 = cat(decoded_andMatrixOutputs_andMatrixInput_4_188, decoded_andMatrixOutputs_andMatrixInput_5_188)
node decoded_andMatrixOutputs_hi_lo_188 = cat(decoded_andMatrixOutputs_hi_lo_hi_184, decoded_andMatrixOutputs_hi_lo_lo_184)
node decoded_andMatrixOutputs_hi_hi_lo_184 = cat(decoded_andMatrixOutputs_andMatrixInput_2_190, decoded_andMatrixOutputs_andMatrixInput_3_188)
node decoded_andMatrixOutputs_hi_hi_hi_187 = cat(decoded_andMatrixOutputs_andMatrixInput_0_190, decoded_andMatrixOutputs_andMatrixInput_1_190)
node decoded_andMatrixOutputs_hi_hi_188 = cat(decoded_andMatrixOutputs_hi_hi_hi_187, decoded_andMatrixOutputs_hi_hi_lo_184)
node decoded_andMatrixOutputs_hi_190 = cat(decoded_andMatrixOutputs_hi_hi_188, decoded_andMatrixOutputs_hi_lo_188)
node _decoded_andMatrixOutputs_T_190 = cat(decoded_andMatrixOutputs_hi_190, decoded_andMatrixOutputs_lo_188)
node decoded_andMatrixOutputs_47_2_2 = andr(_decoded_andMatrixOutputs_T_190)
node decoded_andMatrixOutputs_andMatrixInput_0_191 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_191 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_191 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_189 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_189 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_189 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_189 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_189 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_188 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_185 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_185 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_185 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_185 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_185 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_185 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_112 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_64 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_112 = cat(decoded_andMatrixOutputs_andMatrixInput_15_112, decoded_andMatrixOutputs_andMatrixInput_16_64)
node decoded_andMatrixOutputs_lo_lo_hi_185 = cat(decoded_andMatrixOutputs_andMatrixInput_13_185, decoded_andMatrixOutputs_andMatrixInput_14_185)
node decoded_andMatrixOutputs_lo_lo_189 = cat(decoded_andMatrixOutputs_lo_lo_hi_185, decoded_andMatrixOutputs_lo_lo_lo_112)
node decoded_andMatrixOutputs_lo_hi_lo_185 = cat(decoded_andMatrixOutputs_andMatrixInput_11_185, decoded_andMatrixOutputs_andMatrixInput_12_185)
node decoded_andMatrixOutputs_lo_hi_hi_185 = cat(decoded_andMatrixOutputs_andMatrixInput_9_185, decoded_andMatrixOutputs_andMatrixInput_10_185)
node decoded_andMatrixOutputs_lo_hi_189 = cat(decoded_andMatrixOutputs_lo_hi_hi_185, decoded_andMatrixOutputs_lo_hi_lo_185)
node decoded_andMatrixOutputs_lo_189 = cat(decoded_andMatrixOutputs_lo_hi_189, decoded_andMatrixOutputs_lo_lo_189)
node decoded_andMatrixOutputs_hi_lo_lo_185 = cat(decoded_andMatrixOutputs_andMatrixInput_7_189, decoded_andMatrixOutputs_andMatrixInput_8_188)
node decoded_andMatrixOutputs_hi_lo_hi_185 = cat(decoded_andMatrixOutputs_andMatrixInput_5_189, decoded_andMatrixOutputs_andMatrixInput_6_189)
node decoded_andMatrixOutputs_hi_lo_189 = cat(decoded_andMatrixOutputs_hi_lo_hi_185, decoded_andMatrixOutputs_hi_lo_lo_185)
node decoded_andMatrixOutputs_hi_hi_lo_185 = cat(decoded_andMatrixOutputs_andMatrixInput_3_189, decoded_andMatrixOutputs_andMatrixInput_4_189)
node decoded_andMatrixOutputs_hi_hi_hi_hi_64 = cat(decoded_andMatrixOutputs_andMatrixInput_0_191, decoded_andMatrixOutputs_andMatrixInput_1_191)
node decoded_andMatrixOutputs_hi_hi_hi_188 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_64, decoded_andMatrixOutputs_andMatrixInput_2_191)
node decoded_andMatrixOutputs_hi_hi_189 = cat(decoded_andMatrixOutputs_hi_hi_hi_188, decoded_andMatrixOutputs_hi_hi_lo_185)
node decoded_andMatrixOutputs_hi_191 = cat(decoded_andMatrixOutputs_hi_hi_189, decoded_andMatrixOutputs_hi_lo_189)
node _decoded_andMatrixOutputs_T_191 = cat(decoded_andMatrixOutputs_hi_191, decoded_andMatrixOutputs_lo_189)
node decoded_andMatrixOutputs_51_2_2 = andr(_decoded_andMatrixOutputs_T_191)
node decoded_andMatrixOutputs_andMatrixInput_0_192 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_192 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_192 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_190 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_190 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_190 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_190 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_190 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_189 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_186 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_186 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_186 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_186 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_186 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_186 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_113 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_65 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_113 = cat(decoded_andMatrixOutputs_andMatrixInput_15_113, decoded_andMatrixOutputs_andMatrixInput_16_65)
node decoded_andMatrixOutputs_lo_lo_hi_186 = cat(decoded_andMatrixOutputs_andMatrixInput_13_186, decoded_andMatrixOutputs_andMatrixInput_14_186)
node decoded_andMatrixOutputs_lo_lo_190 = cat(decoded_andMatrixOutputs_lo_lo_hi_186, decoded_andMatrixOutputs_lo_lo_lo_113)
node decoded_andMatrixOutputs_lo_hi_lo_186 = cat(decoded_andMatrixOutputs_andMatrixInput_11_186, decoded_andMatrixOutputs_andMatrixInput_12_186)
node decoded_andMatrixOutputs_lo_hi_hi_186 = cat(decoded_andMatrixOutputs_andMatrixInput_9_186, decoded_andMatrixOutputs_andMatrixInput_10_186)
node decoded_andMatrixOutputs_lo_hi_190 = cat(decoded_andMatrixOutputs_lo_hi_hi_186, decoded_andMatrixOutputs_lo_hi_lo_186)
node decoded_andMatrixOutputs_lo_190 = cat(decoded_andMatrixOutputs_lo_hi_190, decoded_andMatrixOutputs_lo_lo_190)
node decoded_andMatrixOutputs_hi_lo_lo_186 = cat(decoded_andMatrixOutputs_andMatrixInput_7_190, decoded_andMatrixOutputs_andMatrixInput_8_189)
node decoded_andMatrixOutputs_hi_lo_hi_186 = cat(decoded_andMatrixOutputs_andMatrixInput_5_190, decoded_andMatrixOutputs_andMatrixInput_6_190)
node decoded_andMatrixOutputs_hi_lo_190 = cat(decoded_andMatrixOutputs_hi_lo_hi_186, decoded_andMatrixOutputs_hi_lo_lo_186)
node decoded_andMatrixOutputs_hi_hi_lo_186 = cat(decoded_andMatrixOutputs_andMatrixInput_3_190, decoded_andMatrixOutputs_andMatrixInput_4_190)
node decoded_andMatrixOutputs_hi_hi_hi_hi_65 = cat(decoded_andMatrixOutputs_andMatrixInput_0_192, decoded_andMatrixOutputs_andMatrixInput_1_192)
node decoded_andMatrixOutputs_hi_hi_hi_189 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_65, decoded_andMatrixOutputs_andMatrixInput_2_192)
node decoded_andMatrixOutputs_hi_hi_190 = cat(decoded_andMatrixOutputs_hi_hi_hi_189, decoded_andMatrixOutputs_hi_hi_lo_186)
node decoded_andMatrixOutputs_hi_192 = cat(decoded_andMatrixOutputs_hi_hi_190, decoded_andMatrixOutputs_hi_lo_190)
node _decoded_andMatrixOutputs_T_192 = cat(decoded_andMatrixOutputs_hi_192, decoded_andMatrixOutputs_lo_190)
node decoded_andMatrixOutputs_16_2_3 = andr(_decoded_andMatrixOutputs_T_192)
node decoded_andMatrixOutputs_andMatrixInput_0_193 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_193 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_193 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_191 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_191 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_191 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_191 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_191 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_190 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_187 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_187 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_187 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_187 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_187 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_187 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_114 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_66 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_114 = cat(decoded_andMatrixOutputs_andMatrixInput_15_114, decoded_andMatrixOutputs_andMatrixInput_16_66)
node decoded_andMatrixOutputs_lo_lo_hi_187 = cat(decoded_andMatrixOutputs_andMatrixInput_13_187, decoded_andMatrixOutputs_andMatrixInput_14_187)
node decoded_andMatrixOutputs_lo_lo_191 = cat(decoded_andMatrixOutputs_lo_lo_hi_187, decoded_andMatrixOutputs_lo_lo_lo_114)
node decoded_andMatrixOutputs_lo_hi_lo_187 = cat(decoded_andMatrixOutputs_andMatrixInput_11_187, decoded_andMatrixOutputs_andMatrixInput_12_187)
node decoded_andMatrixOutputs_lo_hi_hi_187 = cat(decoded_andMatrixOutputs_andMatrixInput_9_187, decoded_andMatrixOutputs_andMatrixInput_10_187)
node decoded_andMatrixOutputs_lo_hi_191 = cat(decoded_andMatrixOutputs_lo_hi_hi_187, decoded_andMatrixOutputs_lo_hi_lo_187)
node decoded_andMatrixOutputs_lo_191 = cat(decoded_andMatrixOutputs_lo_hi_191, decoded_andMatrixOutputs_lo_lo_191)
node decoded_andMatrixOutputs_hi_lo_lo_187 = cat(decoded_andMatrixOutputs_andMatrixInput_7_191, decoded_andMatrixOutputs_andMatrixInput_8_190)
node decoded_andMatrixOutputs_hi_lo_hi_187 = cat(decoded_andMatrixOutputs_andMatrixInput_5_191, decoded_andMatrixOutputs_andMatrixInput_6_191)
node decoded_andMatrixOutputs_hi_lo_191 = cat(decoded_andMatrixOutputs_hi_lo_hi_187, decoded_andMatrixOutputs_hi_lo_lo_187)
node decoded_andMatrixOutputs_hi_hi_lo_187 = cat(decoded_andMatrixOutputs_andMatrixInput_3_191, decoded_andMatrixOutputs_andMatrixInput_4_191)
node decoded_andMatrixOutputs_hi_hi_hi_hi_66 = cat(decoded_andMatrixOutputs_andMatrixInput_0_193, decoded_andMatrixOutputs_andMatrixInput_1_193)
node decoded_andMatrixOutputs_hi_hi_hi_190 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_66, decoded_andMatrixOutputs_andMatrixInput_2_193)
node decoded_andMatrixOutputs_hi_hi_191 = cat(decoded_andMatrixOutputs_hi_hi_hi_190, decoded_andMatrixOutputs_hi_hi_lo_187)
node decoded_andMatrixOutputs_hi_193 = cat(decoded_andMatrixOutputs_hi_hi_191, decoded_andMatrixOutputs_hi_lo_191)
node _decoded_andMatrixOutputs_T_193 = cat(decoded_andMatrixOutputs_hi_193, decoded_andMatrixOutputs_lo_191)
node decoded_andMatrixOutputs_14_2_3 = andr(_decoded_andMatrixOutputs_T_193)
node decoded_andMatrixOutputs_andMatrixInput_0_194 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_194 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_194 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_192 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_192 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_192 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_192 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_192 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_191 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_188 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_188 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_188 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_188 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_188 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_188 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_115 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_67 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_115 = cat(decoded_andMatrixOutputs_andMatrixInput_15_115, decoded_andMatrixOutputs_andMatrixInput_16_67)
node decoded_andMatrixOutputs_lo_lo_hi_188 = cat(decoded_andMatrixOutputs_andMatrixInput_13_188, decoded_andMatrixOutputs_andMatrixInput_14_188)
node decoded_andMatrixOutputs_lo_lo_192 = cat(decoded_andMatrixOutputs_lo_lo_hi_188, decoded_andMatrixOutputs_lo_lo_lo_115)
node decoded_andMatrixOutputs_lo_hi_lo_188 = cat(decoded_andMatrixOutputs_andMatrixInput_11_188, decoded_andMatrixOutputs_andMatrixInput_12_188)
node decoded_andMatrixOutputs_lo_hi_hi_188 = cat(decoded_andMatrixOutputs_andMatrixInput_9_188, decoded_andMatrixOutputs_andMatrixInput_10_188)
node decoded_andMatrixOutputs_lo_hi_192 = cat(decoded_andMatrixOutputs_lo_hi_hi_188, decoded_andMatrixOutputs_lo_hi_lo_188)
node decoded_andMatrixOutputs_lo_192 = cat(decoded_andMatrixOutputs_lo_hi_192, decoded_andMatrixOutputs_lo_lo_192)
node decoded_andMatrixOutputs_hi_lo_lo_188 = cat(decoded_andMatrixOutputs_andMatrixInput_7_192, decoded_andMatrixOutputs_andMatrixInput_8_191)
node decoded_andMatrixOutputs_hi_lo_hi_188 = cat(decoded_andMatrixOutputs_andMatrixInput_5_192, decoded_andMatrixOutputs_andMatrixInput_6_192)
node decoded_andMatrixOutputs_hi_lo_192 = cat(decoded_andMatrixOutputs_hi_lo_hi_188, decoded_andMatrixOutputs_hi_lo_lo_188)
node decoded_andMatrixOutputs_hi_hi_lo_188 = cat(decoded_andMatrixOutputs_andMatrixInput_3_192, decoded_andMatrixOutputs_andMatrixInput_4_192)
node decoded_andMatrixOutputs_hi_hi_hi_hi_67 = cat(decoded_andMatrixOutputs_andMatrixInput_0_194, decoded_andMatrixOutputs_andMatrixInput_1_194)
node decoded_andMatrixOutputs_hi_hi_hi_191 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_67, decoded_andMatrixOutputs_andMatrixInput_2_194)
node decoded_andMatrixOutputs_hi_hi_192 = cat(decoded_andMatrixOutputs_hi_hi_hi_191, decoded_andMatrixOutputs_hi_hi_lo_188)
node decoded_andMatrixOutputs_hi_194 = cat(decoded_andMatrixOutputs_hi_hi_192, decoded_andMatrixOutputs_hi_lo_192)
node _decoded_andMatrixOutputs_T_194 = cat(decoded_andMatrixOutputs_hi_194, decoded_andMatrixOutputs_lo_192)
node decoded_andMatrixOutputs_54_2_2 = andr(_decoded_andMatrixOutputs_T_194)
node decoded_andMatrixOutputs_andMatrixInput_0_195 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_195 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_195 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_193 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_193 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_193 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_193 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_193 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_192 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_189 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_189 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_189 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_189 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_189 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_189 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_116 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_68 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_116 = cat(decoded_andMatrixOutputs_andMatrixInput_15_116, decoded_andMatrixOutputs_andMatrixInput_16_68)
node decoded_andMatrixOutputs_lo_lo_hi_189 = cat(decoded_andMatrixOutputs_andMatrixInput_13_189, decoded_andMatrixOutputs_andMatrixInput_14_189)
node decoded_andMatrixOutputs_lo_lo_193 = cat(decoded_andMatrixOutputs_lo_lo_hi_189, decoded_andMatrixOutputs_lo_lo_lo_116)
node decoded_andMatrixOutputs_lo_hi_lo_189 = cat(decoded_andMatrixOutputs_andMatrixInput_11_189, decoded_andMatrixOutputs_andMatrixInput_12_189)
node decoded_andMatrixOutputs_lo_hi_hi_189 = cat(decoded_andMatrixOutputs_andMatrixInput_9_189, decoded_andMatrixOutputs_andMatrixInput_10_189)
node decoded_andMatrixOutputs_lo_hi_193 = cat(decoded_andMatrixOutputs_lo_hi_hi_189, decoded_andMatrixOutputs_lo_hi_lo_189)
node decoded_andMatrixOutputs_lo_193 = cat(decoded_andMatrixOutputs_lo_hi_193, decoded_andMatrixOutputs_lo_lo_193)
node decoded_andMatrixOutputs_hi_lo_lo_189 = cat(decoded_andMatrixOutputs_andMatrixInput_7_193, decoded_andMatrixOutputs_andMatrixInput_8_192)
node decoded_andMatrixOutputs_hi_lo_hi_189 = cat(decoded_andMatrixOutputs_andMatrixInput_5_193, decoded_andMatrixOutputs_andMatrixInput_6_193)
node decoded_andMatrixOutputs_hi_lo_193 = cat(decoded_andMatrixOutputs_hi_lo_hi_189, decoded_andMatrixOutputs_hi_lo_lo_189)
node decoded_andMatrixOutputs_hi_hi_lo_189 = cat(decoded_andMatrixOutputs_andMatrixInput_3_193, decoded_andMatrixOutputs_andMatrixInput_4_193)
node decoded_andMatrixOutputs_hi_hi_hi_hi_68 = cat(decoded_andMatrixOutputs_andMatrixInput_0_195, decoded_andMatrixOutputs_andMatrixInput_1_195)
node decoded_andMatrixOutputs_hi_hi_hi_192 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_68, decoded_andMatrixOutputs_andMatrixInput_2_195)
node decoded_andMatrixOutputs_hi_hi_193 = cat(decoded_andMatrixOutputs_hi_hi_hi_192, decoded_andMatrixOutputs_hi_hi_lo_189)
node decoded_andMatrixOutputs_hi_195 = cat(decoded_andMatrixOutputs_hi_hi_193, decoded_andMatrixOutputs_hi_lo_193)
node _decoded_andMatrixOutputs_T_195 = cat(decoded_andMatrixOutputs_hi_195, decoded_andMatrixOutputs_lo_193)
node decoded_andMatrixOutputs_25_2_3 = andr(_decoded_andMatrixOutputs_T_195)
node decoded_andMatrixOutputs_andMatrixInput_0_196 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_196 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_196 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_194 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_194 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_194 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_194 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_194 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_193 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_190 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_190 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_190 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_190 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_190 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_190 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_117 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_69 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_117 = cat(decoded_andMatrixOutputs_andMatrixInput_15_117, decoded_andMatrixOutputs_andMatrixInput_16_69)
node decoded_andMatrixOutputs_lo_lo_hi_190 = cat(decoded_andMatrixOutputs_andMatrixInput_13_190, decoded_andMatrixOutputs_andMatrixInput_14_190)
node decoded_andMatrixOutputs_lo_lo_194 = cat(decoded_andMatrixOutputs_lo_lo_hi_190, decoded_andMatrixOutputs_lo_lo_lo_117)
node decoded_andMatrixOutputs_lo_hi_lo_190 = cat(decoded_andMatrixOutputs_andMatrixInput_11_190, decoded_andMatrixOutputs_andMatrixInput_12_190)
node decoded_andMatrixOutputs_lo_hi_hi_190 = cat(decoded_andMatrixOutputs_andMatrixInput_9_190, decoded_andMatrixOutputs_andMatrixInput_10_190)
node decoded_andMatrixOutputs_lo_hi_194 = cat(decoded_andMatrixOutputs_lo_hi_hi_190, decoded_andMatrixOutputs_lo_hi_lo_190)
node decoded_andMatrixOutputs_lo_194 = cat(decoded_andMatrixOutputs_lo_hi_194, decoded_andMatrixOutputs_lo_lo_194)
node decoded_andMatrixOutputs_hi_lo_lo_190 = cat(decoded_andMatrixOutputs_andMatrixInput_7_194, decoded_andMatrixOutputs_andMatrixInput_8_193)
node decoded_andMatrixOutputs_hi_lo_hi_190 = cat(decoded_andMatrixOutputs_andMatrixInput_5_194, decoded_andMatrixOutputs_andMatrixInput_6_194)
node decoded_andMatrixOutputs_hi_lo_194 = cat(decoded_andMatrixOutputs_hi_lo_hi_190, decoded_andMatrixOutputs_hi_lo_lo_190)
node decoded_andMatrixOutputs_hi_hi_lo_190 = cat(decoded_andMatrixOutputs_andMatrixInput_3_194, decoded_andMatrixOutputs_andMatrixInput_4_194)
node decoded_andMatrixOutputs_hi_hi_hi_hi_69 = cat(decoded_andMatrixOutputs_andMatrixInput_0_196, decoded_andMatrixOutputs_andMatrixInput_1_196)
node decoded_andMatrixOutputs_hi_hi_hi_193 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_69, decoded_andMatrixOutputs_andMatrixInput_2_196)
node decoded_andMatrixOutputs_hi_hi_194 = cat(decoded_andMatrixOutputs_hi_hi_hi_193, decoded_andMatrixOutputs_hi_hi_lo_190)
node decoded_andMatrixOutputs_hi_196 = cat(decoded_andMatrixOutputs_hi_hi_194, decoded_andMatrixOutputs_hi_lo_194)
node _decoded_andMatrixOutputs_T_196 = cat(decoded_andMatrixOutputs_hi_196, decoded_andMatrixOutputs_lo_194)
node decoded_andMatrixOutputs_43_2_3 = andr(_decoded_andMatrixOutputs_T_196)
node decoded_andMatrixOutputs_andMatrixInput_0_197 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_197 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_197 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_195 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_195 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_195 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_195 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_195 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_194 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_191 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_191 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_191 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_191 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_191 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_191 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_118 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_70 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_118 = cat(decoded_andMatrixOutputs_andMatrixInput_15_118, decoded_andMatrixOutputs_andMatrixInput_16_70)
node decoded_andMatrixOutputs_lo_lo_hi_191 = cat(decoded_andMatrixOutputs_andMatrixInput_13_191, decoded_andMatrixOutputs_andMatrixInput_14_191)
node decoded_andMatrixOutputs_lo_lo_195 = cat(decoded_andMatrixOutputs_lo_lo_hi_191, decoded_andMatrixOutputs_lo_lo_lo_118)
node decoded_andMatrixOutputs_lo_hi_lo_191 = cat(decoded_andMatrixOutputs_andMatrixInput_11_191, decoded_andMatrixOutputs_andMatrixInput_12_191)
node decoded_andMatrixOutputs_lo_hi_hi_191 = cat(decoded_andMatrixOutputs_andMatrixInput_9_191, decoded_andMatrixOutputs_andMatrixInput_10_191)
node decoded_andMatrixOutputs_lo_hi_195 = cat(decoded_andMatrixOutputs_lo_hi_hi_191, decoded_andMatrixOutputs_lo_hi_lo_191)
node decoded_andMatrixOutputs_lo_195 = cat(decoded_andMatrixOutputs_lo_hi_195, decoded_andMatrixOutputs_lo_lo_195)
node decoded_andMatrixOutputs_hi_lo_lo_191 = cat(decoded_andMatrixOutputs_andMatrixInput_7_195, decoded_andMatrixOutputs_andMatrixInput_8_194)
node decoded_andMatrixOutputs_hi_lo_hi_191 = cat(decoded_andMatrixOutputs_andMatrixInput_5_195, decoded_andMatrixOutputs_andMatrixInput_6_195)
node decoded_andMatrixOutputs_hi_lo_195 = cat(decoded_andMatrixOutputs_hi_lo_hi_191, decoded_andMatrixOutputs_hi_lo_lo_191)
node decoded_andMatrixOutputs_hi_hi_lo_191 = cat(decoded_andMatrixOutputs_andMatrixInput_3_195, decoded_andMatrixOutputs_andMatrixInput_4_195)
node decoded_andMatrixOutputs_hi_hi_hi_hi_70 = cat(decoded_andMatrixOutputs_andMatrixInput_0_197, decoded_andMatrixOutputs_andMatrixInput_1_197)
node decoded_andMatrixOutputs_hi_hi_hi_194 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_70, decoded_andMatrixOutputs_andMatrixInput_2_197)
node decoded_andMatrixOutputs_hi_hi_195 = cat(decoded_andMatrixOutputs_hi_hi_hi_194, decoded_andMatrixOutputs_hi_hi_lo_191)
node decoded_andMatrixOutputs_hi_197 = cat(decoded_andMatrixOutputs_hi_hi_195, decoded_andMatrixOutputs_hi_lo_195)
node _decoded_andMatrixOutputs_T_197 = cat(decoded_andMatrixOutputs_hi_197, decoded_andMatrixOutputs_lo_195)
node decoded_andMatrixOutputs_9_2_3 = andr(_decoded_andMatrixOutputs_T_197)
node decoded_andMatrixOutputs_andMatrixInput_0_198 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_198 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_198 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_196 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_196 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_196 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_196 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_196 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_195 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_192 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_192 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_192 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_192 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_192 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_192 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_119 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_71 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_119 = cat(decoded_andMatrixOutputs_andMatrixInput_15_119, decoded_andMatrixOutputs_andMatrixInput_16_71)
node decoded_andMatrixOutputs_lo_lo_hi_192 = cat(decoded_andMatrixOutputs_andMatrixInput_13_192, decoded_andMatrixOutputs_andMatrixInput_14_192)
node decoded_andMatrixOutputs_lo_lo_196 = cat(decoded_andMatrixOutputs_lo_lo_hi_192, decoded_andMatrixOutputs_lo_lo_lo_119)
node decoded_andMatrixOutputs_lo_hi_lo_192 = cat(decoded_andMatrixOutputs_andMatrixInput_11_192, decoded_andMatrixOutputs_andMatrixInput_12_192)
node decoded_andMatrixOutputs_lo_hi_hi_192 = cat(decoded_andMatrixOutputs_andMatrixInput_9_192, decoded_andMatrixOutputs_andMatrixInput_10_192)
node decoded_andMatrixOutputs_lo_hi_196 = cat(decoded_andMatrixOutputs_lo_hi_hi_192, decoded_andMatrixOutputs_lo_hi_lo_192)
node decoded_andMatrixOutputs_lo_196 = cat(decoded_andMatrixOutputs_lo_hi_196, decoded_andMatrixOutputs_lo_lo_196)
node decoded_andMatrixOutputs_hi_lo_lo_192 = cat(decoded_andMatrixOutputs_andMatrixInput_7_196, decoded_andMatrixOutputs_andMatrixInput_8_195)
node decoded_andMatrixOutputs_hi_lo_hi_192 = cat(decoded_andMatrixOutputs_andMatrixInput_5_196, decoded_andMatrixOutputs_andMatrixInput_6_196)
node decoded_andMatrixOutputs_hi_lo_196 = cat(decoded_andMatrixOutputs_hi_lo_hi_192, decoded_andMatrixOutputs_hi_lo_lo_192)
node decoded_andMatrixOutputs_hi_hi_lo_192 = cat(decoded_andMatrixOutputs_andMatrixInput_3_196, decoded_andMatrixOutputs_andMatrixInput_4_196)
node decoded_andMatrixOutputs_hi_hi_hi_hi_71 = cat(decoded_andMatrixOutputs_andMatrixInput_0_198, decoded_andMatrixOutputs_andMatrixInput_1_198)
node decoded_andMatrixOutputs_hi_hi_hi_195 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_71, decoded_andMatrixOutputs_andMatrixInput_2_198)
node decoded_andMatrixOutputs_hi_hi_196 = cat(decoded_andMatrixOutputs_hi_hi_hi_195, decoded_andMatrixOutputs_hi_hi_lo_192)
node decoded_andMatrixOutputs_hi_198 = cat(decoded_andMatrixOutputs_hi_hi_196, decoded_andMatrixOutputs_hi_lo_196)
node _decoded_andMatrixOutputs_T_198 = cat(decoded_andMatrixOutputs_hi_198, decoded_andMatrixOutputs_lo_196)
node decoded_andMatrixOutputs_37_2_3 = andr(_decoded_andMatrixOutputs_T_198)
node decoded_andMatrixOutputs_andMatrixInput_0_199 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_199 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_199 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_197 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_197 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_197 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_197 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_197 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_196 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_193 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_193 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_193 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_193 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_193 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_193 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_hi_193 = cat(decoded_andMatrixOutputs_andMatrixInput_12_193, decoded_andMatrixOutputs_andMatrixInput_13_193)
node decoded_andMatrixOutputs_lo_lo_197 = cat(decoded_andMatrixOutputs_lo_lo_hi_193, decoded_andMatrixOutputs_andMatrixInput_14_193)
node decoded_andMatrixOutputs_lo_hi_lo_193 = cat(decoded_andMatrixOutputs_andMatrixInput_10_193, decoded_andMatrixOutputs_andMatrixInput_11_193)
node decoded_andMatrixOutputs_lo_hi_hi_193 = cat(decoded_andMatrixOutputs_andMatrixInput_8_196, decoded_andMatrixOutputs_andMatrixInput_9_193)
node decoded_andMatrixOutputs_lo_hi_197 = cat(decoded_andMatrixOutputs_lo_hi_hi_193, decoded_andMatrixOutputs_lo_hi_lo_193)
node decoded_andMatrixOutputs_lo_197 = cat(decoded_andMatrixOutputs_lo_hi_197, decoded_andMatrixOutputs_lo_lo_197)
node decoded_andMatrixOutputs_hi_lo_lo_193 = cat(decoded_andMatrixOutputs_andMatrixInput_6_197, decoded_andMatrixOutputs_andMatrixInput_7_197)
node decoded_andMatrixOutputs_hi_lo_hi_193 = cat(decoded_andMatrixOutputs_andMatrixInput_4_197, decoded_andMatrixOutputs_andMatrixInput_5_197)
node decoded_andMatrixOutputs_hi_lo_197 = cat(decoded_andMatrixOutputs_hi_lo_hi_193, decoded_andMatrixOutputs_hi_lo_lo_193)
node decoded_andMatrixOutputs_hi_hi_lo_193 = cat(decoded_andMatrixOutputs_andMatrixInput_2_199, decoded_andMatrixOutputs_andMatrixInput_3_197)
node decoded_andMatrixOutputs_hi_hi_hi_196 = cat(decoded_andMatrixOutputs_andMatrixInput_0_199, decoded_andMatrixOutputs_andMatrixInput_1_199)
node decoded_andMatrixOutputs_hi_hi_197 = cat(decoded_andMatrixOutputs_hi_hi_hi_196, decoded_andMatrixOutputs_hi_hi_lo_193)
node decoded_andMatrixOutputs_hi_199 = cat(decoded_andMatrixOutputs_hi_hi_197, decoded_andMatrixOutputs_hi_lo_197)
node _decoded_andMatrixOutputs_T_199 = cat(decoded_andMatrixOutputs_hi_199, decoded_andMatrixOutputs_lo_197)
node decoded_andMatrixOutputs_32_2_3 = andr(_decoded_andMatrixOutputs_T_199)
node decoded_andMatrixOutputs_andMatrixInput_0_200 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_200 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_200 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_198 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_198 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_198 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_198 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_198 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_197 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_194 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_194 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_194 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_194 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_194 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_194 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_120 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_72 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_120 = cat(decoded_andMatrixOutputs_andMatrixInput_15_120, decoded_andMatrixOutputs_andMatrixInput_16_72)
node decoded_andMatrixOutputs_lo_lo_hi_194 = cat(decoded_andMatrixOutputs_andMatrixInput_13_194, decoded_andMatrixOutputs_andMatrixInput_14_194)
node decoded_andMatrixOutputs_lo_lo_198 = cat(decoded_andMatrixOutputs_lo_lo_hi_194, decoded_andMatrixOutputs_lo_lo_lo_120)
node decoded_andMatrixOutputs_lo_hi_lo_194 = cat(decoded_andMatrixOutputs_andMatrixInput_11_194, decoded_andMatrixOutputs_andMatrixInput_12_194)
node decoded_andMatrixOutputs_lo_hi_hi_194 = cat(decoded_andMatrixOutputs_andMatrixInput_9_194, decoded_andMatrixOutputs_andMatrixInput_10_194)
node decoded_andMatrixOutputs_lo_hi_198 = cat(decoded_andMatrixOutputs_lo_hi_hi_194, decoded_andMatrixOutputs_lo_hi_lo_194)
node decoded_andMatrixOutputs_lo_198 = cat(decoded_andMatrixOutputs_lo_hi_198, decoded_andMatrixOutputs_lo_lo_198)
node decoded_andMatrixOutputs_hi_lo_lo_194 = cat(decoded_andMatrixOutputs_andMatrixInput_7_198, decoded_andMatrixOutputs_andMatrixInput_8_197)
node decoded_andMatrixOutputs_hi_lo_hi_194 = cat(decoded_andMatrixOutputs_andMatrixInput_5_198, decoded_andMatrixOutputs_andMatrixInput_6_198)
node decoded_andMatrixOutputs_hi_lo_198 = cat(decoded_andMatrixOutputs_hi_lo_hi_194, decoded_andMatrixOutputs_hi_lo_lo_194)
node decoded_andMatrixOutputs_hi_hi_lo_194 = cat(decoded_andMatrixOutputs_andMatrixInput_3_198, decoded_andMatrixOutputs_andMatrixInput_4_198)
node decoded_andMatrixOutputs_hi_hi_hi_hi_72 = cat(decoded_andMatrixOutputs_andMatrixInput_0_200, decoded_andMatrixOutputs_andMatrixInput_1_200)
node decoded_andMatrixOutputs_hi_hi_hi_197 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_72, decoded_andMatrixOutputs_andMatrixInput_2_200)
node decoded_andMatrixOutputs_hi_hi_198 = cat(decoded_andMatrixOutputs_hi_hi_hi_197, decoded_andMatrixOutputs_hi_hi_lo_194)
node decoded_andMatrixOutputs_hi_200 = cat(decoded_andMatrixOutputs_hi_hi_198, decoded_andMatrixOutputs_hi_lo_198)
node _decoded_andMatrixOutputs_T_200 = cat(decoded_andMatrixOutputs_hi_200, decoded_andMatrixOutputs_lo_198)
node decoded_andMatrixOutputs_10_2_3 = andr(_decoded_andMatrixOutputs_T_200)
node decoded_andMatrixOutputs_andMatrixInput_0_201 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_201 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_201 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_199 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_199 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_199 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_199 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_199 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_198 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_195 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_195 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_195 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_195 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_195 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_195 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_121 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_73 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_121 = cat(decoded_andMatrixOutputs_andMatrixInput_15_121, decoded_andMatrixOutputs_andMatrixInput_16_73)
node decoded_andMatrixOutputs_lo_lo_hi_195 = cat(decoded_andMatrixOutputs_andMatrixInput_13_195, decoded_andMatrixOutputs_andMatrixInput_14_195)
node decoded_andMatrixOutputs_lo_lo_199 = cat(decoded_andMatrixOutputs_lo_lo_hi_195, decoded_andMatrixOutputs_lo_lo_lo_121)
node decoded_andMatrixOutputs_lo_hi_lo_195 = cat(decoded_andMatrixOutputs_andMatrixInput_11_195, decoded_andMatrixOutputs_andMatrixInput_12_195)
node decoded_andMatrixOutputs_lo_hi_hi_195 = cat(decoded_andMatrixOutputs_andMatrixInput_9_195, decoded_andMatrixOutputs_andMatrixInput_10_195)
node decoded_andMatrixOutputs_lo_hi_199 = cat(decoded_andMatrixOutputs_lo_hi_hi_195, decoded_andMatrixOutputs_lo_hi_lo_195)
node decoded_andMatrixOutputs_lo_199 = cat(decoded_andMatrixOutputs_lo_hi_199, decoded_andMatrixOutputs_lo_lo_199)
node decoded_andMatrixOutputs_hi_lo_lo_195 = cat(decoded_andMatrixOutputs_andMatrixInput_7_199, decoded_andMatrixOutputs_andMatrixInput_8_198)
node decoded_andMatrixOutputs_hi_lo_hi_195 = cat(decoded_andMatrixOutputs_andMatrixInput_5_199, decoded_andMatrixOutputs_andMatrixInput_6_199)
node decoded_andMatrixOutputs_hi_lo_199 = cat(decoded_andMatrixOutputs_hi_lo_hi_195, decoded_andMatrixOutputs_hi_lo_lo_195)
node decoded_andMatrixOutputs_hi_hi_lo_195 = cat(decoded_andMatrixOutputs_andMatrixInput_3_199, decoded_andMatrixOutputs_andMatrixInput_4_199)
node decoded_andMatrixOutputs_hi_hi_hi_hi_73 = cat(decoded_andMatrixOutputs_andMatrixInput_0_201, decoded_andMatrixOutputs_andMatrixInput_1_201)
node decoded_andMatrixOutputs_hi_hi_hi_198 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_73, decoded_andMatrixOutputs_andMatrixInput_2_201)
node decoded_andMatrixOutputs_hi_hi_199 = cat(decoded_andMatrixOutputs_hi_hi_hi_198, decoded_andMatrixOutputs_hi_hi_lo_195)
node decoded_andMatrixOutputs_hi_201 = cat(decoded_andMatrixOutputs_hi_hi_199, decoded_andMatrixOutputs_hi_lo_199)
node _decoded_andMatrixOutputs_T_201 = cat(decoded_andMatrixOutputs_hi_201, decoded_andMatrixOutputs_lo_199)
node decoded_andMatrixOutputs_27_2_3 = andr(_decoded_andMatrixOutputs_T_201)
node decoded_andMatrixOutputs_andMatrixInput_0_202 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_202 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_202 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_200 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_200 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_200 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_200 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_200 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_199 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_196 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_196 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_196 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_196 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_196 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_196 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_122 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_74 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_122 = cat(decoded_andMatrixOutputs_andMatrixInput_15_122, decoded_andMatrixOutputs_andMatrixInput_16_74)
node decoded_andMatrixOutputs_lo_lo_hi_196 = cat(decoded_andMatrixOutputs_andMatrixInput_13_196, decoded_andMatrixOutputs_andMatrixInput_14_196)
node decoded_andMatrixOutputs_lo_lo_200 = cat(decoded_andMatrixOutputs_lo_lo_hi_196, decoded_andMatrixOutputs_lo_lo_lo_122)
node decoded_andMatrixOutputs_lo_hi_lo_196 = cat(decoded_andMatrixOutputs_andMatrixInput_11_196, decoded_andMatrixOutputs_andMatrixInput_12_196)
node decoded_andMatrixOutputs_lo_hi_hi_196 = cat(decoded_andMatrixOutputs_andMatrixInput_9_196, decoded_andMatrixOutputs_andMatrixInput_10_196)
node decoded_andMatrixOutputs_lo_hi_200 = cat(decoded_andMatrixOutputs_lo_hi_hi_196, decoded_andMatrixOutputs_lo_hi_lo_196)
node decoded_andMatrixOutputs_lo_200 = cat(decoded_andMatrixOutputs_lo_hi_200, decoded_andMatrixOutputs_lo_lo_200)
node decoded_andMatrixOutputs_hi_lo_lo_196 = cat(decoded_andMatrixOutputs_andMatrixInput_7_200, decoded_andMatrixOutputs_andMatrixInput_8_199)
node decoded_andMatrixOutputs_hi_lo_hi_196 = cat(decoded_andMatrixOutputs_andMatrixInput_5_200, decoded_andMatrixOutputs_andMatrixInput_6_200)
node decoded_andMatrixOutputs_hi_lo_200 = cat(decoded_andMatrixOutputs_hi_lo_hi_196, decoded_andMatrixOutputs_hi_lo_lo_196)
node decoded_andMatrixOutputs_hi_hi_lo_196 = cat(decoded_andMatrixOutputs_andMatrixInput_3_200, decoded_andMatrixOutputs_andMatrixInput_4_200)
node decoded_andMatrixOutputs_hi_hi_hi_hi_74 = cat(decoded_andMatrixOutputs_andMatrixInput_0_202, decoded_andMatrixOutputs_andMatrixInput_1_202)
node decoded_andMatrixOutputs_hi_hi_hi_199 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_74, decoded_andMatrixOutputs_andMatrixInput_2_202)
node decoded_andMatrixOutputs_hi_hi_200 = cat(decoded_andMatrixOutputs_hi_hi_hi_199, decoded_andMatrixOutputs_hi_hi_lo_196)
node decoded_andMatrixOutputs_hi_202 = cat(decoded_andMatrixOutputs_hi_hi_200, decoded_andMatrixOutputs_hi_lo_200)
node _decoded_andMatrixOutputs_T_202 = cat(decoded_andMatrixOutputs_hi_202, decoded_andMatrixOutputs_lo_200)
node decoded_andMatrixOutputs_33_2_3 = andr(_decoded_andMatrixOutputs_T_202)
node decoded_andMatrixOutputs_andMatrixInput_0_203 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_203 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_203 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_201 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_201 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_201 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_201 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_201 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_200 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_197 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_197 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_197 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_197 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_197 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_197 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_197 = cat(decoded_andMatrixOutputs_andMatrixInput_12_197, decoded_andMatrixOutputs_andMatrixInput_13_197)
node decoded_andMatrixOutputs_lo_lo_201 = cat(decoded_andMatrixOutputs_lo_lo_hi_197, decoded_andMatrixOutputs_andMatrixInput_14_197)
node decoded_andMatrixOutputs_lo_hi_lo_197 = cat(decoded_andMatrixOutputs_andMatrixInput_10_197, decoded_andMatrixOutputs_andMatrixInput_11_197)
node decoded_andMatrixOutputs_lo_hi_hi_197 = cat(decoded_andMatrixOutputs_andMatrixInput_8_200, decoded_andMatrixOutputs_andMatrixInput_9_197)
node decoded_andMatrixOutputs_lo_hi_201 = cat(decoded_andMatrixOutputs_lo_hi_hi_197, decoded_andMatrixOutputs_lo_hi_lo_197)
node decoded_andMatrixOutputs_lo_201 = cat(decoded_andMatrixOutputs_lo_hi_201, decoded_andMatrixOutputs_lo_lo_201)
node decoded_andMatrixOutputs_hi_lo_lo_197 = cat(decoded_andMatrixOutputs_andMatrixInput_6_201, decoded_andMatrixOutputs_andMatrixInput_7_201)
node decoded_andMatrixOutputs_hi_lo_hi_197 = cat(decoded_andMatrixOutputs_andMatrixInput_4_201, decoded_andMatrixOutputs_andMatrixInput_5_201)
node decoded_andMatrixOutputs_hi_lo_201 = cat(decoded_andMatrixOutputs_hi_lo_hi_197, decoded_andMatrixOutputs_hi_lo_lo_197)
node decoded_andMatrixOutputs_hi_hi_lo_197 = cat(decoded_andMatrixOutputs_andMatrixInput_2_203, decoded_andMatrixOutputs_andMatrixInput_3_201)
node decoded_andMatrixOutputs_hi_hi_hi_200 = cat(decoded_andMatrixOutputs_andMatrixInput_0_203, decoded_andMatrixOutputs_andMatrixInput_1_203)
node decoded_andMatrixOutputs_hi_hi_201 = cat(decoded_andMatrixOutputs_hi_hi_hi_200, decoded_andMatrixOutputs_hi_hi_lo_197)
node decoded_andMatrixOutputs_hi_203 = cat(decoded_andMatrixOutputs_hi_hi_201, decoded_andMatrixOutputs_hi_lo_201)
node _decoded_andMatrixOutputs_T_203 = cat(decoded_andMatrixOutputs_hi_203, decoded_andMatrixOutputs_lo_201)
node decoded_andMatrixOutputs_36_2_3 = andr(_decoded_andMatrixOutputs_T_203)
node decoded_andMatrixOutputs_andMatrixInput_0_204 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_204 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_204 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_202 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_202 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_202 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_202 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_202 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_201 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_198 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_198 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_198 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_198 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_198 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_198 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_123 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_75 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_123 = cat(decoded_andMatrixOutputs_andMatrixInput_15_123, decoded_andMatrixOutputs_andMatrixInput_16_75)
node decoded_andMatrixOutputs_lo_lo_hi_198 = cat(decoded_andMatrixOutputs_andMatrixInput_13_198, decoded_andMatrixOutputs_andMatrixInput_14_198)
node decoded_andMatrixOutputs_lo_lo_202 = cat(decoded_andMatrixOutputs_lo_lo_hi_198, decoded_andMatrixOutputs_lo_lo_lo_123)
node decoded_andMatrixOutputs_lo_hi_lo_198 = cat(decoded_andMatrixOutputs_andMatrixInput_11_198, decoded_andMatrixOutputs_andMatrixInput_12_198)
node decoded_andMatrixOutputs_lo_hi_hi_198 = cat(decoded_andMatrixOutputs_andMatrixInput_9_198, decoded_andMatrixOutputs_andMatrixInput_10_198)
node decoded_andMatrixOutputs_lo_hi_202 = cat(decoded_andMatrixOutputs_lo_hi_hi_198, decoded_andMatrixOutputs_lo_hi_lo_198)
node decoded_andMatrixOutputs_lo_202 = cat(decoded_andMatrixOutputs_lo_hi_202, decoded_andMatrixOutputs_lo_lo_202)
node decoded_andMatrixOutputs_hi_lo_lo_198 = cat(decoded_andMatrixOutputs_andMatrixInput_7_202, decoded_andMatrixOutputs_andMatrixInput_8_201)
node decoded_andMatrixOutputs_hi_lo_hi_198 = cat(decoded_andMatrixOutputs_andMatrixInput_5_202, decoded_andMatrixOutputs_andMatrixInput_6_202)
node decoded_andMatrixOutputs_hi_lo_202 = cat(decoded_andMatrixOutputs_hi_lo_hi_198, decoded_andMatrixOutputs_hi_lo_lo_198)
node decoded_andMatrixOutputs_hi_hi_lo_198 = cat(decoded_andMatrixOutputs_andMatrixInput_3_202, decoded_andMatrixOutputs_andMatrixInput_4_202)
node decoded_andMatrixOutputs_hi_hi_hi_hi_75 = cat(decoded_andMatrixOutputs_andMatrixInput_0_204, decoded_andMatrixOutputs_andMatrixInput_1_204)
node decoded_andMatrixOutputs_hi_hi_hi_201 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_75, decoded_andMatrixOutputs_andMatrixInput_2_204)
node decoded_andMatrixOutputs_hi_hi_202 = cat(decoded_andMatrixOutputs_hi_hi_hi_201, decoded_andMatrixOutputs_hi_hi_lo_198)
node decoded_andMatrixOutputs_hi_204 = cat(decoded_andMatrixOutputs_hi_hi_202, decoded_andMatrixOutputs_hi_lo_202)
node _decoded_andMatrixOutputs_T_204 = cat(decoded_andMatrixOutputs_hi_204, decoded_andMatrixOutputs_lo_202)
node decoded_andMatrixOutputs_17_2_3 = andr(_decoded_andMatrixOutputs_T_204)
node decoded_andMatrixOutputs_andMatrixInput_0_205 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_205 = bits(decoded_plaInput_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_205 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_203 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_203 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_203 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_203 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_203 = bits(decoded_plaInput_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_202 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_199 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_199 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_199 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_199 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_199 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_199 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_124 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_76 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_124 = cat(decoded_andMatrixOutputs_andMatrixInput_15_124, decoded_andMatrixOutputs_andMatrixInput_16_76)
node decoded_andMatrixOutputs_lo_lo_hi_199 = cat(decoded_andMatrixOutputs_andMatrixInput_13_199, decoded_andMatrixOutputs_andMatrixInput_14_199)
node decoded_andMatrixOutputs_lo_lo_203 = cat(decoded_andMatrixOutputs_lo_lo_hi_199, decoded_andMatrixOutputs_lo_lo_lo_124)
node decoded_andMatrixOutputs_lo_hi_lo_199 = cat(decoded_andMatrixOutputs_andMatrixInput_11_199, decoded_andMatrixOutputs_andMatrixInput_12_199)
node decoded_andMatrixOutputs_lo_hi_hi_199 = cat(decoded_andMatrixOutputs_andMatrixInput_9_199, decoded_andMatrixOutputs_andMatrixInput_10_199)
node decoded_andMatrixOutputs_lo_hi_203 = cat(decoded_andMatrixOutputs_lo_hi_hi_199, decoded_andMatrixOutputs_lo_hi_lo_199)
node decoded_andMatrixOutputs_lo_203 = cat(decoded_andMatrixOutputs_lo_hi_203, decoded_andMatrixOutputs_lo_lo_203)
node decoded_andMatrixOutputs_hi_lo_lo_199 = cat(decoded_andMatrixOutputs_andMatrixInput_7_203, decoded_andMatrixOutputs_andMatrixInput_8_202)
node decoded_andMatrixOutputs_hi_lo_hi_199 = cat(decoded_andMatrixOutputs_andMatrixInput_5_203, decoded_andMatrixOutputs_andMatrixInput_6_203)
node decoded_andMatrixOutputs_hi_lo_203 = cat(decoded_andMatrixOutputs_hi_lo_hi_199, decoded_andMatrixOutputs_hi_lo_lo_199)
node decoded_andMatrixOutputs_hi_hi_lo_199 = cat(decoded_andMatrixOutputs_andMatrixInput_3_203, decoded_andMatrixOutputs_andMatrixInput_4_203)
node decoded_andMatrixOutputs_hi_hi_hi_hi_76 = cat(decoded_andMatrixOutputs_andMatrixInput_0_205, decoded_andMatrixOutputs_andMatrixInput_1_205)
node decoded_andMatrixOutputs_hi_hi_hi_202 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_76, decoded_andMatrixOutputs_andMatrixInput_2_205)
node decoded_andMatrixOutputs_hi_hi_203 = cat(decoded_andMatrixOutputs_hi_hi_hi_202, decoded_andMatrixOutputs_hi_hi_lo_199)
node decoded_andMatrixOutputs_hi_205 = cat(decoded_andMatrixOutputs_hi_hi_203, decoded_andMatrixOutputs_hi_lo_203)
node _decoded_andMatrixOutputs_T_205 = cat(decoded_andMatrixOutputs_hi_205, decoded_andMatrixOutputs_lo_203)
node decoded_andMatrixOutputs_6_2_3 = andr(_decoded_andMatrixOutputs_T_205)
node decoded_andMatrixOutputs_andMatrixInput_0_206 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_206 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_206 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_204 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_204 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_204 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_204 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_204 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_203 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_200 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_200 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_200 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_200 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_200 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_200 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_200 = cat(decoded_andMatrixOutputs_andMatrixInput_12_200, decoded_andMatrixOutputs_andMatrixInput_13_200)
node decoded_andMatrixOutputs_lo_lo_204 = cat(decoded_andMatrixOutputs_lo_lo_hi_200, decoded_andMatrixOutputs_andMatrixInput_14_200)
node decoded_andMatrixOutputs_lo_hi_lo_200 = cat(decoded_andMatrixOutputs_andMatrixInput_10_200, decoded_andMatrixOutputs_andMatrixInput_11_200)
node decoded_andMatrixOutputs_lo_hi_hi_200 = cat(decoded_andMatrixOutputs_andMatrixInput_8_203, decoded_andMatrixOutputs_andMatrixInput_9_200)
node decoded_andMatrixOutputs_lo_hi_204 = cat(decoded_andMatrixOutputs_lo_hi_hi_200, decoded_andMatrixOutputs_lo_hi_lo_200)
node decoded_andMatrixOutputs_lo_204 = cat(decoded_andMatrixOutputs_lo_hi_204, decoded_andMatrixOutputs_lo_lo_204)
node decoded_andMatrixOutputs_hi_lo_lo_200 = cat(decoded_andMatrixOutputs_andMatrixInput_6_204, decoded_andMatrixOutputs_andMatrixInput_7_204)
node decoded_andMatrixOutputs_hi_lo_hi_200 = cat(decoded_andMatrixOutputs_andMatrixInput_4_204, decoded_andMatrixOutputs_andMatrixInput_5_204)
node decoded_andMatrixOutputs_hi_lo_204 = cat(decoded_andMatrixOutputs_hi_lo_hi_200, decoded_andMatrixOutputs_hi_lo_lo_200)
node decoded_andMatrixOutputs_hi_hi_lo_200 = cat(decoded_andMatrixOutputs_andMatrixInput_2_206, decoded_andMatrixOutputs_andMatrixInput_3_204)
node decoded_andMatrixOutputs_hi_hi_hi_203 = cat(decoded_andMatrixOutputs_andMatrixInput_0_206, decoded_andMatrixOutputs_andMatrixInput_1_206)
node decoded_andMatrixOutputs_hi_hi_204 = cat(decoded_andMatrixOutputs_hi_hi_hi_203, decoded_andMatrixOutputs_hi_hi_lo_200)
node decoded_andMatrixOutputs_hi_206 = cat(decoded_andMatrixOutputs_hi_hi_204, decoded_andMatrixOutputs_hi_lo_204)
node _decoded_andMatrixOutputs_T_206 = cat(decoded_andMatrixOutputs_hi_206, decoded_andMatrixOutputs_lo_204)
node decoded_andMatrixOutputs_4_2_3 = andr(_decoded_andMatrixOutputs_T_206)
node decoded_andMatrixOutputs_andMatrixInput_0_207 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_207 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_207 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_205 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_205 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_205 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_205 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_205 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_204 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_201 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_201 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_201 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_201 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_201 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_201 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_201 = cat(decoded_andMatrixOutputs_andMatrixInput_12_201, decoded_andMatrixOutputs_andMatrixInput_13_201)
node decoded_andMatrixOutputs_lo_lo_205 = cat(decoded_andMatrixOutputs_lo_lo_hi_201, decoded_andMatrixOutputs_andMatrixInput_14_201)
node decoded_andMatrixOutputs_lo_hi_lo_201 = cat(decoded_andMatrixOutputs_andMatrixInput_10_201, decoded_andMatrixOutputs_andMatrixInput_11_201)
node decoded_andMatrixOutputs_lo_hi_hi_201 = cat(decoded_andMatrixOutputs_andMatrixInput_8_204, decoded_andMatrixOutputs_andMatrixInput_9_201)
node decoded_andMatrixOutputs_lo_hi_205 = cat(decoded_andMatrixOutputs_lo_hi_hi_201, decoded_andMatrixOutputs_lo_hi_lo_201)
node decoded_andMatrixOutputs_lo_205 = cat(decoded_andMatrixOutputs_lo_hi_205, decoded_andMatrixOutputs_lo_lo_205)
node decoded_andMatrixOutputs_hi_lo_lo_201 = cat(decoded_andMatrixOutputs_andMatrixInput_6_205, decoded_andMatrixOutputs_andMatrixInput_7_205)
node decoded_andMatrixOutputs_hi_lo_hi_201 = cat(decoded_andMatrixOutputs_andMatrixInput_4_205, decoded_andMatrixOutputs_andMatrixInput_5_205)
node decoded_andMatrixOutputs_hi_lo_205 = cat(decoded_andMatrixOutputs_hi_lo_hi_201, decoded_andMatrixOutputs_hi_lo_lo_201)
node decoded_andMatrixOutputs_hi_hi_lo_201 = cat(decoded_andMatrixOutputs_andMatrixInput_2_207, decoded_andMatrixOutputs_andMatrixInput_3_205)
node decoded_andMatrixOutputs_hi_hi_hi_204 = cat(decoded_andMatrixOutputs_andMatrixInput_0_207, decoded_andMatrixOutputs_andMatrixInput_1_207)
node decoded_andMatrixOutputs_hi_hi_205 = cat(decoded_andMatrixOutputs_hi_hi_hi_204, decoded_andMatrixOutputs_hi_hi_lo_201)
node decoded_andMatrixOutputs_hi_207 = cat(decoded_andMatrixOutputs_hi_hi_205, decoded_andMatrixOutputs_hi_lo_205)
node _decoded_andMatrixOutputs_T_207 = cat(decoded_andMatrixOutputs_hi_207, decoded_andMatrixOutputs_lo_205)
node decoded_andMatrixOutputs_11_2_3 = andr(_decoded_andMatrixOutputs_T_207)
node decoded_andMatrixOutputs_andMatrixInput_0_208 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_208 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_208 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_206 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_206 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_206 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_206 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_206 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_205 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_202 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_202 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_202 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_202 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_202 = bits(decoded_plaInput_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_202 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_125 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_77 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_125 = cat(decoded_andMatrixOutputs_andMatrixInput_15_125, decoded_andMatrixOutputs_andMatrixInput_16_77)
node decoded_andMatrixOutputs_lo_lo_hi_202 = cat(decoded_andMatrixOutputs_andMatrixInput_13_202, decoded_andMatrixOutputs_andMatrixInput_14_202)
node decoded_andMatrixOutputs_lo_lo_206 = cat(decoded_andMatrixOutputs_lo_lo_hi_202, decoded_andMatrixOutputs_lo_lo_lo_125)
node decoded_andMatrixOutputs_lo_hi_lo_202 = cat(decoded_andMatrixOutputs_andMatrixInput_11_202, decoded_andMatrixOutputs_andMatrixInput_12_202)
node decoded_andMatrixOutputs_lo_hi_hi_202 = cat(decoded_andMatrixOutputs_andMatrixInput_9_202, decoded_andMatrixOutputs_andMatrixInput_10_202)
node decoded_andMatrixOutputs_lo_hi_206 = cat(decoded_andMatrixOutputs_lo_hi_hi_202, decoded_andMatrixOutputs_lo_hi_lo_202)
node decoded_andMatrixOutputs_lo_206 = cat(decoded_andMatrixOutputs_lo_hi_206, decoded_andMatrixOutputs_lo_lo_206)
node decoded_andMatrixOutputs_hi_lo_lo_202 = cat(decoded_andMatrixOutputs_andMatrixInput_7_206, decoded_andMatrixOutputs_andMatrixInput_8_205)
node decoded_andMatrixOutputs_hi_lo_hi_202 = cat(decoded_andMatrixOutputs_andMatrixInput_5_206, decoded_andMatrixOutputs_andMatrixInput_6_206)
node decoded_andMatrixOutputs_hi_lo_206 = cat(decoded_andMatrixOutputs_hi_lo_hi_202, decoded_andMatrixOutputs_hi_lo_lo_202)
node decoded_andMatrixOutputs_hi_hi_lo_202 = cat(decoded_andMatrixOutputs_andMatrixInput_3_206, decoded_andMatrixOutputs_andMatrixInput_4_206)
node decoded_andMatrixOutputs_hi_hi_hi_hi_77 = cat(decoded_andMatrixOutputs_andMatrixInput_0_208, decoded_andMatrixOutputs_andMatrixInput_1_208)
node decoded_andMatrixOutputs_hi_hi_hi_205 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_77, decoded_andMatrixOutputs_andMatrixInput_2_208)
node decoded_andMatrixOutputs_hi_hi_206 = cat(decoded_andMatrixOutputs_hi_hi_hi_205, decoded_andMatrixOutputs_hi_hi_lo_202)
node decoded_andMatrixOutputs_hi_208 = cat(decoded_andMatrixOutputs_hi_hi_206, decoded_andMatrixOutputs_hi_lo_206)
node _decoded_andMatrixOutputs_T_208 = cat(decoded_andMatrixOutputs_hi_208, decoded_andMatrixOutputs_lo_206)
node decoded_andMatrixOutputs_42_2_3 = andr(_decoded_andMatrixOutputs_T_208)
node decoded_andMatrixOutputs_andMatrixInput_0_209 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_209 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_209 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_207 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_207 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_207 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_207 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_207 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_206 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_203 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_203 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_203 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_203 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_203 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_203 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_126 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_78 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_126 = cat(decoded_andMatrixOutputs_andMatrixInput_15_126, decoded_andMatrixOutputs_andMatrixInput_16_78)
node decoded_andMatrixOutputs_lo_lo_hi_203 = cat(decoded_andMatrixOutputs_andMatrixInput_13_203, decoded_andMatrixOutputs_andMatrixInput_14_203)
node decoded_andMatrixOutputs_lo_lo_207 = cat(decoded_andMatrixOutputs_lo_lo_hi_203, decoded_andMatrixOutputs_lo_lo_lo_126)
node decoded_andMatrixOutputs_lo_hi_lo_203 = cat(decoded_andMatrixOutputs_andMatrixInput_11_203, decoded_andMatrixOutputs_andMatrixInput_12_203)
node decoded_andMatrixOutputs_lo_hi_hi_203 = cat(decoded_andMatrixOutputs_andMatrixInput_9_203, decoded_andMatrixOutputs_andMatrixInput_10_203)
node decoded_andMatrixOutputs_lo_hi_207 = cat(decoded_andMatrixOutputs_lo_hi_hi_203, decoded_andMatrixOutputs_lo_hi_lo_203)
node decoded_andMatrixOutputs_lo_207 = cat(decoded_andMatrixOutputs_lo_hi_207, decoded_andMatrixOutputs_lo_lo_207)
node decoded_andMatrixOutputs_hi_lo_lo_203 = cat(decoded_andMatrixOutputs_andMatrixInput_7_207, decoded_andMatrixOutputs_andMatrixInput_8_206)
node decoded_andMatrixOutputs_hi_lo_hi_203 = cat(decoded_andMatrixOutputs_andMatrixInput_5_207, decoded_andMatrixOutputs_andMatrixInput_6_207)
node decoded_andMatrixOutputs_hi_lo_207 = cat(decoded_andMatrixOutputs_hi_lo_hi_203, decoded_andMatrixOutputs_hi_lo_lo_203)
node decoded_andMatrixOutputs_hi_hi_lo_203 = cat(decoded_andMatrixOutputs_andMatrixInput_3_207, decoded_andMatrixOutputs_andMatrixInput_4_207)
node decoded_andMatrixOutputs_hi_hi_hi_hi_78 = cat(decoded_andMatrixOutputs_andMatrixInput_0_209, decoded_andMatrixOutputs_andMatrixInput_1_209)
node decoded_andMatrixOutputs_hi_hi_hi_206 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_78, decoded_andMatrixOutputs_andMatrixInput_2_209)
node decoded_andMatrixOutputs_hi_hi_207 = cat(decoded_andMatrixOutputs_hi_hi_hi_206, decoded_andMatrixOutputs_hi_hi_lo_203)
node decoded_andMatrixOutputs_hi_209 = cat(decoded_andMatrixOutputs_hi_hi_207, decoded_andMatrixOutputs_hi_lo_207)
node _decoded_andMatrixOutputs_T_209 = cat(decoded_andMatrixOutputs_hi_209, decoded_andMatrixOutputs_lo_207)
node decoded_andMatrixOutputs_0_2_3 = andr(_decoded_andMatrixOutputs_T_209)
node decoded_andMatrixOutputs_andMatrixInput_0_210 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_210 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_210 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_208 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_208 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_208 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_208 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_208 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_207 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_204 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_204 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_204 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_204 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_204 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_204 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_127 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_79 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_127 = cat(decoded_andMatrixOutputs_andMatrixInput_15_127, decoded_andMatrixOutputs_andMatrixInput_16_79)
node decoded_andMatrixOutputs_lo_lo_hi_204 = cat(decoded_andMatrixOutputs_andMatrixInput_13_204, decoded_andMatrixOutputs_andMatrixInput_14_204)
node decoded_andMatrixOutputs_lo_lo_208 = cat(decoded_andMatrixOutputs_lo_lo_hi_204, decoded_andMatrixOutputs_lo_lo_lo_127)
node decoded_andMatrixOutputs_lo_hi_lo_204 = cat(decoded_andMatrixOutputs_andMatrixInput_11_204, decoded_andMatrixOutputs_andMatrixInput_12_204)
node decoded_andMatrixOutputs_lo_hi_hi_204 = cat(decoded_andMatrixOutputs_andMatrixInput_9_204, decoded_andMatrixOutputs_andMatrixInput_10_204)
node decoded_andMatrixOutputs_lo_hi_208 = cat(decoded_andMatrixOutputs_lo_hi_hi_204, decoded_andMatrixOutputs_lo_hi_lo_204)
node decoded_andMatrixOutputs_lo_208 = cat(decoded_andMatrixOutputs_lo_hi_208, decoded_andMatrixOutputs_lo_lo_208)
node decoded_andMatrixOutputs_hi_lo_lo_204 = cat(decoded_andMatrixOutputs_andMatrixInput_7_208, decoded_andMatrixOutputs_andMatrixInput_8_207)
node decoded_andMatrixOutputs_hi_lo_hi_204 = cat(decoded_andMatrixOutputs_andMatrixInput_5_208, decoded_andMatrixOutputs_andMatrixInput_6_208)
node decoded_andMatrixOutputs_hi_lo_208 = cat(decoded_andMatrixOutputs_hi_lo_hi_204, decoded_andMatrixOutputs_hi_lo_lo_204)
node decoded_andMatrixOutputs_hi_hi_lo_204 = cat(decoded_andMatrixOutputs_andMatrixInput_3_208, decoded_andMatrixOutputs_andMatrixInput_4_208)
node decoded_andMatrixOutputs_hi_hi_hi_hi_79 = cat(decoded_andMatrixOutputs_andMatrixInput_0_210, decoded_andMatrixOutputs_andMatrixInput_1_210)
node decoded_andMatrixOutputs_hi_hi_hi_207 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_79, decoded_andMatrixOutputs_andMatrixInput_2_210)
node decoded_andMatrixOutputs_hi_hi_208 = cat(decoded_andMatrixOutputs_hi_hi_hi_207, decoded_andMatrixOutputs_hi_hi_lo_204)
node decoded_andMatrixOutputs_hi_210 = cat(decoded_andMatrixOutputs_hi_hi_208, decoded_andMatrixOutputs_hi_lo_208)
node _decoded_andMatrixOutputs_T_210 = cat(decoded_andMatrixOutputs_hi_210, decoded_andMatrixOutputs_lo_208)
node decoded_andMatrixOutputs_18_2_3 = andr(_decoded_andMatrixOutputs_T_210)
node decoded_andMatrixOutputs_andMatrixInput_0_211 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_211 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_211 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_209 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_209 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_209 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_209 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_209 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_208 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_205 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_205 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_205 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_205 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_205 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_205 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_205 = cat(decoded_andMatrixOutputs_andMatrixInput_12_205, decoded_andMatrixOutputs_andMatrixInput_13_205)
node decoded_andMatrixOutputs_lo_lo_209 = cat(decoded_andMatrixOutputs_lo_lo_hi_205, decoded_andMatrixOutputs_andMatrixInput_14_205)
node decoded_andMatrixOutputs_lo_hi_lo_205 = cat(decoded_andMatrixOutputs_andMatrixInput_10_205, decoded_andMatrixOutputs_andMatrixInput_11_205)
node decoded_andMatrixOutputs_lo_hi_hi_205 = cat(decoded_andMatrixOutputs_andMatrixInput_8_208, decoded_andMatrixOutputs_andMatrixInput_9_205)
node decoded_andMatrixOutputs_lo_hi_209 = cat(decoded_andMatrixOutputs_lo_hi_hi_205, decoded_andMatrixOutputs_lo_hi_lo_205)
node decoded_andMatrixOutputs_lo_209 = cat(decoded_andMatrixOutputs_lo_hi_209, decoded_andMatrixOutputs_lo_lo_209)
node decoded_andMatrixOutputs_hi_lo_lo_205 = cat(decoded_andMatrixOutputs_andMatrixInput_6_209, decoded_andMatrixOutputs_andMatrixInput_7_209)
node decoded_andMatrixOutputs_hi_lo_hi_205 = cat(decoded_andMatrixOutputs_andMatrixInput_4_209, decoded_andMatrixOutputs_andMatrixInput_5_209)
node decoded_andMatrixOutputs_hi_lo_209 = cat(decoded_andMatrixOutputs_hi_lo_hi_205, decoded_andMatrixOutputs_hi_lo_lo_205)
node decoded_andMatrixOutputs_hi_hi_lo_205 = cat(decoded_andMatrixOutputs_andMatrixInput_2_211, decoded_andMatrixOutputs_andMatrixInput_3_209)
node decoded_andMatrixOutputs_hi_hi_hi_208 = cat(decoded_andMatrixOutputs_andMatrixInput_0_211, decoded_andMatrixOutputs_andMatrixInput_1_211)
node decoded_andMatrixOutputs_hi_hi_209 = cat(decoded_andMatrixOutputs_hi_hi_hi_208, decoded_andMatrixOutputs_hi_hi_lo_205)
node decoded_andMatrixOutputs_hi_211 = cat(decoded_andMatrixOutputs_hi_hi_209, decoded_andMatrixOutputs_hi_lo_209)
node _decoded_andMatrixOutputs_T_211 = cat(decoded_andMatrixOutputs_hi_211, decoded_andMatrixOutputs_lo_209)
node decoded_andMatrixOutputs_49_2_2 = andr(_decoded_andMatrixOutputs_T_211)
node decoded_andMatrixOutputs_andMatrixInput_0_212 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_212 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_212 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_210 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_210 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_210 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_210 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_210 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_209 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_206 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_206 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_206 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_206 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_206 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_206 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_128 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_80 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_128 = cat(decoded_andMatrixOutputs_andMatrixInput_15_128, decoded_andMatrixOutputs_andMatrixInput_16_80)
node decoded_andMatrixOutputs_lo_lo_hi_206 = cat(decoded_andMatrixOutputs_andMatrixInput_13_206, decoded_andMatrixOutputs_andMatrixInput_14_206)
node decoded_andMatrixOutputs_lo_lo_210 = cat(decoded_andMatrixOutputs_lo_lo_hi_206, decoded_andMatrixOutputs_lo_lo_lo_128)
node decoded_andMatrixOutputs_lo_hi_lo_206 = cat(decoded_andMatrixOutputs_andMatrixInput_11_206, decoded_andMatrixOutputs_andMatrixInput_12_206)
node decoded_andMatrixOutputs_lo_hi_hi_206 = cat(decoded_andMatrixOutputs_andMatrixInput_9_206, decoded_andMatrixOutputs_andMatrixInput_10_206)
node decoded_andMatrixOutputs_lo_hi_210 = cat(decoded_andMatrixOutputs_lo_hi_hi_206, decoded_andMatrixOutputs_lo_hi_lo_206)
node decoded_andMatrixOutputs_lo_210 = cat(decoded_andMatrixOutputs_lo_hi_210, decoded_andMatrixOutputs_lo_lo_210)
node decoded_andMatrixOutputs_hi_lo_lo_206 = cat(decoded_andMatrixOutputs_andMatrixInput_7_210, decoded_andMatrixOutputs_andMatrixInput_8_209)
node decoded_andMatrixOutputs_hi_lo_hi_206 = cat(decoded_andMatrixOutputs_andMatrixInput_5_210, decoded_andMatrixOutputs_andMatrixInput_6_210)
node decoded_andMatrixOutputs_hi_lo_210 = cat(decoded_andMatrixOutputs_hi_lo_hi_206, decoded_andMatrixOutputs_hi_lo_lo_206)
node decoded_andMatrixOutputs_hi_hi_lo_206 = cat(decoded_andMatrixOutputs_andMatrixInput_3_210, decoded_andMatrixOutputs_andMatrixInput_4_210)
node decoded_andMatrixOutputs_hi_hi_hi_hi_80 = cat(decoded_andMatrixOutputs_andMatrixInput_0_212, decoded_andMatrixOutputs_andMatrixInput_1_212)
node decoded_andMatrixOutputs_hi_hi_hi_209 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_80, decoded_andMatrixOutputs_andMatrixInput_2_212)
node decoded_andMatrixOutputs_hi_hi_210 = cat(decoded_andMatrixOutputs_hi_hi_hi_209, decoded_andMatrixOutputs_hi_hi_lo_206)
node decoded_andMatrixOutputs_hi_212 = cat(decoded_andMatrixOutputs_hi_hi_210, decoded_andMatrixOutputs_hi_lo_210)
node _decoded_andMatrixOutputs_T_212 = cat(decoded_andMatrixOutputs_hi_212, decoded_andMatrixOutputs_lo_210)
node decoded_andMatrixOutputs_28_2_3 = andr(_decoded_andMatrixOutputs_T_212)
node decoded_andMatrixOutputs_andMatrixInput_0_213 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_213 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_213 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_211 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_211 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_211 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_211 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_211 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_210 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_207 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_207 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_207 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_207 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_207 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_207 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_129 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_81 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_129 = cat(decoded_andMatrixOutputs_andMatrixInput_15_129, decoded_andMatrixOutputs_andMatrixInput_16_81)
node decoded_andMatrixOutputs_lo_lo_hi_207 = cat(decoded_andMatrixOutputs_andMatrixInput_13_207, decoded_andMatrixOutputs_andMatrixInput_14_207)
node decoded_andMatrixOutputs_lo_lo_211 = cat(decoded_andMatrixOutputs_lo_lo_hi_207, decoded_andMatrixOutputs_lo_lo_lo_129)
node decoded_andMatrixOutputs_lo_hi_lo_207 = cat(decoded_andMatrixOutputs_andMatrixInput_11_207, decoded_andMatrixOutputs_andMatrixInput_12_207)
node decoded_andMatrixOutputs_lo_hi_hi_207 = cat(decoded_andMatrixOutputs_andMatrixInput_9_207, decoded_andMatrixOutputs_andMatrixInput_10_207)
node decoded_andMatrixOutputs_lo_hi_211 = cat(decoded_andMatrixOutputs_lo_hi_hi_207, decoded_andMatrixOutputs_lo_hi_lo_207)
node decoded_andMatrixOutputs_lo_211 = cat(decoded_andMatrixOutputs_lo_hi_211, decoded_andMatrixOutputs_lo_lo_211)
node decoded_andMatrixOutputs_hi_lo_lo_207 = cat(decoded_andMatrixOutputs_andMatrixInput_7_211, decoded_andMatrixOutputs_andMatrixInput_8_210)
node decoded_andMatrixOutputs_hi_lo_hi_207 = cat(decoded_andMatrixOutputs_andMatrixInput_5_211, decoded_andMatrixOutputs_andMatrixInput_6_211)
node decoded_andMatrixOutputs_hi_lo_211 = cat(decoded_andMatrixOutputs_hi_lo_hi_207, decoded_andMatrixOutputs_hi_lo_lo_207)
node decoded_andMatrixOutputs_hi_hi_lo_207 = cat(decoded_andMatrixOutputs_andMatrixInput_3_211, decoded_andMatrixOutputs_andMatrixInput_4_211)
node decoded_andMatrixOutputs_hi_hi_hi_hi_81 = cat(decoded_andMatrixOutputs_andMatrixInput_0_213, decoded_andMatrixOutputs_andMatrixInput_1_213)
node decoded_andMatrixOutputs_hi_hi_hi_210 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_81, decoded_andMatrixOutputs_andMatrixInput_2_213)
node decoded_andMatrixOutputs_hi_hi_211 = cat(decoded_andMatrixOutputs_hi_hi_hi_210, decoded_andMatrixOutputs_hi_hi_lo_207)
node decoded_andMatrixOutputs_hi_213 = cat(decoded_andMatrixOutputs_hi_hi_211, decoded_andMatrixOutputs_hi_lo_211)
node _decoded_andMatrixOutputs_T_213 = cat(decoded_andMatrixOutputs_hi_213, decoded_andMatrixOutputs_lo_211)
node decoded_andMatrixOutputs_23_2_3 = andr(_decoded_andMatrixOutputs_T_213)
node decoded_andMatrixOutputs_andMatrixInput_0_214 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_214 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_214 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_212 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_212 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_212 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_212 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_212 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_211 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_208 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_208 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_208 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_208 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_208 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_208 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_130 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_82 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_130 = cat(decoded_andMatrixOutputs_andMatrixInput_15_130, decoded_andMatrixOutputs_andMatrixInput_16_82)
node decoded_andMatrixOutputs_lo_lo_hi_208 = cat(decoded_andMatrixOutputs_andMatrixInput_13_208, decoded_andMatrixOutputs_andMatrixInput_14_208)
node decoded_andMatrixOutputs_lo_lo_212 = cat(decoded_andMatrixOutputs_lo_lo_hi_208, decoded_andMatrixOutputs_lo_lo_lo_130)
node decoded_andMatrixOutputs_lo_hi_lo_208 = cat(decoded_andMatrixOutputs_andMatrixInput_11_208, decoded_andMatrixOutputs_andMatrixInput_12_208)
node decoded_andMatrixOutputs_lo_hi_hi_208 = cat(decoded_andMatrixOutputs_andMatrixInput_9_208, decoded_andMatrixOutputs_andMatrixInput_10_208)
node decoded_andMatrixOutputs_lo_hi_212 = cat(decoded_andMatrixOutputs_lo_hi_hi_208, decoded_andMatrixOutputs_lo_hi_lo_208)
node decoded_andMatrixOutputs_lo_212 = cat(decoded_andMatrixOutputs_lo_hi_212, decoded_andMatrixOutputs_lo_lo_212)
node decoded_andMatrixOutputs_hi_lo_lo_208 = cat(decoded_andMatrixOutputs_andMatrixInput_7_212, decoded_andMatrixOutputs_andMatrixInput_8_211)
node decoded_andMatrixOutputs_hi_lo_hi_208 = cat(decoded_andMatrixOutputs_andMatrixInput_5_212, decoded_andMatrixOutputs_andMatrixInput_6_212)
node decoded_andMatrixOutputs_hi_lo_212 = cat(decoded_andMatrixOutputs_hi_lo_hi_208, decoded_andMatrixOutputs_hi_lo_lo_208)
node decoded_andMatrixOutputs_hi_hi_lo_208 = cat(decoded_andMatrixOutputs_andMatrixInput_3_212, decoded_andMatrixOutputs_andMatrixInput_4_212)
node decoded_andMatrixOutputs_hi_hi_hi_hi_82 = cat(decoded_andMatrixOutputs_andMatrixInput_0_214, decoded_andMatrixOutputs_andMatrixInput_1_214)
node decoded_andMatrixOutputs_hi_hi_hi_211 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_82, decoded_andMatrixOutputs_andMatrixInput_2_214)
node decoded_andMatrixOutputs_hi_hi_212 = cat(decoded_andMatrixOutputs_hi_hi_hi_211, decoded_andMatrixOutputs_hi_hi_lo_208)
node decoded_andMatrixOutputs_hi_214 = cat(decoded_andMatrixOutputs_hi_hi_212, decoded_andMatrixOutputs_hi_lo_212)
node _decoded_andMatrixOutputs_T_214 = cat(decoded_andMatrixOutputs_hi_214, decoded_andMatrixOutputs_lo_212)
node decoded_andMatrixOutputs_50_2_2 = andr(_decoded_andMatrixOutputs_T_214)
node decoded_andMatrixOutputs_andMatrixInput_0_215 = bits(decoded_plaInput_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_215 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_215 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_213 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_213 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_213 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_213 = bits(decoded_plaInput_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_213 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_212 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_209 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_209 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_209 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_209 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_209 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_209 = bits(decoded_plaInput_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_131 = bits(decoded_invInputs_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_83 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_131 = cat(decoded_andMatrixOutputs_andMatrixInput_15_131, decoded_andMatrixOutputs_andMatrixInput_16_83)
node decoded_andMatrixOutputs_lo_lo_hi_209 = cat(decoded_andMatrixOutputs_andMatrixInput_13_209, decoded_andMatrixOutputs_andMatrixInput_14_209)
node decoded_andMatrixOutputs_lo_lo_213 = cat(decoded_andMatrixOutputs_lo_lo_hi_209, decoded_andMatrixOutputs_lo_lo_lo_131)
node decoded_andMatrixOutputs_lo_hi_lo_209 = cat(decoded_andMatrixOutputs_andMatrixInput_11_209, decoded_andMatrixOutputs_andMatrixInput_12_209)
node decoded_andMatrixOutputs_lo_hi_hi_209 = cat(decoded_andMatrixOutputs_andMatrixInput_9_209, decoded_andMatrixOutputs_andMatrixInput_10_209)
node decoded_andMatrixOutputs_lo_hi_213 = cat(decoded_andMatrixOutputs_lo_hi_hi_209, decoded_andMatrixOutputs_lo_hi_lo_209)
node decoded_andMatrixOutputs_lo_213 = cat(decoded_andMatrixOutputs_lo_hi_213, decoded_andMatrixOutputs_lo_lo_213)
node decoded_andMatrixOutputs_hi_lo_lo_209 = cat(decoded_andMatrixOutputs_andMatrixInput_7_213, decoded_andMatrixOutputs_andMatrixInput_8_212)
node decoded_andMatrixOutputs_hi_lo_hi_209 = cat(decoded_andMatrixOutputs_andMatrixInput_5_213, decoded_andMatrixOutputs_andMatrixInput_6_213)
node decoded_andMatrixOutputs_hi_lo_213 = cat(decoded_andMatrixOutputs_hi_lo_hi_209, decoded_andMatrixOutputs_hi_lo_lo_209)
node decoded_andMatrixOutputs_hi_hi_lo_209 = cat(decoded_andMatrixOutputs_andMatrixInput_3_213, decoded_andMatrixOutputs_andMatrixInput_4_213)
node decoded_andMatrixOutputs_hi_hi_hi_hi_83 = cat(decoded_andMatrixOutputs_andMatrixInput_0_215, decoded_andMatrixOutputs_andMatrixInput_1_215)
node decoded_andMatrixOutputs_hi_hi_hi_212 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_83, decoded_andMatrixOutputs_andMatrixInput_2_215)
node decoded_andMatrixOutputs_hi_hi_213 = cat(decoded_andMatrixOutputs_hi_hi_hi_212, decoded_andMatrixOutputs_hi_hi_lo_209)
node decoded_andMatrixOutputs_hi_215 = cat(decoded_andMatrixOutputs_hi_hi_213, decoded_andMatrixOutputs_hi_lo_213)
node _decoded_andMatrixOutputs_T_215 = cat(decoded_andMatrixOutputs_hi_215, decoded_andMatrixOutputs_lo_213)
node decoded_andMatrixOutputs_52_2_2 = andr(_decoded_andMatrixOutputs_T_215)
node decoded_andMatrixOutputs_andMatrixInput_0_216 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_216 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_216 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_214 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_214 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_214 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_214 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_214 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_213 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_210 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_210 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_210 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_210 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_210 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_210 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_132 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_84 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_132 = cat(decoded_andMatrixOutputs_andMatrixInput_15_132, decoded_andMatrixOutputs_andMatrixInput_16_84)
node decoded_andMatrixOutputs_lo_lo_hi_210 = cat(decoded_andMatrixOutputs_andMatrixInput_13_210, decoded_andMatrixOutputs_andMatrixInput_14_210)
node decoded_andMatrixOutputs_lo_lo_214 = cat(decoded_andMatrixOutputs_lo_lo_hi_210, decoded_andMatrixOutputs_lo_lo_lo_132)
node decoded_andMatrixOutputs_lo_hi_lo_210 = cat(decoded_andMatrixOutputs_andMatrixInput_11_210, decoded_andMatrixOutputs_andMatrixInput_12_210)
node decoded_andMatrixOutputs_lo_hi_hi_210 = cat(decoded_andMatrixOutputs_andMatrixInput_9_210, decoded_andMatrixOutputs_andMatrixInput_10_210)
node decoded_andMatrixOutputs_lo_hi_214 = cat(decoded_andMatrixOutputs_lo_hi_hi_210, decoded_andMatrixOutputs_lo_hi_lo_210)
node decoded_andMatrixOutputs_lo_214 = cat(decoded_andMatrixOutputs_lo_hi_214, decoded_andMatrixOutputs_lo_lo_214)
node decoded_andMatrixOutputs_hi_lo_lo_210 = cat(decoded_andMatrixOutputs_andMatrixInput_7_214, decoded_andMatrixOutputs_andMatrixInput_8_213)
node decoded_andMatrixOutputs_hi_lo_hi_210 = cat(decoded_andMatrixOutputs_andMatrixInput_5_214, decoded_andMatrixOutputs_andMatrixInput_6_214)
node decoded_andMatrixOutputs_hi_lo_214 = cat(decoded_andMatrixOutputs_hi_lo_hi_210, decoded_andMatrixOutputs_hi_lo_lo_210)
node decoded_andMatrixOutputs_hi_hi_lo_210 = cat(decoded_andMatrixOutputs_andMatrixInput_3_214, decoded_andMatrixOutputs_andMatrixInput_4_214)
node decoded_andMatrixOutputs_hi_hi_hi_hi_84 = cat(decoded_andMatrixOutputs_andMatrixInput_0_216, decoded_andMatrixOutputs_andMatrixInput_1_216)
node decoded_andMatrixOutputs_hi_hi_hi_213 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_84, decoded_andMatrixOutputs_andMatrixInput_2_216)
node decoded_andMatrixOutputs_hi_hi_214 = cat(decoded_andMatrixOutputs_hi_hi_hi_213, decoded_andMatrixOutputs_hi_hi_lo_210)
node decoded_andMatrixOutputs_hi_216 = cat(decoded_andMatrixOutputs_hi_hi_214, decoded_andMatrixOutputs_hi_lo_214)
node _decoded_andMatrixOutputs_T_216 = cat(decoded_andMatrixOutputs_hi_216, decoded_andMatrixOutputs_lo_214)
node decoded_andMatrixOutputs_44_2_2 = andr(_decoded_andMatrixOutputs_T_216)
node decoded_andMatrixOutputs_andMatrixInput_0_217 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_217 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_217 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_215 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_215 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_215 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_215 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_215 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_214 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_211 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_211 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_211 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_211 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_211 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_211 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_133 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_85 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_133 = cat(decoded_andMatrixOutputs_andMatrixInput_15_133, decoded_andMatrixOutputs_andMatrixInput_16_85)
node decoded_andMatrixOutputs_lo_lo_hi_211 = cat(decoded_andMatrixOutputs_andMatrixInput_13_211, decoded_andMatrixOutputs_andMatrixInput_14_211)
node decoded_andMatrixOutputs_lo_lo_215 = cat(decoded_andMatrixOutputs_lo_lo_hi_211, decoded_andMatrixOutputs_lo_lo_lo_133)
node decoded_andMatrixOutputs_lo_hi_lo_211 = cat(decoded_andMatrixOutputs_andMatrixInput_11_211, decoded_andMatrixOutputs_andMatrixInput_12_211)
node decoded_andMatrixOutputs_lo_hi_hi_211 = cat(decoded_andMatrixOutputs_andMatrixInput_9_211, decoded_andMatrixOutputs_andMatrixInput_10_211)
node decoded_andMatrixOutputs_lo_hi_215 = cat(decoded_andMatrixOutputs_lo_hi_hi_211, decoded_andMatrixOutputs_lo_hi_lo_211)
node decoded_andMatrixOutputs_lo_215 = cat(decoded_andMatrixOutputs_lo_hi_215, decoded_andMatrixOutputs_lo_lo_215)
node decoded_andMatrixOutputs_hi_lo_lo_211 = cat(decoded_andMatrixOutputs_andMatrixInput_7_215, decoded_andMatrixOutputs_andMatrixInput_8_214)
node decoded_andMatrixOutputs_hi_lo_hi_211 = cat(decoded_andMatrixOutputs_andMatrixInput_5_215, decoded_andMatrixOutputs_andMatrixInput_6_215)
node decoded_andMatrixOutputs_hi_lo_215 = cat(decoded_andMatrixOutputs_hi_lo_hi_211, decoded_andMatrixOutputs_hi_lo_lo_211)
node decoded_andMatrixOutputs_hi_hi_lo_211 = cat(decoded_andMatrixOutputs_andMatrixInput_3_215, decoded_andMatrixOutputs_andMatrixInput_4_215)
node decoded_andMatrixOutputs_hi_hi_hi_hi_85 = cat(decoded_andMatrixOutputs_andMatrixInput_0_217, decoded_andMatrixOutputs_andMatrixInput_1_217)
node decoded_andMatrixOutputs_hi_hi_hi_214 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_85, decoded_andMatrixOutputs_andMatrixInput_2_217)
node decoded_andMatrixOutputs_hi_hi_215 = cat(decoded_andMatrixOutputs_hi_hi_hi_214, decoded_andMatrixOutputs_hi_hi_lo_211)
node decoded_andMatrixOutputs_hi_217 = cat(decoded_andMatrixOutputs_hi_hi_215, decoded_andMatrixOutputs_hi_lo_215)
node _decoded_andMatrixOutputs_T_217 = cat(decoded_andMatrixOutputs_hi_217, decoded_andMatrixOutputs_lo_215)
node decoded_andMatrixOutputs_39_2_3 = andr(_decoded_andMatrixOutputs_T_217)
node decoded_andMatrixOutputs_andMatrixInput_0_218 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_218 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_218 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_216 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_216 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_216 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_216 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_216 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_215 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_212 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_212 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_212 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_212 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_212 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_212 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_134 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_86 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_134 = cat(decoded_andMatrixOutputs_andMatrixInput_15_134, decoded_andMatrixOutputs_andMatrixInput_16_86)
node decoded_andMatrixOutputs_lo_lo_hi_212 = cat(decoded_andMatrixOutputs_andMatrixInput_13_212, decoded_andMatrixOutputs_andMatrixInput_14_212)
node decoded_andMatrixOutputs_lo_lo_216 = cat(decoded_andMatrixOutputs_lo_lo_hi_212, decoded_andMatrixOutputs_lo_lo_lo_134)
node decoded_andMatrixOutputs_lo_hi_lo_212 = cat(decoded_andMatrixOutputs_andMatrixInput_11_212, decoded_andMatrixOutputs_andMatrixInput_12_212)
node decoded_andMatrixOutputs_lo_hi_hi_212 = cat(decoded_andMatrixOutputs_andMatrixInput_9_212, decoded_andMatrixOutputs_andMatrixInput_10_212)
node decoded_andMatrixOutputs_lo_hi_216 = cat(decoded_andMatrixOutputs_lo_hi_hi_212, decoded_andMatrixOutputs_lo_hi_lo_212)
node decoded_andMatrixOutputs_lo_216 = cat(decoded_andMatrixOutputs_lo_hi_216, decoded_andMatrixOutputs_lo_lo_216)
node decoded_andMatrixOutputs_hi_lo_lo_212 = cat(decoded_andMatrixOutputs_andMatrixInput_7_216, decoded_andMatrixOutputs_andMatrixInput_8_215)
node decoded_andMatrixOutputs_hi_lo_hi_212 = cat(decoded_andMatrixOutputs_andMatrixInput_5_216, decoded_andMatrixOutputs_andMatrixInput_6_216)
node decoded_andMatrixOutputs_hi_lo_216 = cat(decoded_andMatrixOutputs_hi_lo_hi_212, decoded_andMatrixOutputs_hi_lo_lo_212)
node decoded_andMatrixOutputs_hi_hi_lo_212 = cat(decoded_andMatrixOutputs_andMatrixInput_3_216, decoded_andMatrixOutputs_andMatrixInput_4_216)
node decoded_andMatrixOutputs_hi_hi_hi_hi_86 = cat(decoded_andMatrixOutputs_andMatrixInput_0_218, decoded_andMatrixOutputs_andMatrixInput_1_218)
node decoded_andMatrixOutputs_hi_hi_hi_215 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_86, decoded_andMatrixOutputs_andMatrixInput_2_218)
node decoded_andMatrixOutputs_hi_hi_216 = cat(decoded_andMatrixOutputs_hi_hi_hi_215, decoded_andMatrixOutputs_hi_hi_lo_212)
node decoded_andMatrixOutputs_hi_218 = cat(decoded_andMatrixOutputs_hi_hi_216, decoded_andMatrixOutputs_hi_lo_216)
node _decoded_andMatrixOutputs_T_218 = cat(decoded_andMatrixOutputs_hi_218, decoded_andMatrixOutputs_lo_216)
node decoded_andMatrixOutputs_24_2_3 = andr(_decoded_andMatrixOutputs_T_218)
node decoded_andMatrixOutputs_andMatrixInput_0_219 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_219 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_219 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_217 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_217 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_217 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_217 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_217 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_216 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_213 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_213 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_213 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_213 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_213 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_213 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_135 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_87 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_135 = cat(decoded_andMatrixOutputs_andMatrixInput_15_135, decoded_andMatrixOutputs_andMatrixInput_16_87)
node decoded_andMatrixOutputs_lo_lo_hi_213 = cat(decoded_andMatrixOutputs_andMatrixInput_13_213, decoded_andMatrixOutputs_andMatrixInput_14_213)
node decoded_andMatrixOutputs_lo_lo_217 = cat(decoded_andMatrixOutputs_lo_lo_hi_213, decoded_andMatrixOutputs_lo_lo_lo_135)
node decoded_andMatrixOutputs_lo_hi_lo_213 = cat(decoded_andMatrixOutputs_andMatrixInput_11_213, decoded_andMatrixOutputs_andMatrixInput_12_213)
node decoded_andMatrixOutputs_lo_hi_hi_213 = cat(decoded_andMatrixOutputs_andMatrixInput_9_213, decoded_andMatrixOutputs_andMatrixInput_10_213)
node decoded_andMatrixOutputs_lo_hi_217 = cat(decoded_andMatrixOutputs_lo_hi_hi_213, decoded_andMatrixOutputs_lo_hi_lo_213)
node decoded_andMatrixOutputs_lo_217 = cat(decoded_andMatrixOutputs_lo_hi_217, decoded_andMatrixOutputs_lo_lo_217)
node decoded_andMatrixOutputs_hi_lo_lo_213 = cat(decoded_andMatrixOutputs_andMatrixInput_7_217, decoded_andMatrixOutputs_andMatrixInput_8_216)
node decoded_andMatrixOutputs_hi_lo_hi_213 = cat(decoded_andMatrixOutputs_andMatrixInput_5_217, decoded_andMatrixOutputs_andMatrixInput_6_217)
node decoded_andMatrixOutputs_hi_lo_217 = cat(decoded_andMatrixOutputs_hi_lo_hi_213, decoded_andMatrixOutputs_hi_lo_lo_213)
node decoded_andMatrixOutputs_hi_hi_lo_213 = cat(decoded_andMatrixOutputs_andMatrixInput_3_217, decoded_andMatrixOutputs_andMatrixInput_4_217)
node decoded_andMatrixOutputs_hi_hi_hi_hi_87 = cat(decoded_andMatrixOutputs_andMatrixInput_0_219, decoded_andMatrixOutputs_andMatrixInput_1_219)
node decoded_andMatrixOutputs_hi_hi_hi_216 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_87, decoded_andMatrixOutputs_andMatrixInput_2_219)
node decoded_andMatrixOutputs_hi_hi_217 = cat(decoded_andMatrixOutputs_hi_hi_hi_216, decoded_andMatrixOutputs_hi_hi_lo_213)
node decoded_andMatrixOutputs_hi_219 = cat(decoded_andMatrixOutputs_hi_hi_217, decoded_andMatrixOutputs_hi_lo_217)
node _decoded_andMatrixOutputs_T_219 = cat(decoded_andMatrixOutputs_hi_219, decoded_andMatrixOutputs_lo_217)
node decoded_andMatrixOutputs_48_2_2 = andr(_decoded_andMatrixOutputs_T_219)
node decoded_andMatrixOutputs_andMatrixInput_0_220 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_220 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_220 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_218 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_218 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_218 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_218 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_218 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_217 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_214 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_214 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_214 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_214 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_214 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_214 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_136 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_88 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_136 = cat(decoded_andMatrixOutputs_andMatrixInput_15_136, decoded_andMatrixOutputs_andMatrixInput_16_88)
node decoded_andMatrixOutputs_lo_lo_hi_214 = cat(decoded_andMatrixOutputs_andMatrixInput_13_214, decoded_andMatrixOutputs_andMatrixInput_14_214)
node decoded_andMatrixOutputs_lo_lo_218 = cat(decoded_andMatrixOutputs_lo_lo_hi_214, decoded_andMatrixOutputs_lo_lo_lo_136)
node decoded_andMatrixOutputs_lo_hi_lo_214 = cat(decoded_andMatrixOutputs_andMatrixInput_11_214, decoded_andMatrixOutputs_andMatrixInput_12_214)
node decoded_andMatrixOutputs_lo_hi_hi_214 = cat(decoded_andMatrixOutputs_andMatrixInput_9_214, decoded_andMatrixOutputs_andMatrixInput_10_214)
node decoded_andMatrixOutputs_lo_hi_218 = cat(decoded_andMatrixOutputs_lo_hi_hi_214, decoded_andMatrixOutputs_lo_hi_lo_214)
node decoded_andMatrixOutputs_lo_218 = cat(decoded_andMatrixOutputs_lo_hi_218, decoded_andMatrixOutputs_lo_lo_218)
node decoded_andMatrixOutputs_hi_lo_lo_214 = cat(decoded_andMatrixOutputs_andMatrixInput_7_218, decoded_andMatrixOutputs_andMatrixInput_8_217)
node decoded_andMatrixOutputs_hi_lo_hi_214 = cat(decoded_andMatrixOutputs_andMatrixInput_5_218, decoded_andMatrixOutputs_andMatrixInput_6_218)
node decoded_andMatrixOutputs_hi_lo_218 = cat(decoded_andMatrixOutputs_hi_lo_hi_214, decoded_andMatrixOutputs_hi_lo_lo_214)
node decoded_andMatrixOutputs_hi_hi_lo_214 = cat(decoded_andMatrixOutputs_andMatrixInput_3_218, decoded_andMatrixOutputs_andMatrixInput_4_218)
node decoded_andMatrixOutputs_hi_hi_hi_hi_88 = cat(decoded_andMatrixOutputs_andMatrixInput_0_220, decoded_andMatrixOutputs_andMatrixInput_1_220)
node decoded_andMatrixOutputs_hi_hi_hi_217 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_88, decoded_andMatrixOutputs_andMatrixInput_2_220)
node decoded_andMatrixOutputs_hi_hi_218 = cat(decoded_andMatrixOutputs_hi_hi_hi_217, decoded_andMatrixOutputs_hi_hi_lo_214)
node decoded_andMatrixOutputs_hi_220 = cat(decoded_andMatrixOutputs_hi_hi_218, decoded_andMatrixOutputs_hi_lo_218)
node _decoded_andMatrixOutputs_T_220 = cat(decoded_andMatrixOutputs_hi_220, decoded_andMatrixOutputs_lo_218)
node decoded_andMatrixOutputs_29_2_3 = andr(_decoded_andMatrixOutputs_T_220)
node decoded_andMatrixOutputs_andMatrixInput_0_221 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_221 = bits(decoded_invInputs_3, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_221 = bits(decoded_plaInput_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_219 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_219 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_219 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_219 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_219 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_218 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_215 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_215 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_215 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_215 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_215 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_215 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_137 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_89 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_137 = cat(decoded_andMatrixOutputs_andMatrixInput_15_137, decoded_andMatrixOutputs_andMatrixInput_16_89)
node decoded_andMatrixOutputs_lo_lo_hi_215 = cat(decoded_andMatrixOutputs_andMatrixInput_13_215, decoded_andMatrixOutputs_andMatrixInput_14_215)
node decoded_andMatrixOutputs_lo_lo_219 = cat(decoded_andMatrixOutputs_lo_lo_hi_215, decoded_andMatrixOutputs_lo_lo_lo_137)
node decoded_andMatrixOutputs_lo_hi_lo_215 = cat(decoded_andMatrixOutputs_andMatrixInput_11_215, decoded_andMatrixOutputs_andMatrixInput_12_215)
node decoded_andMatrixOutputs_lo_hi_hi_215 = cat(decoded_andMatrixOutputs_andMatrixInput_9_215, decoded_andMatrixOutputs_andMatrixInput_10_215)
node decoded_andMatrixOutputs_lo_hi_219 = cat(decoded_andMatrixOutputs_lo_hi_hi_215, decoded_andMatrixOutputs_lo_hi_lo_215)
node decoded_andMatrixOutputs_lo_219 = cat(decoded_andMatrixOutputs_lo_hi_219, decoded_andMatrixOutputs_lo_lo_219)
node decoded_andMatrixOutputs_hi_lo_lo_215 = cat(decoded_andMatrixOutputs_andMatrixInput_7_219, decoded_andMatrixOutputs_andMatrixInput_8_218)
node decoded_andMatrixOutputs_hi_lo_hi_215 = cat(decoded_andMatrixOutputs_andMatrixInput_5_219, decoded_andMatrixOutputs_andMatrixInput_6_219)
node decoded_andMatrixOutputs_hi_lo_219 = cat(decoded_andMatrixOutputs_hi_lo_hi_215, decoded_andMatrixOutputs_hi_lo_lo_215)
node decoded_andMatrixOutputs_hi_hi_lo_215 = cat(decoded_andMatrixOutputs_andMatrixInput_3_219, decoded_andMatrixOutputs_andMatrixInput_4_219)
node decoded_andMatrixOutputs_hi_hi_hi_hi_89 = cat(decoded_andMatrixOutputs_andMatrixInput_0_221, decoded_andMatrixOutputs_andMatrixInput_1_221)
node decoded_andMatrixOutputs_hi_hi_hi_218 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_89, decoded_andMatrixOutputs_andMatrixInput_2_221)
node decoded_andMatrixOutputs_hi_hi_219 = cat(decoded_andMatrixOutputs_hi_hi_hi_218, decoded_andMatrixOutputs_hi_hi_lo_215)
node decoded_andMatrixOutputs_hi_221 = cat(decoded_andMatrixOutputs_hi_hi_219, decoded_andMatrixOutputs_hi_lo_219)
node _decoded_andMatrixOutputs_T_221 = cat(decoded_andMatrixOutputs_hi_221, decoded_andMatrixOutputs_lo_219)
node decoded_andMatrixOutputs_8_2_3 = andr(_decoded_andMatrixOutputs_T_221)
node decoded_andMatrixOutputs_andMatrixInput_0_222 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_222 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_222 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_220 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_220 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_220 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_220 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_220 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_219 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_216 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_216 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_216 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_216 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_216 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_216 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_138 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_90 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_138 = cat(decoded_andMatrixOutputs_andMatrixInput_15_138, decoded_andMatrixOutputs_andMatrixInput_16_90)
node decoded_andMatrixOutputs_lo_lo_hi_216 = cat(decoded_andMatrixOutputs_andMatrixInput_13_216, decoded_andMatrixOutputs_andMatrixInput_14_216)
node decoded_andMatrixOutputs_lo_lo_220 = cat(decoded_andMatrixOutputs_lo_lo_hi_216, decoded_andMatrixOutputs_lo_lo_lo_138)
node decoded_andMatrixOutputs_lo_hi_lo_216 = cat(decoded_andMatrixOutputs_andMatrixInput_11_216, decoded_andMatrixOutputs_andMatrixInput_12_216)
node decoded_andMatrixOutputs_lo_hi_hi_216 = cat(decoded_andMatrixOutputs_andMatrixInput_9_216, decoded_andMatrixOutputs_andMatrixInput_10_216)
node decoded_andMatrixOutputs_lo_hi_220 = cat(decoded_andMatrixOutputs_lo_hi_hi_216, decoded_andMatrixOutputs_lo_hi_lo_216)
node decoded_andMatrixOutputs_lo_220 = cat(decoded_andMatrixOutputs_lo_hi_220, decoded_andMatrixOutputs_lo_lo_220)
node decoded_andMatrixOutputs_hi_lo_lo_216 = cat(decoded_andMatrixOutputs_andMatrixInput_7_220, decoded_andMatrixOutputs_andMatrixInput_8_219)
node decoded_andMatrixOutputs_hi_lo_hi_216 = cat(decoded_andMatrixOutputs_andMatrixInput_5_220, decoded_andMatrixOutputs_andMatrixInput_6_220)
node decoded_andMatrixOutputs_hi_lo_220 = cat(decoded_andMatrixOutputs_hi_lo_hi_216, decoded_andMatrixOutputs_hi_lo_lo_216)
node decoded_andMatrixOutputs_hi_hi_lo_216 = cat(decoded_andMatrixOutputs_andMatrixInput_3_220, decoded_andMatrixOutputs_andMatrixInput_4_220)
node decoded_andMatrixOutputs_hi_hi_hi_hi_90 = cat(decoded_andMatrixOutputs_andMatrixInput_0_222, decoded_andMatrixOutputs_andMatrixInput_1_222)
node decoded_andMatrixOutputs_hi_hi_hi_219 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_90, decoded_andMatrixOutputs_andMatrixInput_2_222)
node decoded_andMatrixOutputs_hi_hi_220 = cat(decoded_andMatrixOutputs_hi_hi_hi_219, decoded_andMatrixOutputs_hi_hi_lo_216)
node decoded_andMatrixOutputs_hi_222 = cat(decoded_andMatrixOutputs_hi_hi_220, decoded_andMatrixOutputs_hi_lo_220)
node _decoded_andMatrixOutputs_T_222 = cat(decoded_andMatrixOutputs_hi_222, decoded_andMatrixOutputs_lo_220)
node decoded_andMatrixOutputs_31_2_3 = andr(_decoded_andMatrixOutputs_T_222)
node decoded_andMatrixOutputs_andMatrixInput_0_223 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_223 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_223 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_221 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_221 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_221 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_221 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_221 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_220 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_217 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_217 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_217 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_217 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_217 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_14_217 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_217 = cat(decoded_andMatrixOutputs_andMatrixInput_12_217, decoded_andMatrixOutputs_andMatrixInput_13_217)
node decoded_andMatrixOutputs_lo_lo_221 = cat(decoded_andMatrixOutputs_lo_lo_hi_217, decoded_andMatrixOutputs_andMatrixInput_14_217)
node decoded_andMatrixOutputs_lo_hi_lo_217 = cat(decoded_andMatrixOutputs_andMatrixInput_10_217, decoded_andMatrixOutputs_andMatrixInput_11_217)
node decoded_andMatrixOutputs_lo_hi_hi_217 = cat(decoded_andMatrixOutputs_andMatrixInput_8_220, decoded_andMatrixOutputs_andMatrixInput_9_217)
node decoded_andMatrixOutputs_lo_hi_221 = cat(decoded_andMatrixOutputs_lo_hi_hi_217, decoded_andMatrixOutputs_lo_hi_lo_217)
node decoded_andMatrixOutputs_lo_221 = cat(decoded_andMatrixOutputs_lo_hi_221, decoded_andMatrixOutputs_lo_lo_221)
node decoded_andMatrixOutputs_hi_lo_lo_217 = cat(decoded_andMatrixOutputs_andMatrixInput_6_221, decoded_andMatrixOutputs_andMatrixInput_7_221)
node decoded_andMatrixOutputs_hi_lo_hi_217 = cat(decoded_andMatrixOutputs_andMatrixInput_4_221, decoded_andMatrixOutputs_andMatrixInput_5_221)
node decoded_andMatrixOutputs_hi_lo_221 = cat(decoded_andMatrixOutputs_hi_lo_hi_217, decoded_andMatrixOutputs_hi_lo_lo_217)
node decoded_andMatrixOutputs_hi_hi_lo_217 = cat(decoded_andMatrixOutputs_andMatrixInput_2_223, decoded_andMatrixOutputs_andMatrixInput_3_221)
node decoded_andMatrixOutputs_hi_hi_hi_220 = cat(decoded_andMatrixOutputs_andMatrixInput_0_223, decoded_andMatrixOutputs_andMatrixInput_1_223)
node decoded_andMatrixOutputs_hi_hi_221 = cat(decoded_andMatrixOutputs_hi_hi_hi_220, decoded_andMatrixOutputs_hi_hi_lo_217)
node decoded_andMatrixOutputs_hi_223 = cat(decoded_andMatrixOutputs_hi_hi_221, decoded_andMatrixOutputs_hi_lo_221)
node _decoded_andMatrixOutputs_T_223 = cat(decoded_andMatrixOutputs_hi_223, decoded_andMatrixOutputs_lo_221)
node decoded_andMatrixOutputs_38_2_3 = andr(_decoded_andMatrixOutputs_T_223)
node decoded_andMatrixOutputs_andMatrixInput_0_224 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_224 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_224 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_222 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_222 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_222 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_222 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_222 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_221 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_218 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_218 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_218 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_218 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_218 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_218 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_139 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_91 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_139 = cat(decoded_andMatrixOutputs_andMatrixInput_15_139, decoded_andMatrixOutputs_andMatrixInput_16_91)
node decoded_andMatrixOutputs_lo_lo_hi_218 = cat(decoded_andMatrixOutputs_andMatrixInput_13_218, decoded_andMatrixOutputs_andMatrixInput_14_218)
node decoded_andMatrixOutputs_lo_lo_222 = cat(decoded_andMatrixOutputs_lo_lo_hi_218, decoded_andMatrixOutputs_lo_lo_lo_139)
node decoded_andMatrixOutputs_lo_hi_lo_218 = cat(decoded_andMatrixOutputs_andMatrixInput_11_218, decoded_andMatrixOutputs_andMatrixInput_12_218)
node decoded_andMatrixOutputs_lo_hi_hi_218 = cat(decoded_andMatrixOutputs_andMatrixInput_9_218, decoded_andMatrixOutputs_andMatrixInput_10_218)
node decoded_andMatrixOutputs_lo_hi_222 = cat(decoded_andMatrixOutputs_lo_hi_hi_218, decoded_andMatrixOutputs_lo_hi_lo_218)
node decoded_andMatrixOutputs_lo_222 = cat(decoded_andMatrixOutputs_lo_hi_222, decoded_andMatrixOutputs_lo_lo_222)
node decoded_andMatrixOutputs_hi_lo_lo_218 = cat(decoded_andMatrixOutputs_andMatrixInput_7_222, decoded_andMatrixOutputs_andMatrixInput_8_221)
node decoded_andMatrixOutputs_hi_lo_hi_218 = cat(decoded_andMatrixOutputs_andMatrixInput_5_222, decoded_andMatrixOutputs_andMatrixInput_6_222)
node decoded_andMatrixOutputs_hi_lo_222 = cat(decoded_andMatrixOutputs_hi_lo_hi_218, decoded_andMatrixOutputs_hi_lo_lo_218)
node decoded_andMatrixOutputs_hi_hi_lo_218 = cat(decoded_andMatrixOutputs_andMatrixInput_3_222, decoded_andMatrixOutputs_andMatrixInput_4_222)
node decoded_andMatrixOutputs_hi_hi_hi_hi_91 = cat(decoded_andMatrixOutputs_andMatrixInput_0_224, decoded_andMatrixOutputs_andMatrixInput_1_224)
node decoded_andMatrixOutputs_hi_hi_hi_221 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_91, decoded_andMatrixOutputs_andMatrixInput_2_224)
node decoded_andMatrixOutputs_hi_hi_222 = cat(decoded_andMatrixOutputs_hi_hi_hi_221, decoded_andMatrixOutputs_hi_hi_lo_218)
node decoded_andMatrixOutputs_hi_224 = cat(decoded_andMatrixOutputs_hi_hi_222, decoded_andMatrixOutputs_hi_lo_222)
node _decoded_andMatrixOutputs_T_224 = cat(decoded_andMatrixOutputs_hi_224, decoded_andMatrixOutputs_lo_222)
node decoded_andMatrixOutputs_19_2_3 = andr(_decoded_andMatrixOutputs_T_224)
node decoded_andMatrixOutputs_andMatrixInput_0_225 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_225 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_225 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_223 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_223 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_223 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_223 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_223 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_222 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_219 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_219 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_219 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_219 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_219 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_219 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_140 = bits(decoded_plaInput_3, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_92 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_140 = cat(decoded_andMatrixOutputs_andMatrixInput_15_140, decoded_andMatrixOutputs_andMatrixInput_16_92)
node decoded_andMatrixOutputs_lo_lo_hi_219 = cat(decoded_andMatrixOutputs_andMatrixInput_13_219, decoded_andMatrixOutputs_andMatrixInput_14_219)
node decoded_andMatrixOutputs_lo_lo_223 = cat(decoded_andMatrixOutputs_lo_lo_hi_219, decoded_andMatrixOutputs_lo_lo_lo_140)
node decoded_andMatrixOutputs_lo_hi_lo_219 = cat(decoded_andMatrixOutputs_andMatrixInput_11_219, decoded_andMatrixOutputs_andMatrixInput_12_219)
node decoded_andMatrixOutputs_lo_hi_hi_219 = cat(decoded_andMatrixOutputs_andMatrixInput_9_219, decoded_andMatrixOutputs_andMatrixInput_10_219)
node decoded_andMatrixOutputs_lo_hi_223 = cat(decoded_andMatrixOutputs_lo_hi_hi_219, decoded_andMatrixOutputs_lo_hi_lo_219)
node decoded_andMatrixOutputs_lo_223 = cat(decoded_andMatrixOutputs_lo_hi_223, decoded_andMatrixOutputs_lo_lo_223)
node decoded_andMatrixOutputs_hi_lo_lo_219 = cat(decoded_andMatrixOutputs_andMatrixInput_7_223, decoded_andMatrixOutputs_andMatrixInput_8_222)
node decoded_andMatrixOutputs_hi_lo_hi_219 = cat(decoded_andMatrixOutputs_andMatrixInput_5_223, decoded_andMatrixOutputs_andMatrixInput_6_223)
node decoded_andMatrixOutputs_hi_lo_223 = cat(decoded_andMatrixOutputs_hi_lo_hi_219, decoded_andMatrixOutputs_hi_lo_lo_219)
node decoded_andMatrixOutputs_hi_hi_lo_219 = cat(decoded_andMatrixOutputs_andMatrixInput_3_223, decoded_andMatrixOutputs_andMatrixInput_4_223)
node decoded_andMatrixOutputs_hi_hi_hi_hi_92 = cat(decoded_andMatrixOutputs_andMatrixInput_0_225, decoded_andMatrixOutputs_andMatrixInput_1_225)
node decoded_andMatrixOutputs_hi_hi_hi_222 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_92, decoded_andMatrixOutputs_andMatrixInput_2_225)
node decoded_andMatrixOutputs_hi_hi_223 = cat(decoded_andMatrixOutputs_hi_hi_hi_222, decoded_andMatrixOutputs_hi_hi_lo_219)
node decoded_andMatrixOutputs_hi_225 = cat(decoded_andMatrixOutputs_hi_hi_223, decoded_andMatrixOutputs_hi_lo_223)
node _decoded_andMatrixOutputs_T_225 = cat(decoded_andMatrixOutputs_hi_225, decoded_andMatrixOutputs_lo_223)
node decoded_andMatrixOutputs_34_2_3 = andr(_decoded_andMatrixOutputs_T_225)
node decoded_andMatrixOutputs_andMatrixInput_0_226 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_226 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_226 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_224 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_224 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_224 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_224 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_224 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_223 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_220 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_220 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_220 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_220 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_220 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_220 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_141 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_93 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_141 = cat(decoded_andMatrixOutputs_andMatrixInput_15_141, decoded_andMatrixOutputs_andMatrixInput_16_93)
node decoded_andMatrixOutputs_lo_lo_hi_220 = cat(decoded_andMatrixOutputs_andMatrixInput_13_220, decoded_andMatrixOutputs_andMatrixInput_14_220)
node decoded_andMatrixOutputs_lo_lo_224 = cat(decoded_andMatrixOutputs_lo_lo_hi_220, decoded_andMatrixOutputs_lo_lo_lo_141)
node decoded_andMatrixOutputs_lo_hi_lo_220 = cat(decoded_andMatrixOutputs_andMatrixInput_11_220, decoded_andMatrixOutputs_andMatrixInput_12_220)
node decoded_andMatrixOutputs_lo_hi_hi_220 = cat(decoded_andMatrixOutputs_andMatrixInput_9_220, decoded_andMatrixOutputs_andMatrixInput_10_220)
node decoded_andMatrixOutputs_lo_hi_224 = cat(decoded_andMatrixOutputs_lo_hi_hi_220, decoded_andMatrixOutputs_lo_hi_lo_220)
node decoded_andMatrixOutputs_lo_224 = cat(decoded_andMatrixOutputs_lo_hi_224, decoded_andMatrixOutputs_lo_lo_224)
node decoded_andMatrixOutputs_hi_lo_lo_220 = cat(decoded_andMatrixOutputs_andMatrixInput_7_224, decoded_andMatrixOutputs_andMatrixInput_8_223)
node decoded_andMatrixOutputs_hi_lo_hi_220 = cat(decoded_andMatrixOutputs_andMatrixInput_5_224, decoded_andMatrixOutputs_andMatrixInput_6_224)
node decoded_andMatrixOutputs_hi_lo_224 = cat(decoded_andMatrixOutputs_hi_lo_hi_220, decoded_andMatrixOutputs_hi_lo_lo_220)
node decoded_andMatrixOutputs_hi_hi_lo_220 = cat(decoded_andMatrixOutputs_andMatrixInput_3_224, decoded_andMatrixOutputs_andMatrixInput_4_224)
node decoded_andMatrixOutputs_hi_hi_hi_hi_93 = cat(decoded_andMatrixOutputs_andMatrixInput_0_226, decoded_andMatrixOutputs_andMatrixInput_1_226)
node decoded_andMatrixOutputs_hi_hi_hi_223 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_93, decoded_andMatrixOutputs_andMatrixInput_2_226)
node decoded_andMatrixOutputs_hi_hi_224 = cat(decoded_andMatrixOutputs_hi_hi_hi_223, decoded_andMatrixOutputs_hi_hi_lo_220)
node decoded_andMatrixOutputs_hi_226 = cat(decoded_andMatrixOutputs_hi_hi_224, decoded_andMatrixOutputs_hi_lo_224)
node _decoded_andMatrixOutputs_T_226 = cat(decoded_andMatrixOutputs_hi_226, decoded_andMatrixOutputs_lo_224)
node decoded_andMatrixOutputs_40_2_3 = andr(_decoded_andMatrixOutputs_T_226)
node decoded_andMatrixOutputs_andMatrixInput_0_227 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_227 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_2_227 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_3_225 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_4_225 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_5_225 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_6_225 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_7_225 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_8_224 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_9_221 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_10_221 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_11_221 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_12_221 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_13_221 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_14_221 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_hi_221 = cat(decoded_andMatrixOutputs_andMatrixInput_12_221, decoded_andMatrixOutputs_andMatrixInput_13_221)
node decoded_andMatrixOutputs_lo_lo_225 = cat(decoded_andMatrixOutputs_lo_lo_hi_221, decoded_andMatrixOutputs_andMatrixInput_14_221)
node decoded_andMatrixOutputs_lo_hi_lo_221 = cat(decoded_andMatrixOutputs_andMatrixInput_10_221, decoded_andMatrixOutputs_andMatrixInput_11_221)
node decoded_andMatrixOutputs_lo_hi_hi_221 = cat(decoded_andMatrixOutputs_andMatrixInput_8_224, decoded_andMatrixOutputs_andMatrixInput_9_221)
node decoded_andMatrixOutputs_lo_hi_225 = cat(decoded_andMatrixOutputs_lo_hi_hi_221, decoded_andMatrixOutputs_lo_hi_lo_221)
node decoded_andMatrixOutputs_lo_225 = cat(decoded_andMatrixOutputs_lo_hi_225, decoded_andMatrixOutputs_lo_lo_225)
node decoded_andMatrixOutputs_hi_lo_lo_221 = cat(decoded_andMatrixOutputs_andMatrixInput_6_225, decoded_andMatrixOutputs_andMatrixInput_7_225)
node decoded_andMatrixOutputs_hi_lo_hi_221 = cat(decoded_andMatrixOutputs_andMatrixInput_4_225, decoded_andMatrixOutputs_andMatrixInput_5_225)
node decoded_andMatrixOutputs_hi_lo_225 = cat(decoded_andMatrixOutputs_hi_lo_hi_221, decoded_andMatrixOutputs_hi_lo_lo_221)
node decoded_andMatrixOutputs_hi_hi_lo_221 = cat(decoded_andMatrixOutputs_andMatrixInput_2_227, decoded_andMatrixOutputs_andMatrixInput_3_225)
node decoded_andMatrixOutputs_hi_hi_hi_224 = cat(decoded_andMatrixOutputs_andMatrixInput_0_227, decoded_andMatrixOutputs_andMatrixInput_1_227)
node decoded_andMatrixOutputs_hi_hi_225 = cat(decoded_andMatrixOutputs_hi_hi_hi_224, decoded_andMatrixOutputs_hi_hi_lo_221)
node decoded_andMatrixOutputs_hi_227 = cat(decoded_andMatrixOutputs_hi_hi_225, decoded_andMatrixOutputs_hi_lo_225)
node _decoded_andMatrixOutputs_T_227 = cat(decoded_andMatrixOutputs_hi_227, decoded_andMatrixOutputs_lo_225)
node decoded_andMatrixOutputs_3_2_3 = andr(_decoded_andMatrixOutputs_T_227)
node decoded_andMatrixOutputs_andMatrixInput_0_228 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_228 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_228 = bits(decoded_invInputs_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_226 = bits(decoded_plaInput_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_226 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_226 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_226 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_226 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_225 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_222 = bits(decoded_plaInput_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_222 = bits(decoded_invInputs_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_222 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_222 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_222 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_222 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_142 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_94 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_142 = cat(decoded_andMatrixOutputs_andMatrixInput_15_142, decoded_andMatrixOutputs_andMatrixInput_16_94)
node decoded_andMatrixOutputs_lo_lo_hi_222 = cat(decoded_andMatrixOutputs_andMatrixInput_13_222, decoded_andMatrixOutputs_andMatrixInput_14_222)
node decoded_andMatrixOutputs_lo_lo_226 = cat(decoded_andMatrixOutputs_lo_lo_hi_222, decoded_andMatrixOutputs_lo_lo_lo_142)
node decoded_andMatrixOutputs_lo_hi_lo_222 = cat(decoded_andMatrixOutputs_andMatrixInput_11_222, decoded_andMatrixOutputs_andMatrixInput_12_222)
node decoded_andMatrixOutputs_lo_hi_hi_222 = cat(decoded_andMatrixOutputs_andMatrixInput_9_222, decoded_andMatrixOutputs_andMatrixInput_10_222)
node decoded_andMatrixOutputs_lo_hi_226 = cat(decoded_andMatrixOutputs_lo_hi_hi_222, decoded_andMatrixOutputs_lo_hi_lo_222)
node decoded_andMatrixOutputs_lo_226 = cat(decoded_andMatrixOutputs_lo_hi_226, decoded_andMatrixOutputs_lo_lo_226)
node decoded_andMatrixOutputs_hi_lo_lo_222 = cat(decoded_andMatrixOutputs_andMatrixInput_7_226, decoded_andMatrixOutputs_andMatrixInput_8_225)
node decoded_andMatrixOutputs_hi_lo_hi_222 = cat(decoded_andMatrixOutputs_andMatrixInput_5_226, decoded_andMatrixOutputs_andMatrixInput_6_226)
node decoded_andMatrixOutputs_hi_lo_226 = cat(decoded_andMatrixOutputs_hi_lo_hi_222, decoded_andMatrixOutputs_hi_lo_lo_222)
node decoded_andMatrixOutputs_hi_hi_lo_222 = cat(decoded_andMatrixOutputs_andMatrixInput_3_226, decoded_andMatrixOutputs_andMatrixInput_4_226)
node decoded_andMatrixOutputs_hi_hi_hi_hi_94 = cat(decoded_andMatrixOutputs_andMatrixInput_0_228, decoded_andMatrixOutputs_andMatrixInput_1_228)
node decoded_andMatrixOutputs_hi_hi_hi_225 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_94, decoded_andMatrixOutputs_andMatrixInput_2_228)
node decoded_andMatrixOutputs_hi_hi_226 = cat(decoded_andMatrixOutputs_hi_hi_hi_225, decoded_andMatrixOutputs_hi_hi_lo_222)
node decoded_andMatrixOutputs_hi_228 = cat(decoded_andMatrixOutputs_hi_hi_226, decoded_andMatrixOutputs_hi_lo_226)
node _decoded_andMatrixOutputs_T_228 = cat(decoded_andMatrixOutputs_hi_228, decoded_andMatrixOutputs_lo_226)
node decoded_andMatrixOutputs_41_2_3 = andr(_decoded_andMatrixOutputs_T_228)
node decoded_andMatrixOutputs_andMatrixInput_0_229 = bits(decoded_invInputs_3, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_229 = bits(decoded_invInputs_3, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_229 = bits(decoded_plaInput_3, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_227 = bits(decoded_invInputs_3, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_227 = bits(decoded_invInputs_3, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_227 = bits(decoded_invInputs_3, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_227 = bits(decoded_invInputs_3, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_227 = bits(decoded_plaInput_3, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_226 = bits(decoded_plaInput_3, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_223 = bits(decoded_invInputs_3, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_223 = bits(decoded_plaInput_3, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_223 = bits(decoded_invInputs_3, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_223 = bits(decoded_invInputs_3, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_223 = bits(decoded_invInputs_3, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_223 = bits(decoded_plaInput_3, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_143 = bits(decoded_plaInput_3, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_95 = bits(decoded_plaInput_3, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_143 = cat(decoded_andMatrixOutputs_andMatrixInput_15_143, decoded_andMatrixOutputs_andMatrixInput_16_95)
node decoded_andMatrixOutputs_lo_lo_hi_223 = cat(decoded_andMatrixOutputs_andMatrixInput_13_223, decoded_andMatrixOutputs_andMatrixInput_14_223)
node decoded_andMatrixOutputs_lo_lo_227 = cat(decoded_andMatrixOutputs_lo_lo_hi_223, decoded_andMatrixOutputs_lo_lo_lo_143)
node decoded_andMatrixOutputs_lo_hi_lo_223 = cat(decoded_andMatrixOutputs_andMatrixInput_11_223, decoded_andMatrixOutputs_andMatrixInput_12_223)
node decoded_andMatrixOutputs_lo_hi_hi_223 = cat(decoded_andMatrixOutputs_andMatrixInput_9_223, decoded_andMatrixOutputs_andMatrixInput_10_223)
node decoded_andMatrixOutputs_lo_hi_227 = cat(decoded_andMatrixOutputs_lo_hi_hi_223, decoded_andMatrixOutputs_lo_hi_lo_223)
node decoded_andMatrixOutputs_lo_227 = cat(decoded_andMatrixOutputs_lo_hi_227, decoded_andMatrixOutputs_lo_lo_227)
node decoded_andMatrixOutputs_hi_lo_lo_223 = cat(decoded_andMatrixOutputs_andMatrixInput_7_227, decoded_andMatrixOutputs_andMatrixInput_8_226)
node decoded_andMatrixOutputs_hi_lo_hi_223 = cat(decoded_andMatrixOutputs_andMatrixInput_5_227, decoded_andMatrixOutputs_andMatrixInput_6_227)
node decoded_andMatrixOutputs_hi_lo_227 = cat(decoded_andMatrixOutputs_hi_lo_hi_223, decoded_andMatrixOutputs_hi_lo_lo_223)
node decoded_andMatrixOutputs_hi_hi_lo_223 = cat(decoded_andMatrixOutputs_andMatrixInput_3_227, decoded_andMatrixOutputs_andMatrixInput_4_227)
node decoded_andMatrixOutputs_hi_hi_hi_hi_95 = cat(decoded_andMatrixOutputs_andMatrixInput_0_229, decoded_andMatrixOutputs_andMatrixInput_1_229)
node decoded_andMatrixOutputs_hi_hi_hi_226 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_95, decoded_andMatrixOutputs_andMatrixInput_2_229)
node decoded_andMatrixOutputs_hi_hi_227 = cat(decoded_andMatrixOutputs_hi_hi_hi_226, decoded_andMatrixOutputs_hi_hi_lo_223)
node decoded_andMatrixOutputs_hi_229 = cat(decoded_andMatrixOutputs_hi_hi_227, decoded_andMatrixOutputs_hi_lo_227)
node _decoded_andMatrixOutputs_T_229 = cat(decoded_andMatrixOutputs_hi_229, decoded_andMatrixOutputs_lo_227)
node decoded_andMatrixOutputs_45_2_2 = andr(_decoded_andMatrixOutputs_T_229)
node decoded_orMatrixOutputs_lo_lo_56 = cat(decoded_andMatrixOutputs_38_2_3, decoded_andMatrixOutputs_3_2_3)
node decoded_orMatrixOutputs_lo_hi_63 = cat(decoded_andMatrixOutputs_11_2_3, decoded_andMatrixOutputs_49_2_2)
node decoded_orMatrixOutputs_lo_74 = cat(decoded_orMatrixOutputs_lo_hi_63, decoded_orMatrixOutputs_lo_lo_56)
node decoded_orMatrixOutputs_hi_lo_56 = cat(decoded_andMatrixOutputs_32_2_3, decoded_andMatrixOutputs_36_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_51 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_7_2_3)
node decoded_orMatrixOutputs_hi_hi_73 = cat(decoded_orMatrixOutputs_hi_hi_hi_51, decoded_andMatrixOutputs_47_2_2)
node decoded_orMatrixOutputs_hi_80 = cat(decoded_orMatrixOutputs_hi_hi_73, decoded_orMatrixOutputs_hi_lo_56)
node _decoded_orMatrixOutputs_T_163 = cat(decoded_orMatrixOutputs_hi_80, decoded_orMatrixOutputs_lo_74)
node _decoded_orMatrixOutputs_T_164 = orr(_decoded_orMatrixOutputs_T_163)
node decoded_orMatrixOutputs_lo_lo_57 = cat(decoded_andMatrixOutputs_38_2_3, decoded_andMatrixOutputs_3_2_3)
node decoded_orMatrixOutputs_lo_hi_64 = cat(decoded_andMatrixOutputs_11_2_3, decoded_andMatrixOutputs_49_2_2)
node decoded_orMatrixOutputs_lo_75 = cat(decoded_orMatrixOutputs_lo_hi_64, decoded_orMatrixOutputs_lo_lo_57)
node decoded_orMatrixOutputs_hi_lo_57 = cat(decoded_andMatrixOutputs_32_2_3, decoded_andMatrixOutputs_36_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_52 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_7_2_3)
node decoded_orMatrixOutputs_hi_hi_74 = cat(decoded_orMatrixOutputs_hi_hi_hi_52, decoded_andMatrixOutputs_47_2_2)
node decoded_orMatrixOutputs_hi_81 = cat(decoded_orMatrixOutputs_hi_hi_74, decoded_orMatrixOutputs_hi_lo_57)
node _decoded_orMatrixOutputs_T_165 = cat(decoded_orMatrixOutputs_hi_81, decoded_orMatrixOutputs_lo_75)
node _decoded_orMatrixOutputs_T_166 = orr(_decoded_orMatrixOutputs_T_165)
node decoded_orMatrixOutputs_lo_lo_58 = cat(decoded_andMatrixOutputs_38_2_3, decoded_andMatrixOutputs_3_2_3)
node decoded_orMatrixOutputs_lo_hi_65 = cat(decoded_andMatrixOutputs_11_2_3, decoded_andMatrixOutputs_49_2_2)
node decoded_orMatrixOutputs_lo_76 = cat(decoded_orMatrixOutputs_lo_hi_65, decoded_orMatrixOutputs_lo_lo_58)
node decoded_orMatrixOutputs_hi_lo_58 = cat(decoded_andMatrixOutputs_32_2_3, decoded_andMatrixOutputs_36_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_53 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_7_2_3)
node decoded_orMatrixOutputs_hi_hi_75 = cat(decoded_orMatrixOutputs_hi_hi_hi_53, decoded_andMatrixOutputs_47_2_2)
node decoded_orMatrixOutputs_hi_82 = cat(decoded_orMatrixOutputs_hi_hi_75, decoded_orMatrixOutputs_hi_lo_58)
node _decoded_orMatrixOutputs_T_167 = cat(decoded_orMatrixOutputs_hi_82, decoded_orMatrixOutputs_lo_76)
node _decoded_orMatrixOutputs_T_168 = orr(_decoded_orMatrixOutputs_T_167)
node decoded_orMatrixOutputs_lo_lo_59 = cat(decoded_andMatrixOutputs_49_2_2, decoded_andMatrixOutputs_48_2_2)
node decoded_orMatrixOutputs_lo_hi_66 = cat(decoded_andMatrixOutputs_36_2_3, decoded_andMatrixOutputs_11_2_3)
node decoded_orMatrixOutputs_lo_77 = cat(decoded_orMatrixOutputs_lo_hi_66, decoded_orMatrixOutputs_lo_lo_59)
node decoded_orMatrixOutputs_hi_lo_59 = cat(decoded_andMatrixOutputs_47_2_2, decoded_andMatrixOutputs_32_2_3)
node decoded_orMatrixOutputs_hi_hi_76 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_7_2_3)
node decoded_orMatrixOutputs_hi_83 = cat(decoded_orMatrixOutputs_hi_hi_76, decoded_orMatrixOutputs_hi_lo_59)
node _decoded_orMatrixOutputs_T_169 = cat(decoded_orMatrixOutputs_hi_83, decoded_orMatrixOutputs_lo_77)
node _decoded_orMatrixOutputs_T_170 = orr(_decoded_orMatrixOutputs_T_169)
node decoded_orMatrixOutputs_lo_hi_67 = cat(decoded_andMatrixOutputs_36_2_3, decoded_andMatrixOutputs_11_2_3)
node decoded_orMatrixOutputs_lo_78 = cat(decoded_orMatrixOutputs_lo_hi_67, decoded_andMatrixOutputs_49_2_2)
node decoded_orMatrixOutputs_hi_lo_60 = cat(decoded_andMatrixOutputs_47_2_2, decoded_andMatrixOutputs_32_2_3)
node decoded_orMatrixOutputs_hi_hi_77 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_7_2_3)
node decoded_orMatrixOutputs_hi_84 = cat(decoded_orMatrixOutputs_hi_hi_77, decoded_orMatrixOutputs_hi_lo_60)
node _decoded_orMatrixOutputs_T_171 = cat(decoded_orMatrixOutputs_hi_84, decoded_orMatrixOutputs_lo_78)
node _decoded_orMatrixOutputs_T_172 = orr(_decoded_orMatrixOutputs_T_171)
node decoded_orMatrixOutputs_lo_hi_68 = cat(decoded_andMatrixOutputs_36_2_3, decoded_andMatrixOutputs_11_2_3)
node decoded_orMatrixOutputs_lo_79 = cat(decoded_orMatrixOutputs_lo_hi_68, decoded_andMatrixOutputs_23_2_3)
node decoded_orMatrixOutputs_hi_lo_61 = cat(decoded_andMatrixOutputs_47_2_2, decoded_andMatrixOutputs_25_2_3)
node decoded_orMatrixOutputs_hi_hi_78 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_7_2_3)
node decoded_orMatrixOutputs_hi_85 = cat(decoded_orMatrixOutputs_hi_hi_78, decoded_orMatrixOutputs_hi_lo_61)
node _decoded_orMatrixOutputs_T_173 = cat(decoded_orMatrixOutputs_hi_85, decoded_orMatrixOutputs_lo_79)
node _decoded_orMatrixOutputs_T_174 = orr(_decoded_orMatrixOutputs_T_173)
node decoded_orMatrixOutputs_lo_hi_69 = cat(decoded_andMatrixOutputs_51_2_2, decoded_andMatrixOutputs_36_2_3)
node decoded_orMatrixOutputs_lo_80 = cat(decoded_orMatrixOutputs_lo_hi_69, decoded_andMatrixOutputs_42_2_3)
node decoded_orMatrixOutputs_hi_hi_79 = cat(decoded_andMatrixOutputs_30_2_3, decoded_andMatrixOutputs_1_2_3)
node decoded_orMatrixOutputs_hi_86 = cat(decoded_orMatrixOutputs_hi_hi_79, decoded_andMatrixOutputs_7_2_3)
node _decoded_orMatrixOutputs_T_175 = cat(decoded_orMatrixOutputs_hi_86, decoded_orMatrixOutputs_lo_80)
node _decoded_orMatrixOutputs_T_176 = orr(_decoded_orMatrixOutputs_T_175)
node _decoded_orMatrixOutputs_T_177 = orr(decoded_andMatrixOutputs_21_2_3)
node decoded_orMatrixOutputs_lo_lo_lo_12 = cat(decoded_andMatrixOutputs_41_2_3, decoded_andMatrixOutputs_45_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_19_2_3, decoded_andMatrixOutputs_34_2_3)
node decoded_orMatrixOutputs_lo_lo_hi_40 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_3, decoded_andMatrixOutputs_40_2_3)
node decoded_orMatrixOutputs_lo_lo_60 = cat(decoded_orMatrixOutputs_lo_lo_hi_40, decoded_orMatrixOutputs_lo_lo_lo_12)
node decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_28_2_3, decoded_andMatrixOutputs_50_2_2)
node decoded_orMatrixOutputs_lo_hi_lo_24 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_3, decoded_andMatrixOutputs_31_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_6_2_3, decoded_andMatrixOutputs_4_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_45 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_3, decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_hi_70 = cat(decoded_orMatrixOutputs_lo_hi_hi_45, decoded_orMatrixOutputs_lo_hi_lo_24)
node decoded_orMatrixOutputs_lo_81 = cat(decoded_orMatrixOutputs_lo_hi_70, decoded_orMatrixOutputs_lo_lo_60)
node decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_27_2_3, decoded_andMatrixOutputs_33_2_3)
node decoded_orMatrixOutputs_hi_lo_lo_16 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_3, decoded_andMatrixOutputs_17_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_2_2_3, decoded_andMatrixOutputs_37_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_40 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_3, decoded_andMatrixOutputs_10_2_3)
node decoded_orMatrixOutputs_hi_lo_62 = cat(decoded_orMatrixOutputs_hi_lo_hi_40, decoded_orMatrixOutputs_hi_lo_lo_16)
node decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_22_2_3, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_28 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_3, decoded_andMatrixOutputs_5_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_54 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_6, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_hi_80 = cat(decoded_orMatrixOutputs_hi_hi_hi_54, decoded_orMatrixOutputs_hi_hi_lo_28)
node decoded_orMatrixOutputs_hi_87 = cat(decoded_orMatrixOutputs_hi_hi_80, decoded_orMatrixOutputs_hi_lo_62)
node _decoded_orMatrixOutputs_T_178 = cat(decoded_orMatrixOutputs_hi_87, decoded_orMatrixOutputs_lo_81)
node _decoded_orMatrixOutputs_T_179 = orr(_decoded_orMatrixOutputs_T_178)
node decoded_orMatrixOutputs_lo_lo_lo_13 = cat(decoded_andMatrixOutputs_41_2_3, decoded_andMatrixOutputs_45_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_19_2_3, decoded_andMatrixOutputs_34_2_3)
node decoded_orMatrixOutputs_lo_lo_hi_41 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_4, decoded_andMatrixOutputs_40_2_3)
node decoded_orMatrixOutputs_lo_lo_61 = cat(decoded_orMatrixOutputs_lo_lo_hi_41, decoded_orMatrixOutputs_lo_lo_lo_13)
node decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_28_2_3, decoded_andMatrixOutputs_50_2_2)
node decoded_orMatrixOutputs_lo_hi_lo_25 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_4, decoded_andMatrixOutputs_31_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_6_2_3, decoded_andMatrixOutputs_4_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_46 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_4, decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_hi_71 = cat(decoded_orMatrixOutputs_lo_hi_hi_46, decoded_orMatrixOutputs_lo_hi_lo_25)
node decoded_orMatrixOutputs_lo_82 = cat(decoded_orMatrixOutputs_lo_hi_71, decoded_orMatrixOutputs_lo_lo_61)
node decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_27_2_3, decoded_andMatrixOutputs_33_2_3)
node decoded_orMatrixOutputs_hi_lo_lo_17 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_4, decoded_andMatrixOutputs_17_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_2_2_3, decoded_andMatrixOutputs_37_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_41 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_4, decoded_andMatrixOutputs_10_2_3)
node decoded_orMatrixOutputs_hi_lo_63 = cat(decoded_orMatrixOutputs_hi_lo_hi_41, decoded_orMatrixOutputs_hi_lo_lo_17)
node decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_22_2_3, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_29 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_4, decoded_andMatrixOutputs_5_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_55 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_7, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_hi_81 = cat(decoded_orMatrixOutputs_hi_hi_hi_55, decoded_orMatrixOutputs_hi_hi_lo_29)
node decoded_orMatrixOutputs_hi_88 = cat(decoded_orMatrixOutputs_hi_hi_81, decoded_orMatrixOutputs_hi_lo_63)
node _decoded_orMatrixOutputs_T_180 = cat(decoded_orMatrixOutputs_hi_88, decoded_orMatrixOutputs_lo_82)
node _decoded_orMatrixOutputs_T_181 = orr(_decoded_orMatrixOutputs_T_180)
node decoded_orMatrixOutputs_lo_lo_lo_14 = cat(decoded_andMatrixOutputs_41_2_3, decoded_andMatrixOutputs_45_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_19_2_3, decoded_andMatrixOutputs_34_2_3)
node decoded_orMatrixOutputs_lo_lo_hi_42 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_5, decoded_andMatrixOutputs_40_2_3)
node decoded_orMatrixOutputs_lo_lo_62 = cat(decoded_orMatrixOutputs_lo_lo_hi_42, decoded_orMatrixOutputs_lo_lo_lo_14)
node decoded_orMatrixOutputs_lo_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_28_2_3, decoded_andMatrixOutputs_50_2_2)
node decoded_orMatrixOutputs_lo_hi_lo_26 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_5, decoded_andMatrixOutputs_31_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_6_2_3, decoded_andMatrixOutputs_4_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_47 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_5, decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_hi_72 = cat(decoded_orMatrixOutputs_lo_hi_hi_47, decoded_orMatrixOutputs_lo_hi_lo_26)
node decoded_orMatrixOutputs_lo_83 = cat(decoded_orMatrixOutputs_lo_hi_72, decoded_orMatrixOutputs_lo_lo_62)
node decoded_orMatrixOutputs_hi_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_27_2_3, decoded_andMatrixOutputs_33_2_3)
node decoded_orMatrixOutputs_hi_lo_lo_18 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_5, decoded_andMatrixOutputs_17_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_2_2_3, decoded_andMatrixOutputs_37_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_42 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_5, decoded_andMatrixOutputs_10_2_3)
node decoded_orMatrixOutputs_hi_lo_64 = cat(decoded_orMatrixOutputs_hi_lo_hi_42, decoded_orMatrixOutputs_hi_lo_lo_18)
node decoded_orMatrixOutputs_hi_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_22_2_3, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_lo_30 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_5, decoded_andMatrixOutputs_5_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_56 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_8, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_hi_82 = cat(decoded_orMatrixOutputs_hi_hi_hi_56, decoded_orMatrixOutputs_hi_hi_lo_30)
node decoded_orMatrixOutputs_hi_89 = cat(decoded_orMatrixOutputs_hi_hi_82, decoded_orMatrixOutputs_hi_lo_64)
node _decoded_orMatrixOutputs_T_182 = cat(decoded_orMatrixOutputs_hi_89, decoded_orMatrixOutputs_lo_83)
node _decoded_orMatrixOutputs_T_183 = orr(_decoded_orMatrixOutputs_T_182)
node decoded_orMatrixOutputs_lo_lo_lo_15 = cat(decoded_andMatrixOutputs_24_2_3, decoded_andMatrixOutputs_29_2_3)
node decoded_orMatrixOutputs_lo_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_28_2_3, decoded_andMatrixOutputs_50_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_43 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_6, decoded_andMatrixOutputs_44_2_2)
node decoded_orMatrixOutputs_lo_lo_63 = cat(decoded_orMatrixOutputs_lo_lo_hi_43, decoded_orMatrixOutputs_lo_lo_lo_15)
node decoded_orMatrixOutputs_lo_hi_lo_27 = cat(decoded_andMatrixOutputs_4_2_3, decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_33_2_3, decoded_andMatrixOutputs_17_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_48 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_6, decoded_andMatrixOutputs_6_2_3)
node decoded_orMatrixOutputs_lo_hi_73 = cat(decoded_orMatrixOutputs_lo_hi_hi_48, decoded_orMatrixOutputs_lo_hi_lo_27)
node decoded_orMatrixOutputs_lo_84 = cat(decoded_orMatrixOutputs_lo_hi_73, decoded_orMatrixOutputs_lo_lo_63)
node decoded_orMatrixOutputs_hi_lo_lo_19 = cat(decoded_andMatrixOutputs_10_2_3, decoded_andMatrixOutputs_27_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_5_2_3, decoded_andMatrixOutputs_2_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_43 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_6, decoded_andMatrixOutputs_37_2_3)
node decoded_orMatrixOutputs_hi_lo_65 = cat(decoded_orMatrixOutputs_hi_lo_hi_43, decoded_orMatrixOutputs_hi_lo_lo_19)
node decoded_orMatrixOutputs_hi_hi_lo_31 = cat(decoded_andMatrixOutputs_22_2_3, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_57 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_9, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_hi_83 = cat(decoded_orMatrixOutputs_hi_hi_hi_57, decoded_orMatrixOutputs_hi_hi_lo_31)
node decoded_orMatrixOutputs_hi_90 = cat(decoded_orMatrixOutputs_hi_hi_83, decoded_orMatrixOutputs_hi_lo_65)
node _decoded_orMatrixOutputs_T_184 = cat(decoded_orMatrixOutputs_hi_90, decoded_orMatrixOutputs_lo_84)
node _decoded_orMatrixOutputs_T_185 = orr(_decoded_orMatrixOutputs_T_184)
node decoded_orMatrixOutputs_lo_lo_lo_16 = cat(decoded_andMatrixOutputs_28_2_3, decoded_andMatrixOutputs_50_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_44 = cat(decoded_andMatrixOutputs_4_2_3, decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_lo_64 = cat(decoded_orMatrixOutputs_lo_lo_hi_44, decoded_orMatrixOutputs_lo_lo_lo_16)
node decoded_orMatrixOutputs_lo_hi_lo_28 = cat(decoded_andMatrixOutputs_17_2_3, decoded_andMatrixOutputs_6_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_49 = cat(decoded_andMatrixOutputs_27_2_3, decoded_andMatrixOutputs_33_2_3)
node decoded_orMatrixOutputs_lo_hi_74 = cat(decoded_orMatrixOutputs_lo_hi_hi_49, decoded_orMatrixOutputs_lo_hi_lo_28)
node decoded_orMatrixOutputs_lo_85 = cat(decoded_orMatrixOutputs_lo_hi_74, decoded_orMatrixOutputs_lo_lo_64)
node decoded_orMatrixOutputs_hi_lo_lo_20 = cat(decoded_andMatrixOutputs_37_2_3, decoded_andMatrixOutputs_10_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_44 = cat(decoded_andMatrixOutputs_5_2_3, decoded_andMatrixOutputs_2_2_3)
node decoded_orMatrixOutputs_hi_lo_66 = cat(decoded_orMatrixOutputs_hi_lo_hi_44, decoded_orMatrixOutputs_hi_lo_lo_20)
node decoded_orMatrixOutputs_hi_hi_lo_32 = cat(decoded_andMatrixOutputs_22_2_3, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_58 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_10, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_hi_84 = cat(decoded_orMatrixOutputs_hi_hi_hi_58, decoded_orMatrixOutputs_hi_hi_lo_32)
node decoded_orMatrixOutputs_hi_91 = cat(decoded_orMatrixOutputs_hi_hi_84, decoded_orMatrixOutputs_hi_lo_66)
node _decoded_orMatrixOutputs_T_186 = cat(decoded_orMatrixOutputs_hi_91, decoded_orMatrixOutputs_lo_85)
node _decoded_orMatrixOutputs_T_187 = orr(_decoded_orMatrixOutputs_T_186)
node decoded_orMatrixOutputs_lo_lo_lo_17 = cat(decoded_andMatrixOutputs_28_2_3, decoded_andMatrixOutputs_50_2_2)
node decoded_orMatrixOutputs_lo_lo_hi_45 = cat(decoded_andMatrixOutputs_4_2_3, decoded_andMatrixOutputs_0_2_3)
node decoded_orMatrixOutputs_lo_lo_65 = cat(decoded_orMatrixOutputs_lo_lo_hi_45, decoded_orMatrixOutputs_lo_lo_lo_17)
node decoded_orMatrixOutputs_lo_hi_lo_29 = cat(decoded_andMatrixOutputs_17_2_3, decoded_andMatrixOutputs_6_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_50 = cat(decoded_andMatrixOutputs_43_2_3, decoded_andMatrixOutputs_33_2_3)
node decoded_orMatrixOutputs_lo_hi_75 = cat(decoded_orMatrixOutputs_lo_hi_hi_50, decoded_orMatrixOutputs_lo_hi_lo_29)
node decoded_orMatrixOutputs_lo_86 = cat(decoded_orMatrixOutputs_lo_hi_75, decoded_orMatrixOutputs_lo_lo_65)
node decoded_orMatrixOutputs_hi_lo_lo_21 = cat(decoded_andMatrixOutputs_16_2_3, decoded_andMatrixOutputs_54_2_2)
node decoded_orMatrixOutputs_hi_lo_hi_45 = cat(decoded_andMatrixOutputs_5_2_3, decoded_andMatrixOutputs_2_2_3)
node decoded_orMatrixOutputs_hi_lo_67 = cat(decoded_orMatrixOutputs_hi_lo_hi_45, decoded_orMatrixOutputs_hi_lo_lo_21)
node decoded_orMatrixOutputs_hi_hi_lo_33 = cat(decoded_andMatrixOutputs_22_2_3, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_hi_59 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_11, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_hi_85 = cat(decoded_orMatrixOutputs_hi_hi_hi_59, decoded_orMatrixOutputs_hi_hi_lo_33)
node decoded_orMatrixOutputs_hi_92 = cat(decoded_orMatrixOutputs_hi_hi_85, decoded_orMatrixOutputs_hi_lo_67)
node _decoded_orMatrixOutputs_T_188 = cat(decoded_orMatrixOutputs_hi_92, decoded_orMatrixOutputs_lo_86)
node _decoded_orMatrixOutputs_T_189 = orr(_decoded_orMatrixOutputs_T_188)
node decoded_orMatrixOutputs_lo_lo_hi_46 = cat(decoded_andMatrixOutputs_17_2_3, decoded_andMatrixOutputs_6_2_3)
node decoded_orMatrixOutputs_lo_lo_66 = cat(decoded_orMatrixOutputs_lo_lo_hi_46, decoded_andMatrixOutputs_4_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_51 = cat(decoded_andMatrixOutputs_5_2_3, decoded_andMatrixOutputs_2_2_3)
node decoded_orMatrixOutputs_lo_hi_76 = cat(decoded_orMatrixOutputs_lo_hi_hi_51, decoded_andMatrixOutputs_33_2_3)
node decoded_orMatrixOutputs_lo_87 = cat(decoded_orMatrixOutputs_lo_hi_76, decoded_orMatrixOutputs_lo_lo_66)
node decoded_orMatrixOutputs_hi_lo_hi_46 = cat(decoded_andMatrixOutputs_12_2_3, decoded_andMatrixOutputs_22_2_3)
node decoded_orMatrixOutputs_hi_lo_68 = cat(decoded_orMatrixOutputs_hi_lo_hi_46, decoded_andMatrixOutputs_53_2_2)
node decoded_orMatrixOutputs_hi_hi_hi_60 = cat(decoded_andMatrixOutputs_20_2_3, decoded_andMatrixOutputs_15_2_3)
node decoded_orMatrixOutputs_hi_hi_86 = cat(decoded_orMatrixOutputs_hi_hi_hi_60, decoded_andMatrixOutputs_35_2_3)
node decoded_orMatrixOutputs_hi_93 = cat(decoded_orMatrixOutputs_hi_hi_86, decoded_orMatrixOutputs_hi_lo_68)
node _decoded_orMatrixOutputs_T_190 = cat(decoded_orMatrixOutputs_hi_93, decoded_orMatrixOutputs_lo_87)
node _decoded_orMatrixOutputs_T_191 = orr(_decoded_orMatrixOutputs_T_190)
node _decoded_orMatrixOutputs_T_192 = orr(decoded_andMatrixOutputs_26_2_3)
node decoded_orMatrixOutputs_lo_lo_67 = cat(decoded_andMatrixOutputs_39_2_3, decoded_andMatrixOutputs_8_2_3)
node decoded_orMatrixOutputs_lo_hi_77 = cat(decoded_andMatrixOutputs_18_2_3, decoded_andMatrixOutputs_52_2_2)
node decoded_orMatrixOutputs_lo_88 = cat(decoded_orMatrixOutputs_lo_hi_77, decoded_orMatrixOutputs_lo_lo_67)
node decoded_orMatrixOutputs_hi_lo_69 = cat(decoded_andMatrixOutputs_14_2_3, decoded_andMatrixOutputs_9_2_3)
node decoded_orMatrixOutputs_hi_hi_87 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node decoded_orMatrixOutputs_hi_94 = cat(decoded_orMatrixOutputs_hi_hi_87, decoded_orMatrixOutputs_hi_lo_69)
node _decoded_orMatrixOutputs_T_193 = cat(decoded_orMatrixOutputs_hi_94, decoded_orMatrixOutputs_lo_88)
node _decoded_orMatrixOutputs_T_194 = orr(_decoded_orMatrixOutputs_T_193)
node decoded_orMatrixOutputs_lo_lo_68 = cat(decoded_andMatrixOutputs_39_2_3, decoded_andMatrixOutputs_8_2_3)
node decoded_orMatrixOutputs_lo_hi_78 = cat(decoded_andMatrixOutputs_18_2_3, decoded_andMatrixOutputs_52_2_2)
node decoded_orMatrixOutputs_lo_89 = cat(decoded_orMatrixOutputs_lo_hi_78, decoded_orMatrixOutputs_lo_lo_68)
node decoded_orMatrixOutputs_hi_lo_70 = cat(decoded_andMatrixOutputs_14_2_3, decoded_andMatrixOutputs_9_2_3)
node decoded_orMatrixOutputs_hi_hi_88 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node decoded_orMatrixOutputs_hi_95 = cat(decoded_orMatrixOutputs_hi_hi_88, decoded_orMatrixOutputs_hi_lo_70)
node _decoded_orMatrixOutputs_T_195 = cat(decoded_orMatrixOutputs_hi_95, decoded_orMatrixOutputs_lo_89)
node _decoded_orMatrixOutputs_T_196 = orr(_decoded_orMatrixOutputs_T_195)
node decoded_orMatrixOutputs_lo_lo_69 = cat(decoded_andMatrixOutputs_39_2_3, decoded_andMatrixOutputs_8_2_3)
node decoded_orMatrixOutputs_lo_hi_79 = cat(decoded_andMatrixOutputs_18_2_3, decoded_andMatrixOutputs_52_2_2)
node decoded_orMatrixOutputs_lo_90 = cat(decoded_orMatrixOutputs_lo_hi_79, decoded_orMatrixOutputs_lo_lo_69)
node decoded_orMatrixOutputs_hi_lo_71 = cat(decoded_andMatrixOutputs_14_2_3, decoded_andMatrixOutputs_9_2_3)
node decoded_orMatrixOutputs_hi_hi_89 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node decoded_orMatrixOutputs_hi_96 = cat(decoded_orMatrixOutputs_hi_hi_89, decoded_orMatrixOutputs_hi_lo_71)
node _decoded_orMatrixOutputs_T_197 = cat(decoded_orMatrixOutputs_hi_96, decoded_orMatrixOutputs_lo_90)
node _decoded_orMatrixOutputs_T_198 = orr(_decoded_orMatrixOutputs_T_197)
node decoded_orMatrixOutputs_lo_lo_70 = cat(decoded_andMatrixOutputs_39_2_3, decoded_andMatrixOutputs_8_2_3)
node decoded_orMatrixOutputs_lo_hi_80 = cat(decoded_andMatrixOutputs_18_2_3, decoded_andMatrixOutputs_52_2_2)
node decoded_orMatrixOutputs_lo_91 = cat(decoded_orMatrixOutputs_lo_hi_80, decoded_orMatrixOutputs_lo_lo_70)
node decoded_orMatrixOutputs_hi_lo_72 = cat(decoded_andMatrixOutputs_14_2_3, decoded_andMatrixOutputs_9_2_3)
node decoded_orMatrixOutputs_hi_hi_90 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node decoded_orMatrixOutputs_hi_97 = cat(decoded_orMatrixOutputs_hi_hi_90, decoded_orMatrixOutputs_hi_lo_72)
node _decoded_orMatrixOutputs_T_199 = cat(decoded_orMatrixOutputs_hi_97, decoded_orMatrixOutputs_lo_91)
node _decoded_orMatrixOutputs_T_200 = orr(_decoded_orMatrixOutputs_T_199)
node decoded_orMatrixOutputs_lo_hi_81 = cat(decoded_andMatrixOutputs_9_2_3, decoded_andMatrixOutputs_18_2_3)
node decoded_orMatrixOutputs_lo_92 = cat(decoded_orMatrixOutputs_lo_hi_81, decoded_andMatrixOutputs_52_2_2)
node decoded_orMatrixOutputs_hi_hi_91 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node decoded_orMatrixOutputs_hi_98 = cat(decoded_orMatrixOutputs_hi_hi_91, decoded_andMatrixOutputs_14_2_3)
node _decoded_orMatrixOutputs_T_201 = cat(decoded_orMatrixOutputs_hi_98, decoded_orMatrixOutputs_lo_92)
node _decoded_orMatrixOutputs_T_202 = orr(_decoded_orMatrixOutputs_T_201)
node decoded_orMatrixOutputs_lo_hi_82 = cat(decoded_andMatrixOutputs_9_2_3, decoded_andMatrixOutputs_18_2_3)
node decoded_orMatrixOutputs_lo_93 = cat(decoded_orMatrixOutputs_lo_hi_82, decoded_andMatrixOutputs_52_2_2)
node decoded_orMatrixOutputs_hi_hi_92 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node decoded_orMatrixOutputs_hi_99 = cat(decoded_orMatrixOutputs_hi_hi_92, decoded_andMatrixOutputs_14_2_3)
node _decoded_orMatrixOutputs_T_203 = cat(decoded_orMatrixOutputs_hi_99, decoded_orMatrixOutputs_lo_93)
node _decoded_orMatrixOutputs_T_204 = orr(_decoded_orMatrixOutputs_T_203)
node _decoded_orMatrixOutputs_T_205 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node _decoded_orMatrixOutputs_T_206 = orr(_decoded_orMatrixOutputs_T_205)
node _decoded_orMatrixOutputs_T_207 = cat(decoded_andMatrixOutputs_13_2_3, decoded_andMatrixOutputs_46_2_2)
node _decoded_orMatrixOutputs_T_208 = orr(_decoded_orMatrixOutputs_T_207)
node decoded_orMatrixOutputs_lo_lo_lo_lo_3 = cat(_decoded_orMatrixOutputs_T_166, _decoded_orMatrixOutputs_T_164)
node decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = cat(_decoded_orMatrixOutputs_T_172, _decoded_orMatrixOutputs_T_170)
node decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, _decoded_orMatrixOutputs_T_168)
node decoded_orMatrixOutputs_lo_lo_lo_18 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_3, decoded_orMatrixOutputs_lo_lo_lo_lo_3)
node decoded_orMatrixOutputs_lo_lo_hi_lo_3 = cat(_decoded_orMatrixOutputs_T_176, _decoded_orMatrixOutputs_T_174)
node decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_hi_hi_7 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, _decoded_orMatrixOutputs_T_177)
node decoded_orMatrixOutputs_lo_lo_hi_47 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_7, decoded_orMatrixOutputs_lo_lo_hi_lo_3)
node decoded_orMatrixOutputs_lo_lo_71 = cat(decoded_orMatrixOutputs_lo_lo_hi_47, decoded_orMatrixOutputs_lo_lo_lo_18)
node decoded_orMatrixOutputs_lo_hi_lo_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_lo_hi_6 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_lo_30 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_6, decoded_orMatrixOutputs_lo_hi_lo_lo_3)
node decoded_orMatrixOutputs_lo_hi_hi_lo_3 = cat(_decoded_orMatrixOutputs_T_179, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = cat(_decoded_orMatrixOutputs_T_185, _decoded_orMatrixOutputs_T_183)
node decoded_orMatrixOutputs_lo_hi_hi_hi_7 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, _decoded_orMatrixOutputs_T_181)
node decoded_orMatrixOutputs_lo_hi_hi_52 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_7, decoded_orMatrixOutputs_lo_hi_hi_lo_3)
node decoded_orMatrixOutputs_lo_hi_83 = cat(decoded_orMatrixOutputs_lo_hi_hi_52, decoded_orMatrixOutputs_lo_hi_lo_30)
node decoded_orMatrixOutputs_lo_94 = cat(decoded_orMatrixOutputs_lo_hi_83, decoded_orMatrixOutputs_lo_lo_71)
node decoded_orMatrixOutputs_hi_lo_lo_lo_3 = cat(_decoded_orMatrixOutputs_T_189, _decoded_orMatrixOutputs_T_187)
node decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_192)
node decoded_orMatrixOutputs_hi_lo_lo_hi_6 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, _decoded_orMatrixOutputs_T_191)
node decoded_orMatrixOutputs_hi_lo_lo_22 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_6, decoded_orMatrixOutputs_hi_lo_lo_lo_3)
node decoded_orMatrixOutputs_hi_lo_hi_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_hi_hi_7 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_lo_hi_47 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_7, decoded_orMatrixOutputs_hi_lo_hi_lo_3)
node decoded_orMatrixOutputs_hi_lo_73 = cat(decoded_orMatrixOutputs_hi_lo_hi_47, decoded_orMatrixOutputs_hi_lo_lo_22)
node decoded_orMatrixOutputs_hi_hi_lo_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = cat(_decoded_orMatrixOutputs_T_198, _decoded_orMatrixOutputs_T_196)
node decoded_orMatrixOutputs_hi_hi_lo_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, _decoded_orMatrixOutputs_T_194)
node decoded_orMatrixOutputs_hi_hi_lo_34 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_6, decoded_orMatrixOutputs_hi_hi_lo_lo_3)
node decoded_orMatrixOutputs_hi_hi_hi_lo_3 = cat(_decoded_orMatrixOutputs_T_202, _decoded_orMatrixOutputs_T_200)
node decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(_decoded_orMatrixOutputs_T_208, _decoded_orMatrixOutputs_T_206)
node decoded_orMatrixOutputs_hi_hi_hi_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, _decoded_orMatrixOutputs_T_204)
node decoded_orMatrixOutputs_hi_hi_hi_61 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_12, decoded_orMatrixOutputs_hi_hi_hi_lo_3)
node decoded_orMatrixOutputs_hi_hi_93 = cat(decoded_orMatrixOutputs_hi_hi_hi_61, decoded_orMatrixOutputs_hi_hi_lo_34)
node decoded_orMatrixOutputs_hi_100 = cat(decoded_orMatrixOutputs_hi_hi_93, decoded_orMatrixOutputs_hi_lo_73)
node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_100, decoded_orMatrixOutputs_lo_94)
node _decoded_invMatrixOutputs_T_120 = bits(decoded_orMatrixOutputs_3, 0, 0)
node _decoded_invMatrixOutputs_T_121 = bits(decoded_orMatrixOutputs_3, 1, 1)
node _decoded_invMatrixOutputs_T_122 = bits(decoded_orMatrixOutputs_3, 2, 2)
node _decoded_invMatrixOutputs_T_123 = bits(decoded_orMatrixOutputs_3, 3, 3)
node _decoded_invMatrixOutputs_T_124 = bits(decoded_orMatrixOutputs_3, 4, 4)
node _decoded_invMatrixOutputs_T_125 = bits(decoded_orMatrixOutputs_3, 5, 5)
node _decoded_invMatrixOutputs_T_126 = bits(decoded_orMatrixOutputs_3, 6, 6)
node _decoded_invMatrixOutputs_T_127 = bits(decoded_orMatrixOutputs_3, 7, 7)
node _decoded_invMatrixOutputs_T_128 = bits(decoded_orMatrixOutputs_3, 8, 8)
node _decoded_invMatrixOutputs_T_129 = bits(decoded_orMatrixOutputs_3, 9, 9)
node _decoded_invMatrixOutputs_T_130 = bits(decoded_orMatrixOutputs_3, 10, 10)
node _decoded_invMatrixOutputs_T_131 = bits(decoded_orMatrixOutputs_3, 11, 11)
node _decoded_invMatrixOutputs_T_132 = bits(decoded_orMatrixOutputs_3, 12, 12)
node _decoded_invMatrixOutputs_T_133 = bits(decoded_orMatrixOutputs_3, 13, 13)
node _decoded_invMatrixOutputs_T_134 = bits(decoded_orMatrixOutputs_3, 14, 14)
node _decoded_invMatrixOutputs_T_135 = bits(decoded_orMatrixOutputs_3, 15, 15)
node _decoded_invMatrixOutputs_T_136 = bits(decoded_orMatrixOutputs_3, 16, 16)
node _decoded_invMatrixOutputs_T_137 = bits(decoded_orMatrixOutputs_3, 17, 17)
node _decoded_invMatrixOutputs_T_138 = bits(decoded_orMatrixOutputs_3, 18, 18)
node _decoded_invMatrixOutputs_T_139 = bits(decoded_orMatrixOutputs_3, 19, 19)
node _decoded_invMatrixOutputs_T_140 = bits(decoded_orMatrixOutputs_3, 20, 20)
node _decoded_invMatrixOutputs_T_141 = bits(decoded_orMatrixOutputs_3, 21, 21)
node _decoded_invMatrixOutputs_T_142 = bits(decoded_orMatrixOutputs_3, 22, 22)
node _decoded_invMatrixOutputs_T_143 = bits(decoded_orMatrixOutputs_3, 23, 23)
node _decoded_invMatrixOutputs_T_144 = bits(decoded_orMatrixOutputs_3, 24, 24)
node _decoded_invMatrixOutputs_T_145 = bits(decoded_orMatrixOutputs_3, 25, 25)
node _decoded_invMatrixOutputs_T_146 = bits(decoded_orMatrixOutputs_3, 26, 26)
node _decoded_invMatrixOutputs_T_147 = bits(decoded_orMatrixOutputs_3, 27, 27)
node _decoded_invMatrixOutputs_T_148 = bits(decoded_orMatrixOutputs_3, 28, 28)
node _decoded_invMatrixOutputs_T_149 = bits(decoded_orMatrixOutputs_3, 29, 29)
node _decoded_invMatrixOutputs_T_150 = bits(decoded_orMatrixOutputs_3, 30, 30)
node _decoded_invMatrixOutputs_T_151 = bits(decoded_orMatrixOutputs_3, 31, 31)
node _decoded_invMatrixOutputs_T_152 = bits(decoded_orMatrixOutputs_3, 32, 32)
node _decoded_invMatrixOutputs_T_153 = bits(decoded_orMatrixOutputs_3, 33, 33)
node _decoded_invMatrixOutputs_T_154 = bits(decoded_orMatrixOutputs_3, 34, 34)
node _decoded_invMatrixOutputs_T_155 = bits(decoded_orMatrixOutputs_3, 35, 35)
node _decoded_invMatrixOutputs_T_156 = bits(decoded_orMatrixOutputs_3, 36, 36)
node _decoded_invMatrixOutputs_T_157 = bits(decoded_orMatrixOutputs_3, 37, 37)
node _decoded_invMatrixOutputs_T_158 = bits(decoded_orMatrixOutputs_3, 38, 38)
node _decoded_invMatrixOutputs_T_159 = bits(decoded_orMatrixOutputs_3, 39, 39)
node decoded_invMatrixOutputs_lo_lo_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_121, _decoded_invMatrixOutputs_T_120)
node decoded_invMatrixOutputs_lo_lo_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_124, _decoded_invMatrixOutputs_T_123)
node decoded_invMatrixOutputs_lo_lo_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_hi_3, _decoded_invMatrixOutputs_T_122)
node decoded_invMatrixOutputs_lo_lo_lo_3 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_3, decoded_invMatrixOutputs_lo_lo_lo_lo_3)
node decoded_invMatrixOutputs_lo_lo_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_126, _decoded_invMatrixOutputs_T_125)
node decoded_invMatrixOutputs_lo_lo_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_129, _decoded_invMatrixOutputs_T_128)
node decoded_invMatrixOutputs_lo_lo_hi_hi_3 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_hi_3, _decoded_invMatrixOutputs_T_127)
node decoded_invMatrixOutputs_lo_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_3, decoded_invMatrixOutputs_lo_lo_hi_lo_3)
node decoded_invMatrixOutputs_lo_lo_3 = cat(decoded_invMatrixOutputs_lo_lo_hi_3, decoded_invMatrixOutputs_lo_lo_lo_3)
node decoded_invMatrixOutputs_lo_hi_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_131, _decoded_invMatrixOutputs_T_130)
node decoded_invMatrixOutputs_lo_hi_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_134, _decoded_invMatrixOutputs_T_133)
node decoded_invMatrixOutputs_lo_hi_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_hi_3, _decoded_invMatrixOutputs_T_132)
node decoded_invMatrixOutputs_lo_hi_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_3, decoded_invMatrixOutputs_lo_hi_lo_lo_3)
node decoded_invMatrixOutputs_lo_hi_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_136, _decoded_invMatrixOutputs_T_135)
node decoded_invMatrixOutputs_lo_hi_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_139, _decoded_invMatrixOutputs_T_138)
node decoded_invMatrixOutputs_lo_hi_hi_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_hi_3, _decoded_invMatrixOutputs_T_137)
node decoded_invMatrixOutputs_lo_hi_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_3, decoded_invMatrixOutputs_lo_hi_hi_lo_3)
node decoded_invMatrixOutputs_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_hi_3, decoded_invMatrixOutputs_lo_hi_lo_3)
node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3)
node decoded_invMatrixOutputs_hi_lo_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_141, _decoded_invMatrixOutputs_T_140)
node decoded_invMatrixOutputs_hi_lo_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_144, _decoded_invMatrixOutputs_T_143)
node decoded_invMatrixOutputs_hi_lo_lo_hi_3 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_hi_3, _decoded_invMatrixOutputs_T_142)
node decoded_invMatrixOutputs_hi_lo_lo_3 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_3, decoded_invMatrixOutputs_hi_lo_lo_lo_3)
node decoded_invMatrixOutputs_hi_lo_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_146, _decoded_invMatrixOutputs_T_145)
node decoded_invMatrixOutputs_hi_lo_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_149, _decoded_invMatrixOutputs_T_148)
node decoded_invMatrixOutputs_hi_lo_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_hi_3, _decoded_invMatrixOutputs_T_147)
node decoded_invMatrixOutputs_hi_lo_hi_3 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_3, decoded_invMatrixOutputs_hi_lo_hi_lo_3)
node decoded_invMatrixOutputs_hi_lo_3 = cat(decoded_invMatrixOutputs_hi_lo_hi_3, decoded_invMatrixOutputs_hi_lo_lo_3)
node decoded_invMatrixOutputs_hi_hi_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_151, _decoded_invMatrixOutputs_T_150)
node decoded_invMatrixOutputs_hi_hi_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_154, _decoded_invMatrixOutputs_T_153)
node decoded_invMatrixOutputs_hi_hi_lo_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_hi_3, _decoded_invMatrixOutputs_T_152)
node decoded_invMatrixOutputs_hi_hi_lo_3 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_3, decoded_invMatrixOutputs_hi_hi_lo_lo_3)
node decoded_invMatrixOutputs_hi_hi_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_156, _decoded_invMatrixOutputs_T_155)
node decoded_invMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_159, _decoded_invMatrixOutputs_T_158)
node decoded_invMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_hi_3, _decoded_invMatrixOutputs_T_157)
node decoded_invMatrixOutputs_hi_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_3, decoded_invMatrixOutputs_hi_hi_hi_lo_3)
node decoded_invMatrixOutputs_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_3, decoded_invMatrixOutputs_hi_hi_lo_3)
node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3)
node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3)
connect decoded_plaOutput_3, decoded_invMatrixOutputs_3
connect decoded_plaInput_3, addr_3
node _decoded_T_240 = bits(decoded_plaOutput_3, 31, 0)
node _decoded_T_241 = shl(UInt<16>(0hffff), 16)
node _decoded_T_242 = xor(UInt<32>(0hffffffff), _decoded_T_241)
node _decoded_T_243 = shr(_decoded_T_240, 16)
node _decoded_T_244 = and(_decoded_T_243, _decoded_T_242)
node _decoded_T_245 = bits(_decoded_T_240, 15, 0)
node _decoded_T_246 = shl(_decoded_T_245, 16)
node _decoded_T_247 = not(_decoded_T_242)
node _decoded_T_248 = and(_decoded_T_246, _decoded_T_247)
node _decoded_T_249 = or(_decoded_T_244, _decoded_T_248)
node _decoded_T_250 = bits(_decoded_T_242, 23, 0)
node _decoded_T_251 = shl(_decoded_T_250, 8)
node _decoded_T_252 = xor(_decoded_T_242, _decoded_T_251)
node _decoded_T_253 = shr(_decoded_T_249, 8)
node _decoded_T_254 = and(_decoded_T_253, _decoded_T_252)
node _decoded_T_255 = bits(_decoded_T_249, 23, 0)
node _decoded_T_256 = shl(_decoded_T_255, 8)
node _decoded_T_257 = not(_decoded_T_252)
node _decoded_T_258 = and(_decoded_T_256, _decoded_T_257)
node _decoded_T_259 = or(_decoded_T_254, _decoded_T_258)
node _decoded_T_260 = bits(_decoded_T_252, 27, 0)
node _decoded_T_261 = shl(_decoded_T_260, 4)
node _decoded_T_262 = xor(_decoded_T_252, _decoded_T_261)
node _decoded_T_263 = shr(_decoded_T_259, 4)
node _decoded_T_264 = and(_decoded_T_263, _decoded_T_262)
node _decoded_T_265 = bits(_decoded_T_259, 27, 0)
node _decoded_T_266 = shl(_decoded_T_265, 4)
node _decoded_T_267 = not(_decoded_T_262)
node _decoded_T_268 = and(_decoded_T_266, _decoded_T_267)
node _decoded_T_269 = or(_decoded_T_264, _decoded_T_268)
node _decoded_T_270 = bits(_decoded_T_262, 29, 0)
node _decoded_T_271 = shl(_decoded_T_270, 2)
node _decoded_T_272 = xor(_decoded_T_262, _decoded_T_271)
node _decoded_T_273 = shr(_decoded_T_269, 2)
node _decoded_T_274 = and(_decoded_T_273, _decoded_T_272)
node _decoded_T_275 = bits(_decoded_T_269, 29, 0)
node _decoded_T_276 = shl(_decoded_T_275, 2)
node _decoded_T_277 = not(_decoded_T_272)
node _decoded_T_278 = and(_decoded_T_276, _decoded_T_277)
node _decoded_T_279 = or(_decoded_T_274, _decoded_T_278)
node _decoded_T_280 = bits(_decoded_T_272, 30, 0)
node _decoded_T_281 = shl(_decoded_T_280, 1)
node _decoded_T_282 = xor(_decoded_T_272, _decoded_T_281)
node _decoded_T_283 = shr(_decoded_T_279, 1)
node _decoded_T_284 = and(_decoded_T_283, _decoded_T_282)
node _decoded_T_285 = bits(_decoded_T_279, 30, 0)
node _decoded_T_286 = shl(_decoded_T_285, 1)
node _decoded_T_287 = not(_decoded_T_282)
node _decoded_T_288 = and(_decoded_T_286, _decoded_T_287)
node _decoded_T_289 = or(_decoded_T_284, _decoded_T_288)
node _decoded_T_290 = bits(decoded_plaOutput_3, 39, 32)
node _decoded_T_291 = shl(UInt<4>(0hf), 4)
node _decoded_T_292 = xor(UInt<8>(0hff), _decoded_T_291)
node _decoded_T_293 = shr(_decoded_T_290, 4)
node _decoded_T_294 = and(_decoded_T_293, _decoded_T_292)
node _decoded_T_295 = bits(_decoded_T_290, 3, 0)
node _decoded_T_296 = shl(_decoded_T_295, 4)
node _decoded_T_297 = not(_decoded_T_292)
node _decoded_T_298 = and(_decoded_T_296, _decoded_T_297)
node _decoded_T_299 = or(_decoded_T_294, _decoded_T_298)
node _decoded_T_300 = bits(_decoded_T_292, 5, 0)
node _decoded_T_301 = shl(_decoded_T_300, 2)
node _decoded_T_302 = xor(_decoded_T_292, _decoded_T_301)
node _decoded_T_303 = shr(_decoded_T_299, 2)
node _decoded_T_304 = and(_decoded_T_303, _decoded_T_302)
node _decoded_T_305 = bits(_decoded_T_299, 5, 0)
node _decoded_T_306 = shl(_decoded_T_305, 2)
node _decoded_T_307 = not(_decoded_T_302)
node _decoded_T_308 = and(_decoded_T_306, _decoded_T_307)
node _decoded_T_309 = or(_decoded_T_304, _decoded_T_308)
node _decoded_T_310 = bits(_decoded_T_302, 6, 0)
node _decoded_T_311 = shl(_decoded_T_310, 1)
node _decoded_T_312 = xor(_decoded_T_302, _decoded_T_311)
node _decoded_T_313 = shr(_decoded_T_309, 1)
node _decoded_T_314 = and(_decoded_T_313, _decoded_T_312)
node _decoded_T_315 = bits(_decoded_T_309, 6, 0)
node _decoded_T_316 = shl(_decoded_T_315, 1)
node _decoded_T_317 = not(_decoded_T_312)
node _decoded_T_318 = and(_decoded_T_316, _decoded_T_317)
node _decoded_T_319 = or(_decoded_T_314, _decoded_T_318)
node decoded_3 = cat(_decoded_T_289, _decoded_T_319)
node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0)
connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T
node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1)
connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T
node _io_resp_3_vc_sel_0_2_T = bits(decoded_3, 2, 2)
connect io.resp.`3`.vc_sel.`0`[2], _io_resp_3_vc_sel_0_2_T
node _io_resp_3_vc_sel_0_3_T = bits(decoded_3, 3, 3)
connect io.resp.`3`.vc_sel.`0`[3], _io_resp_3_vc_sel_0_3_T
node _io_resp_3_vc_sel_0_4_T = bits(decoded_3, 4, 4)
connect io.resp.`3`.vc_sel.`0`[4], _io_resp_3_vc_sel_0_4_T
node _io_resp_3_vc_sel_0_5_T = bits(decoded_3, 5, 5)
connect io.resp.`3`.vc_sel.`0`[5], _io_resp_3_vc_sel_0_5_T
node _io_resp_3_vc_sel_0_6_T = bits(decoded_3, 6, 6)
connect io.resp.`3`.vc_sel.`0`[6], _io_resp_3_vc_sel_0_6_T
node _io_resp_3_vc_sel_0_7_T = bits(decoded_3, 7, 7)
connect io.resp.`3`.vc_sel.`0`[7], _io_resp_3_vc_sel_0_7_T
node _io_resp_3_vc_sel_1_0_T = bits(decoded_3, 8, 8)
connect io.resp.`3`.vc_sel.`1`[0], _io_resp_3_vc_sel_1_0_T
node _io_resp_3_vc_sel_1_1_T = bits(decoded_3, 9, 9)
connect io.resp.`3`.vc_sel.`1`[1], _io_resp_3_vc_sel_1_1_T
node _io_resp_3_vc_sel_1_2_T = bits(decoded_3, 10, 10)
connect io.resp.`3`.vc_sel.`1`[2], _io_resp_3_vc_sel_1_2_T
node _io_resp_3_vc_sel_1_3_T = bits(decoded_3, 11, 11)
connect io.resp.`3`.vc_sel.`1`[3], _io_resp_3_vc_sel_1_3_T
node _io_resp_3_vc_sel_1_4_T = bits(decoded_3, 12, 12)
connect io.resp.`3`.vc_sel.`1`[4], _io_resp_3_vc_sel_1_4_T
node _io_resp_3_vc_sel_1_5_T = bits(decoded_3, 13, 13)
connect io.resp.`3`.vc_sel.`1`[5], _io_resp_3_vc_sel_1_5_T
node _io_resp_3_vc_sel_1_6_T = bits(decoded_3, 14, 14)
connect io.resp.`3`.vc_sel.`1`[6], _io_resp_3_vc_sel_1_6_T
node _io_resp_3_vc_sel_1_7_T = bits(decoded_3, 15, 15)
connect io.resp.`3`.vc_sel.`1`[7], _io_resp_3_vc_sel_1_7_T
node _io_resp_3_vc_sel_2_0_T = bits(decoded_3, 16, 16)
connect io.resp.`3`.vc_sel.`2`[0], _io_resp_3_vc_sel_2_0_T
node _io_resp_3_vc_sel_2_1_T = bits(decoded_3, 17, 17)
connect io.resp.`3`.vc_sel.`2`[1], _io_resp_3_vc_sel_2_1_T
node _io_resp_3_vc_sel_2_2_T = bits(decoded_3, 18, 18)
connect io.resp.`3`.vc_sel.`2`[2], _io_resp_3_vc_sel_2_2_T
node _io_resp_3_vc_sel_2_3_T = bits(decoded_3, 19, 19)
connect io.resp.`3`.vc_sel.`2`[3], _io_resp_3_vc_sel_2_3_T
node _io_resp_3_vc_sel_2_4_T = bits(decoded_3, 20, 20)
connect io.resp.`3`.vc_sel.`2`[4], _io_resp_3_vc_sel_2_4_T
node _io_resp_3_vc_sel_2_5_T = bits(decoded_3, 21, 21)
connect io.resp.`3`.vc_sel.`2`[5], _io_resp_3_vc_sel_2_5_T
node _io_resp_3_vc_sel_2_6_T = bits(decoded_3, 22, 22)
connect io.resp.`3`.vc_sel.`2`[6], _io_resp_3_vc_sel_2_6_T
node _io_resp_3_vc_sel_2_7_T = bits(decoded_3, 23, 23)
connect io.resp.`3`.vc_sel.`2`[7], _io_resp_3_vc_sel_2_7_T
node _io_resp_3_vc_sel_3_0_T = bits(decoded_3, 24, 24)
connect io.resp.`3`.vc_sel.`3`[0], _io_resp_3_vc_sel_3_0_T
node _io_resp_3_vc_sel_3_1_T = bits(decoded_3, 25, 25)
connect io.resp.`3`.vc_sel.`3`[1], _io_resp_3_vc_sel_3_1_T
node _io_resp_3_vc_sel_3_2_T = bits(decoded_3, 26, 26)
connect io.resp.`3`.vc_sel.`3`[2], _io_resp_3_vc_sel_3_2_T
node _io_resp_3_vc_sel_3_3_T = bits(decoded_3, 27, 27)
connect io.resp.`3`.vc_sel.`3`[3], _io_resp_3_vc_sel_3_3_T
node _io_resp_3_vc_sel_3_4_T = bits(decoded_3, 28, 28)
connect io.resp.`3`.vc_sel.`3`[4], _io_resp_3_vc_sel_3_4_T
node _io_resp_3_vc_sel_3_5_T = bits(decoded_3, 29, 29)
connect io.resp.`3`.vc_sel.`3`[5], _io_resp_3_vc_sel_3_5_T
node _io_resp_3_vc_sel_3_6_T = bits(decoded_3, 30, 30)
connect io.resp.`3`.vc_sel.`3`[6], _io_resp_3_vc_sel_3_6_T
node _io_resp_3_vc_sel_3_7_T = bits(decoded_3, 31, 31)
connect io.resp.`3`.vc_sel.`3`[7], _io_resp_3_vc_sel_3_7_T
node _io_resp_3_vc_sel_4_0_T = bits(decoded_3, 32, 32)
connect io.resp.`3`.vc_sel.`4`[0], _io_resp_3_vc_sel_4_0_T
node _io_resp_3_vc_sel_4_1_T = bits(decoded_3, 33, 33)
connect io.resp.`3`.vc_sel.`4`[1], _io_resp_3_vc_sel_4_1_T
node _io_resp_3_vc_sel_4_2_T = bits(decoded_3, 34, 34)
connect io.resp.`3`.vc_sel.`4`[2], _io_resp_3_vc_sel_4_2_T
node _io_resp_3_vc_sel_4_3_T = bits(decoded_3, 35, 35)
connect io.resp.`3`.vc_sel.`4`[3], _io_resp_3_vc_sel_4_3_T
node _io_resp_3_vc_sel_4_4_T = bits(decoded_3, 36, 36)
connect io.resp.`3`.vc_sel.`4`[4], _io_resp_3_vc_sel_4_4_T
node _io_resp_3_vc_sel_4_5_T = bits(decoded_3, 37, 37)
connect io.resp.`3`.vc_sel.`4`[5], _io_resp_3_vc_sel_4_5_T
node _io_resp_3_vc_sel_4_6_T = bits(decoded_3, 38, 38)
connect io.resp.`3`.vc_sel.`4`[6], _io_resp_3_vc_sel_4_6_T
node _io_resp_3_vc_sel_4_7_T = bits(decoded_3, 39, 39)
connect io.resp.`3`.vc_sel.`4`[7], _io_resp_3_vc_sel_4_7_T
connect io.req.`4`.ready, UInt<1>(0h1)
node addr_lo_4 = cat(io.req.`4`.bits.flow.egress_node, io.req.`4`.bits.flow.egress_node_id)
node addr_hi_hi_4 = cat(io.req.`4`.bits.flow.vnet_id, io.req.`4`.bits.flow.ingress_node)
node addr_hi_4 = cat(addr_hi_hi_4, io.req.`4`.bits.flow.ingress_node_id)
node _addr_T_4 = cat(addr_hi_4, addr_lo_4)
node addr_4 = cat(io.req.`4`.bits.src_virt_id, _addr_T_4)
wire decoded_plaInput_4 : UInt<20>
node decoded_invInputs_4 = not(decoded_plaInput_4)
wire decoded_plaOutput_4 : UInt<40>
node decoded_andMatrixOutputs_andMatrixInput_0_230 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_230 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_230 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_hi_230 = cat(decoded_andMatrixOutputs_andMatrixInput_0_230, decoded_andMatrixOutputs_andMatrixInput_1_230)
node _decoded_andMatrixOutputs_T_230 = cat(decoded_andMatrixOutputs_hi_230, decoded_andMatrixOutputs_andMatrixInput_2_230)
node decoded_andMatrixOutputs_14_2_4 = andr(_decoded_andMatrixOutputs_T_230)
node decoded_andMatrixOutputs_andMatrixInput_0_231 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_231 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_231 = bits(decoded_plaInput_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_228 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_4_228 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_5_228 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_6_228 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_7_228 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_8_227 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_lo_lo_228 = cat(decoded_andMatrixOutputs_andMatrixInput_7_228, decoded_andMatrixOutputs_andMatrixInput_8_227)
node decoded_andMatrixOutputs_lo_hi_228 = cat(decoded_andMatrixOutputs_andMatrixInput_5_228, decoded_andMatrixOutputs_andMatrixInput_6_228)
node decoded_andMatrixOutputs_lo_228 = cat(decoded_andMatrixOutputs_lo_hi_228, decoded_andMatrixOutputs_lo_lo_228)
node decoded_andMatrixOutputs_hi_lo_228 = cat(decoded_andMatrixOutputs_andMatrixInput_3_228, decoded_andMatrixOutputs_andMatrixInput_4_228)
node decoded_andMatrixOutputs_hi_hi_hi_227 = cat(decoded_andMatrixOutputs_andMatrixInput_0_231, decoded_andMatrixOutputs_andMatrixInput_1_231)
node decoded_andMatrixOutputs_hi_hi_228 = cat(decoded_andMatrixOutputs_hi_hi_hi_227, decoded_andMatrixOutputs_andMatrixInput_2_231)
node decoded_andMatrixOutputs_hi_231 = cat(decoded_andMatrixOutputs_hi_hi_228, decoded_andMatrixOutputs_hi_lo_228)
node _decoded_andMatrixOutputs_T_231 = cat(decoded_andMatrixOutputs_hi_231, decoded_andMatrixOutputs_lo_228)
node decoded_andMatrixOutputs_21_2_4 = andr(_decoded_andMatrixOutputs_T_231)
node decoded_andMatrixOutputs_andMatrixInput_0_232 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_232 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_232 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_229 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_229 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_229 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_229 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_229 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_228 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_224 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_224 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_224 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_224 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_224 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_224 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_144 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_96 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_144 = cat(decoded_andMatrixOutputs_andMatrixInput_15_144, decoded_andMatrixOutputs_andMatrixInput_16_96)
node decoded_andMatrixOutputs_lo_lo_hi_224 = cat(decoded_andMatrixOutputs_andMatrixInput_13_224, decoded_andMatrixOutputs_andMatrixInput_14_224)
node decoded_andMatrixOutputs_lo_lo_229 = cat(decoded_andMatrixOutputs_lo_lo_hi_224, decoded_andMatrixOutputs_lo_lo_lo_144)
node decoded_andMatrixOutputs_lo_hi_lo_224 = cat(decoded_andMatrixOutputs_andMatrixInput_11_224, decoded_andMatrixOutputs_andMatrixInput_12_224)
node decoded_andMatrixOutputs_lo_hi_hi_224 = cat(decoded_andMatrixOutputs_andMatrixInput_9_224, decoded_andMatrixOutputs_andMatrixInput_10_224)
node decoded_andMatrixOutputs_lo_hi_229 = cat(decoded_andMatrixOutputs_lo_hi_hi_224, decoded_andMatrixOutputs_lo_hi_lo_224)
node decoded_andMatrixOutputs_lo_229 = cat(decoded_andMatrixOutputs_lo_hi_229, decoded_andMatrixOutputs_lo_lo_229)
node decoded_andMatrixOutputs_hi_lo_lo_224 = cat(decoded_andMatrixOutputs_andMatrixInput_7_229, decoded_andMatrixOutputs_andMatrixInput_8_228)
node decoded_andMatrixOutputs_hi_lo_hi_224 = cat(decoded_andMatrixOutputs_andMatrixInput_5_229, decoded_andMatrixOutputs_andMatrixInput_6_229)
node decoded_andMatrixOutputs_hi_lo_229 = cat(decoded_andMatrixOutputs_hi_lo_hi_224, decoded_andMatrixOutputs_hi_lo_lo_224)
node decoded_andMatrixOutputs_hi_hi_lo_224 = cat(decoded_andMatrixOutputs_andMatrixInput_3_229, decoded_andMatrixOutputs_andMatrixInput_4_229)
node decoded_andMatrixOutputs_hi_hi_hi_hi_96 = cat(decoded_andMatrixOutputs_andMatrixInput_0_232, decoded_andMatrixOutputs_andMatrixInput_1_232)
node decoded_andMatrixOutputs_hi_hi_hi_228 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_96, decoded_andMatrixOutputs_andMatrixInput_2_232)
node decoded_andMatrixOutputs_hi_hi_229 = cat(decoded_andMatrixOutputs_hi_hi_hi_228, decoded_andMatrixOutputs_hi_hi_lo_224)
node decoded_andMatrixOutputs_hi_232 = cat(decoded_andMatrixOutputs_hi_hi_229, decoded_andMatrixOutputs_hi_lo_229)
node _decoded_andMatrixOutputs_T_232 = cat(decoded_andMatrixOutputs_hi_232, decoded_andMatrixOutputs_lo_229)
node decoded_andMatrixOutputs_30_2_4 = andr(_decoded_andMatrixOutputs_T_232)
node decoded_andMatrixOutputs_andMatrixInput_0_233 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_233 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_233 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_230 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_230 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_230 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_230 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_230 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_229 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_225 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_225 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_225 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_225 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_225 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_225 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_145 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_97 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_145 = cat(decoded_andMatrixOutputs_andMatrixInput_15_145, decoded_andMatrixOutputs_andMatrixInput_16_97)
node decoded_andMatrixOutputs_lo_lo_hi_225 = cat(decoded_andMatrixOutputs_andMatrixInput_13_225, decoded_andMatrixOutputs_andMatrixInput_14_225)
node decoded_andMatrixOutputs_lo_lo_230 = cat(decoded_andMatrixOutputs_lo_lo_hi_225, decoded_andMatrixOutputs_lo_lo_lo_145)
node decoded_andMatrixOutputs_lo_hi_lo_225 = cat(decoded_andMatrixOutputs_andMatrixInput_11_225, decoded_andMatrixOutputs_andMatrixInput_12_225)
node decoded_andMatrixOutputs_lo_hi_hi_225 = cat(decoded_andMatrixOutputs_andMatrixInput_9_225, decoded_andMatrixOutputs_andMatrixInput_10_225)
node decoded_andMatrixOutputs_lo_hi_230 = cat(decoded_andMatrixOutputs_lo_hi_hi_225, decoded_andMatrixOutputs_lo_hi_lo_225)
node decoded_andMatrixOutputs_lo_230 = cat(decoded_andMatrixOutputs_lo_hi_230, decoded_andMatrixOutputs_lo_lo_230)
node decoded_andMatrixOutputs_hi_lo_lo_225 = cat(decoded_andMatrixOutputs_andMatrixInput_7_230, decoded_andMatrixOutputs_andMatrixInput_8_229)
node decoded_andMatrixOutputs_hi_lo_hi_225 = cat(decoded_andMatrixOutputs_andMatrixInput_5_230, decoded_andMatrixOutputs_andMatrixInput_6_230)
node decoded_andMatrixOutputs_hi_lo_230 = cat(decoded_andMatrixOutputs_hi_lo_hi_225, decoded_andMatrixOutputs_hi_lo_lo_225)
node decoded_andMatrixOutputs_hi_hi_lo_225 = cat(decoded_andMatrixOutputs_andMatrixInput_3_230, decoded_andMatrixOutputs_andMatrixInput_4_230)
node decoded_andMatrixOutputs_hi_hi_hi_hi_97 = cat(decoded_andMatrixOutputs_andMatrixInput_0_233, decoded_andMatrixOutputs_andMatrixInput_1_233)
node decoded_andMatrixOutputs_hi_hi_hi_229 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_97, decoded_andMatrixOutputs_andMatrixInput_2_233)
node decoded_andMatrixOutputs_hi_hi_230 = cat(decoded_andMatrixOutputs_hi_hi_hi_229, decoded_andMatrixOutputs_hi_hi_lo_225)
node decoded_andMatrixOutputs_hi_233 = cat(decoded_andMatrixOutputs_hi_hi_230, decoded_andMatrixOutputs_hi_lo_230)
node _decoded_andMatrixOutputs_T_233 = cat(decoded_andMatrixOutputs_hi_233, decoded_andMatrixOutputs_lo_230)
node decoded_andMatrixOutputs_38_2_4 = andr(_decoded_andMatrixOutputs_T_233)
node decoded_andMatrixOutputs_andMatrixInput_0_234 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_234 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_234 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_231 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_231 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_231 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_231 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_231 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_230 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_226 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_226 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_226 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_226 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_226 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_226 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_146 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_146 = cat(decoded_andMatrixOutputs_andMatrixInput_14_226, decoded_andMatrixOutputs_andMatrixInput_15_146)
node decoded_andMatrixOutputs_lo_lo_hi_226 = cat(decoded_andMatrixOutputs_andMatrixInput_12_226, decoded_andMatrixOutputs_andMatrixInput_13_226)
node decoded_andMatrixOutputs_lo_lo_231 = cat(decoded_andMatrixOutputs_lo_lo_hi_226, decoded_andMatrixOutputs_lo_lo_lo_146)
node decoded_andMatrixOutputs_lo_hi_lo_226 = cat(decoded_andMatrixOutputs_andMatrixInput_10_226, decoded_andMatrixOutputs_andMatrixInput_11_226)
node decoded_andMatrixOutputs_lo_hi_hi_226 = cat(decoded_andMatrixOutputs_andMatrixInput_8_230, decoded_andMatrixOutputs_andMatrixInput_9_226)
node decoded_andMatrixOutputs_lo_hi_231 = cat(decoded_andMatrixOutputs_lo_hi_hi_226, decoded_andMatrixOutputs_lo_hi_lo_226)
node decoded_andMatrixOutputs_lo_231 = cat(decoded_andMatrixOutputs_lo_hi_231, decoded_andMatrixOutputs_lo_lo_231)
node decoded_andMatrixOutputs_hi_lo_lo_226 = cat(decoded_andMatrixOutputs_andMatrixInput_6_231, decoded_andMatrixOutputs_andMatrixInput_7_231)
node decoded_andMatrixOutputs_hi_lo_hi_226 = cat(decoded_andMatrixOutputs_andMatrixInput_4_231, decoded_andMatrixOutputs_andMatrixInput_5_231)
node decoded_andMatrixOutputs_hi_lo_231 = cat(decoded_andMatrixOutputs_hi_lo_hi_226, decoded_andMatrixOutputs_hi_lo_lo_226)
node decoded_andMatrixOutputs_hi_hi_lo_226 = cat(decoded_andMatrixOutputs_andMatrixInput_2_234, decoded_andMatrixOutputs_andMatrixInput_3_231)
node decoded_andMatrixOutputs_hi_hi_hi_230 = cat(decoded_andMatrixOutputs_andMatrixInput_0_234, decoded_andMatrixOutputs_andMatrixInput_1_234)
node decoded_andMatrixOutputs_hi_hi_231 = cat(decoded_andMatrixOutputs_hi_hi_hi_230, decoded_andMatrixOutputs_hi_hi_lo_226)
node decoded_andMatrixOutputs_hi_234 = cat(decoded_andMatrixOutputs_hi_hi_231, decoded_andMatrixOutputs_hi_lo_231)
node _decoded_andMatrixOutputs_T_234 = cat(decoded_andMatrixOutputs_hi_234, decoded_andMatrixOutputs_lo_231)
node decoded_andMatrixOutputs_5_2_4 = andr(_decoded_andMatrixOutputs_T_234)
node decoded_andMatrixOutputs_andMatrixInput_0_235 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_235 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_235 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_232 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_232 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_232 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_232 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_232 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_231 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_227 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_227 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_227 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_227 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_227 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_227 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_147 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_147 = cat(decoded_andMatrixOutputs_andMatrixInput_14_227, decoded_andMatrixOutputs_andMatrixInput_15_147)
node decoded_andMatrixOutputs_lo_lo_hi_227 = cat(decoded_andMatrixOutputs_andMatrixInput_12_227, decoded_andMatrixOutputs_andMatrixInput_13_227)
node decoded_andMatrixOutputs_lo_lo_232 = cat(decoded_andMatrixOutputs_lo_lo_hi_227, decoded_andMatrixOutputs_lo_lo_lo_147)
node decoded_andMatrixOutputs_lo_hi_lo_227 = cat(decoded_andMatrixOutputs_andMatrixInput_10_227, decoded_andMatrixOutputs_andMatrixInput_11_227)
node decoded_andMatrixOutputs_lo_hi_hi_227 = cat(decoded_andMatrixOutputs_andMatrixInput_8_231, decoded_andMatrixOutputs_andMatrixInput_9_227)
node decoded_andMatrixOutputs_lo_hi_232 = cat(decoded_andMatrixOutputs_lo_hi_hi_227, decoded_andMatrixOutputs_lo_hi_lo_227)
node decoded_andMatrixOutputs_lo_232 = cat(decoded_andMatrixOutputs_lo_hi_232, decoded_andMatrixOutputs_lo_lo_232)
node decoded_andMatrixOutputs_hi_lo_lo_227 = cat(decoded_andMatrixOutputs_andMatrixInput_6_232, decoded_andMatrixOutputs_andMatrixInput_7_232)
node decoded_andMatrixOutputs_hi_lo_hi_227 = cat(decoded_andMatrixOutputs_andMatrixInput_4_232, decoded_andMatrixOutputs_andMatrixInput_5_232)
node decoded_andMatrixOutputs_hi_lo_232 = cat(decoded_andMatrixOutputs_hi_lo_hi_227, decoded_andMatrixOutputs_hi_lo_lo_227)
node decoded_andMatrixOutputs_hi_hi_lo_227 = cat(decoded_andMatrixOutputs_andMatrixInput_2_235, decoded_andMatrixOutputs_andMatrixInput_3_232)
node decoded_andMatrixOutputs_hi_hi_hi_231 = cat(decoded_andMatrixOutputs_andMatrixInput_0_235, decoded_andMatrixOutputs_andMatrixInput_1_235)
node decoded_andMatrixOutputs_hi_hi_232 = cat(decoded_andMatrixOutputs_hi_hi_hi_231, decoded_andMatrixOutputs_hi_hi_lo_227)
node decoded_andMatrixOutputs_hi_235 = cat(decoded_andMatrixOutputs_hi_hi_232, decoded_andMatrixOutputs_hi_lo_232)
node _decoded_andMatrixOutputs_T_235 = cat(decoded_andMatrixOutputs_hi_235, decoded_andMatrixOutputs_lo_232)
node decoded_andMatrixOutputs_37_2_4 = andr(_decoded_andMatrixOutputs_T_235)
node decoded_andMatrixOutputs_andMatrixInput_0_236 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_236 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_236 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_233 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_233 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_233 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_233 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_233 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_232 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_228 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_228 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_228 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_228 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_228 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_228 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_148 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_98 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_148 = cat(decoded_andMatrixOutputs_andMatrixInput_15_148, decoded_andMatrixOutputs_andMatrixInput_16_98)
node decoded_andMatrixOutputs_lo_lo_hi_228 = cat(decoded_andMatrixOutputs_andMatrixInput_13_228, decoded_andMatrixOutputs_andMatrixInput_14_228)
node decoded_andMatrixOutputs_lo_lo_233 = cat(decoded_andMatrixOutputs_lo_lo_hi_228, decoded_andMatrixOutputs_lo_lo_lo_148)
node decoded_andMatrixOutputs_lo_hi_lo_228 = cat(decoded_andMatrixOutputs_andMatrixInput_11_228, decoded_andMatrixOutputs_andMatrixInput_12_228)
node decoded_andMatrixOutputs_lo_hi_hi_228 = cat(decoded_andMatrixOutputs_andMatrixInput_9_228, decoded_andMatrixOutputs_andMatrixInput_10_228)
node decoded_andMatrixOutputs_lo_hi_233 = cat(decoded_andMatrixOutputs_lo_hi_hi_228, decoded_andMatrixOutputs_lo_hi_lo_228)
node decoded_andMatrixOutputs_lo_233 = cat(decoded_andMatrixOutputs_lo_hi_233, decoded_andMatrixOutputs_lo_lo_233)
node decoded_andMatrixOutputs_hi_lo_lo_228 = cat(decoded_andMatrixOutputs_andMatrixInput_7_233, decoded_andMatrixOutputs_andMatrixInput_8_232)
node decoded_andMatrixOutputs_hi_lo_hi_228 = cat(decoded_andMatrixOutputs_andMatrixInput_5_233, decoded_andMatrixOutputs_andMatrixInput_6_233)
node decoded_andMatrixOutputs_hi_lo_233 = cat(decoded_andMatrixOutputs_hi_lo_hi_228, decoded_andMatrixOutputs_hi_lo_lo_228)
node decoded_andMatrixOutputs_hi_hi_lo_228 = cat(decoded_andMatrixOutputs_andMatrixInput_3_233, decoded_andMatrixOutputs_andMatrixInput_4_233)
node decoded_andMatrixOutputs_hi_hi_hi_hi_98 = cat(decoded_andMatrixOutputs_andMatrixInput_0_236, decoded_andMatrixOutputs_andMatrixInput_1_236)
node decoded_andMatrixOutputs_hi_hi_hi_232 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_98, decoded_andMatrixOutputs_andMatrixInput_2_236)
node decoded_andMatrixOutputs_hi_hi_233 = cat(decoded_andMatrixOutputs_hi_hi_hi_232, decoded_andMatrixOutputs_hi_hi_lo_228)
node decoded_andMatrixOutputs_hi_236 = cat(decoded_andMatrixOutputs_hi_hi_233, decoded_andMatrixOutputs_hi_lo_233)
node _decoded_andMatrixOutputs_T_236 = cat(decoded_andMatrixOutputs_hi_236, decoded_andMatrixOutputs_lo_233)
node decoded_andMatrixOutputs_65_2_1 = andr(_decoded_andMatrixOutputs_T_236)
node decoded_andMatrixOutputs_andMatrixInput_0_237 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_237 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_237 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_234 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_234 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_234 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_234 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_234 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_233 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_229 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_229 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_229 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_229 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_229 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_229 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_149 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_99 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_149 = cat(decoded_andMatrixOutputs_andMatrixInput_15_149, decoded_andMatrixOutputs_andMatrixInput_16_99)
node decoded_andMatrixOutputs_lo_lo_hi_229 = cat(decoded_andMatrixOutputs_andMatrixInput_13_229, decoded_andMatrixOutputs_andMatrixInput_14_229)
node decoded_andMatrixOutputs_lo_lo_234 = cat(decoded_andMatrixOutputs_lo_lo_hi_229, decoded_andMatrixOutputs_lo_lo_lo_149)
node decoded_andMatrixOutputs_lo_hi_lo_229 = cat(decoded_andMatrixOutputs_andMatrixInput_11_229, decoded_andMatrixOutputs_andMatrixInput_12_229)
node decoded_andMatrixOutputs_lo_hi_hi_229 = cat(decoded_andMatrixOutputs_andMatrixInput_9_229, decoded_andMatrixOutputs_andMatrixInput_10_229)
node decoded_andMatrixOutputs_lo_hi_234 = cat(decoded_andMatrixOutputs_lo_hi_hi_229, decoded_andMatrixOutputs_lo_hi_lo_229)
node decoded_andMatrixOutputs_lo_234 = cat(decoded_andMatrixOutputs_lo_hi_234, decoded_andMatrixOutputs_lo_lo_234)
node decoded_andMatrixOutputs_hi_lo_lo_229 = cat(decoded_andMatrixOutputs_andMatrixInput_7_234, decoded_andMatrixOutputs_andMatrixInput_8_233)
node decoded_andMatrixOutputs_hi_lo_hi_229 = cat(decoded_andMatrixOutputs_andMatrixInput_5_234, decoded_andMatrixOutputs_andMatrixInput_6_234)
node decoded_andMatrixOutputs_hi_lo_234 = cat(decoded_andMatrixOutputs_hi_lo_hi_229, decoded_andMatrixOutputs_hi_lo_lo_229)
node decoded_andMatrixOutputs_hi_hi_lo_229 = cat(decoded_andMatrixOutputs_andMatrixInput_3_234, decoded_andMatrixOutputs_andMatrixInput_4_234)
node decoded_andMatrixOutputs_hi_hi_hi_hi_99 = cat(decoded_andMatrixOutputs_andMatrixInput_0_237, decoded_andMatrixOutputs_andMatrixInput_1_237)
node decoded_andMatrixOutputs_hi_hi_hi_233 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_99, decoded_andMatrixOutputs_andMatrixInput_2_237)
node decoded_andMatrixOutputs_hi_hi_234 = cat(decoded_andMatrixOutputs_hi_hi_hi_233, decoded_andMatrixOutputs_hi_hi_lo_229)
node decoded_andMatrixOutputs_hi_237 = cat(decoded_andMatrixOutputs_hi_hi_234, decoded_andMatrixOutputs_hi_lo_234)
node _decoded_andMatrixOutputs_T_237 = cat(decoded_andMatrixOutputs_hi_237, decoded_andMatrixOutputs_lo_234)
node decoded_andMatrixOutputs_48_2_3 = andr(_decoded_andMatrixOutputs_T_237)
node decoded_andMatrixOutputs_andMatrixInput_0_238 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_238 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_238 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_235 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_235 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_235 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_235 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_235 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_234 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_230 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_230 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_230 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_230 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_230 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_230 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_150 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_100 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_150 = cat(decoded_andMatrixOutputs_andMatrixInput_15_150, decoded_andMatrixOutputs_andMatrixInput_16_100)
node decoded_andMatrixOutputs_lo_lo_hi_230 = cat(decoded_andMatrixOutputs_andMatrixInput_13_230, decoded_andMatrixOutputs_andMatrixInput_14_230)
node decoded_andMatrixOutputs_lo_lo_235 = cat(decoded_andMatrixOutputs_lo_lo_hi_230, decoded_andMatrixOutputs_lo_lo_lo_150)
node decoded_andMatrixOutputs_lo_hi_lo_230 = cat(decoded_andMatrixOutputs_andMatrixInput_11_230, decoded_andMatrixOutputs_andMatrixInput_12_230)
node decoded_andMatrixOutputs_lo_hi_hi_230 = cat(decoded_andMatrixOutputs_andMatrixInput_9_230, decoded_andMatrixOutputs_andMatrixInput_10_230)
node decoded_andMatrixOutputs_lo_hi_235 = cat(decoded_andMatrixOutputs_lo_hi_hi_230, decoded_andMatrixOutputs_lo_hi_lo_230)
node decoded_andMatrixOutputs_lo_235 = cat(decoded_andMatrixOutputs_lo_hi_235, decoded_andMatrixOutputs_lo_lo_235)
node decoded_andMatrixOutputs_hi_lo_lo_230 = cat(decoded_andMatrixOutputs_andMatrixInput_7_235, decoded_andMatrixOutputs_andMatrixInput_8_234)
node decoded_andMatrixOutputs_hi_lo_hi_230 = cat(decoded_andMatrixOutputs_andMatrixInput_5_235, decoded_andMatrixOutputs_andMatrixInput_6_235)
node decoded_andMatrixOutputs_hi_lo_235 = cat(decoded_andMatrixOutputs_hi_lo_hi_230, decoded_andMatrixOutputs_hi_lo_lo_230)
node decoded_andMatrixOutputs_hi_hi_lo_230 = cat(decoded_andMatrixOutputs_andMatrixInput_3_235, decoded_andMatrixOutputs_andMatrixInput_4_235)
node decoded_andMatrixOutputs_hi_hi_hi_hi_100 = cat(decoded_andMatrixOutputs_andMatrixInput_0_238, decoded_andMatrixOutputs_andMatrixInput_1_238)
node decoded_andMatrixOutputs_hi_hi_hi_234 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_100, decoded_andMatrixOutputs_andMatrixInput_2_238)
node decoded_andMatrixOutputs_hi_hi_235 = cat(decoded_andMatrixOutputs_hi_hi_hi_234, decoded_andMatrixOutputs_hi_hi_lo_230)
node decoded_andMatrixOutputs_hi_238 = cat(decoded_andMatrixOutputs_hi_hi_235, decoded_andMatrixOutputs_hi_lo_235)
node _decoded_andMatrixOutputs_T_238 = cat(decoded_andMatrixOutputs_hi_238, decoded_andMatrixOutputs_lo_235)
node decoded_andMatrixOutputs_47_2_3 = andr(_decoded_andMatrixOutputs_T_238)
node decoded_andMatrixOutputs_andMatrixInput_0_239 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_239 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_239 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_236 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_236 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_236 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_236 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_236 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_235 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_231 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_231 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_231 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_231 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_231 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_231 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_151 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_101 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_lo_lo_lo_151 = cat(decoded_andMatrixOutputs_andMatrixInput_15_151, decoded_andMatrixOutputs_andMatrixInput_16_101)
node decoded_andMatrixOutputs_lo_lo_hi_231 = cat(decoded_andMatrixOutputs_andMatrixInput_13_231, decoded_andMatrixOutputs_andMatrixInput_14_231)
node decoded_andMatrixOutputs_lo_lo_236 = cat(decoded_andMatrixOutputs_lo_lo_hi_231, decoded_andMatrixOutputs_lo_lo_lo_151)
node decoded_andMatrixOutputs_lo_hi_lo_231 = cat(decoded_andMatrixOutputs_andMatrixInput_11_231, decoded_andMatrixOutputs_andMatrixInput_12_231)
node decoded_andMatrixOutputs_lo_hi_hi_231 = cat(decoded_andMatrixOutputs_andMatrixInput_9_231, decoded_andMatrixOutputs_andMatrixInput_10_231)
node decoded_andMatrixOutputs_lo_hi_236 = cat(decoded_andMatrixOutputs_lo_hi_hi_231, decoded_andMatrixOutputs_lo_hi_lo_231)
node decoded_andMatrixOutputs_lo_236 = cat(decoded_andMatrixOutputs_lo_hi_236, decoded_andMatrixOutputs_lo_lo_236)
node decoded_andMatrixOutputs_hi_lo_lo_231 = cat(decoded_andMatrixOutputs_andMatrixInput_7_236, decoded_andMatrixOutputs_andMatrixInput_8_235)
node decoded_andMatrixOutputs_hi_lo_hi_231 = cat(decoded_andMatrixOutputs_andMatrixInput_5_236, decoded_andMatrixOutputs_andMatrixInput_6_236)
node decoded_andMatrixOutputs_hi_lo_236 = cat(decoded_andMatrixOutputs_hi_lo_hi_231, decoded_andMatrixOutputs_hi_lo_lo_231)
node decoded_andMatrixOutputs_hi_hi_lo_231 = cat(decoded_andMatrixOutputs_andMatrixInput_3_236, decoded_andMatrixOutputs_andMatrixInput_4_236)
node decoded_andMatrixOutputs_hi_hi_hi_hi_101 = cat(decoded_andMatrixOutputs_andMatrixInput_0_239, decoded_andMatrixOutputs_andMatrixInput_1_239)
node decoded_andMatrixOutputs_hi_hi_hi_235 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_101, decoded_andMatrixOutputs_andMatrixInput_2_239)
node decoded_andMatrixOutputs_hi_hi_236 = cat(decoded_andMatrixOutputs_hi_hi_hi_235, decoded_andMatrixOutputs_hi_hi_lo_231)
node decoded_andMatrixOutputs_hi_239 = cat(decoded_andMatrixOutputs_hi_hi_236, decoded_andMatrixOutputs_hi_lo_236)
node _decoded_andMatrixOutputs_T_239 = cat(decoded_andMatrixOutputs_hi_239, decoded_andMatrixOutputs_lo_236)
node decoded_andMatrixOutputs_32_2_4 = andr(_decoded_andMatrixOutputs_T_239)
node decoded_andMatrixOutputs_andMatrixInput_0_240 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_240 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_240 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_237 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_237 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_237 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_237 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_237 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_236 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_232 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_232 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_232 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_232 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_232 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_232 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_152 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_102 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_152 = cat(decoded_andMatrixOutputs_andMatrixInput_15_152, decoded_andMatrixOutputs_andMatrixInput_16_102)
node decoded_andMatrixOutputs_lo_lo_hi_232 = cat(decoded_andMatrixOutputs_andMatrixInput_13_232, decoded_andMatrixOutputs_andMatrixInput_14_232)
node decoded_andMatrixOutputs_lo_lo_237 = cat(decoded_andMatrixOutputs_lo_lo_hi_232, decoded_andMatrixOutputs_lo_lo_lo_152)
node decoded_andMatrixOutputs_lo_hi_lo_232 = cat(decoded_andMatrixOutputs_andMatrixInput_11_232, decoded_andMatrixOutputs_andMatrixInput_12_232)
node decoded_andMatrixOutputs_lo_hi_hi_232 = cat(decoded_andMatrixOutputs_andMatrixInput_9_232, decoded_andMatrixOutputs_andMatrixInput_10_232)
node decoded_andMatrixOutputs_lo_hi_237 = cat(decoded_andMatrixOutputs_lo_hi_hi_232, decoded_andMatrixOutputs_lo_hi_lo_232)
node decoded_andMatrixOutputs_lo_237 = cat(decoded_andMatrixOutputs_lo_hi_237, decoded_andMatrixOutputs_lo_lo_237)
node decoded_andMatrixOutputs_hi_lo_lo_232 = cat(decoded_andMatrixOutputs_andMatrixInput_7_237, decoded_andMatrixOutputs_andMatrixInput_8_236)
node decoded_andMatrixOutputs_hi_lo_hi_232 = cat(decoded_andMatrixOutputs_andMatrixInput_5_237, decoded_andMatrixOutputs_andMatrixInput_6_237)
node decoded_andMatrixOutputs_hi_lo_237 = cat(decoded_andMatrixOutputs_hi_lo_hi_232, decoded_andMatrixOutputs_hi_lo_lo_232)
node decoded_andMatrixOutputs_hi_hi_lo_232 = cat(decoded_andMatrixOutputs_andMatrixInput_3_237, decoded_andMatrixOutputs_andMatrixInput_4_237)
node decoded_andMatrixOutputs_hi_hi_hi_hi_102 = cat(decoded_andMatrixOutputs_andMatrixInput_0_240, decoded_andMatrixOutputs_andMatrixInput_1_240)
node decoded_andMatrixOutputs_hi_hi_hi_236 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_102, decoded_andMatrixOutputs_andMatrixInput_2_240)
node decoded_andMatrixOutputs_hi_hi_237 = cat(decoded_andMatrixOutputs_hi_hi_hi_236, decoded_andMatrixOutputs_hi_hi_lo_232)
node decoded_andMatrixOutputs_hi_240 = cat(decoded_andMatrixOutputs_hi_hi_237, decoded_andMatrixOutputs_hi_lo_237)
node _decoded_andMatrixOutputs_T_240 = cat(decoded_andMatrixOutputs_hi_240, decoded_andMatrixOutputs_lo_237)
node decoded_andMatrixOutputs_40_2_4 = andr(_decoded_andMatrixOutputs_T_240)
node decoded_andMatrixOutputs_andMatrixInput_0_241 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_241 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_241 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_238 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_238 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_238 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_238 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_238 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_237 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_233 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_233 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_233 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_233 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_233 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_233 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_153 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_103 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_153 = cat(decoded_andMatrixOutputs_andMatrixInput_15_153, decoded_andMatrixOutputs_andMatrixInput_16_103)
node decoded_andMatrixOutputs_lo_lo_hi_233 = cat(decoded_andMatrixOutputs_andMatrixInput_13_233, decoded_andMatrixOutputs_andMatrixInput_14_233)
node decoded_andMatrixOutputs_lo_lo_238 = cat(decoded_andMatrixOutputs_lo_lo_hi_233, decoded_andMatrixOutputs_lo_lo_lo_153)
node decoded_andMatrixOutputs_lo_hi_lo_233 = cat(decoded_andMatrixOutputs_andMatrixInput_11_233, decoded_andMatrixOutputs_andMatrixInput_12_233)
node decoded_andMatrixOutputs_lo_hi_hi_233 = cat(decoded_andMatrixOutputs_andMatrixInput_9_233, decoded_andMatrixOutputs_andMatrixInput_10_233)
node decoded_andMatrixOutputs_lo_hi_238 = cat(decoded_andMatrixOutputs_lo_hi_hi_233, decoded_andMatrixOutputs_lo_hi_lo_233)
node decoded_andMatrixOutputs_lo_238 = cat(decoded_andMatrixOutputs_lo_hi_238, decoded_andMatrixOutputs_lo_lo_238)
node decoded_andMatrixOutputs_hi_lo_lo_233 = cat(decoded_andMatrixOutputs_andMatrixInput_7_238, decoded_andMatrixOutputs_andMatrixInput_8_237)
node decoded_andMatrixOutputs_hi_lo_hi_233 = cat(decoded_andMatrixOutputs_andMatrixInput_5_238, decoded_andMatrixOutputs_andMatrixInput_6_238)
node decoded_andMatrixOutputs_hi_lo_238 = cat(decoded_andMatrixOutputs_hi_lo_hi_233, decoded_andMatrixOutputs_hi_lo_lo_233)
node decoded_andMatrixOutputs_hi_hi_lo_233 = cat(decoded_andMatrixOutputs_andMatrixInput_3_238, decoded_andMatrixOutputs_andMatrixInput_4_238)
node decoded_andMatrixOutputs_hi_hi_hi_hi_103 = cat(decoded_andMatrixOutputs_andMatrixInput_0_241, decoded_andMatrixOutputs_andMatrixInput_1_241)
node decoded_andMatrixOutputs_hi_hi_hi_237 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_103, decoded_andMatrixOutputs_andMatrixInput_2_241)
node decoded_andMatrixOutputs_hi_hi_238 = cat(decoded_andMatrixOutputs_hi_hi_hi_237, decoded_andMatrixOutputs_hi_hi_lo_233)
node decoded_andMatrixOutputs_hi_241 = cat(decoded_andMatrixOutputs_hi_hi_238, decoded_andMatrixOutputs_hi_lo_238)
node _decoded_andMatrixOutputs_T_241 = cat(decoded_andMatrixOutputs_hi_241, decoded_andMatrixOutputs_lo_238)
node decoded_andMatrixOutputs_69_2_1 = andr(_decoded_andMatrixOutputs_T_241)
node decoded_andMatrixOutputs_andMatrixInput_0_242 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_242 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_242 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_239 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_239 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_239 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_239 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_239 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_238 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_234 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_234 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_234 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_234 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_234 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_234 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_154 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_154 = cat(decoded_andMatrixOutputs_andMatrixInput_14_234, decoded_andMatrixOutputs_andMatrixInput_15_154)
node decoded_andMatrixOutputs_lo_lo_hi_234 = cat(decoded_andMatrixOutputs_andMatrixInput_12_234, decoded_andMatrixOutputs_andMatrixInput_13_234)
node decoded_andMatrixOutputs_lo_lo_239 = cat(decoded_andMatrixOutputs_lo_lo_hi_234, decoded_andMatrixOutputs_lo_lo_lo_154)
node decoded_andMatrixOutputs_lo_hi_lo_234 = cat(decoded_andMatrixOutputs_andMatrixInput_10_234, decoded_andMatrixOutputs_andMatrixInput_11_234)
node decoded_andMatrixOutputs_lo_hi_hi_234 = cat(decoded_andMatrixOutputs_andMatrixInput_8_238, decoded_andMatrixOutputs_andMatrixInput_9_234)
node decoded_andMatrixOutputs_lo_hi_239 = cat(decoded_andMatrixOutputs_lo_hi_hi_234, decoded_andMatrixOutputs_lo_hi_lo_234)
node decoded_andMatrixOutputs_lo_239 = cat(decoded_andMatrixOutputs_lo_hi_239, decoded_andMatrixOutputs_lo_lo_239)
node decoded_andMatrixOutputs_hi_lo_lo_234 = cat(decoded_andMatrixOutputs_andMatrixInput_6_239, decoded_andMatrixOutputs_andMatrixInput_7_239)
node decoded_andMatrixOutputs_hi_lo_hi_234 = cat(decoded_andMatrixOutputs_andMatrixInput_4_239, decoded_andMatrixOutputs_andMatrixInput_5_239)
node decoded_andMatrixOutputs_hi_lo_239 = cat(decoded_andMatrixOutputs_hi_lo_hi_234, decoded_andMatrixOutputs_hi_lo_lo_234)
node decoded_andMatrixOutputs_hi_hi_lo_234 = cat(decoded_andMatrixOutputs_andMatrixInput_2_242, decoded_andMatrixOutputs_andMatrixInput_3_239)
node decoded_andMatrixOutputs_hi_hi_hi_238 = cat(decoded_andMatrixOutputs_andMatrixInput_0_242, decoded_andMatrixOutputs_andMatrixInput_1_242)
node decoded_andMatrixOutputs_hi_hi_239 = cat(decoded_andMatrixOutputs_hi_hi_hi_238, decoded_andMatrixOutputs_hi_hi_lo_234)
node decoded_andMatrixOutputs_hi_242 = cat(decoded_andMatrixOutputs_hi_hi_239, decoded_andMatrixOutputs_hi_lo_239)
node _decoded_andMatrixOutputs_T_242 = cat(decoded_andMatrixOutputs_hi_242, decoded_andMatrixOutputs_lo_239)
node decoded_andMatrixOutputs_51_2_3 = andr(_decoded_andMatrixOutputs_T_242)
node decoded_andMatrixOutputs_andMatrixInput_0_243 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_243 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_243 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_240 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_240 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_240 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_240 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_240 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_239 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_235 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_235 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_235 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_235 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_235 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_235 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_155 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_155 = cat(decoded_andMatrixOutputs_andMatrixInput_14_235, decoded_andMatrixOutputs_andMatrixInput_15_155)
node decoded_andMatrixOutputs_lo_lo_hi_235 = cat(decoded_andMatrixOutputs_andMatrixInput_12_235, decoded_andMatrixOutputs_andMatrixInput_13_235)
node decoded_andMatrixOutputs_lo_lo_240 = cat(decoded_andMatrixOutputs_lo_lo_hi_235, decoded_andMatrixOutputs_lo_lo_lo_155)
node decoded_andMatrixOutputs_lo_hi_lo_235 = cat(decoded_andMatrixOutputs_andMatrixInput_10_235, decoded_andMatrixOutputs_andMatrixInput_11_235)
node decoded_andMatrixOutputs_lo_hi_hi_235 = cat(decoded_andMatrixOutputs_andMatrixInput_8_239, decoded_andMatrixOutputs_andMatrixInput_9_235)
node decoded_andMatrixOutputs_lo_hi_240 = cat(decoded_andMatrixOutputs_lo_hi_hi_235, decoded_andMatrixOutputs_lo_hi_lo_235)
node decoded_andMatrixOutputs_lo_240 = cat(decoded_andMatrixOutputs_lo_hi_240, decoded_andMatrixOutputs_lo_lo_240)
node decoded_andMatrixOutputs_hi_lo_lo_235 = cat(decoded_andMatrixOutputs_andMatrixInput_6_240, decoded_andMatrixOutputs_andMatrixInput_7_240)
node decoded_andMatrixOutputs_hi_lo_hi_235 = cat(decoded_andMatrixOutputs_andMatrixInput_4_240, decoded_andMatrixOutputs_andMatrixInput_5_240)
node decoded_andMatrixOutputs_hi_lo_240 = cat(decoded_andMatrixOutputs_hi_lo_hi_235, decoded_andMatrixOutputs_hi_lo_lo_235)
node decoded_andMatrixOutputs_hi_hi_lo_235 = cat(decoded_andMatrixOutputs_andMatrixInput_2_243, decoded_andMatrixOutputs_andMatrixInput_3_240)
node decoded_andMatrixOutputs_hi_hi_hi_239 = cat(decoded_andMatrixOutputs_andMatrixInput_0_243, decoded_andMatrixOutputs_andMatrixInput_1_243)
node decoded_andMatrixOutputs_hi_hi_240 = cat(decoded_andMatrixOutputs_hi_hi_hi_239, decoded_andMatrixOutputs_hi_hi_lo_235)
node decoded_andMatrixOutputs_hi_243 = cat(decoded_andMatrixOutputs_hi_hi_240, decoded_andMatrixOutputs_hi_lo_240)
node _decoded_andMatrixOutputs_T_243 = cat(decoded_andMatrixOutputs_hi_243, decoded_andMatrixOutputs_lo_240)
node decoded_andMatrixOutputs_67_2_1 = andr(_decoded_andMatrixOutputs_T_243)
node decoded_andMatrixOutputs_andMatrixInput_0_244 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_244 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_244 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_241 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_241 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_241 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_241 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_241 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_240 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_236 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_236 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_236 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_236 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_236 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_236 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_156 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_104 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_156 = cat(decoded_andMatrixOutputs_andMatrixInput_15_156, decoded_andMatrixOutputs_andMatrixInput_16_104)
node decoded_andMatrixOutputs_lo_lo_hi_236 = cat(decoded_andMatrixOutputs_andMatrixInput_13_236, decoded_andMatrixOutputs_andMatrixInput_14_236)
node decoded_andMatrixOutputs_lo_lo_241 = cat(decoded_andMatrixOutputs_lo_lo_hi_236, decoded_andMatrixOutputs_lo_lo_lo_156)
node decoded_andMatrixOutputs_lo_hi_lo_236 = cat(decoded_andMatrixOutputs_andMatrixInput_11_236, decoded_andMatrixOutputs_andMatrixInput_12_236)
node decoded_andMatrixOutputs_lo_hi_hi_236 = cat(decoded_andMatrixOutputs_andMatrixInput_9_236, decoded_andMatrixOutputs_andMatrixInput_10_236)
node decoded_andMatrixOutputs_lo_hi_241 = cat(decoded_andMatrixOutputs_lo_hi_hi_236, decoded_andMatrixOutputs_lo_hi_lo_236)
node decoded_andMatrixOutputs_lo_241 = cat(decoded_andMatrixOutputs_lo_hi_241, decoded_andMatrixOutputs_lo_lo_241)
node decoded_andMatrixOutputs_hi_lo_lo_236 = cat(decoded_andMatrixOutputs_andMatrixInput_7_241, decoded_andMatrixOutputs_andMatrixInput_8_240)
node decoded_andMatrixOutputs_hi_lo_hi_236 = cat(decoded_andMatrixOutputs_andMatrixInput_5_241, decoded_andMatrixOutputs_andMatrixInput_6_241)
node decoded_andMatrixOutputs_hi_lo_241 = cat(decoded_andMatrixOutputs_hi_lo_hi_236, decoded_andMatrixOutputs_hi_lo_lo_236)
node decoded_andMatrixOutputs_hi_hi_lo_236 = cat(decoded_andMatrixOutputs_andMatrixInput_3_241, decoded_andMatrixOutputs_andMatrixInput_4_241)
node decoded_andMatrixOutputs_hi_hi_hi_hi_104 = cat(decoded_andMatrixOutputs_andMatrixInput_0_244, decoded_andMatrixOutputs_andMatrixInput_1_244)
node decoded_andMatrixOutputs_hi_hi_hi_240 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_104, decoded_andMatrixOutputs_andMatrixInput_2_244)
node decoded_andMatrixOutputs_hi_hi_241 = cat(decoded_andMatrixOutputs_hi_hi_hi_240, decoded_andMatrixOutputs_hi_hi_lo_236)
node decoded_andMatrixOutputs_hi_244 = cat(decoded_andMatrixOutputs_hi_hi_241, decoded_andMatrixOutputs_hi_lo_241)
node _decoded_andMatrixOutputs_T_244 = cat(decoded_andMatrixOutputs_hi_244, decoded_andMatrixOutputs_lo_241)
node decoded_andMatrixOutputs_27_2_4 = andr(_decoded_andMatrixOutputs_T_244)
node decoded_andMatrixOutputs_andMatrixInput_0_245 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_245 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_245 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_242 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_242 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_242 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_242 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_242 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_241 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_237 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_237 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_237 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_237 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_237 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_237 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_157 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_157 = cat(decoded_andMatrixOutputs_andMatrixInput_14_237, decoded_andMatrixOutputs_andMatrixInput_15_157)
node decoded_andMatrixOutputs_lo_lo_hi_237 = cat(decoded_andMatrixOutputs_andMatrixInput_12_237, decoded_andMatrixOutputs_andMatrixInput_13_237)
node decoded_andMatrixOutputs_lo_lo_242 = cat(decoded_andMatrixOutputs_lo_lo_hi_237, decoded_andMatrixOutputs_lo_lo_lo_157)
node decoded_andMatrixOutputs_lo_hi_lo_237 = cat(decoded_andMatrixOutputs_andMatrixInput_10_237, decoded_andMatrixOutputs_andMatrixInput_11_237)
node decoded_andMatrixOutputs_lo_hi_hi_237 = cat(decoded_andMatrixOutputs_andMatrixInput_8_241, decoded_andMatrixOutputs_andMatrixInput_9_237)
node decoded_andMatrixOutputs_lo_hi_242 = cat(decoded_andMatrixOutputs_lo_hi_hi_237, decoded_andMatrixOutputs_lo_hi_lo_237)
node decoded_andMatrixOutputs_lo_242 = cat(decoded_andMatrixOutputs_lo_hi_242, decoded_andMatrixOutputs_lo_lo_242)
node decoded_andMatrixOutputs_hi_lo_lo_237 = cat(decoded_andMatrixOutputs_andMatrixInput_6_242, decoded_andMatrixOutputs_andMatrixInput_7_242)
node decoded_andMatrixOutputs_hi_lo_hi_237 = cat(decoded_andMatrixOutputs_andMatrixInput_4_242, decoded_andMatrixOutputs_andMatrixInput_5_242)
node decoded_andMatrixOutputs_hi_lo_242 = cat(decoded_andMatrixOutputs_hi_lo_hi_237, decoded_andMatrixOutputs_hi_lo_lo_237)
node decoded_andMatrixOutputs_hi_hi_lo_237 = cat(decoded_andMatrixOutputs_andMatrixInput_2_245, decoded_andMatrixOutputs_andMatrixInput_3_242)
node decoded_andMatrixOutputs_hi_hi_hi_241 = cat(decoded_andMatrixOutputs_andMatrixInput_0_245, decoded_andMatrixOutputs_andMatrixInput_1_245)
node decoded_andMatrixOutputs_hi_hi_242 = cat(decoded_andMatrixOutputs_hi_hi_hi_241, decoded_andMatrixOutputs_hi_hi_lo_237)
node decoded_andMatrixOutputs_hi_245 = cat(decoded_andMatrixOutputs_hi_hi_242, decoded_andMatrixOutputs_hi_lo_242)
node _decoded_andMatrixOutputs_T_245 = cat(decoded_andMatrixOutputs_hi_245, decoded_andMatrixOutputs_lo_242)
node decoded_andMatrixOutputs_4_2_4 = andr(_decoded_andMatrixOutputs_T_245)
node decoded_andMatrixOutputs_andMatrixInput_0_246 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_246 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_246 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_243 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_243 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_243 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_243 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_243 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_242 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_238 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_238 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_238 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_238 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_238 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_238 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_158 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_105 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_158 = cat(decoded_andMatrixOutputs_andMatrixInput_15_158, decoded_andMatrixOutputs_andMatrixInput_16_105)
node decoded_andMatrixOutputs_lo_lo_hi_238 = cat(decoded_andMatrixOutputs_andMatrixInput_13_238, decoded_andMatrixOutputs_andMatrixInput_14_238)
node decoded_andMatrixOutputs_lo_lo_243 = cat(decoded_andMatrixOutputs_lo_lo_hi_238, decoded_andMatrixOutputs_lo_lo_lo_158)
node decoded_andMatrixOutputs_lo_hi_lo_238 = cat(decoded_andMatrixOutputs_andMatrixInput_11_238, decoded_andMatrixOutputs_andMatrixInput_12_238)
node decoded_andMatrixOutputs_lo_hi_hi_238 = cat(decoded_andMatrixOutputs_andMatrixInput_9_238, decoded_andMatrixOutputs_andMatrixInput_10_238)
node decoded_andMatrixOutputs_lo_hi_243 = cat(decoded_andMatrixOutputs_lo_hi_hi_238, decoded_andMatrixOutputs_lo_hi_lo_238)
node decoded_andMatrixOutputs_lo_243 = cat(decoded_andMatrixOutputs_lo_hi_243, decoded_andMatrixOutputs_lo_lo_243)
node decoded_andMatrixOutputs_hi_lo_lo_238 = cat(decoded_andMatrixOutputs_andMatrixInput_7_243, decoded_andMatrixOutputs_andMatrixInput_8_242)
node decoded_andMatrixOutputs_hi_lo_hi_238 = cat(decoded_andMatrixOutputs_andMatrixInput_5_243, decoded_andMatrixOutputs_andMatrixInput_6_243)
node decoded_andMatrixOutputs_hi_lo_243 = cat(decoded_andMatrixOutputs_hi_lo_hi_238, decoded_andMatrixOutputs_hi_lo_lo_238)
node decoded_andMatrixOutputs_hi_hi_lo_238 = cat(decoded_andMatrixOutputs_andMatrixInput_3_243, decoded_andMatrixOutputs_andMatrixInput_4_243)
node decoded_andMatrixOutputs_hi_hi_hi_hi_105 = cat(decoded_andMatrixOutputs_andMatrixInput_0_246, decoded_andMatrixOutputs_andMatrixInput_1_246)
node decoded_andMatrixOutputs_hi_hi_hi_242 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_105, decoded_andMatrixOutputs_andMatrixInput_2_246)
node decoded_andMatrixOutputs_hi_hi_243 = cat(decoded_andMatrixOutputs_hi_hi_hi_242, decoded_andMatrixOutputs_hi_hi_lo_238)
node decoded_andMatrixOutputs_hi_246 = cat(decoded_andMatrixOutputs_hi_hi_243, decoded_andMatrixOutputs_hi_lo_243)
node _decoded_andMatrixOutputs_T_246 = cat(decoded_andMatrixOutputs_hi_246, decoded_andMatrixOutputs_lo_243)
node decoded_andMatrixOutputs_55_2_2 = andr(_decoded_andMatrixOutputs_T_246)
node decoded_andMatrixOutputs_andMatrixInput_0_247 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_247 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_247 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_244 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_244 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_244 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_244 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_244 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_243 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_239 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_239 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_239 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_239 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_239 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_239 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_159 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_106 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_159 = cat(decoded_andMatrixOutputs_andMatrixInput_15_159, decoded_andMatrixOutputs_andMatrixInput_16_106)
node decoded_andMatrixOutputs_lo_lo_hi_239 = cat(decoded_andMatrixOutputs_andMatrixInput_13_239, decoded_andMatrixOutputs_andMatrixInput_14_239)
node decoded_andMatrixOutputs_lo_lo_244 = cat(decoded_andMatrixOutputs_lo_lo_hi_239, decoded_andMatrixOutputs_lo_lo_lo_159)
node decoded_andMatrixOutputs_lo_hi_lo_239 = cat(decoded_andMatrixOutputs_andMatrixInput_11_239, decoded_andMatrixOutputs_andMatrixInput_12_239)
node decoded_andMatrixOutputs_lo_hi_hi_239 = cat(decoded_andMatrixOutputs_andMatrixInput_9_239, decoded_andMatrixOutputs_andMatrixInput_10_239)
node decoded_andMatrixOutputs_lo_hi_244 = cat(decoded_andMatrixOutputs_lo_hi_hi_239, decoded_andMatrixOutputs_lo_hi_lo_239)
node decoded_andMatrixOutputs_lo_244 = cat(decoded_andMatrixOutputs_lo_hi_244, decoded_andMatrixOutputs_lo_lo_244)
node decoded_andMatrixOutputs_hi_lo_lo_239 = cat(decoded_andMatrixOutputs_andMatrixInput_7_244, decoded_andMatrixOutputs_andMatrixInput_8_243)
node decoded_andMatrixOutputs_hi_lo_hi_239 = cat(decoded_andMatrixOutputs_andMatrixInput_5_244, decoded_andMatrixOutputs_andMatrixInput_6_244)
node decoded_andMatrixOutputs_hi_lo_244 = cat(decoded_andMatrixOutputs_hi_lo_hi_239, decoded_andMatrixOutputs_hi_lo_lo_239)
node decoded_andMatrixOutputs_hi_hi_lo_239 = cat(decoded_andMatrixOutputs_andMatrixInput_3_244, decoded_andMatrixOutputs_andMatrixInput_4_244)
node decoded_andMatrixOutputs_hi_hi_hi_hi_106 = cat(decoded_andMatrixOutputs_andMatrixInput_0_247, decoded_andMatrixOutputs_andMatrixInput_1_247)
node decoded_andMatrixOutputs_hi_hi_hi_243 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_106, decoded_andMatrixOutputs_andMatrixInput_2_247)
node decoded_andMatrixOutputs_hi_hi_244 = cat(decoded_andMatrixOutputs_hi_hi_hi_243, decoded_andMatrixOutputs_hi_hi_lo_239)
node decoded_andMatrixOutputs_hi_247 = cat(decoded_andMatrixOutputs_hi_hi_244, decoded_andMatrixOutputs_hi_lo_244)
node _decoded_andMatrixOutputs_T_247 = cat(decoded_andMatrixOutputs_hi_247, decoded_andMatrixOutputs_lo_244)
node decoded_andMatrixOutputs_64_2_1 = andr(_decoded_andMatrixOutputs_T_247)
node decoded_andMatrixOutputs_andMatrixInput_0_248 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_248 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_248 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_245 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_245 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_245 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_245 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_245 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_244 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_240 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_240 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_240 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_240 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_240 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_240 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_160 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_107 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_160 = cat(decoded_andMatrixOutputs_andMatrixInput_15_160, decoded_andMatrixOutputs_andMatrixInput_16_107)
node decoded_andMatrixOutputs_lo_lo_hi_240 = cat(decoded_andMatrixOutputs_andMatrixInput_13_240, decoded_andMatrixOutputs_andMatrixInput_14_240)
node decoded_andMatrixOutputs_lo_lo_245 = cat(decoded_andMatrixOutputs_lo_lo_hi_240, decoded_andMatrixOutputs_lo_lo_lo_160)
node decoded_andMatrixOutputs_lo_hi_lo_240 = cat(decoded_andMatrixOutputs_andMatrixInput_11_240, decoded_andMatrixOutputs_andMatrixInput_12_240)
node decoded_andMatrixOutputs_lo_hi_hi_240 = cat(decoded_andMatrixOutputs_andMatrixInput_9_240, decoded_andMatrixOutputs_andMatrixInput_10_240)
node decoded_andMatrixOutputs_lo_hi_245 = cat(decoded_andMatrixOutputs_lo_hi_hi_240, decoded_andMatrixOutputs_lo_hi_lo_240)
node decoded_andMatrixOutputs_lo_245 = cat(decoded_andMatrixOutputs_lo_hi_245, decoded_andMatrixOutputs_lo_lo_245)
node decoded_andMatrixOutputs_hi_lo_lo_240 = cat(decoded_andMatrixOutputs_andMatrixInput_7_245, decoded_andMatrixOutputs_andMatrixInput_8_244)
node decoded_andMatrixOutputs_hi_lo_hi_240 = cat(decoded_andMatrixOutputs_andMatrixInput_5_245, decoded_andMatrixOutputs_andMatrixInput_6_245)
node decoded_andMatrixOutputs_hi_lo_245 = cat(decoded_andMatrixOutputs_hi_lo_hi_240, decoded_andMatrixOutputs_hi_lo_lo_240)
node decoded_andMatrixOutputs_hi_hi_lo_240 = cat(decoded_andMatrixOutputs_andMatrixInput_3_245, decoded_andMatrixOutputs_andMatrixInput_4_245)
node decoded_andMatrixOutputs_hi_hi_hi_hi_107 = cat(decoded_andMatrixOutputs_andMatrixInput_0_248, decoded_andMatrixOutputs_andMatrixInput_1_248)
node decoded_andMatrixOutputs_hi_hi_hi_244 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_107, decoded_andMatrixOutputs_andMatrixInput_2_248)
node decoded_andMatrixOutputs_hi_hi_245 = cat(decoded_andMatrixOutputs_hi_hi_hi_244, decoded_andMatrixOutputs_hi_hi_lo_240)
node decoded_andMatrixOutputs_hi_248 = cat(decoded_andMatrixOutputs_hi_hi_245, decoded_andMatrixOutputs_hi_lo_245)
node _decoded_andMatrixOutputs_T_248 = cat(decoded_andMatrixOutputs_hi_248, decoded_andMatrixOutputs_lo_245)
node decoded_andMatrixOutputs_10_2_4 = andr(_decoded_andMatrixOutputs_T_248)
node decoded_andMatrixOutputs_andMatrixInput_0_249 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_249 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_249 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_3_246 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_4_246 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_5_246 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_6_246 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_7_246 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_8_245 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_246 = cat(decoded_andMatrixOutputs_andMatrixInput_7_246, decoded_andMatrixOutputs_andMatrixInput_8_245)
node decoded_andMatrixOutputs_lo_hi_246 = cat(decoded_andMatrixOutputs_andMatrixInput_5_246, decoded_andMatrixOutputs_andMatrixInput_6_246)
node decoded_andMatrixOutputs_lo_246 = cat(decoded_andMatrixOutputs_lo_hi_246, decoded_andMatrixOutputs_lo_lo_246)
node decoded_andMatrixOutputs_hi_lo_246 = cat(decoded_andMatrixOutputs_andMatrixInput_3_246, decoded_andMatrixOutputs_andMatrixInput_4_246)
node decoded_andMatrixOutputs_hi_hi_hi_245 = cat(decoded_andMatrixOutputs_andMatrixInput_0_249, decoded_andMatrixOutputs_andMatrixInput_1_249)
node decoded_andMatrixOutputs_hi_hi_246 = cat(decoded_andMatrixOutputs_hi_hi_hi_245, decoded_andMatrixOutputs_andMatrixInput_2_249)
node decoded_andMatrixOutputs_hi_249 = cat(decoded_andMatrixOutputs_hi_hi_246, decoded_andMatrixOutputs_hi_lo_246)
node _decoded_andMatrixOutputs_T_249 = cat(decoded_andMatrixOutputs_hi_249, decoded_andMatrixOutputs_lo_246)
node decoded_andMatrixOutputs_39_2_4 = andr(_decoded_andMatrixOutputs_T_249)
node decoded_andMatrixOutputs_andMatrixInput_0_250 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_250 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_250 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_247 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_247 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_247 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_247 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_247 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_246 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_241 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_241 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_241 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_241 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_241 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_241 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_161 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_108 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_161 = cat(decoded_andMatrixOutputs_andMatrixInput_15_161, decoded_andMatrixOutputs_andMatrixInput_16_108)
node decoded_andMatrixOutputs_lo_lo_hi_241 = cat(decoded_andMatrixOutputs_andMatrixInput_13_241, decoded_andMatrixOutputs_andMatrixInput_14_241)
node decoded_andMatrixOutputs_lo_lo_247 = cat(decoded_andMatrixOutputs_lo_lo_hi_241, decoded_andMatrixOutputs_lo_lo_lo_161)
node decoded_andMatrixOutputs_lo_hi_lo_241 = cat(decoded_andMatrixOutputs_andMatrixInput_11_241, decoded_andMatrixOutputs_andMatrixInput_12_241)
node decoded_andMatrixOutputs_lo_hi_hi_241 = cat(decoded_andMatrixOutputs_andMatrixInput_9_241, decoded_andMatrixOutputs_andMatrixInput_10_241)
node decoded_andMatrixOutputs_lo_hi_247 = cat(decoded_andMatrixOutputs_lo_hi_hi_241, decoded_andMatrixOutputs_lo_hi_lo_241)
node decoded_andMatrixOutputs_lo_247 = cat(decoded_andMatrixOutputs_lo_hi_247, decoded_andMatrixOutputs_lo_lo_247)
node decoded_andMatrixOutputs_hi_lo_lo_241 = cat(decoded_andMatrixOutputs_andMatrixInput_7_247, decoded_andMatrixOutputs_andMatrixInput_8_246)
node decoded_andMatrixOutputs_hi_lo_hi_241 = cat(decoded_andMatrixOutputs_andMatrixInput_5_247, decoded_andMatrixOutputs_andMatrixInput_6_247)
node decoded_andMatrixOutputs_hi_lo_247 = cat(decoded_andMatrixOutputs_hi_lo_hi_241, decoded_andMatrixOutputs_hi_lo_lo_241)
node decoded_andMatrixOutputs_hi_hi_lo_241 = cat(decoded_andMatrixOutputs_andMatrixInput_3_247, decoded_andMatrixOutputs_andMatrixInput_4_247)
node decoded_andMatrixOutputs_hi_hi_hi_hi_108 = cat(decoded_andMatrixOutputs_andMatrixInput_0_250, decoded_andMatrixOutputs_andMatrixInput_1_250)
node decoded_andMatrixOutputs_hi_hi_hi_246 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_108, decoded_andMatrixOutputs_andMatrixInput_2_250)
node decoded_andMatrixOutputs_hi_hi_247 = cat(decoded_andMatrixOutputs_hi_hi_hi_246, decoded_andMatrixOutputs_hi_hi_lo_241)
node decoded_andMatrixOutputs_hi_250 = cat(decoded_andMatrixOutputs_hi_hi_247, decoded_andMatrixOutputs_hi_lo_247)
node _decoded_andMatrixOutputs_T_250 = cat(decoded_andMatrixOutputs_hi_250, decoded_andMatrixOutputs_lo_247)
node decoded_andMatrixOutputs_54_2_3 = andr(_decoded_andMatrixOutputs_T_250)
node decoded_andMatrixOutputs_andMatrixInput_0_251 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_251 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_251 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_248 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_248 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_248 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_248 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_248 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_247 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_242 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_242 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_242 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_242 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_242 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_242 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_162 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_109 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_162 = cat(decoded_andMatrixOutputs_andMatrixInput_15_162, decoded_andMatrixOutputs_andMatrixInput_16_109)
node decoded_andMatrixOutputs_lo_lo_hi_242 = cat(decoded_andMatrixOutputs_andMatrixInput_13_242, decoded_andMatrixOutputs_andMatrixInput_14_242)
node decoded_andMatrixOutputs_lo_lo_248 = cat(decoded_andMatrixOutputs_lo_lo_hi_242, decoded_andMatrixOutputs_lo_lo_lo_162)
node decoded_andMatrixOutputs_lo_hi_lo_242 = cat(decoded_andMatrixOutputs_andMatrixInput_11_242, decoded_andMatrixOutputs_andMatrixInput_12_242)
node decoded_andMatrixOutputs_lo_hi_hi_242 = cat(decoded_andMatrixOutputs_andMatrixInput_9_242, decoded_andMatrixOutputs_andMatrixInput_10_242)
node decoded_andMatrixOutputs_lo_hi_248 = cat(decoded_andMatrixOutputs_lo_hi_hi_242, decoded_andMatrixOutputs_lo_hi_lo_242)
node decoded_andMatrixOutputs_lo_248 = cat(decoded_andMatrixOutputs_lo_hi_248, decoded_andMatrixOutputs_lo_lo_248)
node decoded_andMatrixOutputs_hi_lo_lo_242 = cat(decoded_andMatrixOutputs_andMatrixInput_7_248, decoded_andMatrixOutputs_andMatrixInput_8_247)
node decoded_andMatrixOutputs_hi_lo_hi_242 = cat(decoded_andMatrixOutputs_andMatrixInput_5_248, decoded_andMatrixOutputs_andMatrixInput_6_248)
node decoded_andMatrixOutputs_hi_lo_248 = cat(decoded_andMatrixOutputs_hi_lo_hi_242, decoded_andMatrixOutputs_hi_lo_lo_242)
node decoded_andMatrixOutputs_hi_hi_lo_242 = cat(decoded_andMatrixOutputs_andMatrixInput_3_248, decoded_andMatrixOutputs_andMatrixInput_4_248)
node decoded_andMatrixOutputs_hi_hi_hi_hi_109 = cat(decoded_andMatrixOutputs_andMatrixInput_0_251, decoded_andMatrixOutputs_andMatrixInput_1_251)
node decoded_andMatrixOutputs_hi_hi_hi_247 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_109, decoded_andMatrixOutputs_andMatrixInput_2_251)
node decoded_andMatrixOutputs_hi_hi_248 = cat(decoded_andMatrixOutputs_hi_hi_hi_247, decoded_andMatrixOutputs_hi_hi_lo_242)
node decoded_andMatrixOutputs_hi_251 = cat(decoded_andMatrixOutputs_hi_hi_248, decoded_andMatrixOutputs_hi_lo_248)
node _decoded_andMatrixOutputs_T_251 = cat(decoded_andMatrixOutputs_hi_251, decoded_andMatrixOutputs_lo_248)
node decoded_andMatrixOutputs_63_2_1 = andr(_decoded_andMatrixOutputs_T_251)
node decoded_andMatrixOutputs_andMatrixInput_0_252 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_252 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_252 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_249 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_249 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_249 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_249 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_249 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_248 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_243 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_243 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_243 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_243 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_243 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_243 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_163 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_110 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_163 = cat(decoded_andMatrixOutputs_andMatrixInput_15_163, decoded_andMatrixOutputs_andMatrixInput_16_110)
node decoded_andMatrixOutputs_lo_lo_hi_243 = cat(decoded_andMatrixOutputs_andMatrixInput_13_243, decoded_andMatrixOutputs_andMatrixInput_14_243)
node decoded_andMatrixOutputs_lo_lo_249 = cat(decoded_andMatrixOutputs_lo_lo_hi_243, decoded_andMatrixOutputs_lo_lo_lo_163)
node decoded_andMatrixOutputs_lo_hi_lo_243 = cat(decoded_andMatrixOutputs_andMatrixInput_11_243, decoded_andMatrixOutputs_andMatrixInput_12_243)
node decoded_andMatrixOutputs_lo_hi_hi_243 = cat(decoded_andMatrixOutputs_andMatrixInput_9_243, decoded_andMatrixOutputs_andMatrixInput_10_243)
node decoded_andMatrixOutputs_lo_hi_249 = cat(decoded_andMatrixOutputs_lo_hi_hi_243, decoded_andMatrixOutputs_lo_hi_lo_243)
node decoded_andMatrixOutputs_lo_249 = cat(decoded_andMatrixOutputs_lo_hi_249, decoded_andMatrixOutputs_lo_lo_249)
node decoded_andMatrixOutputs_hi_lo_lo_243 = cat(decoded_andMatrixOutputs_andMatrixInput_7_249, decoded_andMatrixOutputs_andMatrixInput_8_248)
node decoded_andMatrixOutputs_hi_lo_hi_243 = cat(decoded_andMatrixOutputs_andMatrixInput_5_249, decoded_andMatrixOutputs_andMatrixInput_6_249)
node decoded_andMatrixOutputs_hi_lo_249 = cat(decoded_andMatrixOutputs_hi_lo_hi_243, decoded_andMatrixOutputs_hi_lo_lo_243)
node decoded_andMatrixOutputs_hi_hi_lo_243 = cat(decoded_andMatrixOutputs_andMatrixInput_3_249, decoded_andMatrixOutputs_andMatrixInput_4_249)
node decoded_andMatrixOutputs_hi_hi_hi_hi_110 = cat(decoded_andMatrixOutputs_andMatrixInput_0_252, decoded_andMatrixOutputs_andMatrixInput_1_252)
node decoded_andMatrixOutputs_hi_hi_hi_248 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_110, decoded_andMatrixOutputs_andMatrixInput_2_252)
node decoded_andMatrixOutputs_hi_hi_249 = cat(decoded_andMatrixOutputs_hi_hi_hi_248, decoded_andMatrixOutputs_hi_hi_lo_243)
node decoded_andMatrixOutputs_hi_252 = cat(decoded_andMatrixOutputs_hi_hi_249, decoded_andMatrixOutputs_hi_lo_249)
node _decoded_andMatrixOutputs_T_252 = cat(decoded_andMatrixOutputs_hi_252, decoded_andMatrixOutputs_lo_249)
node decoded_andMatrixOutputs_35_2_4 = andr(_decoded_andMatrixOutputs_T_252)
node decoded_andMatrixOutputs_andMatrixInput_0_253 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_253 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_253 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_250 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_250 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_250 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_250 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_250 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_249 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_244 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_244 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_244 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_244 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_244 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_244 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_164 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_111 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_164 = cat(decoded_andMatrixOutputs_andMatrixInput_15_164, decoded_andMatrixOutputs_andMatrixInput_16_111)
node decoded_andMatrixOutputs_lo_lo_hi_244 = cat(decoded_andMatrixOutputs_andMatrixInput_13_244, decoded_andMatrixOutputs_andMatrixInput_14_244)
node decoded_andMatrixOutputs_lo_lo_250 = cat(decoded_andMatrixOutputs_lo_lo_hi_244, decoded_andMatrixOutputs_lo_lo_lo_164)
node decoded_andMatrixOutputs_lo_hi_lo_244 = cat(decoded_andMatrixOutputs_andMatrixInput_11_244, decoded_andMatrixOutputs_andMatrixInput_12_244)
node decoded_andMatrixOutputs_lo_hi_hi_244 = cat(decoded_andMatrixOutputs_andMatrixInput_9_244, decoded_andMatrixOutputs_andMatrixInput_10_244)
node decoded_andMatrixOutputs_lo_hi_250 = cat(decoded_andMatrixOutputs_lo_hi_hi_244, decoded_andMatrixOutputs_lo_hi_lo_244)
node decoded_andMatrixOutputs_lo_250 = cat(decoded_andMatrixOutputs_lo_hi_250, decoded_andMatrixOutputs_lo_lo_250)
node decoded_andMatrixOutputs_hi_lo_lo_244 = cat(decoded_andMatrixOutputs_andMatrixInput_7_250, decoded_andMatrixOutputs_andMatrixInput_8_249)
node decoded_andMatrixOutputs_hi_lo_hi_244 = cat(decoded_andMatrixOutputs_andMatrixInput_5_250, decoded_andMatrixOutputs_andMatrixInput_6_250)
node decoded_andMatrixOutputs_hi_lo_250 = cat(decoded_andMatrixOutputs_hi_lo_hi_244, decoded_andMatrixOutputs_hi_lo_lo_244)
node decoded_andMatrixOutputs_hi_hi_lo_244 = cat(decoded_andMatrixOutputs_andMatrixInput_3_250, decoded_andMatrixOutputs_andMatrixInput_4_250)
node decoded_andMatrixOutputs_hi_hi_hi_hi_111 = cat(decoded_andMatrixOutputs_andMatrixInput_0_253, decoded_andMatrixOutputs_andMatrixInput_1_253)
node decoded_andMatrixOutputs_hi_hi_hi_249 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_111, decoded_andMatrixOutputs_andMatrixInput_2_253)
node decoded_andMatrixOutputs_hi_hi_250 = cat(decoded_andMatrixOutputs_hi_hi_hi_249, decoded_andMatrixOutputs_hi_hi_lo_244)
node decoded_andMatrixOutputs_hi_253 = cat(decoded_andMatrixOutputs_hi_hi_250, decoded_andMatrixOutputs_hi_lo_250)
node _decoded_andMatrixOutputs_T_253 = cat(decoded_andMatrixOutputs_hi_253, decoded_andMatrixOutputs_lo_250)
node decoded_andMatrixOutputs_12_2_4 = andr(_decoded_andMatrixOutputs_T_253)
node decoded_andMatrixOutputs_andMatrixInput_0_254 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_254 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_254 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_251 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_251 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_251 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_251 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_251 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_250 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_245 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_245 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_245 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_245 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_245 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_245 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_165 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_112 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_165 = cat(decoded_andMatrixOutputs_andMatrixInput_15_165, decoded_andMatrixOutputs_andMatrixInput_16_112)
node decoded_andMatrixOutputs_lo_lo_hi_245 = cat(decoded_andMatrixOutputs_andMatrixInput_13_245, decoded_andMatrixOutputs_andMatrixInput_14_245)
node decoded_andMatrixOutputs_lo_lo_251 = cat(decoded_andMatrixOutputs_lo_lo_hi_245, decoded_andMatrixOutputs_lo_lo_lo_165)
node decoded_andMatrixOutputs_lo_hi_lo_245 = cat(decoded_andMatrixOutputs_andMatrixInput_11_245, decoded_andMatrixOutputs_andMatrixInput_12_245)
node decoded_andMatrixOutputs_lo_hi_hi_245 = cat(decoded_andMatrixOutputs_andMatrixInput_9_245, decoded_andMatrixOutputs_andMatrixInput_10_245)
node decoded_andMatrixOutputs_lo_hi_251 = cat(decoded_andMatrixOutputs_lo_hi_hi_245, decoded_andMatrixOutputs_lo_hi_lo_245)
node decoded_andMatrixOutputs_lo_251 = cat(decoded_andMatrixOutputs_lo_hi_251, decoded_andMatrixOutputs_lo_lo_251)
node decoded_andMatrixOutputs_hi_lo_lo_245 = cat(decoded_andMatrixOutputs_andMatrixInput_7_251, decoded_andMatrixOutputs_andMatrixInput_8_250)
node decoded_andMatrixOutputs_hi_lo_hi_245 = cat(decoded_andMatrixOutputs_andMatrixInput_5_251, decoded_andMatrixOutputs_andMatrixInput_6_251)
node decoded_andMatrixOutputs_hi_lo_251 = cat(decoded_andMatrixOutputs_hi_lo_hi_245, decoded_andMatrixOutputs_hi_lo_lo_245)
node decoded_andMatrixOutputs_hi_hi_lo_245 = cat(decoded_andMatrixOutputs_andMatrixInput_3_251, decoded_andMatrixOutputs_andMatrixInput_4_251)
node decoded_andMatrixOutputs_hi_hi_hi_hi_112 = cat(decoded_andMatrixOutputs_andMatrixInput_0_254, decoded_andMatrixOutputs_andMatrixInput_1_254)
node decoded_andMatrixOutputs_hi_hi_hi_250 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_112, decoded_andMatrixOutputs_andMatrixInput_2_254)
node decoded_andMatrixOutputs_hi_hi_251 = cat(decoded_andMatrixOutputs_hi_hi_hi_250, decoded_andMatrixOutputs_hi_hi_lo_245)
node decoded_andMatrixOutputs_hi_254 = cat(decoded_andMatrixOutputs_hi_hi_251, decoded_andMatrixOutputs_hi_lo_251)
node _decoded_andMatrixOutputs_T_254 = cat(decoded_andMatrixOutputs_hi_254, decoded_andMatrixOutputs_lo_251)
node decoded_andMatrixOutputs_18_2_4 = andr(_decoded_andMatrixOutputs_T_254)
node decoded_andMatrixOutputs_andMatrixInput_0_255 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_255 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_255 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_252 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_252 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_252 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_252 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_252 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_251 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_246 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_246 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_246 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_246 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_246 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_246 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_166 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_113 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_166 = cat(decoded_andMatrixOutputs_andMatrixInput_15_166, decoded_andMatrixOutputs_andMatrixInput_16_113)
node decoded_andMatrixOutputs_lo_lo_hi_246 = cat(decoded_andMatrixOutputs_andMatrixInput_13_246, decoded_andMatrixOutputs_andMatrixInput_14_246)
node decoded_andMatrixOutputs_lo_lo_252 = cat(decoded_andMatrixOutputs_lo_lo_hi_246, decoded_andMatrixOutputs_lo_lo_lo_166)
node decoded_andMatrixOutputs_lo_hi_lo_246 = cat(decoded_andMatrixOutputs_andMatrixInput_11_246, decoded_andMatrixOutputs_andMatrixInput_12_246)
node decoded_andMatrixOutputs_lo_hi_hi_246 = cat(decoded_andMatrixOutputs_andMatrixInput_9_246, decoded_andMatrixOutputs_andMatrixInput_10_246)
node decoded_andMatrixOutputs_lo_hi_252 = cat(decoded_andMatrixOutputs_lo_hi_hi_246, decoded_andMatrixOutputs_lo_hi_lo_246)
node decoded_andMatrixOutputs_lo_252 = cat(decoded_andMatrixOutputs_lo_hi_252, decoded_andMatrixOutputs_lo_lo_252)
node decoded_andMatrixOutputs_hi_lo_lo_246 = cat(decoded_andMatrixOutputs_andMatrixInput_7_252, decoded_andMatrixOutputs_andMatrixInput_8_251)
node decoded_andMatrixOutputs_hi_lo_hi_246 = cat(decoded_andMatrixOutputs_andMatrixInput_5_252, decoded_andMatrixOutputs_andMatrixInput_6_252)
node decoded_andMatrixOutputs_hi_lo_252 = cat(decoded_andMatrixOutputs_hi_lo_hi_246, decoded_andMatrixOutputs_hi_lo_lo_246)
node decoded_andMatrixOutputs_hi_hi_lo_246 = cat(decoded_andMatrixOutputs_andMatrixInput_3_252, decoded_andMatrixOutputs_andMatrixInput_4_252)
node decoded_andMatrixOutputs_hi_hi_hi_hi_113 = cat(decoded_andMatrixOutputs_andMatrixInput_0_255, decoded_andMatrixOutputs_andMatrixInput_1_255)
node decoded_andMatrixOutputs_hi_hi_hi_251 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_113, decoded_andMatrixOutputs_andMatrixInput_2_255)
node decoded_andMatrixOutputs_hi_hi_252 = cat(decoded_andMatrixOutputs_hi_hi_hi_251, decoded_andMatrixOutputs_hi_hi_lo_246)
node decoded_andMatrixOutputs_hi_255 = cat(decoded_andMatrixOutputs_hi_hi_252, decoded_andMatrixOutputs_hi_lo_252)
node _decoded_andMatrixOutputs_T_255 = cat(decoded_andMatrixOutputs_hi_255, decoded_andMatrixOutputs_lo_252)
node decoded_andMatrixOutputs_26_2_4 = andr(_decoded_andMatrixOutputs_T_255)
node decoded_andMatrixOutputs_andMatrixInput_0_256 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_256 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_256 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_253 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_253 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_253 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_253 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_253 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_252 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_247 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_247 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_247 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_247 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_247 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_247 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_167 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_167 = cat(decoded_andMatrixOutputs_andMatrixInput_14_247, decoded_andMatrixOutputs_andMatrixInput_15_167)
node decoded_andMatrixOutputs_lo_lo_hi_247 = cat(decoded_andMatrixOutputs_andMatrixInput_12_247, decoded_andMatrixOutputs_andMatrixInput_13_247)
node decoded_andMatrixOutputs_lo_lo_253 = cat(decoded_andMatrixOutputs_lo_lo_hi_247, decoded_andMatrixOutputs_lo_lo_lo_167)
node decoded_andMatrixOutputs_lo_hi_lo_247 = cat(decoded_andMatrixOutputs_andMatrixInput_10_247, decoded_andMatrixOutputs_andMatrixInput_11_247)
node decoded_andMatrixOutputs_lo_hi_hi_247 = cat(decoded_andMatrixOutputs_andMatrixInput_8_252, decoded_andMatrixOutputs_andMatrixInput_9_247)
node decoded_andMatrixOutputs_lo_hi_253 = cat(decoded_andMatrixOutputs_lo_hi_hi_247, decoded_andMatrixOutputs_lo_hi_lo_247)
node decoded_andMatrixOutputs_lo_253 = cat(decoded_andMatrixOutputs_lo_hi_253, decoded_andMatrixOutputs_lo_lo_253)
node decoded_andMatrixOutputs_hi_lo_lo_247 = cat(decoded_andMatrixOutputs_andMatrixInput_6_253, decoded_andMatrixOutputs_andMatrixInput_7_253)
node decoded_andMatrixOutputs_hi_lo_hi_247 = cat(decoded_andMatrixOutputs_andMatrixInput_4_253, decoded_andMatrixOutputs_andMatrixInput_5_253)
node decoded_andMatrixOutputs_hi_lo_253 = cat(decoded_andMatrixOutputs_hi_lo_hi_247, decoded_andMatrixOutputs_hi_lo_lo_247)
node decoded_andMatrixOutputs_hi_hi_lo_247 = cat(decoded_andMatrixOutputs_andMatrixInput_2_256, decoded_andMatrixOutputs_andMatrixInput_3_253)
node decoded_andMatrixOutputs_hi_hi_hi_252 = cat(decoded_andMatrixOutputs_andMatrixInput_0_256, decoded_andMatrixOutputs_andMatrixInput_1_256)
node decoded_andMatrixOutputs_hi_hi_253 = cat(decoded_andMatrixOutputs_hi_hi_hi_252, decoded_andMatrixOutputs_hi_hi_lo_247)
node decoded_andMatrixOutputs_hi_256 = cat(decoded_andMatrixOutputs_hi_hi_253, decoded_andMatrixOutputs_hi_lo_253)
node _decoded_andMatrixOutputs_T_256 = cat(decoded_andMatrixOutputs_hi_256, decoded_andMatrixOutputs_lo_253)
node decoded_andMatrixOutputs_2_2_4 = andr(_decoded_andMatrixOutputs_T_256)
node decoded_andMatrixOutputs_andMatrixInput_0_257 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_257 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_257 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_254 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_254 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_254 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_254 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_254 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_253 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_248 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_248 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_248 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_248 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_248 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_248 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_168 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_168 = cat(decoded_andMatrixOutputs_andMatrixInput_14_248, decoded_andMatrixOutputs_andMatrixInput_15_168)
node decoded_andMatrixOutputs_lo_lo_hi_248 = cat(decoded_andMatrixOutputs_andMatrixInput_12_248, decoded_andMatrixOutputs_andMatrixInput_13_248)
node decoded_andMatrixOutputs_lo_lo_254 = cat(decoded_andMatrixOutputs_lo_lo_hi_248, decoded_andMatrixOutputs_lo_lo_lo_168)
node decoded_andMatrixOutputs_lo_hi_lo_248 = cat(decoded_andMatrixOutputs_andMatrixInput_10_248, decoded_andMatrixOutputs_andMatrixInput_11_248)
node decoded_andMatrixOutputs_lo_hi_hi_248 = cat(decoded_andMatrixOutputs_andMatrixInput_8_253, decoded_andMatrixOutputs_andMatrixInput_9_248)
node decoded_andMatrixOutputs_lo_hi_254 = cat(decoded_andMatrixOutputs_lo_hi_hi_248, decoded_andMatrixOutputs_lo_hi_lo_248)
node decoded_andMatrixOutputs_lo_254 = cat(decoded_andMatrixOutputs_lo_hi_254, decoded_andMatrixOutputs_lo_lo_254)
node decoded_andMatrixOutputs_hi_lo_lo_248 = cat(decoded_andMatrixOutputs_andMatrixInput_6_254, decoded_andMatrixOutputs_andMatrixInput_7_254)
node decoded_andMatrixOutputs_hi_lo_hi_248 = cat(decoded_andMatrixOutputs_andMatrixInput_4_254, decoded_andMatrixOutputs_andMatrixInput_5_254)
node decoded_andMatrixOutputs_hi_lo_254 = cat(decoded_andMatrixOutputs_hi_lo_hi_248, decoded_andMatrixOutputs_hi_lo_lo_248)
node decoded_andMatrixOutputs_hi_hi_lo_248 = cat(decoded_andMatrixOutputs_andMatrixInput_2_257, decoded_andMatrixOutputs_andMatrixInput_3_254)
node decoded_andMatrixOutputs_hi_hi_hi_253 = cat(decoded_andMatrixOutputs_andMatrixInput_0_257, decoded_andMatrixOutputs_andMatrixInput_1_257)
node decoded_andMatrixOutputs_hi_hi_254 = cat(decoded_andMatrixOutputs_hi_hi_hi_253, decoded_andMatrixOutputs_hi_hi_lo_248)
node decoded_andMatrixOutputs_hi_257 = cat(decoded_andMatrixOutputs_hi_hi_254, decoded_andMatrixOutputs_hi_lo_254)
node _decoded_andMatrixOutputs_T_257 = cat(decoded_andMatrixOutputs_hi_257, decoded_andMatrixOutputs_lo_254)
node decoded_andMatrixOutputs_31_2_4 = andr(_decoded_andMatrixOutputs_T_257)
node decoded_andMatrixOutputs_andMatrixInput_0_258 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_258 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_258 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_255 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_255 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_255 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_255 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_255 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_254 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_249 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_249 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_249 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_249 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_249 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_249 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_169 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_169 = cat(decoded_andMatrixOutputs_andMatrixInput_14_249, decoded_andMatrixOutputs_andMatrixInput_15_169)
node decoded_andMatrixOutputs_lo_lo_hi_249 = cat(decoded_andMatrixOutputs_andMatrixInput_12_249, decoded_andMatrixOutputs_andMatrixInput_13_249)
node decoded_andMatrixOutputs_lo_lo_255 = cat(decoded_andMatrixOutputs_lo_lo_hi_249, decoded_andMatrixOutputs_lo_lo_lo_169)
node decoded_andMatrixOutputs_lo_hi_lo_249 = cat(decoded_andMatrixOutputs_andMatrixInput_10_249, decoded_andMatrixOutputs_andMatrixInput_11_249)
node decoded_andMatrixOutputs_lo_hi_hi_249 = cat(decoded_andMatrixOutputs_andMatrixInput_8_254, decoded_andMatrixOutputs_andMatrixInput_9_249)
node decoded_andMatrixOutputs_lo_hi_255 = cat(decoded_andMatrixOutputs_lo_hi_hi_249, decoded_andMatrixOutputs_lo_hi_lo_249)
node decoded_andMatrixOutputs_lo_255 = cat(decoded_andMatrixOutputs_lo_hi_255, decoded_andMatrixOutputs_lo_lo_255)
node decoded_andMatrixOutputs_hi_lo_lo_249 = cat(decoded_andMatrixOutputs_andMatrixInput_6_255, decoded_andMatrixOutputs_andMatrixInput_7_255)
node decoded_andMatrixOutputs_hi_lo_hi_249 = cat(decoded_andMatrixOutputs_andMatrixInput_4_255, decoded_andMatrixOutputs_andMatrixInput_5_255)
node decoded_andMatrixOutputs_hi_lo_255 = cat(decoded_andMatrixOutputs_hi_lo_hi_249, decoded_andMatrixOutputs_hi_lo_lo_249)
node decoded_andMatrixOutputs_hi_hi_lo_249 = cat(decoded_andMatrixOutputs_andMatrixInput_2_258, decoded_andMatrixOutputs_andMatrixInput_3_255)
node decoded_andMatrixOutputs_hi_hi_hi_254 = cat(decoded_andMatrixOutputs_andMatrixInput_0_258, decoded_andMatrixOutputs_andMatrixInput_1_258)
node decoded_andMatrixOutputs_hi_hi_255 = cat(decoded_andMatrixOutputs_hi_hi_hi_254, decoded_andMatrixOutputs_hi_hi_lo_249)
node decoded_andMatrixOutputs_hi_258 = cat(decoded_andMatrixOutputs_hi_hi_255, decoded_andMatrixOutputs_hi_lo_255)
node _decoded_andMatrixOutputs_T_258 = cat(decoded_andMatrixOutputs_hi_258, decoded_andMatrixOutputs_lo_255)
node decoded_andMatrixOutputs_59_2_1 = andr(_decoded_andMatrixOutputs_T_258)
node decoded_andMatrixOutputs_andMatrixInput_0_259 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_259 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_259 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_256 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_256 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_256 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_256 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_256 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_255 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_250 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_250 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_250 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_250 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_250 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_250 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_170 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_114 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_170 = cat(decoded_andMatrixOutputs_andMatrixInput_15_170, decoded_andMatrixOutputs_andMatrixInput_16_114)
node decoded_andMatrixOutputs_lo_lo_hi_250 = cat(decoded_andMatrixOutputs_andMatrixInput_13_250, decoded_andMatrixOutputs_andMatrixInput_14_250)
node decoded_andMatrixOutputs_lo_lo_256 = cat(decoded_andMatrixOutputs_lo_lo_hi_250, decoded_andMatrixOutputs_lo_lo_lo_170)
node decoded_andMatrixOutputs_lo_hi_lo_250 = cat(decoded_andMatrixOutputs_andMatrixInput_11_250, decoded_andMatrixOutputs_andMatrixInput_12_250)
node decoded_andMatrixOutputs_lo_hi_hi_250 = cat(decoded_andMatrixOutputs_andMatrixInput_9_250, decoded_andMatrixOutputs_andMatrixInput_10_250)
node decoded_andMatrixOutputs_lo_hi_256 = cat(decoded_andMatrixOutputs_lo_hi_hi_250, decoded_andMatrixOutputs_lo_hi_lo_250)
node decoded_andMatrixOutputs_lo_256 = cat(decoded_andMatrixOutputs_lo_hi_256, decoded_andMatrixOutputs_lo_lo_256)
node decoded_andMatrixOutputs_hi_lo_lo_250 = cat(decoded_andMatrixOutputs_andMatrixInput_7_256, decoded_andMatrixOutputs_andMatrixInput_8_255)
node decoded_andMatrixOutputs_hi_lo_hi_250 = cat(decoded_andMatrixOutputs_andMatrixInput_5_256, decoded_andMatrixOutputs_andMatrixInput_6_256)
node decoded_andMatrixOutputs_hi_lo_256 = cat(decoded_andMatrixOutputs_hi_lo_hi_250, decoded_andMatrixOutputs_hi_lo_lo_250)
node decoded_andMatrixOutputs_hi_hi_lo_250 = cat(decoded_andMatrixOutputs_andMatrixInput_3_256, decoded_andMatrixOutputs_andMatrixInput_4_256)
node decoded_andMatrixOutputs_hi_hi_hi_hi_114 = cat(decoded_andMatrixOutputs_andMatrixInput_0_259, decoded_andMatrixOutputs_andMatrixInput_1_259)
node decoded_andMatrixOutputs_hi_hi_hi_255 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_114, decoded_andMatrixOutputs_andMatrixInput_2_259)
node decoded_andMatrixOutputs_hi_hi_256 = cat(decoded_andMatrixOutputs_hi_hi_hi_255, decoded_andMatrixOutputs_hi_hi_lo_250)
node decoded_andMatrixOutputs_hi_259 = cat(decoded_andMatrixOutputs_hi_hi_256, decoded_andMatrixOutputs_hi_lo_256)
node _decoded_andMatrixOutputs_T_259 = cat(decoded_andMatrixOutputs_hi_259, decoded_andMatrixOutputs_lo_256)
node decoded_andMatrixOutputs_28_2_4 = andr(_decoded_andMatrixOutputs_T_259)
node decoded_andMatrixOutputs_andMatrixInput_0_260 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_260 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_260 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_257 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_257 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_257 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_257 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_257 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_256 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_251 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_251 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_251 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_251 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_251 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_251 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_171 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_115 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_lo_lo_lo_171 = cat(decoded_andMatrixOutputs_andMatrixInput_15_171, decoded_andMatrixOutputs_andMatrixInput_16_115)
node decoded_andMatrixOutputs_lo_lo_hi_251 = cat(decoded_andMatrixOutputs_andMatrixInput_13_251, decoded_andMatrixOutputs_andMatrixInput_14_251)
node decoded_andMatrixOutputs_lo_lo_257 = cat(decoded_andMatrixOutputs_lo_lo_hi_251, decoded_andMatrixOutputs_lo_lo_lo_171)
node decoded_andMatrixOutputs_lo_hi_lo_251 = cat(decoded_andMatrixOutputs_andMatrixInput_11_251, decoded_andMatrixOutputs_andMatrixInput_12_251)
node decoded_andMatrixOutputs_lo_hi_hi_251 = cat(decoded_andMatrixOutputs_andMatrixInput_9_251, decoded_andMatrixOutputs_andMatrixInput_10_251)
node decoded_andMatrixOutputs_lo_hi_257 = cat(decoded_andMatrixOutputs_lo_hi_hi_251, decoded_andMatrixOutputs_lo_hi_lo_251)
node decoded_andMatrixOutputs_lo_257 = cat(decoded_andMatrixOutputs_lo_hi_257, decoded_andMatrixOutputs_lo_lo_257)
node decoded_andMatrixOutputs_hi_lo_lo_251 = cat(decoded_andMatrixOutputs_andMatrixInput_7_257, decoded_andMatrixOutputs_andMatrixInput_8_256)
node decoded_andMatrixOutputs_hi_lo_hi_251 = cat(decoded_andMatrixOutputs_andMatrixInput_5_257, decoded_andMatrixOutputs_andMatrixInput_6_257)
node decoded_andMatrixOutputs_hi_lo_257 = cat(decoded_andMatrixOutputs_hi_lo_hi_251, decoded_andMatrixOutputs_hi_lo_lo_251)
node decoded_andMatrixOutputs_hi_hi_lo_251 = cat(decoded_andMatrixOutputs_andMatrixInput_3_257, decoded_andMatrixOutputs_andMatrixInput_4_257)
node decoded_andMatrixOutputs_hi_hi_hi_hi_115 = cat(decoded_andMatrixOutputs_andMatrixInput_0_260, decoded_andMatrixOutputs_andMatrixInput_1_260)
node decoded_andMatrixOutputs_hi_hi_hi_256 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_115, decoded_andMatrixOutputs_andMatrixInput_2_260)
node decoded_andMatrixOutputs_hi_hi_257 = cat(decoded_andMatrixOutputs_hi_hi_hi_256, decoded_andMatrixOutputs_hi_hi_lo_251)
node decoded_andMatrixOutputs_hi_260 = cat(decoded_andMatrixOutputs_hi_hi_257, decoded_andMatrixOutputs_hi_lo_257)
node _decoded_andMatrixOutputs_T_260 = cat(decoded_andMatrixOutputs_hi_260, decoded_andMatrixOutputs_lo_257)
node decoded_andMatrixOutputs_17_2_4 = andr(_decoded_andMatrixOutputs_T_260)
node decoded_andMatrixOutputs_andMatrixInput_0_261 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_261 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_261 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_258 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_258 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_258 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_258 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_258 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_257 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_252 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_252 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_252 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_252 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_252 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_252 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_172 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_116 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_172 = cat(decoded_andMatrixOutputs_andMatrixInput_15_172, decoded_andMatrixOutputs_andMatrixInput_16_116)
node decoded_andMatrixOutputs_lo_lo_hi_252 = cat(decoded_andMatrixOutputs_andMatrixInput_13_252, decoded_andMatrixOutputs_andMatrixInput_14_252)
node decoded_andMatrixOutputs_lo_lo_258 = cat(decoded_andMatrixOutputs_lo_lo_hi_252, decoded_andMatrixOutputs_lo_lo_lo_172)
node decoded_andMatrixOutputs_lo_hi_lo_252 = cat(decoded_andMatrixOutputs_andMatrixInput_11_252, decoded_andMatrixOutputs_andMatrixInput_12_252)
node decoded_andMatrixOutputs_lo_hi_hi_252 = cat(decoded_andMatrixOutputs_andMatrixInput_9_252, decoded_andMatrixOutputs_andMatrixInput_10_252)
node decoded_andMatrixOutputs_lo_hi_258 = cat(decoded_andMatrixOutputs_lo_hi_hi_252, decoded_andMatrixOutputs_lo_hi_lo_252)
node decoded_andMatrixOutputs_lo_258 = cat(decoded_andMatrixOutputs_lo_hi_258, decoded_andMatrixOutputs_lo_lo_258)
node decoded_andMatrixOutputs_hi_lo_lo_252 = cat(decoded_andMatrixOutputs_andMatrixInput_7_258, decoded_andMatrixOutputs_andMatrixInput_8_257)
node decoded_andMatrixOutputs_hi_lo_hi_252 = cat(decoded_andMatrixOutputs_andMatrixInput_5_258, decoded_andMatrixOutputs_andMatrixInput_6_258)
node decoded_andMatrixOutputs_hi_lo_258 = cat(decoded_andMatrixOutputs_hi_lo_hi_252, decoded_andMatrixOutputs_hi_lo_lo_252)
node decoded_andMatrixOutputs_hi_hi_lo_252 = cat(decoded_andMatrixOutputs_andMatrixInput_3_258, decoded_andMatrixOutputs_andMatrixInput_4_258)
node decoded_andMatrixOutputs_hi_hi_hi_hi_116 = cat(decoded_andMatrixOutputs_andMatrixInput_0_261, decoded_andMatrixOutputs_andMatrixInput_1_261)
node decoded_andMatrixOutputs_hi_hi_hi_257 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_116, decoded_andMatrixOutputs_andMatrixInput_2_261)
node decoded_andMatrixOutputs_hi_hi_258 = cat(decoded_andMatrixOutputs_hi_hi_hi_257, decoded_andMatrixOutputs_hi_hi_lo_252)
node decoded_andMatrixOutputs_hi_261 = cat(decoded_andMatrixOutputs_hi_hi_258, decoded_andMatrixOutputs_hi_lo_258)
node _decoded_andMatrixOutputs_T_261 = cat(decoded_andMatrixOutputs_hi_261, decoded_andMatrixOutputs_lo_258)
node decoded_andMatrixOutputs_43_2_4 = andr(_decoded_andMatrixOutputs_T_261)
node decoded_andMatrixOutputs_andMatrixInput_0_262 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_262 = bits(decoded_plaInput_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_262 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_259 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_259 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_259 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_259 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_259 = bits(decoded_plaInput_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_258 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_253 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_253 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_253 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_253 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_253 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_253 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_173 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_117 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_173 = cat(decoded_andMatrixOutputs_andMatrixInput_15_173, decoded_andMatrixOutputs_andMatrixInput_16_117)
node decoded_andMatrixOutputs_lo_lo_hi_253 = cat(decoded_andMatrixOutputs_andMatrixInput_13_253, decoded_andMatrixOutputs_andMatrixInput_14_253)
node decoded_andMatrixOutputs_lo_lo_259 = cat(decoded_andMatrixOutputs_lo_lo_hi_253, decoded_andMatrixOutputs_lo_lo_lo_173)
node decoded_andMatrixOutputs_lo_hi_lo_253 = cat(decoded_andMatrixOutputs_andMatrixInput_11_253, decoded_andMatrixOutputs_andMatrixInput_12_253)
node decoded_andMatrixOutputs_lo_hi_hi_253 = cat(decoded_andMatrixOutputs_andMatrixInput_9_253, decoded_andMatrixOutputs_andMatrixInput_10_253)
node decoded_andMatrixOutputs_lo_hi_259 = cat(decoded_andMatrixOutputs_lo_hi_hi_253, decoded_andMatrixOutputs_lo_hi_lo_253)
node decoded_andMatrixOutputs_lo_259 = cat(decoded_andMatrixOutputs_lo_hi_259, decoded_andMatrixOutputs_lo_lo_259)
node decoded_andMatrixOutputs_hi_lo_lo_253 = cat(decoded_andMatrixOutputs_andMatrixInput_7_259, decoded_andMatrixOutputs_andMatrixInput_8_258)
node decoded_andMatrixOutputs_hi_lo_hi_253 = cat(decoded_andMatrixOutputs_andMatrixInput_5_259, decoded_andMatrixOutputs_andMatrixInput_6_259)
node decoded_andMatrixOutputs_hi_lo_259 = cat(decoded_andMatrixOutputs_hi_lo_hi_253, decoded_andMatrixOutputs_hi_lo_lo_253)
node decoded_andMatrixOutputs_hi_hi_lo_253 = cat(decoded_andMatrixOutputs_andMatrixInput_3_259, decoded_andMatrixOutputs_andMatrixInput_4_259)
node decoded_andMatrixOutputs_hi_hi_hi_hi_117 = cat(decoded_andMatrixOutputs_andMatrixInput_0_262, decoded_andMatrixOutputs_andMatrixInput_1_262)
node decoded_andMatrixOutputs_hi_hi_hi_258 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_117, decoded_andMatrixOutputs_andMatrixInput_2_262)
node decoded_andMatrixOutputs_hi_hi_259 = cat(decoded_andMatrixOutputs_hi_hi_hi_258, decoded_andMatrixOutputs_hi_hi_lo_253)
node decoded_andMatrixOutputs_hi_262 = cat(decoded_andMatrixOutputs_hi_hi_259, decoded_andMatrixOutputs_hi_lo_259)
node _decoded_andMatrixOutputs_T_262 = cat(decoded_andMatrixOutputs_hi_262, decoded_andMatrixOutputs_lo_259)
node decoded_andMatrixOutputs_53_2_3 = andr(_decoded_andMatrixOutputs_T_262)
node decoded_andMatrixOutputs_andMatrixInput_0_263 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_263 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_263 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_260 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_260 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_260 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_260 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_260 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_259 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_254 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_254 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_254 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_254 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_254 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_254 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_174 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_174 = cat(decoded_andMatrixOutputs_andMatrixInput_14_254, decoded_andMatrixOutputs_andMatrixInput_15_174)
node decoded_andMatrixOutputs_lo_lo_hi_254 = cat(decoded_andMatrixOutputs_andMatrixInput_12_254, decoded_andMatrixOutputs_andMatrixInput_13_254)
node decoded_andMatrixOutputs_lo_lo_260 = cat(decoded_andMatrixOutputs_lo_lo_hi_254, decoded_andMatrixOutputs_lo_lo_lo_174)
node decoded_andMatrixOutputs_lo_hi_lo_254 = cat(decoded_andMatrixOutputs_andMatrixInput_10_254, decoded_andMatrixOutputs_andMatrixInput_11_254)
node decoded_andMatrixOutputs_lo_hi_hi_254 = cat(decoded_andMatrixOutputs_andMatrixInput_8_259, decoded_andMatrixOutputs_andMatrixInput_9_254)
node decoded_andMatrixOutputs_lo_hi_260 = cat(decoded_andMatrixOutputs_lo_hi_hi_254, decoded_andMatrixOutputs_lo_hi_lo_254)
node decoded_andMatrixOutputs_lo_260 = cat(decoded_andMatrixOutputs_lo_hi_260, decoded_andMatrixOutputs_lo_lo_260)
node decoded_andMatrixOutputs_hi_lo_lo_254 = cat(decoded_andMatrixOutputs_andMatrixInput_6_260, decoded_andMatrixOutputs_andMatrixInput_7_260)
node decoded_andMatrixOutputs_hi_lo_hi_254 = cat(decoded_andMatrixOutputs_andMatrixInput_4_260, decoded_andMatrixOutputs_andMatrixInput_5_260)
node decoded_andMatrixOutputs_hi_lo_260 = cat(decoded_andMatrixOutputs_hi_lo_hi_254, decoded_andMatrixOutputs_hi_lo_lo_254)
node decoded_andMatrixOutputs_hi_hi_lo_254 = cat(decoded_andMatrixOutputs_andMatrixInput_2_263, decoded_andMatrixOutputs_andMatrixInput_3_260)
node decoded_andMatrixOutputs_hi_hi_hi_259 = cat(decoded_andMatrixOutputs_andMatrixInput_0_263, decoded_andMatrixOutputs_andMatrixInput_1_263)
node decoded_andMatrixOutputs_hi_hi_260 = cat(decoded_andMatrixOutputs_hi_hi_hi_259, decoded_andMatrixOutputs_hi_hi_lo_254)
node decoded_andMatrixOutputs_hi_263 = cat(decoded_andMatrixOutputs_hi_hi_260, decoded_andMatrixOutputs_hi_lo_260)
node _decoded_andMatrixOutputs_T_263 = cat(decoded_andMatrixOutputs_hi_263, decoded_andMatrixOutputs_lo_260)
node decoded_andMatrixOutputs_42_2_4 = andr(_decoded_andMatrixOutputs_T_263)
node decoded_andMatrixOutputs_andMatrixInput_0_264 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_264 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_264 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_261 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_261 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_261 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_261 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_261 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_260 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_255 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_255 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_255 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_255 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_255 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_255 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_175 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_175 = cat(decoded_andMatrixOutputs_andMatrixInput_14_255, decoded_andMatrixOutputs_andMatrixInput_15_175)
node decoded_andMatrixOutputs_lo_lo_hi_255 = cat(decoded_andMatrixOutputs_andMatrixInput_12_255, decoded_andMatrixOutputs_andMatrixInput_13_255)
node decoded_andMatrixOutputs_lo_lo_261 = cat(decoded_andMatrixOutputs_lo_lo_hi_255, decoded_andMatrixOutputs_lo_lo_lo_175)
node decoded_andMatrixOutputs_lo_hi_lo_255 = cat(decoded_andMatrixOutputs_andMatrixInput_10_255, decoded_andMatrixOutputs_andMatrixInput_11_255)
node decoded_andMatrixOutputs_lo_hi_hi_255 = cat(decoded_andMatrixOutputs_andMatrixInput_8_260, decoded_andMatrixOutputs_andMatrixInput_9_255)
node decoded_andMatrixOutputs_lo_hi_261 = cat(decoded_andMatrixOutputs_lo_hi_hi_255, decoded_andMatrixOutputs_lo_hi_lo_255)
node decoded_andMatrixOutputs_lo_261 = cat(decoded_andMatrixOutputs_lo_hi_261, decoded_andMatrixOutputs_lo_lo_261)
node decoded_andMatrixOutputs_hi_lo_lo_255 = cat(decoded_andMatrixOutputs_andMatrixInput_6_261, decoded_andMatrixOutputs_andMatrixInput_7_261)
node decoded_andMatrixOutputs_hi_lo_hi_255 = cat(decoded_andMatrixOutputs_andMatrixInput_4_261, decoded_andMatrixOutputs_andMatrixInput_5_261)
node decoded_andMatrixOutputs_hi_lo_261 = cat(decoded_andMatrixOutputs_hi_lo_hi_255, decoded_andMatrixOutputs_hi_lo_lo_255)
node decoded_andMatrixOutputs_hi_hi_lo_255 = cat(decoded_andMatrixOutputs_andMatrixInput_2_264, decoded_andMatrixOutputs_andMatrixInput_3_261)
node decoded_andMatrixOutputs_hi_hi_hi_260 = cat(decoded_andMatrixOutputs_andMatrixInput_0_264, decoded_andMatrixOutputs_andMatrixInput_1_264)
node decoded_andMatrixOutputs_hi_hi_261 = cat(decoded_andMatrixOutputs_hi_hi_hi_260, decoded_andMatrixOutputs_hi_hi_lo_255)
node decoded_andMatrixOutputs_hi_264 = cat(decoded_andMatrixOutputs_hi_hi_261, decoded_andMatrixOutputs_hi_lo_261)
node _decoded_andMatrixOutputs_T_264 = cat(decoded_andMatrixOutputs_hi_264, decoded_andMatrixOutputs_lo_261)
node decoded_andMatrixOutputs_44_2_3 = andr(_decoded_andMatrixOutputs_T_264)
node decoded_andMatrixOutputs_andMatrixInput_0_265 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_265 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_265 = bits(decoded_invInputs_4, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_262 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_262 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_262 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_262 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_262 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_261 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_256 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_256 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_256 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_256 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_256 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_256 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_176 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_118 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_176 = cat(decoded_andMatrixOutputs_andMatrixInput_15_176, decoded_andMatrixOutputs_andMatrixInput_16_118)
node decoded_andMatrixOutputs_lo_lo_hi_256 = cat(decoded_andMatrixOutputs_andMatrixInput_13_256, decoded_andMatrixOutputs_andMatrixInput_14_256)
node decoded_andMatrixOutputs_lo_lo_262 = cat(decoded_andMatrixOutputs_lo_lo_hi_256, decoded_andMatrixOutputs_lo_lo_lo_176)
node decoded_andMatrixOutputs_lo_hi_lo_256 = cat(decoded_andMatrixOutputs_andMatrixInput_11_256, decoded_andMatrixOutputs_andMatrixInput_12_256)
node decoded_andMatrixOutputs_lo_hi_hi_256 = cat(decoded_andMatrixOutputs_andMatrixInput_9_256, decoded_andMatrixOutputs_andMatrixInput_10_256)
node decoded_andMatrixOutputs_lo_hi_262 = cat(decoded_andMatrixOutputs_lo_hi_hi_256, decoded_andMatrixOutputs_lo_hi_lo_256)
node decoded_andMatrixOutputs_lo_262 = cat(decoded_andMatrixOutputs_lo_hi_262, decoded_andMatrixOutputs_lo_lo_262)
node decoded_andMatrixOutputs_hi_lo_lo_256 = cat(decoded_andMatrixOutputs_andMatrixInput_7_262, decoded_andMatrixOutputs_andMatrixInput_8_261)
node decoded_andMatrixOutputs_hi_lo_hi_256 = cat(decoded_andMatrixOutputs_andMatrixInput_5_262, decoded_andMatrixOutputs_andMatrixInput_6_262)
node decoded_andMatrixOutputs_hi_lo_262 = cat(decoded_andMatrixOutputs_hi_lo_hi_256, decoded_andMatrixOutputs_hi_lo_lo_256)
node decoded_andMatrixOutputs_hi_hi_lo_256 = cat(decoded_andMatrixOutputs_andMatrixInput_3_262, decoded_andMatrixOutputs_andMatrixInput_4_262)
node decoded_andMatrixOutputs_hi_hi_hi_hi_118 = cat(decoded_andMatrixOutputs_andMatrixInput_0_265, decoded_andMatrixOutputs_andMatrixInput_1_265)
node decoded_andMatrixOutputs_hi_hi_hi_261 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_118, decoded_andMatrixOutputs_andMatrixInput_2_265)
node decoded_andMatrixOutputs_hi_hi_262 = cat(decoded_andMatrixOutputs_hi_hi_hi_261, decoded_andMatrixOutputs_hi_hi_lo_256)
node decoded_andMatrixOutputs_hi_265 = cat(decoded_andMatrixOutputs_hi_hi_262, decoded_andMatrixOutputs_hi_lo_262)
node _decoded_andMatrixOutputs_T_265 = cat(decoded_andMatrixOutputs_hi_265, decoded_andMatrixOutputs_lo_262)
node decoded_andMatrixOutputs_45_2_3 = andr(_decoded_andMatrixOutputs_T_265)
node decoded_andMatrixOutputs_andMatrixInput_0_266 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_266 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_266 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_263 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_263 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_263 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_263 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_263 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_262 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_257 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_257 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_257 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_257 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_257 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_257 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_177 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_177 = cat(decoded_andMatrixOutputs_andMatrixInput_14_257, decoded_andMatrixOutputs_andMatrixInput_15_177)
node decoded_andMatrixOutputs_lo_lo_hi_257 = cat(decoded_andMatrixOutputs_andMatrixInput_12_257, decoded_andMatrixOutputs_andMatrixInput_13_257)
node decoded_andMatrixOutputs_lo_lo_263 = cat(decoded_andMatrixOutputs_lo_lo_hi_257, decoded_andMatrixOutputs_lo_lo_lo_177)
node decoded_andMatrixOutputs_lo_hi_lo_257 = cat(decoded_andMatrixOutputs_andMatrixInput_10_257, decoded_andMatrixOutputs_andMatrixInput_11_257)
node decoded_andMatrixOutputs_lo_hi_hi_257 = cat(decoded_andMatrixOutputs_andMatrixInput_8_262, decoded_andMatrixOutputs_andMatrixInput_9_257)
node decoded_andMatrixOutputs_lo_hi_263 = cat(decoded_andMatrixOutputs_lo_hi_hi_257, decoded_andMatrixOutputs_lo_hi_lo_257)
node decoded_andMatrixOutputs_lo_263 = cat(decoded_andMatrixOutputs_lo_hi_263, decoded_andMatrixOutputs_lo_lo_263)
node decoded_andMatrixOutputs_hi_lo_lo_257 = cat(decoded_andMatrixOutputs_andMatrixInput_6_263, decoded_andMatrixOutputs_andMatrixInput_7_263)
node decoded_andMatrixOutputs_hi_lo_hi_257 = cat(decoded_andMatrixOutputs_andMatrixInput_4_263, decoded_andMatrixOutputs_andMatrixInput_5_263)
node decoded_andMatrixOutputs_hi_lo_263 = cat(decoded_andMatrixOutputs_hi_lo_hi_257, decoded_andMatrixOutputs_hi_lo_lo_257)
node decoded_andMatrixOutputs_hi_hi_lo_257 = cat(decoded_andMatrixOutputs_andMatrixInput_2_266, decoded_andMatrixOutputs_andMatrixInput_3_263)
node decoded_andMatrixOutputs_hi_hi_hi_262 = cat(decoded_andMatrixOutputs_andMatrixInput_0_266, decoded_andMatrixOutputs_andMatrixInput_1_266)
node decoded_andMatrixOutputs_hi_hi_263 = cat(decoded_andMatrixOutputs_hi_hi_hi_262, decoded_andMatrixOutputs_hi_hi_lo_257)
node decoded_andMatrixOutputs_hi_266 = cat(decoded_andMatrixOutputs_hi_hi_263, decoded_andMatrixOutputs_hi_lo_263)
node _decoded_andMatrixOutputs_T_266 = cat(decoded_andMatrixOutputs_hi_266, decoded_andMatrixOutputs_lo_263)
node decoded_andMatrixOutputs_7_2_4 = andr(_decoded_andMatrixOutputs_T_266)
node decoded_andMatrixOutputs_andMatrixInput_0_267 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_267 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_267 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_264 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_264 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_264 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_264 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_264 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_263 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_258 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_258 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_258 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_258 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_258 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_258 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_178 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_119 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_178 = cat(decoded_andMatrixOutputs_andMatrixInput_15_178, decoded_andMatrixOutputs_andMatrixInput_16_119)
node decoded_andMatrixOutputs_lo_lo_hi_258 = cat(decoded_andMatrixOutputs_andMatrixInput_13_258, decoded_andMatrixOutputs_andMatrixInput_14_258)
node decoded_andMatrixOutputs_lo_lo_264 = cat(decoded_andMatrixOutputs_lo_lo_hi_258, decoded_andMatrixOutputs_lo_lo_lo_178)
node decoded_andMatrixOutputs_lo_hi_lo_258 = cat(decoded_andMatrixOutputs_andMatrixInput_11_258, decoded_andMatrixOutputs_andMatrixInput_12_258)
node decoded_andMatrixOutputs_lo_hi_hi_258 = cat(decoded_andMatrixOutputs_andMatrixInput_9_258, decoded_andMatrixOutputs_andMatrixInput_10_258)
node decoded_andMatrixOutputs_lo_hi_264 = cat(decoded_andMatrixOutputs_lo_hi_hi_258, decoded_andMatrixOutputs_lo_hi_lo_258)
node decoded_andMatrixOutputs_lo_264 = cat(decoded_andMatrixOutputs_lo_hi_264, decoded_andMatrixOutputs_lo_lo_264)
node decoded_andMatrixOutputs_hi_lo_lo_258 = cat(decoded_andMatrixOutputs_andMatrixInput_7_264, decoded_andMatrixOutputs_andMatrixInput_8_263)
node decoded_andMatrixOutputs_hi_lo_hi_258 = cat(decoded_andMatrixOutputs_andMatrixInput_5_264, decoded_andMatrixOutputs_andMatrixInput_6_264)
node decoded_andMatrixOutputs_hi_lo_264 = cat(decoded_andMatrixOutputs_hi_lo_hi_258, decoded_andMatrixOutputs_hi_lo_lo_258)
node decoded_andMatrixOutputs_hi_hi_lo_258 = cat(decoded_andMatrixOutputs_andMatrixInput_3_264, decoded_andMatrixOutputs_andMatrixInput_4_264)
node decoded_andMatrixOutputs_hi_hi_hi_hi_119 = cat(decoded_andMatrixOutputs_andMatrixInput_0_267, decoded_andMatrixOutputs_andMatrixInput_1_267)
node decoded_andMatrixOutputs_hi_hi_hi_263 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_119, decoded_andMatrixOutputs_andMatrixInput_2_267)
node decoded_andMatrixOutputs_hi_hi_264 = cat(decoded_andMatrixOutputs_hi_hi_hi_263, decoded_andMatrixOutputs_hi_hi_lo_258)
node decoded_andMatrixOutputs_hi_267 = cat(decoded_andMatrixOutputs_hi_hi_264, decoded_andMatrixOutputs_hi_lo_264)
node _decoded_andMatrixOutputs_T_267 = cat(decoded_andMatrixOutputs_hi_267, decoded_andMatrixOutputs_lo_264)
node decoded_andMatrixOutputs_34_2_4 = andr(_decoded_andMatrixOutputs_T_267)
node decoded_andMatrixOutputs_andMatrixInput_0_268 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_268 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_268 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_265 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_265 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_265 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_265 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_265 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_264 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_259 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_259 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_259 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_259 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_259 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_259 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_179 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_120 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_179 = cat(decoded_andMatrixOutputs_andMatrixInput_15_179, decoded_andMatrixOutputs_andMatrixInput_16_120)
node decoded_andMatrixOutputs_lo_lo_hi_259 = cat(decoded_andMatrixOutputs_andMatrixInput_13_259, decoded_andMatrixOutputs_andMatrixInput_14_259)
node decoded_andMatrixOutputs_lo_lo_265 = cat(decoded_andMatrixOutputs_lo_lo_hi_259, decoded_andMatrixOutputs_lo_lo_lo_179)
node decoded_andMatrixOutputs_lo_hi_lo_259 = cat(decoded_andMatrixOutputs_andMatrixInput_11_259, decoded_andMatrixOutputs_andMatrixInput_12_259)
node decoded_andMatrixOutputs_lo_hi_hi_259 = cat(decoded_andMatrixOutputs_andMatrixInput_9_259, decoded_andMatrixOutputs_andMatrixInput_10_259)
node decoded_andMatrixOutputs_lo_hi_265 = cat(decoded_andMatrixOutputs_lo_hi_hi_259, decoded_andMatrixOutputs_lo_hi_lo_259)
node decoded_andMatrixOutputs_lo_265 = cat(decoded_andMatrixOutputs_lo_hi_265, decoded_andMatrixOutputs_lo_lo_265)
node decoded_andMatrixOutputs_hi_lo_lo_259 = cat(decoded_andMatrixOutputs_andMatrixInput_7_265, decoded_andMatrixOutputs_andMatrixInput_8_264)
node decoded_andMatrixOutputs_hi_lo_hi_259 = cat(decoded_andMatrixOutputs_andMatrixInput_5_265, decoded_andMatrixOutputs_andMatrixInput_6_265)
node decoded_andMatrixOutputs_hi_lo_265 = cat(decoded_andMatrixOutputs_hi_lo_hi_259, decoded_andMatrixOutputs_hi_lo_lo_259)
node decoded_andMatrixOutputs_hi_hi_lo_259 = cat(decoded_andMatrixOutputs_andMatrixInput_3_265, decoded_andMatrixOutputs_andMatrixInput_4_265)
node decoded_andMatrixOutputs_hi_hi_hi_hi_120 = cat(decoded_andMatrixOutputs_andMatrixInput_0_268, decoded_andMatrixOutputs_andMatrixInput_1_268)
node decoded_andMatrixOutputs_hi_hi_hi_264 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_120, decoded_andMatrixOutputs_andMatrixInput_2_268)
node decoded_andMatrixOutputs_hi_hi_265 = cat(decoded_andMatrixOutputs_hi_hi_hi_264, decoded_andMatrixOutputs_hi_hi_lo_259)
node decoded_andMatrixOutputs_hi_268 = cat(decoded_andMatrixOutputs_hi_hi_265, decoded_andMatrixOutputs_hi_lo_265)
node _decoded_andMatrixOutputs_T_268 = cat(decoded_andMatrixOutputs_hi_268, decoded_andMatrixOutputs_lo_265)
node decoded_andMatrixOutputs_0_2_4 = andr(_decoded_andMatrixOutputs_T_268)
node decoded_andMatrixOutputs_andMatrixInput_0_269 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_269 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_269 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_266 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_266 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_266 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_266 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_266 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_265 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_260 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_260 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_260 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_260 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_260 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_260 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_180 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_121 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_180 = cat(decoded_andMatrixOutputs_andMatrixInput_15_180, decoded_andMatrixOutputs_andMatrixInput_16_121)
node decoded_andMatrixOutputs_lo_lo_hi_260 = cat(decoded_andMatrixOutputs_andMatrixInput_13_260, decoded_andMatrixOutputs_andMatrixInput_14_260)
node decoded_andMatrixOutputs_lo_lo_266 = cat(decoded_andMatrixOutputs_lo_lo_hi_260, decoded_andMatrixOutputs_lo_lo_lo_180)
node decoded_andMatrixOutputs_lo_hi_lo_260 = cat(decoded_andMatrixOutputs_andMatrixInput_11_260, decoded_andMatrixOutputs_andMatrixInput_12_260)
node decoded_andMatrixOutputs_lo_hi_hi_260 = cat(decoded_andMatrixOutputs_andMatrixInput_9_260, decoded_andMatrixOutputs_andMatrixInput_10_260)
node decoded_andMatrixOutputs_lo_hi_266 = cat(decoded_andMatrixOutputs_lo_hi_hi_260, decoded_andMatrixOutputs_lo_hi_lo_260)
node decoded_andMatrixOutputs_lo_266 = cat(decoded_andMatrixOutputs_lo_hi_266, decoded_andMatrixOutputs_lo_lo_266)
node decoded_andMatrixOutputs_hi_lo_lo_260 = cat(decoded_andMatrixOutputs_andMatrixInput_7_266, decoded_andMatrixOutputs_andMatrixInput_8_265)
node decoded_andMatrixOutputs_hi_lo_hi_260 = cat(decoded_andMatrixOutputs_andMatrixInput_5_266, decoded_andMatrixOutputs_andMatrixInput_6_266)
node decoded_andMatrixOutputs_hi_lo_266 = cat(decoded_andMatrixOutputs_hi_lo_hi_260, decoded_andMatrixOutputs_hi_lo_lo_260)
node decoded_andMatrixOutputs_hi_hi_lo_260 = cat(decoded_andMatrixOutputs_andMatrixInput_3_266, decoded_andMatrixOutputs_andMatrixInput_4_266)
node decoded_andMatrixOutputs_hi_hi_hi_hi_121 = cat(decoded_andMatrixOutputs_andMatrixInput_0_269, decoded_andMatrixOutputs_andMatrixInput_1_269)
node decoded_andMatrixOutputs_hi_hi_hi_265 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_121, decoded_andMatrixOutputs_andMatrixInput_2_269)
node decoded_andMatrixOutputs_hi_hi_266 = cat(decoded_andMatrixOutputs_hi_hi_hi_265, decoded_andMatrixOutputs_hi_hi_lo_260)
node decoded_andMatrixOutputs_hi_269 = cat(decoded_andMatrixOutputs_hi_hi_266, decoded_andMatrixOutputs_hi_lo_266)
node _decoded_andMatrixOutputs_T_269 = cat(decoded_andMatrixOutputs_hi_269, decoded_andMatrixOutputs_lo_266)
node decoded_andMatrixOutputs_3_2_4 = andr(_decoded_andMatrixOutputs_T_269)
node decoded_andMatrixOutputs_andMatrixInput_0_270 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_270 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_270 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_3_267 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_4_267 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_5_267 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_6_267 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_7_267 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_8_266 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_267 = cat(decoded_andMatrixOutputs_andMatrixInput_7_267, decoded_andMatrixOutputs_andMatrixInput_8_266)
node decoded_andMatrixOutputs_lo_hi_267 = cat(decoded_andMatrixOutputs_andMatrixInput_5_267, decoded_andMatrixOutputs_andMatrixInput_6_267)
node decoded_andMatrixOutputs_lo_267 = cat(decoded_andMatrixOutputs_lo_hi_267, decoded_andMatrixOutputs_lo_lo_267)
node decoded_andMatrixOutputs_hi_lo_267 = cat(decoded_andMatrixOutputs_andMatrixInput_3_267, decoded_andMatrixOutputs_andMatrixInput_4_267)
node decoded_andMatrixOutputs_hi_hi_hi_266 = cat(decoded_andMatrixOutputs_andMatrixInput_0_270, decoded_andMatrixOutputs_andMatrixInput_1_270)
node decoded_andMatrixOutputs_hi_hi_267 = cat(decoded_andMatrixOutputs_hi_hi_hi_266, decoded_andMatrixOutputs_andMatrixInput_2_270)
node decoded_andMatrixOutputs_hi_270 = cat(decoded_andMatrixOutputs_hi_hi_267, decoded_andMatrixOutputs_hi_lo_267)
node _decoded_andMatrixOutputs_T_270 = cat(decoded_andMatrixOutputs_hi_270, decoded_andMatrixOutputs_lo_267)
node decoded_andMatrixOutputs_50_2_3 = andr(_decoded_andMatrixOutputs_T_270)
node decoded_andMatrixOutputs_andMatrixInput_0_271 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_271 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_271 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_268 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_268 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_268 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_268 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_268 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_267 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_261 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_261 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_261 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_261 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_261 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_261 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_181 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_122 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_181 = cat(decoded_andMatrixOutputs_andMatrixInput_15_181, decoded_andMatrixOutputs_andMatrixInput_16_122)
node decoded_andMatrixOutputs_lo_lo_hi_261 = cat(decoded_andMatrixOutputs_andMatrixInput_13_261, decoded_andMatrixOutputs_andMatrixInput_14_261)
node decoded_andMatrixOutputs_lo_lo_268 = cat(decoded_andMatrixOutputs_lo_lo_hi_261, decoded_andMatrixOutputs_lo_lo_lo_181)
node decoded_andMatrixOutputs_lo_hi_lo_261 = cat(decoded_andMatrixOutputs_andMatrixInput_11_261, decoded_andMatrixOutputs_andMatrixInput_12_261)
node decoded_andMatrixOutputs_lo_hi_hi_261 = cat(decoded_andMatrixOutputs_andMatrixInput_9_261, decoded_andMatrixOutputs_andMatrixInput_10_261)
node decoded_andMatrixOutputs_lo_hi_268 = cat(decoded_andMatrixOutputs_lo_hi_hi_261, decoded_andMatrixOutputs_lo_hi_lo_261)
node decoded_andMatrixOutputs_lo_268 = cat(decoded_andMatrixOutputs_lo_hi_268, decoded_andMatrixOutputs_lo_lo_268)
node decoded_andMatrixOutputs_hi_lo_lo_261 = cat(decoded_andMatrixOutputs_andMatrixInput_7_268, decoded_andMatrixOutputs_andMatrixInput_8_267)
node decoded_andMatrixOutputs_hi_lo_hi_261 = cat(decoded_andMatrixOutputs_andMatrixInput_5_268, decoded_andMatrixOutputs_andMatrixInput_6_268)
node decoded_andMatrixOutputs_hi_lo_268 = cat(decoded_andMatrixOutputs_hi_lo_hi_261, decoded_andMatrixOutputs_hi_lo_lo_261)
node decoded_andMatrixOutputs_hi_hi_lo_261 = cat(decoded_andMatrixOutputs_andMatrixInput_3_268, decoded_andMatrixOutputs_andMatrixInput_4_268)
node decoded_andMatrixOutputs_hi_hi_hi_hi_122 = cat(decoded_andMatrixOutputs_andMatrixInput_0_271, decoded_andMatrixOutputs_andMatrixInput_1_271)
node decoded_andMatrixOutputs_hi_hi_hi_267 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_122, decoded_andMatrixOutputs_andMatrixInput_2_271)
node decoded_andMatrixOutputs_hi_hi_268 = cat(decoded_andMatrixOutputs_hi_hi_hi_267, decoded_andMatrixOutputs_hi_hi_lo_261)
node decoded_andMatrixOutputs_hi_271 = cat(decoded_andMatrixOutputs_hi_hi_268, decoded_andMatrixOutputs_hi_lo_268)
node _decoded_andMatrixOutputs_T_271 = cat(decoded_andMatrixOutputs_hi_271, decoded_andMatrixOutputs_lo_268)
node decoded_andMatrixOutputs_57_2_1 = andr(_decoded_andMatrixOutputs_T_271)
node decoded_andMatrixOutputs_andMatrixInput_0_272 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_272 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_272 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_269 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_269 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_269 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_269 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_269 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_268 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_262 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_262 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_262 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_262 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_262 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_262 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_182 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_123 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_182 = cat(decoded_andMatrixOutputs_andMatrixInput_15_182, decoded_andMatrixOutputs_andMatrixInput_16_123)
node decoded_andMatrixOutputs_lo_lo_hi_262 = cat(decoded_andMatrixOutputs_andMatrixInput_13_262, decoded_andMatrixOutputs_andMatrixInput_14_262)
node decoded_andMatrixOutputs_lo_lo_269 = cat(decoded_andMatrixOutputs_lo_lo_hi_262, decoded_andMatrixOutputs_lo_lo_lo_182)
node decoded_andMatrixOutputs_lo_hi_lo_262 = cat(decoded_andMatrixOutputs_andMatrixInput_11_262, decoded_andMatrixOutputs_andMatrixInput_12_262)
node decoded_andMatrixOutputs_lo_hi_hi_262 = cat(decoded_andMatrixOutputs_andMatrixInput_9_262, decoded_andMatrixOutputs_andMatrixInput_10_262)
node decoded_andMatrixOutputs_lo_hi_269 = cat(decoded_andMatrixOutputs_lo_hi_hi_262, decoded_andMatrixOutputs_lo_hi_lo_262)
node decoded_andMatrixOutputs_lo_269 = cat(decoded_andMatrixOutputs_lo_hi_269, decoded_andMatrixOutputs_lo_lo_269)
node decoded_andMatrixOutputs_hi_lo_lo_262 = cat(decoded_andMatrixOutputs_andMatrixInput_7_269, decoded_andMatrixOutputs_andMatrixInput_8_268)
node decoded_andMatrixOutputs_hi_lo_hi_262 = cat(decoded_andMatrixOutputs_andMatrixInput_5_269, decoded_andMatrixOutputs_andMatrixInput_6_269)
node decoded_andMatrixOutputs_hi_lo_269 = cat(decoded_andMatrixOutputs_hi_lo_hi_262, decoded_andMatrixOutputs_hi_lo_lo_262)
node decoded_andMatrixOutputs_hi_hi_lo_262 = cat(decoded_andMatrixOutputs_andMatrixInput_3_269, decoded_andMatrixOutputs_andMatrixInput_4_269)
node decoded_andMatrixOutputs_hi_hi_hi_hi_123 = cat(decoded_andMatrixOutputs_andMatrixInput_0_272, decoded_andMatrixOutputs_andMatrixInput_1_272)
node decoded_andMatrixOutputs_hi_hi_hi_268 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_123, decoded_andMatrixOutputs_andMatrixInput_2_272)
node decoded_andMatrixOutputs_hi_hi_269 = cat(decoded_andMatrixOutputs_hi_hi_hi_268, decoded_andMatrixOutputs_hi_hi_lo_262)
node decoded_andMatrixOutputs_hi_272 = cat(decoded_andMatrixOutputs_hi_hi_269, decoded_andMatrixOutputs_hi_lo_269)
node _decoded_andMatrixOutputs_T_272 = cat(decoded_andMatrixOutputs_hi_272, decoded_andMatrixOutputs_lo_269)
node decoded_andMatrixOutputs_58_2_1 = andr(_decoded_andMatrixOutputs_T_272)
node decoded_andMatrixOutputs_andMatrixInput_0_273 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_273 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_273 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_270 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_270 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_270 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_270 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_270 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_269 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_263 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_263 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_263 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_263 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_263 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_263 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_183 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_124 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_183 = cat(decoded_andMatrixOutputs_andMatrixInput_15_183, decoded_andMatrixOutputs_andMatrixInput_16_124)
node decoded_andMatrixOutputs_lo_lo_hi_263 = cat(decoded_andMatrixOutputs_andMatrixInput_13_263, decoded_andMatrixOutputs_andMatrixInput_14_263)
node decoded_andMatrixOutputs_lo_lo_270 = cat(decoded_andMatrixOutputs_lo_lo_hi_263, decoded_andMatrixOutputs_lo_lo_lo_183)
node decoded_andMatrixOutputs_lo_hi_lo_263 = cat(decoded_andMatrixOutputs_andMatrixInput_11_263, decoded_andMatrixOutputs_andMatrixInput_12_263)
node decoded_andMatrixOutputs_lo_hi_hi_263 = cat(decoded_andMatrixOutputs_andMatrixInput_9_263, decoded_andMatrixOutputs_andMatrixInput_10_263)
node decoded_andMatrixOutputs_lo_hi_270 = cat(decoded_andMatrixOutputs_lo_hi_hi_263, decoded_andMatrixOutputs_lo_hi_lo_263)
node decoded_andMatrixOutputs_lo_270 = cat(decoded_andMatrixOutputs_lo_hi_270, decoded_andMatrixOutputs_lo_lo_270)
node decoded_andMatrixOutputs_hi_lo_lo_263 = cat(decoded_andMatrixOutputs_andMatrixInput_7_270, decoded_andMatrixOutputs_andMatrixInput_8_269)
node decoded_andMatrixOutputs_hi_lo_hi_263 = cat(decoded_andMatrixOutputs_andMatrixInput_5_270, decoded_andMatrixOutputs_andMatrixInput_6_270)
node decoded_andMatrixOutputs_hi_lo_270 = cat(decoded_andMatrixOutputs_hi_lo_hi_263, decoded_andMatrixOutputs_hi_lo_lo_263)
node decoded_andMatrixOutputs_hi_hi_lo_263 = cat(decoded_andMatrixOutputs_andMatrixInput_3_270, decoded_andMatrixOutputs_andMatrixInput_4_270)
node decoded_andMatrixOutputs_hi_hi_hi_hi_124 = cat(decoded_andMatrixOutputs_andMatrixInput_0_273, decoded_andMatrixOutputs_andMatrixInput_1_273)
node decoded_andMatrixOutputs_hi_hi_hi_269 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_124, decoded_andMatrixOutputs_andMatrixInput_2_273)
node decoded_andMatrixOutputs_hi_hi_270 = cat(decoded_andMatrixOutputs_hi_hi_hi_269, decoded_andMatrixOutputs_hi_hi_lo_263)
node decoded_andMatrixOutputs_hi_273 = cat(decoded_andMatrixOutputs_hi_hi_270, decoded_andMatrixOutputs_hi_lo_270)
node _decoded_andMatrixOutputs_T_273 = cat(decoded_andMatrixOutputs_hi_273, decoded_andMatrixOutputs_lo_270)
node decoded_andMatrixOutputs_13_2_4 = andr(_decoded_andMatrixOutputs_T_273)
node decoded_andMatrixOutputs_andMatrixInput_0_274 = bits(decoded_plaInput_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_274 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_274 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_271 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_271 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_271 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_271 = bits(decoded_plaInput_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_271 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_270 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_264 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_264 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_264 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_264 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_264 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_264 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_184 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_125 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_184 = cat(decoded_andMatrixOutputs_andMatrixInput_15_184, decoded_andMatrixOutputs_andMatrixInput_16_125)
node decoded_andMatrixOutputs_lo_lo_hi_264 = cat(decoded_andMatrixOutputs_andMatrixInput_13_264, decoded_andMatrixOutputs_andMatrixInput_14_264)
node decoded_andMatrixOutputs_lo_lo_271 = cat(decoded_andMatrixOutputs_lo_lo_hi_264, decoded_andMatrixOutputs_lo_lo_lo_184)
node decoded_andMatrixOutputs_lo_hi_lo_264 = cat(decoded_andMatrixOutputs_andMatrixInput_11_264, decoded_andMatrixOutputs_andMatrixInput_12_264)
node decoded_andMatrixOutputs_lo_hi_hi_264 = cat(decoded_andMatrixOutputs_andMatrixInput_9_264, decoded_andMatrixOutputs_andMatrixInput_10_264)
node decoded_andMatrixOutputs_lo_hi_271 = cat(decoded_andMatrixOutputs_lo_hi_hi_264, decoded_andMatrixOutputs_lo_hi_lo_264)
node decoded_andMatrixOutputs_lo_271 = cat(decoded_andMatrixOutputs_lo_hi_271, decoded_andMatrixOutputs_lo_lo_271)
node decoded_andMatrixOutputs_hi_lo_lo_264 = cat(decoded_andMatrixOutputs_andMatrixInput_7_271, decoded_andMatrixOutputs_andMatrixInput_8_270)
node decoded_andMatrixOutputs_hi_lo_hi_264 = cat(decoded_andMatrixOutputs_andMatrixInput_5_271, decoded_andMatrixOutputs_andMatrixInput_6_271)
node decoded_andMatrixOutputs_hi_lo_271 = cat(decoded_andMatrixOutputs_hi_lo_hi_264, decoded_andMatrixOutputs_hi_lo_lo_264)
node decoded_andMatrixOutputs_hi_hi_lo_264 = cat(decoded_andMatrixOutputs_andMatrixInput_3_271, decoded_andMatrixOutputs_andMatrixInput_4_271)
node decoded_andMatrixOutputs_hi_hi_hi_hi_125 = cat(decoded_andMatrixOutputs_andMatrixInput_0_274, decoded_andMatrixOutputs_andMatrixInput_1_274)
node decoded_andMatrixOutputs_hi_hi_hi_270 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_125, decoded_andMatrixOutputs_andMatrixInput_2_274)
node decoded_andMatrixOutputs_hi_hi_271 = cat(decoded_andMatrixOutputs_hi_hi_hi_270, decoded_andMatrixOutputs_hi_hi_lo_264)
node decoded_andMatrixOutputs_hi_274 = cat(decoded_andMatrixOutputs_hi_hi_271, decoded_andMatrixOutputs_hi_lo_271)
node _decoded_andMatrixOutputs_T_274 = cat(decoded_andMatrixOutputs_hi_274, decoded_andMatrixOutputs_lo_271)
node decoded_andMatrixOutputs_24_2_4 = andr(_decoded_andMatrixOutputs_T_274)
node decoded_andMatrixOutputs_andMatrixInput_0_275 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_275 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_275 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_272 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_272 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_272 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_272 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_272 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_271 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_265 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_265 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_265 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_265 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_265 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_265 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_185 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_185 = cat(decoded_andMatrixOutputs_andMatrixInput_14_265, decoded_andMatrixOutputs_andMatrixInput_15_185)
node decoded_andMatrixOutputs_lo_lo_hi_265 = cat(decoded_andMatrixOutputs_andMatrixInput_12_265, decoded_andMatrixOutputs_andMatrixInput_13_265)
node decoded_andMatrixOutputs_lo_lo_272 = cat(decoded_andMatrixOutputs_lo_lo_hi_265, decoded_andMatrixOutputs_lo_lo_lo_185)
node decoded_andMatrixOutputs_lo_hi_lo_265 = cat(decoded_andMatrixOutputs_andMatrixInput_10_265, decoded_andMatrixOutputs_andMatrixInput_11_265)
node decoded_andMatrixOutputs_lo_hi_hi_265 = cat(decoded_andMatrixOutputs_andMatrixInput_8_271, decoded_andMatrixOutputs_andMatrixInput_9_265)
node decoded_andMatrixOutputs_lo_hi_272 = cat(decoded_andMatrixOutputs_lo_hi_hi_265, decoded_andMatrixOutputs_lo_hi_lo_265)
node decoded_andMatrixOutputs_lo_272 = cat(decoded_andMatrixOutputs_lo_hi_272, decoded_andMatrixOutputs_lo_lo_272)
node decoded_andMatrixOutputs_hi_lo_lo_265 = cat(decoded_andMatrixOutputs_andMatrixInput_6_272, decoded_andMatrixOutputs_andMatrixInput_7_272)
node decoded_andMatrixOutputs_hi_lo_hi_265 = cat(decoded_andMatrixOutputs_andMatrixInput_4_272, decoded_andMatrixOutputs_andMatrixInput_5_272)
node decoded_andMatrixOutputs_hi_lo_272 = cat(decoded_andMatrixOutputs_hi_lo_hi_265, decoded_andMatrixOutputs_hi_lo_lo_265)
node decoded_andMatrixOutputs_hi_hi_lo_265 = cat(decoded_andMatrixOutputs_andMatrixInput_2_275, decoded_andMatrixOutputs_andMatrixInput_3_272)
node decoded_andMatrixOutputs_hi_hi_hi_271 = cat(decoded_andMatrixOutputs_andMatrixInput_0_275, decoded_andMatrixOutputs_andMatrixInput_1_275)
node decoded_andMatrixOutputs_hi_hi_272 = cat(decoded_andMatrixOutputs_hi_hi_hi_271, decoded_andMatrixOutputs_hi_hi_lo_265)
node decoded_andMatrixOutputs_hi_275 = cat(decoded_andMatrixOutputs_hi_hi_272, decoded_andMatrixOutputs_hi_lo_272)
node _decoded_andMatrixOutputs_T_275 = cat(decoded_andMatrixOutputs_hi_275, decoded_andMatrixOutputs_lo_272)
node decoded_andMatrixOutputs_8_2_4 = andr(_decoded_andMatrixOutputs_T_275)
node decoded_andMatrixOutputs_andMatrixInput_0_276 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_276 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_276 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_273 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_273 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_273 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_273 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_273 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_272 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_266 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_266 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_266 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_266 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_266 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_266 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_186 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_186 = cat(decoded_andMatrixOutputs_andMatrixInput_14_266, decoded_andMatrixOutputs_andMatrixInput_15_186)
node decoded_andMatrixOutputs_lo_lo_hi_266 = cat(decoded_andMatrixOutputs_andMatrixInput_12_266, decoded_andMatrixOutputs_andMatrixInput_13_266)
node decoded_andMatrixOutputs_lo_lo_273 = cat(decoded_andMatrixOutputs_lo_lo_hi_266, decoded_andMatrixOutputs_lo_lo_lo_186)
node decoded_andMatrixOutputs_lo_hi_lo_266 = cat(decoded_andMatrixOutputs_andMatrixInput_10_266, decoded_andMatrixOutputs_andMatrixInput_11_266)
node decoded_andMatrixOutputs_lo_hi_hi_266 = cat(decoded_andMatrixOutputs_andMatrixInput_8_272, decoded_andMatrixOutputs_andMatrixInput_9_266)
node decoded_andMatrixOutputs_lo_hi_273 = cat(decoded_andMatrixOutputs_lo_hi_hi_266, decoded_andMatrixOutputs_lo_hi_lo_266)
node decoded_andMatrixOutputs_lo_273 = cat(decoded_andMatrixOutputs_lo_hi_273, decoded_andMatrixOutputs_lo_lo_273)
node decoded_andMatrixOutputs_hi_lo_lo_266 = cat(decoded_andMatrixOutputs_andMatrixInput_6_273, decoded_andMatrixOutputs_andMatrixInput_7_273)
node decoded_andMatrixOutputs_hi_lo_hi_266 = cat(decoded_andMatrixOutputs_andMatrixInput_4_273, decoded_andMatrixOutputs_andMatrixInput_5_273)
node decoded_andMatrixOutputs_hi_lo_273 = cat(decoded_andMatrixOutputs_hi_lo_hi_266, decoded_andMatrixOutputs_hi_lo_lo_266)
node decoded_andMatrixOutputs_hi_hi_lo_266 = cat(decoded_andMatrixOutputs_andMatrixInput_2_276, decoded_andMatrixOutputs_andMatrixInput_3_273)
node decoded_andMatrixOutputs_hi_hi_hi_272 = cat(decoded_andMatrixOutputs_andMatrixInput_0_276, decoded_andMatrixOutputs_andMatrixInput_1_276)
node decoded_andMatrixOutputs_hi_hi_273 = cat(decoded_andMatrixOutputs_hi_hi_hi_272, decoded_andMatrixOutputs_hi_hi_lo_266)
node decoded_andMatrixOutputs_hi_276 = cat(decoded_andMatrixOutputs_hi_hi_273, decoded_andMatrixOutputs_hi_lo_273)
node _decoded_andMatrixOutputs_T_276 = cat(decoded_andMatrixOutputs_hi_276, decoded_andMatrixOutputs_lo_273)
node decoded_andMatrixOutputs_23_2_4 = andr(_decoded_andMatrixOutputs_T_276)
node decoded_andMatrixOutputs_andMatrixInput_0_277 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_277 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_277 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_274 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_274 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_274 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_274 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_274 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_273 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_267 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_267 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_267 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_267 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_267 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_267 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_187 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_187 = cat(decoded_andMatrixOutputs_andMatrixInput_14_267, decoded_andMatrixOutputs_andMatrixInput_15_187)
node decoded_andMatrixOutputs_lo_lo_hi_267 = cat(decoded_andMatrixOutputs_andMatrixInput_12_267, decoded_andMatrixOutputs_andMatrixInput_13_267)
node decoded_andMatrixOutputs_lo_lo_274 = cat(decoded_andMatrixOutputs_lo_lo_hi_267, decoded_andMatrixOutputs_lo_lo_lo_187)
node decoded_andMatrixOutputs_lo_hi_lo_267 = cat(decoded_andMatrixOutputs_andMatrixInput_10_267, decoded_andMatrixOutputs_andMatrixInput_11_267)
node decoded_andMatrixOutputs_lo_hi_hi_267 = cat(decoded_andMatrixOutputs_andMatrixInput_8_273, decoded_andMatrixOutputs_andMatrixInput_9_267)
node decoded_andMatrixOutputs_lo_hi_274 = cat(decoded_andMatrixOutputs_lo_hi_hi_267, decoded_andMatrixOutputs_lo_hi_lo_267)
node decoded_andMatrixOutputs_lo_274 = cat(decoded_andMatrixOutputs_lo_hi_274, decoded_andMatrixOutputs_lo_lo_274)
node decoded_andMatrixOutputs_hi_lo_lo_267 = cat(decoded_andMatrixOutputs_andMatrixInput_6_274, decoded_andMatrixOutputs_andMatrixInput_7_274)
node decoded_andMatrixOutputs_hi_lo_hi_267 = cat(decoded_andMatrixOutputs_andMatrixInput_4_274, decoded_andMatrixOutputs_andMatrixInput_5_274)
node decoded_andMatrixOutputs_hi_lo_274 = cat(decoded_andMatrixOutputs_hi_lo_hi_267, decoded_andMatrixOutputs_hi_lo_lo_267)
node decoded_andMatrixOutputs_hi_hi_lo_267 = cat(decoded_andMatrixOutputs_andMatrixInput_2_277, decoded_andMatrixOutputs_andMatrixInput_3_274)
node decoded_andMatrixOutputs_hi_hi_hi_273 = cat(decoded_andMatrixOutputs_andMatrixInput_0_277, decoded_andMatrixOutputs_andMatrixInput_1_277)
node decoded_andMatrixOutputs_hi_hi_274 = cat(decoded_andMatrixOutputs_hi_hi_hi_273, decoded_andMatrixOutputs_hi_hi_lo_267)
node decoded_andMatrixOutputs_hi_277 = cat(decoded_andMatrixOutputs_hi_hi_274, decoded_andMatrixOutputs_hi_lo_274)
node _decoded_andMatrixOutputs_T_277 = cat(decoded_andMatrixOutputs_hi_277, decoded_andMatrixOutputs_lo_274)
node decoded_andMatrixOutputs_25_2_4 = andr(_decoded_andMatrixOutputs_T_277)
node decoded_andMatrixOutputs_andMatrixInput_0_278 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_278 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_278 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_275 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_275 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_275 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_275 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_275 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_274 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_268 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_268 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_268 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_268 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_268 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_268 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_188 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_188 = cat(decoded_andMatrixOutputs_andMatrixInput_14_268, decoded_andMatrixOutputs_andMatrixInput_15_188)
node decoded_andMatrixOutputs_lo_lo_hi_268 = cat(decoded_andMatrixOutputs_andMatrixInput_12_268, decoded_andMatrixOutputs_andMatrixInput_13_268)
node decoded_andMatrixOutputs_lo_lo_275 = cat(decoded_andMatrixOutputs_lo_lo_hi_268, decoded_andMatrixOutputs_lo_lo_lo_188)
node decoded_andMatrixOutputs_lo_hi_lo_268 = cat(decoded_andMatrixOutputs_andMatrixInput_10_268, decoded_andMatrixOutputs_andMatrixInput_11_268)
node decoded_andMatrixOutputs_lo_hi_hi_268 = cat(decoded_andMatrixOutputs_andMatrixInput_8_274, decoded_andMatrixOutputs_andMatrixInput_9_268)
node decoded_andMatrixOutputs_lo_hi_275 = cat(decoded_andMatrixOutputs_lo_hi_hi_268, decoded_andMatrixOutputs_lo_hi_lo_268)
node decoded_andMatrixOutputs_lo_275 = cat(decoded_andMatrixOutputs_lo_hi_275, decoded_andMatrixOutputs_lo_lo_275)
node decoded_andMatrixOutputs_hi_lo_lo_268 = cat(decoded_andMatrixOutputs_andMatrixInput_6_275, decoded_andMatrixOutputs_andMatrixInput_7_275)
node decoded_andMatrixOutputs_hi_lo_hi_268 = cat(decoded_andMatrixOutputs_andMatrixInput_4_275, decoded_andMatrixOutputs_andMatrixInput_5_275)
node decoded_andMatrixOutputs_hi_lo_275 = cat(decoded_andMatrixOutputs_hi_lo_hi_268, decoded_andMatrixOutputs_hi_lo_lo_268)
node decoded_andMatrixOutputs_hi_hi_lo_268 = cat(decoded_andMatrixOutputs_andMatrixInput_2_278, decoded_andMatrixOutputs_andMatrixInput_3_275)
node decoded_andMatrixOutputs_hi_hi_hi_274 = cat(decoded_andMatrixOutputs_andMatrixInput_0_278, decoded_andMatrixOutputs_andMatrixInput_1_278)
node decoded_andMatrixOutputs_hi_hi_275 = cat(decoded_andMatrixOutputs_hi_hi_hi_274, decoded_andMatrixOutputs_hi_hi_lo_268)
node decoded_andMatrixOutputs_hi_278 = cat(decoded_andMatrixOutputs_hi_hi_275, decoded_andMatrixOutputs_hi_lo_275)
node _decoded_andMatrixOutputs_T_278 = cat(decoded_andMatrixOutputs_hi_278, decoded_andMatrixOutputs_lo_275)
node decoded_andMatrixOutputs_60_2_1 = andr(_decoded_andMatrixOutputs_T_278)
node decoded_andMatrixOutputs_andMatrixInput_0_279 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_279 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_279 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_276 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_276 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_276 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_276 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_276 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_275 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_269 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_269 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_269 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_269 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_269 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_269 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_189 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_126 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_189 = cat(decoded_andMatrixOutputs_andMatrixInput_15_189, decoded_andMatrixOutputs_andMatrixInput_16_126)
node decoded_andMatrixOutputs_lo_lo_hi_269 = cat(decoded_andMatrixOutputs_andMatrixInput_13_269, decoded_andMatrixOutputs_andMatrixInput_14_269)
node decoded_andMatrixOutputs_lo_lo_276 = cat(decoded_andMatrixOutputs_lo_lo_hi_269, decoded_andMatrixOutputs_lo_lo_lo_189)
node decoded_andMatrixOutputs_lo_hi_lo_269 = cat(decoded_andMatrixOutputs_andMatrixInput_11_269, decoded_andMatrixOutputs_andMatrixInput_12_269)
node decoded_andMatrixOutputs_lo_hi_hi_269 = cat(decoded_andMatrixOutputs_andMatrixInput_9_269, decoded_andMatrixOutputs_andMatrixInput_10_269)
node decoded_andMatrixOutputs_lo_hi_276 = cat(decoded_andMatrixOutputs_lo_hi_hi_269, decoded_andMatrixOutputs_lo_hi_lo_269)
node decoded_andMatrixOutputs_lo_276 = cat(decoded_andMatrixOutputs_lo_hi_276, decoded_andMatrixOutputs_lo_lo_276)
node decoded_andMatrixOutputs_hi_lo_lo_269 = cat(decoded_andMatrixOutputs_andMatrixInput_7_276, decoded_andMatrixOutputs_andMatrixInput_8_275)
node decoded_andMatrixOutputs_hi_lo_hi_269 = cat(decoded_andMatrixOutputs_andMatrixInput_5_276, decoded_andMatrixOutputs_andMatrixInput_6_276)
node decoded_andMatrixOutputs_hi_lo_276 = cat(decoded_andMatrixOutputs_hi_lo_hi_269, decoded_andMatrixOutputs_hi_lo_lo_269)
node decoded_andMatrixOutputs_hi_hi_lo_269 = cat(decoded_andMatrixOutputs_andMatrixInput_3_276, decoded_andMatrixOutputs_andMatrixInput_4_276)
node decoded_andMatrixOutputs_hi_hi_hi_hi_126 = cat(decoded_andMatrixOutputs_andMatrixInput_0_279, decoded_andMatrixOutputs_andMatrixInput_1_279)
node decoded_andMatrixOutputs_hi_hi_hi_275 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_126, decoded_andMatrixOutputs_andMatrixInput_2_279)
node decoded_andMatrixOutputs_hi_hi_276 = cat(decoded_andMatrixOutputs_hi_hi_hi_275, decoded_andMatrixOutputs_hi_hi_lo_269)
node decoded_andMatrixOutputs_hi_279 = cat(decoded_andMatrixOutputs_hi_hi_276, decoded_andMatrixOutputs_hi_lo_276)
node _decoded_andMatrixOutputs_T_279 = cat(decoded_andMatrixOutputs_hi_279, decoded_andMatrixOutputs_lo_276)
node decoded_andMatrixOutputs_6_2_4 = andr(_decoded_andMatrixOutputs_T_279)
node decoded_andMatrixOutputs_andMatrixInput_0_280 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_280 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_280 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_277 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_277 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_277 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_277 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_277 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_276 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_270 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_270 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_270 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_270 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_270 = bits(decoded_plaInput_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_270 = bits(decoded_plaInput_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_190 = bits(decoded_invInputs_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_127 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_190 = cat(decoded_andMatrixOutputs_andMatrixInput_15_190, decoded_andMatrixOutputs_andMatrixInput_16_127)
node decoded_andMatrixOutputs_lo_lo_hi_270 = cat(decoded_andMatrixOutputs_andMatrixInput_13_270, decoded_andMatrixOutputs_andMatrixInput_14_270)
node decoded_andMatrixOutputs_lo_lo_277 = cat(decoded_andMatrixOutputs_lo_lo_hi_270, decoded_andMatrixOutputs_lo_lo_lo_190)
node decoded_andMatrixOutputs_lo_hi_lo_270 = cat(decoded_andMatrixOutputs_andMatrixInput_11_270, decoded_andMatrixOutputs_andMatrixInput_12_270)
node decoded_andMatrixOutputs_lo_hi_hi_270 = cat(decoded_andMatrixOutputs_andMatrixInput_9_270, decoded_andMatrixOutputs_andMatrixInput_10_270)
node decoded_andMatrixOutputs_lo_hi_277 = cat(decoded_andMatrixOutputs_lo_hi_hi_270, decoded_andMatrixOutputs_lo_hi_lo_270)
node decoded_andMatrixOutputs_lo_277 = cat(decoded_andMatrixOutputs_lo_hi_277, decoded_andMatrixOutputs_lo_lo_277)
node decoded_andMatrixOutputs_hi_lo_lo_270 = cat(decoded_andMatrixOutputs_andMatrixInput_7_277, decoded_andMatrixOutputs_andMatrixInput_8_276)
node decoded_andMatrixOutputs_hi_lo_hi_270 = cat(decoded_andMatrixOutputs_andMatrixInput_5_277, decoded_andMatrixOutputs_andMatrixInput_6_277)
node decoded_andMatrixOutputs_hi_lo_277 = cat(decoded_andMatrixOutputs_hi_lo_hi_270, decoded_andMatrixOutputs_hi_lo_lo_270)
node decoded_andMatrixOutputs_hi_hi_lo_270 = cat(decoded_andMatrixOutputs_andMatrixInput_3_277, decoded_andMatrixOutputs_andMatrixInput_4_277)
node decoded_andMatrixOutputs_hi_hi_hi_hi_127 = cat(decoded_andMatrixOutputs_andMatrixInput_0_280, decoded_andMatrixOutputs_andMatrixInput_1_280)
node decoded_andMatrixOutputs_hi_hi_hi_276 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_127, decoded_andMatrixOutputs_andMatrixInput_2_280)
node decoded_andMatrixOutputs_hi_hi_277 = cat(decoded_andMatrixOutputs_hi_hi_hi_276, decoded_andMatrixOutputs_hi_hi_lo_270)
node decoded_andMatrixOutputs_hi_280 = cat(decoded_andMatrixOutputs_hi_hi_277, decoded_andMatrixOutputs_hi_lo_277)
node _decoded_andMatrixOutputs_T_280 = cat(decoded_andMatrixOutputs_hi_280, decoded_andMatrixOutputs_lo_277)
node decoded_andMatrixOutputs_16_2_4 = andr(_decoded_andMatrixOutputs_T_280)
node decoded_andMatrixOutputs_andMatrixInput_0_281 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_281 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_281 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_278 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_278 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_278 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_278 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_278 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_277 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_271 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_271 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_271 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_271 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_271 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_271 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_191 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_191 = cat(decoded_andMatrixOutputs_andMatrixInput_14_271, decoded_andMatrixOutputs_andMatrixInput_15_191)
node decoded_andMatrixOutputs_lo_lo_hi_271 = cat(decoded_andMatrixOutputs_andMatrixInput_12_271, decoded_andMatrixOutputs_andMatrixInput_13_271)
node decoded_andMatrixOutputs_lo_lo_278 = cat(decoded_andMatrixOutputs_lo_lo_hi_271, decoded_andMatrixOutputs_lo_lo_lo_191)
node decoded_andMatrixOutputs_lo_hi_lo_271 = cat(decoded_andMatrixOutputs_andMatrixInput_10_271, decoded_andMatrixOutputs_andMatrixInput_11_271)
node decoded_andMatrixOutputs_lo_hi_hi_271 = cat(decoded_andMatrixOutputs_andMatrixInput_8_277, decoded_andMatrixOutputs_andMatrixInput_9_271)
node decoded_andMatrixOutputs_lo_hi_278 = cat(decoded_andMatrixOutputs_lo_hi_hi_271, decoded_andMatrixOutputs_lo_hi_lo_271)
node decoded_andMatrixOutputs_lo_278 = cat(decoded_andMatrixOutputs_lo_hi_278, decoded_andMatrixOutputs_lo_lo_278)
node decoded_andMatrixOutputs_hi_lo_lo_271 = cat(decoded_andMatrixOutputs_andMatrixInput_6_278, decoded_andMatrixOutputs_andMatrixInput_7_278)
node decoded_andMatrixOutputs_hi_lo_hi_271 = cat(decoded_andMatrixOutputs_andMatrixInput_4_278, decoded_andMatrixOutputs_andMatrixInput_5_278)
node decoded_andMatrixOutputs_hi_lo_278 = cat(decoded_andMatrixOutputs_hi_lo_hi_271, decoded_andMatrixOutputs_hi_lo_lo_271)
node decoded_andMatrixOutputs_hi_hi_lo_271 = cat(decoded_andMatrixOutputs_andMatrixInput_2_281, decoded_andMatrixOutputs_andMatrixInput_3_278)
node decoded_andMatrixOutputs_hi_hi_hi_277 = cat(decoded_andMatrixOutputs_andMatrixInput_0_281, decoded_andMatrixOutputs_andMatrixInput_1_281)
node decoded_andMatrixOutputs_hi_hi_278 = cat(decoded_andMatrixOutputs_hi_hi_hi_277, decoded_andMatrixOutputs_hi_hi_lo_271)
node decoded_andMatrixOutputs_hi_281 = cat(decoded_andMatrixOutputs_hi_hi_278, decoded_andMatrixOutputs_hi_lo_278)
node _decoded_andMatrixOutputs_T_281 = cat(decoded_andMatrixOutputs_hi_281, decoded_andMatrixOutputs_lo_278)
node decoded_andMatrixOutputs_19_2_4 = andr(_decoded_andMatrixOutputs_T_281)
node decoded_andMatrixOutputs_andMatrixInput_0_282 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_282 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_282 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_279 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_279 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_279 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_279 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_279 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_278 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_272 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_272 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_272 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_272 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_272 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_272 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_192 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_192 = cat(decoded_andMatrixOutputs_andMatrixInput_14_272, decoded_andMatrixOutputs_andMatrixInput_15_192)
node decoded_andMatrixOutputs_lo_lo_hi_272 = cat(decoded_andMatrixOutputs_andMatrixInput_12_272, decoded_andMatrixOutputs_andMatrixInput_13_272)
node decoded_andMatrixOutputs_lo_lo_279 = cat(decoded_andMatrixOutputs_lo_lo_hi_272, decoded_andMatrixOutputs_lo_lo_lo_192)
node decoded_andMatrixOutputs_lo_hi_lo_272 = cat(decoded_andMatrixOutputs_andMatrixInput_10_272, decoded_andMatrixOutputs_andMatrixInput_11_272)
node decoded_andMatrixOutputs_lo_hi_hi_272 = cat(decoded_andMatrixOutputs_andMatrixInput_8_278, decoded_andMatrixOutputs_andMatrixInput_9_272)
node decoded_andMatrixOutputs_lo_hi_279 = cat(decoded_andMatrixOutputs_lo_hi_hi_272, decoded_andMatrixOutputs_lo_hi_lo_272)
node decoded_andMatrixOutputs_lo_279 = cat(decoded_andMatrixOutputs_lo_hi_279, decoded_andMatrixOutputs_lo_lo_279)
node decoded_andMatrixOutputs_hi_lo_lo_272 = cat(decoded_andMatrixOutputs_andMatrixInput_6_279, decoded_andMatrixOutputs_andMatrixInput_7_279)
node decoded_andMatrixOutputs_hi_lo_hi_272 = cat(decoded_andMatrixOutputs_andMatrixInput_4_279, decoded_andMatrixOutputs_andMatrixInput_5_279)
node decoded_andMatrixOutputs_hi_lo_279 = cat(decoded_andMatrixOutputs_hi_lo_hi_272, decoded_andMatrixOutputs_hi_lo_lo_272)
node decoded_andMatrixOutputs_hi_hi_lo_272 = cat(decoded_andMatrixOutputs_andMatrixInput_2_282, decoded_andMatrixOutputs_andMatrixInput_3_279)
node decoded_andMatrixOutputs_hi_hi_hi_278 = cat(decoded_andMatrixOutputs_andMatrixInput_0_282, decoded_andMatrixOutputs_andMatrixInput_1_282)
node decoded_andMatrixOutputs_hi_hi_279 = cat(decoded_andMatrixOutputs_hi_hi_hi_278, decoded_andMatrixOutputs_hi_hi_lo_272)
node decoded_andMatrixOutputs_hi_282 = cat(decoded_andMatrixOutputs_hi_hi_279, decoded_andMatrixOutputs_hi_lo_279)
node _decoded_andMatrixOutputs_T_282 = cat(decoded_andMatrixOutputs_hi_282, decoded_andMatrixOutputs_lo_279)
node decoded_andMatrixOutputs_11_2_4 = andr(_decoded_andMatrixOutputs_T_282)
node decoded_andMatrixOutputs_andMatrixInput_0_283 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_283 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_283 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_280 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_280 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_280 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_280 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_280 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_279 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_273 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_273 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_273 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_273 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_273 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_273 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_193 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_128 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_193 = cat(decoded_andMatrixOutputs_andMatrixInput_15_193, decoded_andMatrixOutputs_andMatrixInput_16_128)
node decoded_andMatrixOutputs_lo_lo_hi_273 = cat(decoded_andMatrixOutputs_andMatrixInput_13_273, decoded_andMatrixOutputs_andMatrixInput_14_273)
node decoded_andMatrixOutputs_lo_lo_280 = cat(decoded_andMatrixOutputs_lo_lo_hi_273, decoded_andMatrixOutputs_lo_lo_lo_193)
node decoded_andMatrixOutputs_lo_hi_lo_273 = cat(decoded_andMatrixOutputs_andMatrixInput_11_273, decoded_andMatrixOutputs_andMatrixInput_12_273)
node decoded_andMatrixOutputs_lo_hi_hi_273 = cat(decoded_andMatrixOutputs_andMatrixInput_9_273, decoded_andMatrixOutputs_andMatrixInput_10_273)
node decoded_andMatrixOutputs_lo_hi_280 = cat(decoded_andMatrixOutputs_lo_hi_hi_273, decoded_andMatrixOutputs_lo_hi_lo_273)
node decoded_andMatrixOutputs_lo_280 = cat(decoded_andMatrixOutputs_lo_hi_280, decoded_andMatrixOutputs_lo_lo_280)
node decoded_andMatrixOutputs_hi_lo_lo_273 = cat(decoded_andMatrixOutputs_andMatrixInput_7_280, decoded_andMatrixOutputs_andMatrixInput_8_279)
node decoded_andMatrixOutputs_hi_lo_hi_273 = cat(decoded_andMatrixOutputs_andMatrixInput_5_280, decoded_andMatrixOutputs_andMatrixInput_6_280)
node decoded_andMatrixOutputs_hi_lo_280 = cat(decoded_andMatrixOutputs_hi_lo_hi_273, decoded_andMatrixOutputs_hi_lo_lo_273)
node decoded_andMatrixOutputs_hi_hi_lo_273 = cat(decoded_andMatrixOutputs_andMatrixInput_3_280, decoded_andMatrixOutputs_andMatrixInput_4_280)
node decoded_andMatrixOutputs_hi_hi_hi_hi_128 = cat(decoded_andMatrixOutputs_andMatrixInput_0_283, decoded_andMatrixOutputs_andMatrixInput_1_283)
node decoded_andMatrixOutputs_hi_hi_hi_279 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_128, decoded_andMatrixOutputs_andMatrixInput_2_283)
node decoded_andMatrixOutputs_hi_hi_280 = cat(decoded_andMatrixOutputs_hi_hi_hi_279, decoded_andMatrixOutputs_hi_hi_lo_273)
node decoded_andMatrixOutputs_hi_283 = cat(decoded_andMatrixOutputs_hi_hi_280, decoded_andMatrixOutputs_hi_lo_280)
node _decoded_andMatrixOutputs_T_283 = cat(decoded_andMatrixOutputs_hi_283, decoded_andMatrixOutputs_lo_280)
node decoded_andMatrixOutputs_20_2_4 = andr(_decoded_andMatrixOutputs_T_283)
node decoded_andMatrixOutputs_andMatrixInput_0_284 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_284 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_284 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_281 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_281 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_281 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_281 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_281 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_280 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_274 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_274 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_274 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_274 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_274 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_274 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_194 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_129 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_194 = cat(decoded_andMatrixOutputs_andMatrixInput_15_194, decoded_andMatrixOutputs_andMatrixInput_16_129)
node decoded_andMatrixOutputs_lo_lo_hi_274 = cat(decoded_andMatrixOutputs_andMatrixInput_13_274, decoded_andMatrixOutputs_andMatrixInput_14_274)
node decoded_andMatrixOutputs_lo_lo_281 = cat(decoded_andMatrixOutputs_lo_lo_hi_274, decoded_andMatrixOutputs_lo_lo_lo_194)
node decoded_andMatrixOutputs_lo_hi_lo_274 = cat(decoded_andMatrixOutputs_andMatrixInput_11_274, decoded_andMatrixOutputs_andMatrixInput_12_274)
node decoded_andMatrixOutputs_lo_hi_hi_274 = cat(decoded_andMatrixOutputs_andMatrixInput_9_274, decoded_andMatrixOutputs_andMatrixInput_10_274)
node decoded_andMatrixOutputs_lo_hi_281 = cat(decoded_andMatrixOutputs_lo_hi_hi_274, decoded_andMatrixOutputs_lo_hi_lo_274)
node decoded_andMatrixOutputs_lo_281 = cat(decoded_andMatrixOutputs_lo_hi_281, decoded_andMatrixOutputs_lo_lo_281)
node decoded_andMatrixOutputs_hi_lo_lo_274 = cat(decoded_andMatrixOutputs_andMatrixInput_7_281, decoded_andMatrixOutputs_andMatrixInput_8_280)
node decoded_andMatrixOutputs_hi_lo_hi_274 = cat(decoded_andMatrixOutputs_andMatrixInput_5_281, decoded_andMatrixOutputs_andMatrixInput_6_281)
node decoded_andMatrixOutputs_hi_lo_281 = cat(decoded_andMatrixOutputs_hi_lo_hi_274, decoded_andMatrixOutputs_hi_lo_lo_274)
node decoded_andMatrixOutputs_hi_hi_lo_274 = cat(decoded_andMatrixOutputs_andMatrixInput_3_281, decoded_andMatrixOutputs_andMatrixInput_4_281)
node decoded_andMatrixOutputs_hi_hi_hi_hi_129 = cat(decoded_andMatrixOutputs_andMatrixInput_0_284, decoded_andMatrixOutputs_andMatrixInput_1_284)
node decoded_andMatrixOutputs_hi_hi_hi_280 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_129, decoded_andMatrixOutputs_andMatrixInput_2_284)
node decoded_andMatrixOutputs_hi_hi_281 = cat(decoded_andMatrixOutputs_hi_hi_hi_280, decoded_andMatrixOutputs_hi_hi_lo_274)
node decoded_andMatrixOutputs_hi_284 = cat(decoded_andMatrixOutputs_hi_hi_281, decoded_andMatrixOutputs_hi_lo_281)
node _decoded_andMatrixOutputs_T_284 = cat(decoded_andMatrixOutputs_hi_284, decoded_andMatrixOutputs_lo_281)
node decoded_andMatrixOutputs_46_2_3 = andr(_decoded_andMatrixOutputs_T_284)
node decoded_andMatrixOutputs_andMatrixInput_0_285 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_285 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_285 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_282 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_282 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_282 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_282 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_282 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_281 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_275 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_275 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_275 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_275 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_275 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_275 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_195 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_195 = cat(decoded_andMatrixOutputs_andMatrixInput_14_275, decoded_andMatrixOutputs_andMatrixInput_15_195)
node decoded_andMatrixOutputs_lo_lo_hi_275 = cat(decoded_andMatrixOutputs_andMatrixInput_12_275, decoded_andMatrixOutputs_andMatrixInput_13_275)
node decoded_andMatrixOutputs_lo_lo_282 = cat(decoded_andMatrixOutputs_lo_lo_hi_275, decoded_andMatrixOutputs_lo_lo_lo_195)
node decoded_andMatrixOutputs_lo_hi_lo_275 = cat(decoded_andMatrixOutputs_andMatrixInput_10_275, decoded_andMatrixOutputs_andMatrixInput_11_275)
node decoded_andMatrixOutputs_lo_hi_hi_275 = cat(decoded_andMatrixOutputs_andMatrixInput_8_281, decoded_andMatrixOutputs_andMatrixInput_9_275)
node decoded_andMatrixOutputs_lo_hi_282 = cat(decoded_andMatrixOutputs_lo_hi_hi_275, decoded_andMatrixOutputs_lo_hi_lo_275)
node decoded_andMatrixOutputs_lo_282 = cat(decoded_andMatrixOutputs_lo_hi_282, decoded_andMatrixOutputs_lo_lo_282)
node decoded_andMatrixOutputs_hi_lo_lo_275 = cat(decoded_andMatrixOutputs_andMatrixInput_6_282, decoded_andMatrixOutputs_andMatrixInput_7_282)
node decoded_andMatrixOutputs_hi_lo_hi_275 = cat(decoded_andMatrixOutputs_andMatrixInput_4_282, decoded_andMatrixOutputs_andMatrixInput_5_282)
node decoded_andMatrixOutputs_hi_lo_282 = cat(decoded_andMatrixOutputs_hi_lo_hi_275, decoded_andMatrixOutputs_hi_lo_lo_275)
node decoded_andMatrixOutputs_hi_hi_lo_275 = cat(decoded_andMatrixOutputs_andMatrixInput_2_285, decoded_andMatrixOutputs_andMatrixInput_3_282)
node decoded_andMatrixOutputs_hi_hi_hi_281 = cat(decoded_andMatrixOutputs_andMatrixInput_0_285, decoded_andMatrixOutputs_andMatrixInput_1_285)
node decoded_andMatrixOutputs_hi_hi_282 = cat(decoded_andMatrixOutputs_hi_hi_hi_281, decoded_andMatrixOutputs_hi_hi_lo_275)
node decoded_andMatrixOutputs_hi_285 = cat(decoded_andMatrixOutputs_hi_hi_282, decoded_andMatrixOutputs_hi_lo_282)
node _decoded_andMatrixOutputs_T_285 = cat(decoded_andMatrixOutputs_hi_285, decoded_andMatrixOutputs_lo_282)
node decoded_andMatrixOutputs_41_2_4 = andr(_decoded_andMatrixOutputs_T_285)
node decoded_andMatrixOutputs_andMatrixInput_0_286 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_286 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_286 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_283 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_283 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_283 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_283 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_283 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_282 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_276 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_276 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_276 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_276 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_276 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_276 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_196 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_196 = cat(decoded_andMatrixOutputs_andMatrixInput_14_276, decoded_andMatrixOutputs_andMatrixInput_15_196)
node decoded_andMatrixOutputs_lo_lo_hi_276 = cat(decoded_andMatrixOutputs_andMatrixInput_12_276, decoded_andMatrixOutputs_andMatrixInput_13_276)
node decoded_andMatrixOutputs_lo_lo_283 = cat(decoded_andMatrixOutputs_lo_lo_hi_276, decoded_andMatrixOutputs_lo_lo_lo_196)
node decoded_andMatrixOutputs_lo_hi_lo_276 = cat(decoded_andMatrixOutputs_andMatrixInput_10_276, decoded_andMatrixOutputs_andMatrixInput_11_276)
node decoded_andMatrixOutputs_lo_hi_hi_276 = cat(decoded_andMatrixOutputs_andMatrixInput_8_282, decoded_andMatrixOutputs_andMatrixInput_9_276)
node decoded_andMatrixOutputs_lo_hi_283 = cat(decoded_andMatrixOutputs_lo_hi_hi_276, decoded_andMatrixOutputs_lo_hi_lo_276)
node decoded_andMatrixOutputs_lo_283 = cat(decoded_andMatrixOutputs_lo_hi_283, decoded_andMatrixOutputs_lo_lo_283)
node decoded_andMatrixOutputs_hi_lo_lo_276 = cat(decoded_andMatrixOutputs_andMatrixInput_6_283, decoded_andMatrixOutputs_andMatrixInput_7_283)
node decoded_andMatrixOutputs_hi_lo_hi_276 = cat(decoded_andMatrixOutputs_andMatrixInput_4_283, decoded_andMatrixOutputs_andMatrixInput_5_283)
node decoded_andMatrixOutputs_hi_lo_283 = cat(decoded_andMatrixOutputs_hi_lo_hi_276, decoded_andMatrixOutputs_hi_lo_lo_276)
node decoded_andMatrixOutputs_hi_hi_lo_276 = cat(decoded_andMatrixOutputs_andMatrixInput_2_286, decoded_andMatrixOutputs_andMatrixInput_3_283)
node decoded_andMatrixOutputs_hi_hi_hi_282 = cat(decoded_andMatrixOutputs_andMatrixInput_0_286, decoded_andMatrixOutputs_andMatrixInput_1_286)
node decoded_andMatrixOutputs_hi_hi_283 = cat(decoded_andMatrixOutputs_hi_hi_hi_282, decoded_andMatrixOutputs_hi_hi_lo_276)
node decoded_andMatrixOutputs_hi_286 = cat(decoded_andMatrixOutputs_hi_hi_283, decoded_andMatrixOutputs_hi_lo_283)
node _decoded_andMatrixOutputs_T_286 = cat(decoded_andMatrixOutputs_hi_286, decoded_andMatrixOutputs_lo_283)
node decoded_andMatrixOutputs_62_2_1 = andr(_decoded_andMatrixOutputs_T_286)
node decoded_andMatrixOutputs_andMatrixInput_0_287 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_287 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_287 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_284 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_284 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_284 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_284 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_284 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_283 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_277 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_277 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_277 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_277 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_277 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_277 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_197 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_197 = cat(decoded_andMatrixOutputs_andMatrixInput_14_277, decoded_andMatrixOutputs_andMatrixInput_15_197)
node decoded_andMatrixOutputs_lo_lo_hi_277 = cat(decoded_andMatrixOutputs_andMatrixInput_12_277, decoded_andMatrixOutputs_andMatrixInput_13_277)
node decoded_andMatrixOutputs_lo_lo_284 = cat(decoded_andMatrixOutputs_lo_lo_hi_277, decoded_andMatrixOutputs_lo_lo_lo_197)
node decoded_andMatrixOutputs_lo_hi_lo_277 = cat(decoded_andMatrixOutputs_andMatrixInput_10_277, decoded_andMatrixOutputs_andMatrixInput_11_277)
node decoded_andMatrixOutputs_lo_hi_hi_277 = cat(decoded_andMatrixOutputs_andMatrixInput_8_283, decoded_andMatrixOutputs_andMatrixInput_9_277)
node decoded_andMatrixOutputs_lo_hi_284 = cat(decoded_andMatrixOutputs_lo_hi_hi_277, decoded_andMatrixOutputs_lo_hi_lo_277)
node decoded_andMatrixOutputs_lo_284 = cat(decoded_andMatrixOutputs_lo_hi_284, decoded_andMatrixOutputs_lo_lo_284)
node decoded_andMatrixOutputs_hi_lo_lo_277 = cat(decoded_andMatrixOutputs_andMatrixInput_6_284, decoded_andMatrixOutputs_andMatrixInput_7_284)
node decoded_andMatrixOutputs_hi_lo_hi_277 = cat(decoded_andMatrixOutputs_andMatrixInput_4_284, decoded_andMatrixOutputs_andMatrixInput_5_284)
node decoded_andMatrixOutputs_hi_lo_284 = cat(decoded_andMatrixOutputs_hi_lo_hi_277, decoded_andMatrixOutputs_hi_lo_lo_277)
node decoded_andMatrixOutputs_hi_hi_lo_277 = cat(decoded_andMatrixOutputs_andMatrixInput_2_287, decoded_andMatrixOutputs_andMatrixInput_3_284)
node decoded_andMatrixOutputs_hi_hi_hi_283 = cat(decoded_andMatrixOutputs_andMatrixInput_0_287, decoded_andMatrixOutputs_andMatrixInput_1_287)
node decoded_andMatrixOutputs_hi_hi_284 = cat(decoded_andMatrixOutputs_hi_hi_hi_283, decoded_andMatrixOutputs_hi_hi_lo_277)
node decoded_andMatrixOutputs_hi_287 = cat(decoded_andMatrixOutputs_hi_hi_284, decoded_andMatrixOutputs_hi_lo_284)
node _decoded_andMatrixOutputs_T_287 = cat(decoded_andMatrixOutputs_hi_287, decoded_andMatrixOutputs_lo_284)
node decoded_andMatrixOutputs_68_2_1 = andr(_decoded_andMatrixOutputs_T_287)
node decoded_andMatrixOutputs_andMatrixInput_0_288 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_288 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_288 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_285 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_285 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_285 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_285 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_285 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_284 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_278 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_278 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_278 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_278 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_278 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_278 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_198 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_130 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_198 = cat(decoded_andMatrixOutputs_andMatrixInput_15_198, decoded_andMatrixOutputs_andMatrixInput_16_130)
node decoded_andMatrixOutputs_lo_lo_hi_278 = cat(decoded_andMatrixOutputs_andMatrixInput_13_278, decoded_andMatrixOutputs_andMatrixInput_14_278)
node decoded_andMatrixOutputs_lo_lo_285 = cat(decoded_andMatrixOutputs_lo_lo_hi_278, decoded_andMatrixOutputs_lo_lo_lo_198)
node decoded_andMatrixOutputs_lo_hi_lo_278 = cat(decoded_andMatrixOutputs_andMatrixInput_11_278, decoded_andMatrixOutputs_andMatrixInput_12_278)
node decoded_andMatrixOutputs_lo_hi_hi_278 = cat(decoded_andMatrixOutputs_andMatrixInput_9_278, decoded_andMatrixOutputs_andMatrixInput_10_278)
node decoded_andMatrixOutputs_lo_hi_285 = cat(decoded_andMatrixOutputs_lo_hi_hi_278, decoded_andMatrixOutputs_lo_hi_lo_278)
node decoded_andMatrixOutputs_lo_285 = cat(decoded_andMatrixOutputs_lo_hi_285, decoded_andMatrixOutputs_lo_lo_285)
node decoded_andMatrixOutputs_hi_lo_lo_278 = cat(decoded_andMatrixOutputs_andMatrixInput_7_285, decoded_andMatrixOutputs_andMatrixInput_8_284)
node decoded_andMatrixOutputs_hi_lo_hi_278 = cat(decoded_andMatrixOutputs_andMatrixInput_5_285, decoded_andMatrixOutputs_andMatrixInput_6_285)
node decoded_andMatrixOutputs_hi_lo_285 = cat(decoded_andMatrixOutputs_hi_lo_hi_278, decoded_andMatrixOutputs_hi_lo_lo_278)
node decoded_andMatrixOutputs_hi_hi_lo_278 = cat(decoded_andMatrixOutputs_andMatrixInput_3_285, decoded_andMatrixOutputs_andMatrixInput_4_285)
node decoded_andMatrixOutputs_hi_hi_hi_hi_130 = cat(decoded_andMatrixOutputs_andMatrixInput_0_288, decoded_andMatrixOutputs_andMatrixInput_1_288)
node decoded_andMatrixOutputs_hi_hi_hi_284 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_130, decoded_andMatrixOutputs_andMatrixInput_2_288)
node decoded_andMatrixOutputs_hi_hi_285 = cat(decoded_andMatrixOutputs_hi_hi_hi_284, decoded_andMatrixOutputs_hi_hi_lo_278)
node decoded_andMatrixOutputs_hi_288 = cat(decoded_andMatrixOutputs_hi_hi_285, decoded_andMatrixOutputs_hi_lo_285)
node _decoded_andMatrixOutputs_T_288 = cat(decoded_andMatrixOutputs_hi_288, decoded_andMatrixOutputs_lo_285)
node decoded_andMatrixOutputs_66_2_1 = andr(_decoded_andMatrixOutputs_T_288)
node decoded_andMatrixOutputs_andMatrixInput_0_289 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_289 = bits(decoded_invInputs_4, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_289 = bits(decoded_plaInput_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_3_286 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_4_286 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_5_286 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_6_286 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_7_286 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_8_285 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_9_279 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_10_279 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_11_279 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_12_279 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_13_279 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_14_279 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_15_199 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_16_131 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_199 = cat(decoded_andMatrixOutputs_andMatrixInput_15_199, decoded_andMatrixOutputs_andMatrixInput_16_131)
node decoded_andMatrixOutputs_lo_lo_hi_279 = cat(decoded_andMatrixOutputs_andMatrixInput_13_279, decoded_andMatrixOutputs_andMatrixInput_14_279)
node decoded_andMatrixOutputs_lo_lo_286 = cat(decoded_andMatrixOutputs_lo_lo_hi_279, decoded_andMatrixOutputs_lo_lo_lo_199)
node decoded_andMatrixOutputs_lo_hi_lo_279 = cat(decoded_andMatrixOutputs_andMatrixInput_11_279, decoded_andMatrixOutputs_andMatrixInput_12_279)
node decoded_andMatrixOutputs_lo_hi_hi_279 = cat(decoded_andMatrixOutputs_andMatrixInput_9_279, decoded_andMatrixOutputs_andMatrixInput_10_279)
node decoded_andMatrixOutputs_lo_hi_286 = cat(decoded_andMatrixOutputs_lo_hi_hi_279, decoded_andMatrixOutputs_lo_hi_lo_279)
node decoded_andMatrixOutputs_lo_286 = cat(decoded_andMatrixOutputs_lo_hi_286, decoded_andMatrixOutputs_lo_lo_286)
node decoded_andMatrixOutputs_hi_lo_lo_279 = cat(decoded_andMatrixOutputs_andMatrixInput_7_286, decoded_andMatrixOutputs_andMatrixInput_8_285)
node decoded_andMatrixOutputs_hi_lo_hi_279 = cat(decoded_andMatrixOutputs_andMatrixInput_5_286, decoded_andMatrixOutputs_andMatrixInput_6_286)
node decoded_andMatrixOutputs_hi_lo_286 = cat(decoded_andMatrixOutputs_hi_lo_hi_279, decoded_andMatrixOutputs_hi_lo_lo_279)
node decoded_andMatrixOutputs_hi_hi_lo_279 = cat(decoded_andMatrixOutputs_andMatrixInput_3_286, decoded_andMatrixOutputs_andMatrixInput_4_286)
node decoded_andMatrixOutputs_hi_hi_hi_hi_131 = cat(decoded_andMatrixOutputs_andMatrixInput_0_289, decoded_andMatrixOutputs_andMatrixInput_1_289)
node decoded_andMatrixOutputs_hi_hi_hi_285 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_131, decoded_andMatrixOutputs_andMatrixInput_2_289)
node decoded_andMatrixOutputs_hi_hi_286 = cat(decoded_andMatrixOutputs_hi_hi_hi_285, decoded_andMatrixOutputs_hi_hi_lo_279)
node decoded_andMatrixOutputs_hi_289 = cat(decoded_andMatrixOutputs_hi_hi_286, decoded_andMatrixOutputs_hi_lo_286)
node _decoded_andMatrixOutputs_T_289 = cat(decoded_andMatrixOutputs_hi_289, decoded_andMatrixOutputs_lo_286)
node decoded_andMatrixOutputs_22_2_4 = andr(_decoded_andMatrixOutputs_T_289)
node decoded_andMatrixOutputs_andMatrixInput_0_290 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_290 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_290 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_287 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_287 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_287 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_287 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_287 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_286 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_280 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_280 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_280 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_280 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_280 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_280 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_200 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_200 = cat(decoded_andMatrixOutputs_andMatrixInput_14_280, decoded_andMatrixOutputs_andMatrixInput_15_200)
node decoded_andMatrixOutputs_lo_lo_hi_280 = cat(decoded_andMatrixOutputs_andMatrixInput_12_280, decoded_andMatrixOutputs_andMatrixInput_13_280)
node decoded_andMatrixOutputs_lo_lo_287 = cat(decoded_andMatrixOutputs_lo_lo_hi_280, decoded_andMatrixOutputs_lo_lo_lo_200)
node decoded_andMatrixOutputs_lo_hi_lo_280 = cat(decoded_andMatrixOutputs_andMatrixInput_10_280, decoded_andMatrixOutputs_andMatrixInput_11_280)
node decoded_andMatrixOutputs_lo_hi_hi_280 = cat(decoded_andMatrixOutputs_andMatrixInput_8_286, decoded_andMatrixOutputs_andMatrixInput_9_280)
node decoded_andMatrixOutputs_lo_hi_287 = cat(decoded_andMatrixOutputs_lo_hi_hi_280, decoded_andMatrixOutputs_lo_hi_lo_280)
node decoded_andMatrixOutputs_lo_287 = cat(decoded_andMatrixOutputs_lo_hi_287, decoded_andMatrixOutputs_lo_lo_287)
node decoded_andMatrixOutputs_hi_lo_lo_280 = cat(decoded_andMatrixOutputs_andMatrixInput_6_287, decoded_andMatrixOutputs_andMatrixInput_7_287)
node decoded_andMatrixOutputs_hi_lo_hi_280 = cat(decoded_andMatrixOutputs_andMatrixInput_4_287, decoded_andMatrixOutputs_andMatrixInput_5_287)
node decoded_andMatrixOutputs_hi_lo_287 = cat(decoded_andMatrixOutputs_hi_lo_hi_280, decoded_andMatrixOutputs_hi_lo_lo_280)
node decoded_andMatrixOutputs_hi_hi_lo_280 = cat(decoded_andMatrixOutputs_andMatrixInput_2_290, decoded_andMatrixOutputs_andMatrixInput_3_287)
node decoded_andMatrixOutputs_hi_hi_hi_286 = cat(decoded_andMatrixOutputs_andMatrixInput_0_290, decoded_andMatrixOutputs_andMatrixInput_1_290)
node decoded_andMatrixOutputs_hi_hi_287 = cat(decoded_andMatrixOutputs_hi_hi_hi_286, decoded_andMatrixOutputs_hi_hi_lo_280)
node decoded_andMatrixOutputs_hi_290 = cat(decoded_andMatrixOutputs_hi_hi_287, decoded_andMatrixOutputs_hi_lo_287)
node _decoded_andMatrixOutputs_T_290 = cat(decoded_andMatrixOutputs_hi_290, decoded_andMatrixOutputs_lo_287)
node decoded_andMatrixOutputs_52_2_3 = andr(_decoded_andMatrixOutputs_T_290)
node decoded_andMatrixOutputs_andMatrixInput_0_291 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_291 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_291 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_288 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_288 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_288 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_288 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_288 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_287 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_281 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_281 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_281 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_281 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_281 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_281 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_201 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_132 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_201 = cat(decoded_andMatrixOutputs_andMatrixInput_15_201, decoded_andMatrixOutputs_andMatrixInput_16_132)
node decoded_andMatrixOutputs_lo_lo_hi_281 = cat(decoded_andMatrixOutputs_andMatrixInput_13_281, decoded_andMatrixOutputs_andMatrixInput_14_281)
node decoded_andMatrixOutputs_lo_lo_288 = cat(decoded_andMatrixOutputs_lo_lo_hi_281, decoded_andMatrixOutputs_lo_lo_lo_201)
node decoded_andMatrixOutputs_lo_hi_lo_281 = cat(decoded_andMatrixOutputs_andMatrixInput_11_281, decoded_andMatrixOutputs_andMatrixInput_12_281)
node decoded_andMatrixOutputs_lo_hi_hi_281 = cat(decoded_andMatrixOutputs_andMatrixInput_9_281, decoded_andMatrixOutputs_andMatrixInput_10_281)
node decoded_andMatrixOutputs_lo_hi_288 = cat(decoded_andMatrixOutputs_lo_hi_hi_281, decoded_andMatrixOutputs_lo_hi_lo_281)
node decoded_andMatrixOutputs_lo_288 = cat(decoded_andMatrixOutputs_lo_hi_288, decoded_andMatrixOutputs_lo_lo_288)
node decoded_andMatrixOutputs_hi_lo_lo_281 = cat(decoded_andMatrixOutputs_andMatrixInput_7_288, decoded_andMatrixOutputs_andMatrixInput_8_287)
node decoded_andMatrixOutputs_hi_lo_hi_281 = cat(decoded_andMatrixOutputs_andMatrixInput_5_288, decoded_andMatrixOutputs_andMatrixInput_6_288)
node decoded_andMatrixOutputs_hi_lo_288 = cat(decoded_andMatrixOutputs_hi_lo_hi_281, decoded_andMatrixOutputs_hi_lo_lo_281)
node decoded_andMatrixOutputs_hi_hi_lo_281 = cat(decoded_andMatrixOutputs_andMatrixInput_3_288, decoded_andMatrixOutputs_andMatrixInput_4_288)
node decoded_andMatrixOutputs_hi_hi_hi_hi_132 = cat(decoded_andMatrixOutputs_andMatrixInput_0_291, decoded_andMatrixOutputs_andMatrixInput_1_291)
node decoded_andMatrixOutputs_hi_hi_hi_287 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_132, decoded_andMatrixOutputs_andMatrixInput_2_291)
node decoded_andMatrixOutputs_hi_hi_288 = cat(decoded_andMatrixOutputs_hi_hi_hi_287, decoded_andMatrixOutputs_hi_hi_lo_281)
node decoded_andMatrixOutputs_hi_291 = cat(decoded_andMatrixOutputs_hi_hi_288, decoded_andMatrixOutputs_hi_lo_288)
node _decoded_andMatrixOutputs_T_291 = cat(decoded_andMatrixOutputs_hi_291, decoded_andMatrixOutputs_lo_288)
node decoded_andMatrixOutputs_29_2_4 = andr(_decoded_andMatrixOutputs_T_291)
node decoded_andMatrixOutputs_andMatrixInput_0_292 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_292 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_292 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_289 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_289 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_289 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_289 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_289 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_288 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_282 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_282 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_282 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_282 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_282 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_282 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_202 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_202 = cat(decoded_andMatrixOutputs_andMatrixInput_14_282, decoded_andMatrixOutputs_andMatrixInput_15_202)
node decoded_andMatrixOutputs_lo_lo_hi_282 = cat(decoded_andMatrixOutputs_andMatrixInput_12_282, decoded_andMatrixOutputs_andMatrixInput_13_282)
node decoded_andMatrixOutputs_lo_lo_289 = cat(decoded_andMatrixOutputs_lo_lo_hi_282, decoded_andMatrixOutputs_lo_lo_lo_202)
node decoded_andMatrixOutputs_lo_hi_lo_282 = cat(decoded_andMatrixOutputs_andMatrixInput_10_282, decoded_andMatrixOutputs_andMatrixInput_11_282)
node decoded_andMatrixOutputs_lo_hi_hi_282 = cat(decoded_andMatrixOutputs_andMatrixInput_8_288, decoded_andMatrixOutputs_andMatrixInput_9_282)
node decoded_andMatrixOutputs_lo_hi_289 = cat(decoded_andMatrixOutputs_lo_hi_hi_282, decoded_andMatrixOutputs_lo_hi_lo_282)
node decoded_andMatrixOutputs_lo_289 = cat(decoded_andMatrixOutputs_lo_hi_289, decoded_andMatrixOutputs_lo_lo_289)
node decoded_andMatrixOutputs_hi_lo_lo_282 = cat(decoded_andMatrixOutputs_andMatrixInput_6_289, decoded_andMatrixOutputs_andMatrixInput_7_289)
node decoded_andMatrixOutputs_hi_lo_hi_282 = cat(decoded_andMatrixOutputs_andMatrixInput_4_289, decoded_andMatrixOutputs_andMatrixInput_5_289)
node decoded_andMatrixOutputs_hi_lo_289 = cat(decoded_andMatrixOutputs_hi_lo_hi_282, decoded_andMatrixOutputs_hi_lo_lo_282)
node decoded_andMatrixOutputs_hi_hi_lo_282 = cat(decoded_andMatrixOutputs_andMatrixInput_2_292, decoded_andMatrixOutputs_andMatrixInput_3_289)
node decoded_andMatrixOutputs_hi_hi_hi_288 = cat(decoded_andMatrixOutputs_andMatrixInput_0_292, decoded_andMatrixOutputs_andMatrixInput_1_292)
node decoded_andMatrixOutputs_hi_hi_289 = cat(decoded_andMatrixOutputs_hi_hi_hi_288, decoded_andMatrixOutputs_hi_hi_lo_282)
node decoded_andMatrixOutputs_hi_292 = cat(decoded_andMatrixOutputs_hi_hi_289, decoded_andMatrixOutputs_hi_lo_289)
node _decoded_andMatrixOutputs_T_292 = cat(decoded_andMatrixOutputs_hi_292, decoded_andMatrixOutputs_lo_289)
node decoded_andMatrixOutputs_33_2_4 = andr(_decoded_andMatrixOutputs_T_292)
node decoded_andMatrixOutputs_andMatrixInput_0_293 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_293 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_293 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_290 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_290 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_290 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_290 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_290 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_289 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_283 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_283 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_283 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_283 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_283 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_283 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_15_203 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_203 = cat(decoded_andMatrixOutputs_andMatrixInput_14_283, decoded_andMatrixOutputs_andMatrixInput_15_203)
node decoded_andMatrixOutputs_lo_lo_hi_283 = cat(decoded_andMatrixOutputs_andMatrixInput_12_283, decoded_andMatrixOutputs_andMatrixInput_13_283)
node decoded_andMatrixOutputs_lo_lo_290 = cat(decoded_andMatrixOutputs_lo_lo_hi_283, decoded_andMatrixOutputs_lo_lo_lo_203)
node decoded_andMatrixOutputs_lo_hi_lo_283 = cat(decoded_andMatrixOutputs_andMatrixInput_10_283, decoded_andMatrixOutputs_andMatrixInput_11_283)
node decoded_andMatrixOutputs_lo_hi_hi_283 = cat(decoded_andMatrixOutputs_andMatrixInput_8_289, decoded_andMatrixOutputs_andMatrixInput_9_283)
node decoded_andMatrixOutputs_lo_hi_290 = cat(decoded_andMatrixOutputs_lo_hi_hi_283, decoded_andMatrixOutputs_lo_hi_lo_283)
node decoded_andMatrixOutputs_lo_290 = cat(decoded_andMatrixOutputs_lo_hi_290, decoded_andMatrixOutputs_lo_lo_290)
node decoded_andMatrixOutputs_hi_lo_lo_283 = cat(decoded_andMatrixOutputs_andMatrixInput_6_290, decoded_andMatrixOutputs_andMatrixInput_7_290)
node decoded_andMatrixOutputs_hi_lo_hi_283 = cat(decoded_andMatrixOutputs_andMatrixInput_4_290, decoded_andMatrixOutputs_andMatrixInput_5_290)
node decoded_andMatrixOutputs_hi_lo_290 = cat(decoded_andMatrixOutputs_hi_lo_hi_283, decoded_andMatrixOutputs_hi_lo_lo_283)
node decoded_andMatrixOutputs_hi_hi_lo_283 = cat(decoded_andMatrixOutputs_andMatrixInput_2_293, decoded_andMatrixOutputs_andMatrixInput_3_290)
node decoded_andMatrixOutputs_hi_hi_hi_289 = cat(decoded_andMatrixOutputs_andMatrixInput_0_293, decoded_andMatrixOutputs_andMatrixInput_1_293)
node decoded_andMatrixOutputs_hi_hi_290 = cat(decoded_andMatrixOutputs_hi_hi_hi_289, decoded_andMatrixOutputs_hi_hi_lo_283)
node decoded_andMatrixOutputs_hi_293 = cat(decoded_andMatrixOutputs_hi_hi_290, decoded_andMatrixOutputs_hi_lo_290)
node _decoded_andMatrixOutputs_T_293 = cat(decoded_andMatrixOutputs_hi_293, decoded_andMatrixOutputs_lo_290)
node decoded_andMatrixOutputs_1_2_4 = andr(_decoded_andMatrixOutputs_T_293)
node decoded_andMatrixOutputs_andMatrixInput_0_294 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_294 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_294 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_291 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_291 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_291 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_291 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_291 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_290 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_284 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_284 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_284 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_284 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_284 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_284 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_204 = bits(decoded_plaInput_4, 17, 17)
node decoded_andMatrixOutputs_andMatrixInput_16_133 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_204 = cat(decoded_andMatrixOutputs_andMatrixInput_15_204, decoded_andMatrixOutputs_andMatrixInput_16_133)
node decoded_andMatrixOutputs_lo_lo_hi_284 = cat(decoded_andMatrixOutputs_andMatrixInput_13_284, decoded_andMatrixOutputs_andMatrixInput_14_284)
node decoded_andMatrixOutputs_lo_lo_291 = cat(decoded_andMatrixOutputs_lo_lo_hi_284, decoded_andMatrixOutputs_lo_lo_lo_204)
node decoded_andMatrixOutputs_lo_hi_lo_284 = cat(decoded_andMatrixOutputs_andMatrixInput_11_284, decoded_andMatrixOutputs_andMatrixInput_12_284)
node decoded_andMatrixOutputs_lo_hi_hi_284 = cat(decoded_andMatrixOutputs_andMatrixInput_9_284, decoded_andMatrixOutputs_andMatrixInput_10_284)
node decoded_andMatrixOutputs_lo_hi_291 = cat(decoded_andMatrixOutputs_lo_hi_hi_284, decoded_andMatrixOutputs_lo_hi_lo_284)
node decoded_andMatrixOutputs_lo_291 = cat(decoded_andMatrixOutputs_lo_hi_291, decoded_andMatrixOutputs_lo_lo_291)
node decoded_andMatrixOutputs_hi_lo_lo_284 = cat(decoded_andMatrixOutputs_andMatrixInput_7_291, decoded_andMatrixOutputs_andMatrixInput_8_290)
node decoded_andMatrixOutputs_hi_lo_hi_284 = cat(decoded_andMatrixOutputs_andMatrixInput_5_291, decoded_andMatrixOutputs_andMatrixInput_6_291)
node decoded_andMatrixOutputs_hi_lo_291 = cat(decoded_andMatrixOutputs_hi_lo_hi_284, decoded_andMatrixOutputs_hi_lo_lo_284)
node decoded_andMatrixOutputs_hi_hi_lo_284 = cat(decoded_andMatrixOutputs_andMatrixInput_3_291, decoded_andMatrixOutputs_andMatrixInput_4_291)
node decoded_andMatrixOutputs_hi_hi_hi_hi_133 = cat(decoded_andMatrixOutputs_andMatrixInput_0_294, decoded_andMatrixOutputs_andMatrixInput_1_294)
node decoded_andMatrixOutputs_hi_hi_hi_290 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_133, decoded_andMatrixOutputs_andMatrixInput_2_294)
node decoded_andMatrixOutputs_hi_hi_291 = cat(decoded_andMatrixOutputs_hi_hi_hi_290, decoded_andMatrixOutputs_hi_hi_lo_284)
node decoded_andMatrixOutputs_hi_294 = cat(decoded_andMatrixOutputs_hi_hi_291, decoded_andMatrixOutputs_hi_lo_291)
node _decoded_andMatrixOutputs_T_294 = cat(decoded_andMatrixOutputs_hi_294, decoded_andMatrixOutputs_lo_291)
node decoded_andMatrixOutputs_49_2_3 = andr(_decoded_andMatrixOutputs_T_294)
node decoded_andMatrixOutputs_andMatrixInput_0_295 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_295 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_295 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_292 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_292 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_292 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_292 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_292 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_291 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_285 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_285 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_285 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_285 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_285 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_285 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_15_205 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_205 = cat(decoded_andMatrixOutputs_andMatrixInput_14_285, decoded_andMatrixOutputs_andMatrixInput_15_205)
node decoded_andMatrixOutputs_lo_lo_hi_285 = cat(decoded_andMatrixOutputs_andMatrixInput_12_285, decoded_andMatrixOutputs_andMatrixInput_13_285)
node decoded_andMatrixOutputs_lo_lo_292 = cat(decoded_andMatrixOutputs_lo_lo_hi_285, decoded_andMatrixOutputs_lo_lo_lo_205)
node decoded_andMatrixOutputs_lo_hi_lo_285 = cat(decoded_andMatrixOutputs_andMatrixInput_10_285, decoded_andMatrixOutputs_andMatrixInput_11_285)
node decoded_andMatrixOutputs_lo_hi_hi_285 = cat(decoded_andMatrixOutputs_andMatrixInput_8_291, decoded_andMatrixOutputs_andMatrixInput_9_285)
node decoded_andMatrixOutputs_lo_hi_292 = cat(decoded_andMatrixOutputs_lo_hi_hi_285, decoded_andMatrixOutputs_lo_hi_lo_285)
node decoded_andMatrixOutputs_lo_292 = cat(decoded_andMatrixOutputs_lo_hi_292, decoded_andMatrixOutputs_lo_lo_292)
node decoded_andMatrixOutputs_hi_lo_lo_285 = cat(decoded_andMatrixOutputs_andMatrixInput_6_292, decoded_andMatrixOutputs_andMatrixInput_7_292)
node decoded_andMatrixOutputs_hi_lo_hi_285 = cat(decoded_andMatrixOutputs_andMatrixInput_4_292, decoded_andMatrixOutputs_andMatrixInput_5_292)
node decoded_andMatrixOutputs_hi_lo_292 = cat(decoded_andMatrixOutputs_hi_lo_hi_285, decoded_andMatrixOutputs_hi_lo_lo_285)
node decoded_andMatrixOutputs_hi_hi_lo_285 = cat(decoded_andMatrixOutputs_andMatrixInput_2_295, decoded_andMatrixOutputs_andMatrixInput_3_292)
node decoded_andMatrixOutputs_hi_hi_hi_291 = cat(decoded_andMatrixOutputs_andMatrixInput_0_295, decoded_andMatrixOutputs_andMatrixInput_1_295)
node decoded_andMatrixOutputs_hi_hi_292 = cat(decoded_andMatrixOutputs_hi_hi_hi_291, decoded_andMatrixOutputs_hi_hi_lo_285)
node decoded_andMatrixOutputs_hi_295 = cat(decoded_andMatrixOutputs_hi_hi_292, decoded_andMatrixOutputs_hi_lo_292)
node _decoded_andMatrixOutputs_T_295 = cat(decoded_andMatrixOutputs_hi_295, decoded_andMatrixOutputs_lo_292)
node decoded_andMatrixOutputs_9_2_4 = andr(_decoded_andMatrixOutputs_T_295)
node decoded_andMatrixOutputs_andMatrixInput_0_296 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_296 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_296 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_293 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_293 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_293 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_293 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_293 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_292 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_286 = bits(decoded_invInputs_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_286 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_286 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_286 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_286 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_286 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_206 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_134 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_206 = cat(decoded_andMatrixOutputs_andMatrixInput_15_206, decoded_andMatrixOutputs_andMatrixInput_16_134)
node decoded_andMatrixOutputs_lo_lo_hi_286 = cat(decoded_andMatrixOutputs_andMatrixInput_13_286, decoded_andMatrixOutputs_andMatrixInput_14_286)
node decoded_andMatrixOutputs_lo_lo_293 = cat(decoded_andMatrixOutputs_lo_lo_hi_286, decoded_andMatrixOutputs_lo_lo_lo_206)
node decoded_andMatrixOutputs_lo_hi_lo_286 = cat(decoded_andMatrixOutputs_andMatrixInput_11_286, decoded_andMatrixOutputs_andMatrixInput_12_286)
node decoded_andMatrixOutputs_lo_hi_hi_286 = cat(decoded_andMatrixOutputs_andMatrixInput_9_286, decoded_andMatrixOutputs_andMatrixInput_10_286)
node decoded_andMatrixOutputs_lo_hi_293 = cat(decoded_andMatrixOutputs_lo_hi_hi_286, decoded_andMatrixOutputs_lo_hi_lo_286)
node decoded_andMatrixOutputs_lo_293 = cat(decoded_andMatrixOutputs_lo_hi_293, decoded_andMatrixOutputs_lo_lo_293)
node decoded_andMatrixOutputs_hi_lo_lo_286 = cat(decoded_andMatrixOutputs_andMatrixInput_7_293, decoded_andMatrixOutputs_andMatrixInput_8_292)
node decoded_andMatrixOutputs_hi_lo_hi_286 = cat(decoded_andMatrixOutputs_andMatrixInput_5_293, decoded_andMatrixOutputs_andMatrixInput_6_293)
node decoded_andMatrixOutputs_hi_lo_293 = cat(decoded_andMatrixOutputs_hi_lo_hi_286, decoded_andMatrixOutputs_hi_lo_lo_286)
node decoded_andMatrixOutputs_hi_hi_lo_286 = cat(decoded_andMatrixOutputs_andMatrixInput_3_293, decoded_andMatrixOutputs_andMatrixInput_4_293)
node decoded_andMatrixOutputs_hi_hi_hi_hi_134 = cat(decoded_andMatrixOutputs_andMatrixInput_0_296, decoded_andMatrixOutputs_andMatrixInput_1_296)
node decoded_andMatrixOutputs_hi_hi_hi_292 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_134, decoded_andMatrixOutputs_andMatrixInput_2_296)
node decoded_andMatrixOutputs_hi_hi_293 = cat(decoded_andMatrixOutputs_hi_hi_hi_292, decoded_andMatrixOutputs_hi_hi_lo_286)
node decoded_andMatrixOutputs_hi_296 = cat(decoded_andMatrixOutputs_hi_hi_293, decoded_andMatrixOutputs_hi_lo_293)
node _decoded_andMatrixOutputs_T_296 = cat(decoded_andMatrixOutputs_hi_296, decoded_andMatrixOutputs_lo_293)
node decoded_andMatrixOutputs_56_2_1 = andr(_decoded_andMatrixOutputs_T_296)
node decoded_andMatrixOutputs_andMatrixInput_0_297 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_297 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_297 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_294 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_294 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_294 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_294 = bits(decoded_plaInput_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_294 = bits(decoded_invInputs_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_293 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_287 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_287 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_287 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_287 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_287 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_287 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_15_207 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_207 = cat(decoded_andMatrixOutputs_andMatrixInput_14_287, decoded_andMatrixOutputs_andMatrixInput_15_207)
node decoded_andMatrixOutputs_lo_lo_hi_287 = cat(decoded_andMatrixOutputs_andMatrixInput_12_287, decoded_andMatrixOutputs_andMatrixInput_13_287)
node decoded_andMatrixOutputs_lo_lo_294 = cat(decoded_andMatrixOutputs_lo_lo_hi_287, decoded_andMatrixOutputs_lo_lo_lo_207)
node decoded_andMatrixOutputs_lo_hi_lo_287 = cat(decoded_andMatrixOutputs_andMatrixInput_10_287, decoded_andMatrixOutputs_andMatrixInput_11_287)
node decoded_andMatrixOutputs_lo_hi_hi_287 = cat(decoded_andMatrixOutputs_andMatrixInput_8_293, decoded_andMatrixOutputs_andMatrixInput_9_287)
node decoded_andMatrixOutputs_lo_hi_294 = cat(decoded_andMatrixOutputs_lo_hi_hi_287, decoded_andMatrixOutputs_lo_hi_lo_287)
node decoded_andMatrixOutputs_lo_294 = cat(decoded_andMatrixOutputs_lo_hi_294, decoded_andMatrixOutputs_lo_lo_294)
node decoded_andMatrixOutputs_hi_lo_lo_287 = cat(decoded_andMatrixOutputs_andMatrixInput_6_294, decoded_andMatrixOutputs_andMatrixInput_7_294)
node decoded_andMatrixOutputs_hi_lo_hi_287 = cat(decoded_andMatrixOutputs_andMatrixInput_4_294, decoded_andMatrixOutputs_andMatrixInput_5_294)
node decoded_andMatrixOutputs_hi_lo_294 = cat(decoded_andMatrixOutputs_hi_lo_hi_287, decoded_andMatrixOutputs_hi_lo_lo_287)
node decoded_andMatrixOutputs_hi_hi_lo_287 = cat(decoded_andMatrixOutputs_andMatrixInput_2_297, decoded_andMatrixOutputs_andMatrixInput_3_294)
node decoded_andMatrixOutputs_hi_hi_hi_293 = cat(decoded_andMatrixOutputs_andMatrixInput_0_297, decoded_andMatrixOutputs_andMatrixInput_1_297)
node decoded_andMatrixOutputs_hi_hi_294 = cat(decoded_andMatrixOutputs_hi_hi_hi_293, decoded_andMatrixOutputs_hi_hi_lo_287)
node decoded_andMatrixOutputs_hi_297 = cat(decoded_andMatrixOutputs_hi_hi_294, decoded_andMatrixOutputs_hi_lo_294)
node _decoded_andMatrixOutputs_T_297 = cat(decoded_andMatrixOutputs_hi_297, decoded_andMatrixOutputs_lo_294)
node decoded_andMatrixOutputs_61_2_1 = andr(_decoded_andMatrixOutputs_T_297)
node decoded_andMatrixOutputs_andMatrixInput_0_298 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_298 = bits(decoded_invInputs_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_2_298 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_3_295 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_4_295 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_5_295 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_6_295 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_7_295 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_8_294 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_9_288 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_10_288 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_11_288 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_12_288 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_13_288 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_14_288 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_15_208 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_208 = cat(decoded_andMatrixOutputs_andMatrixInput_14_288, decoded_andMatrixOutputs_andMatrixInput_15_208)
node decoded_andMatrixOutputs_lo_lo_hi_288 = cat(decoded_andMatrixOutputs_andMatrixInput_12_288, decoded_andMatrixOutputs_andMatrixInput_13_288)
node decoded_andMatrixOutputs_lo_lo_295 = cat(decoded_andMatrixOutputs_lo_lo_hi_288, decoded_andMatrixOutputs_lo_lo_lo_208)
node decoded_andMatrixOutputs_lo_hi_lo_288 = cat(decoded_andMatrixOutputs_andMatrixInput_10_288, decoded_andMatrixOutputs_andMatrixInput_11_288)
node decoded_andMatrixOutputs_lo_hi_hi_288 = cat(decoded_andMatrixOutputs_andMatrixInput_8_294, decoded_andMatrixOutputs_andMatrixInput_9_288)
node decoded_andMatrixOutputs_lo_hi_295 = cat(decoded_andMatrixOutputs_lo_hi_hi_288, decoded_andMatrixOutputs_lo_hi_lo_288)
node decoded_andMatrixOutputs_lo_295 = cat(decoded_andMatrixOutputs_lo_hi_295, decoded_andMatrixOutputs_lo_lo_295)
node decoded_andMatrixOutputs_hi_lo_lo_288 = cat(decoded_andMatrixOutputs_andMatrixInput_6_295, decoded_andMatrixOutputs_andMatrixInput_7_295)
node decoded_andMatrixOutputs_hi_lo_hi_288 = cat(decoded_andMatrixOutputs_andMatrixInput_4_295, decoded_andMatrixOutputs_andMatrixInput_5_295)
node decoded_andMatrixOutputs_hi_lo_295 = cat(decoded_andMatrixOutputs_hi_lo_hi_288, decoded_andMatrixOutputs_hi_lo_lo_288)
node decoded_andMatrixOutputs_hi_hi_lo_288 = cat(decoded_andMatrixOutputs_andMatrixInput_2_298, decoded_andMatrixOutputs_andMatrixInput_3_295)
node decoded_andMatrixOutputs_hi_hi_hi_294 = cat(decoded_andMatrixOutputs_andMatrixInput_0_298, decoded_andMatrixOutputs_andMatrixInput_1_298)
node decoded_andMatrixOutputs_hi_hi_295 = cat(decoded_andMatrixOutputs_hi_hi_hi_294, decoded_andMatrixOutputs_hi_hi_lo_288)
node decoded_andMatrixOutputs_hi_298 = cat(decoded_andMatrixOutputs_hi_hi_295, decoded_andMatrixOutputs_hi_lo_295)
node _decoded_andMatrixOutputs_T_298 = cat(decoded_andMatrixOutputs_hi_298, decoded_andMatrixOutputs_lo_295)
node decoded_andMatrixOutputs_15_2_4 = andr(_decoded_andMatrixOutputs_T_298)
node decoded_andMatrixOutputs_andMatrixInput_0_299 = bits(decoded_invInputs_4, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_299 = bits(decoded_invInputs_4, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_2_299 = bits(decoded_plaInput_4, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_3_296 = bits(decoded_invInputs_4, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_4_296 = bits(decoded_invInputs_4, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_5_296 = bits(decoded_invInputs_4, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_6_296 = bits(decoded_invInputs_4, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_7_296 = bits(decoded_invInputs_4, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_8_295 = bits(decoded_plaInput_4, 10, 10)
node decoded_andMatrixOutputs_andMatrixInput_9_289 = bits(decoded_plaInput_4, 11, 11)
node decoded_andMatrixOutputs_andMatrixInput_10_289 = bits(decoded_plaInput_4, 12, 12)
node decoded_andMatrixOutputs_andMatrixInput_11_289 = bits(decoded_invInputs_4, 13, 13)
node decoded_andMatrixOutputs_andMatrixInput_12_289 = bits(decoded_invInputs_4, 14, 14)
node decoded_andMatrixOutputs_andMatrixInput_13_289 = bits(decoded_invInputs_4, 15, 15)
node decoded_andMatrixOutputs_andMatrixInput_14_289 = bits(decoded_plaInput_4, 16, 16)
node decoded_andMatrixOutputs_andMatrixInput_15_209 = bits(decoded_plaInput_4, 18, 18)
node decoded_andMatrixOutputs_andMatrixInput_16_135 = bits(decoded_plaInput_4, 19, 19)
node decoded_andMatrixOutputs_lo_lo_lo_209 = cat(decoded_andMatrixOutputs_andMatrixInput_15_209, decoded_andMatrixOutputs_andMatrixInput_16_135)
node decoded_andMatrixOutputs_lo_lo_hi_289 = cat(decoded_andMatrixOutputs_andMatrixInput_13_289, decoded_andMatrixOutputs_andMatrixInput_14_289)
node decoded_andMatrixOutputs_lo_lo_296 = cat(decoded_andMatrixOutputs_lo_lo_hi_289, decoded_andMatrixOutputs_lo_lo_lo_209)
node decoded_andMatrixOutputs_lo_hi_lo_289 = cat(decoded_andMatrixOutputs_andMatrixInput_11_289, decoded_andMatrixOutputs_andMatrixInput_12_289)
node decoded_andMatrixOutputs_lo_hi_hi_289 = cat(decoded_andMatrixOutputs_andMatrixInput_9_289, decoded_andMatrixOutputs_andMatrixInput_10_289)
node decoded_andMatrixOutputs_lo_hi_296 = cat(decoded_andMatrixOutputs_lo_hi_hi_289, decoded_andMatrixOutputs_lo_hi_lo_289)
node decoded_andMatrixOutputs_lo_296 = cat(decoded_andMatrixOutputs_lo_hi_296, decoded_andMatrixOutputs_lo_lo_296)
node decoded_andMatrixOutputs_hi_lo_lo_289 = cat(decoded_andMatrixOutputs_andMatrixInput_7_296, decoded_andMatrixOutputs_andMatrixInput_8_295)
node decoded_andMatrixOutputs_hi_lo_hi_289 = cat(decoded_andMatrixOutputs_andMatrixInput_5_296, decoded_andMatrixOutputs_andMatrixInput_6_296)
node decoded_andMatrixOutputs_hi_lo_296 = cat(decoded_andMatrixOutputs_hi_lo_hi_289, decoded_andMatrixOutputs_hi_lo_lo_289)
node decoded_andMatrixOutputs_hi_hi_lo_289 = cat(decoded_andMatrixOutputs_andMatrixInput_3_296, decoded_andMatrixOutputs_andMatrixInput_4_296)
node decoded_andMatrixOutputs_hi_hi_hi_hi_135 = cat(decoded_andMatrixOutputs_andMatrixInput_0_299, decoded_andMatrixOutputs_andMatrixInput_1_299)
node decoded_andMatrixOutputs_hi_hi_hi_295 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_135, decoded_andMatrixOutputs_andMatrixInput_2_299)
node decoded_andMatrixOutputs_hi_hi_296 = cat(decoded_andMatrixOutputs_hi_hi_hi_295, decoded_andMatrixOutputs_hi_hi_lo_289)
node decoded_andMatrixOutputs_hi_299 = cat(decoded_andMatrixOutputs_hi_hi_296, decoded_andMatrixOutputs_hi_lo_296)
node _decoded_andMatrixOutputs_T_299 = cat(decoded_andMatrixOutputs_hi_299, decoded_andMatrixOutputs_lo_296)
node decoded_andMatrixOutputs_36_2_4 = andr(_decoded_andMatrixOutputs_T_299)
node decoded_orMatrixOutputs_lo_lo_hi_48 = cat(decoded_andMatrixOutputs_9_2_4, decoded_andMatrixOutputs_61_2_1)
node decoded_orMatrixOutputs_lo_lo_72 = cat(decoded_orMatrixOutputs_lo_lo_hi_48, decoded_andMatrixOutputs_15_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_53 = cat(decoded_andMatrixOutputs_52_2_3, decoded_andMatrixOutputs_33_2_4)
node decoded_orMatrixOutputs_lo_hi_84 = cat(decoded_orMatrixOutputs_lo_hi_hi_53, decoded_andMatrixOutputs_1_2_4)
node decoded_orMatrixOutputs_lo_95 = cat(decoded_orMatrixOutputs_lo_hi_84, decoded_orMatrixOutputs_lo_lo_72)
node decoded_orMatrixOutputs_hi_lo_hi_48 = cat(decoded_andMatrixOutputs_3_2_4, decoded_andMatrixOutputs_23_2_4)
node decoded_orMatrixOutputs_hi_lo_74 = cat(decoded_orMatrixOutputs_hi_lo_hi_48, decoded_andMatrixOutputs_16_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_62 = cat(decoded_andMatrixOutputs_67_2_1, decoded_andMatrixOutputs_10_2_4)
node decoded_orMatrixOutputs_hi_hi_94 = cat(decoded_orMatrixOutputs_hi_hi_hi_62, decoded_andMatrixOutputs_44_2_3)
node decoded_orMatrixOutputs_hi_101 = cat(decoded_orMatrixOutputs_hi_hi_94, decoded_orMatrixOutputs_hi_lo_74)
node _decoded_orMatrixOutputs_T_209 = cat(decoded_orMatrixOutputs_hi_101, decoded_orMatrixOutputs_lo_95)
node _decoded_orMatrixOutputs_T_210 = orr(_decoded_orMatrixOutputs_T_209)
node decoded_orMatrixOutputs_lo_lo_hi_49 = cat(decoded_andMatrixOutputs_9_2_4, decoded_andMatrixOutputs_61_2_1)
node decoded_orMatrixOutputs_lo_lo_73 = cat(decoded_orMatrixOutputs_lo_lo_hi_49, decoded_andMatrixOutputs_15_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_54 = cat(decoded_andMatrixOutputs_52_2_3, decoded_andMatrixOutputs_33_2_4)
node decoded_orMatrixOutputs_lo_hi_85 = cat(decoded_orMatrixOutputs_lo_hi_hi_54, decoded_andMatrixOutputs_1_2_4)
node decoded_orMatrixOutputs_lo_96 = cat(decoded_orMatrixOutputs_lo_hi_85, decoded_orMatrixOutputs_lo_lo_73)
node decoded_orMatrixOutputs_hi_lo_hi_49 = cat(decoded_andMatrixOutputs_3_2_4, decoded_andMatrixOutputs_23_2_4)
node decoded_orMatrixOutputs_hi_lo_75 = cat(decoded_orMatrixOutputs_hi_lo_hi_49, decoded_andMatrixOutputs_16_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_63 = cat(decoded_andMatrixOutputs_67_2_1, decoded_andMatrixOutputs_10_2_4)
node decoded_orMatrixOutputs_hi_hi_95 = cat(decoded_orMatrixOutputs_hi_hi_hi_63, decoded_andMatrixOutputs_44_2_3)
node decoded_orMatrixOutputs_hi_102 = cat(decoded_orMatrixOutputs_hi_hi_95, decoded_orMatrixOutputs_hi_lo_75)
node _decoded_orMatrixOutputs_T_211 = cat(decoded_orMatrixOutputs_hi_102, decoded_orMatrixOutputs_lo_96)
node _decoded_orMatrixOutputs_T_212 = orr(_decoded_orMatrixOutputs_T_211)
node decoded_orMatrixOutputs_lo_lo_hi_50 = cat(decoded_andMatrixOutputs_9_2_4, decoded_andMatrixOutputs_61_2_1)
node decoded_orMatrixOutputs_lo_lo_74 = cat(decoded_orMatrixOutputs_lo_lo_hi_50, decoded_andMatrixOutputs_15_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_55 = cat(decoded_andMatrixOutputs_52_2_3, decoded_andMatrixOutputs_33_2_4)
node decoded_orMatrixOutputs_lo_hi_86 = cat(decoded_orMatrixOutputs_lo_hi_hi_55, decoded_andMatrixOutputs_1_2_4)
node decoded_orMatrixOutputs_lo_97 = cat(decoded_orMatrixOutputs_lo_hi_86, decoded_orMatrixOutputs_lo_lo_74)
node decoded_orMatrixOutputs_hi_lo_hi_50 = cat(decoded_andMatrixOutputs_3_2_4, decoded_andMatrixOutputs_23_2_4)
node decoded_orMatrixOutputs_hi_lo_76 = cat(decoded_orMatrixOutputs_hi_lo_hi_50, decoded_andMatrixOutputs_16_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_64 = cat(decoded_andMatrixOutputs_67_2_1, decoded_andMatrixOutputs_10_2_4)
node decoded_orMatrixOutputs_hi_hi_96 = cat(decoded_orMatrixOutputs_hi_hi_hi_64, decoded_andMatrixOutputs_44_2_3)
node decoded_orMatrixOutputs_hi_103 = cat(decoded_orMatrixOutputs_hi_hi_96, decoded_orMatrixOutputs_hi_lo_76)
node _decoded_orMatrixOutputs_T_213 = cat(decoded_orMatrixOutputs_hi_103, decoded_orMatrixOutputs_lo_97)
node _decoded_orMatrixOutputs_T_214 = orr(_decoded_orMatrixOutputs_T_213)
node decoded_orMatrixOutputs_lo_lo_75 = cat(decoded_andMatrixOutputs_41_2_4, decoded_andMatrixOutputs_68_2_1)
node decoded_orMatrixOutputs_lo_hi_87 = cat(decoded_andMatrixOutputs_16_2_4, decoded_andMatrixOutputs_19_2_4)
node decoded_orMatrixOutputs_lo_98 = cat(decoded_orMatrixOutputs_lo_hi_87, decoded_orMatrixOutputs_lo_lo_75)
node decoded_orMatrixOutputs_hi_lo_77 = cat(decoded_andMatrixOutputs_3_2_4, decoded_andMatrixOutputs_23_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_65 = cat(decoded_andMatrixOutputs_67_2_1, decoded_andMatrixOutputs_10_2_4)
node decoded_orMatrixOutputs_hi_hi_97 = cat(decoded_orMatrixOutputs_hi_hi_hi_65, decoded_andMatrixOutputs_44_2_3)
node decoded_orMatrixOutputs_hi_104 = cat(decoded_orMatrixOutputs_hi_hi_97, decoded_orMatrixOutputs_hi_lo_77)
node _decoded_orMatrixOutputs_T_215 = cat(decoded_orMatrixOutputs_hi_104, decoded_orMatrixOutputs_lo_98)
node _decoded_orMatrixOutputs_T_216 = orr(_decoded_orMatrixOutputs_T_215)
node decoded_orMatrixOutputs_lo_lo_76 = cat(decoded_andMatrixOutputs_23_2_4, decoded_andMatrixOutputs_16_2_4)
node decoded_orMatrixOutputs_lo_hi_88 = cat(decoded_andMatrixOutputs_44_2_3, decoded_andMatrixOutputs_3_2_4)
node decoded_orMatrixOutputs_lo_99 = cat(decoded_orMatrixOutputs_lo_hi_88, decoded_orMatrixOutputs_lo_lo_76)
node decoded_orMatrixOutputs_hi_lo_78 = cat(decoded_andMatrixOutputs_31_2_4, decoded_andMatrixOutputs_17_2_4)
node decoded_orMatrixOutputs_hi_hi_98 = cat(decoded_andMatrixOutputs_67_2_1, decoded_andMatrixOutputs_10_2_4)
node decoded_orMatrixOutputs_hi_105 = cat(decoded_orMatrixOutputs_hi_hi_98, decoded_orMatrixOutputs_hi_lo_78)
node _decoded_orMatrixOutputs_T_217 = cat(decoded_orMatrixOutputs_hi_105, decoded_orMatrixOutputs_lo_99)
node _decoded_orMatrixOutputs_T_218 = orr(_decoded_orMatrixOutputs_T_217)
node decoded_orMatrixOutputs_lo_100 = cat(decoded_andMatrixOutputs_44_2_3, decoded_andMatrixOutputs_3_2_4)
node decoded_orMatrixOutputs_hi_106 = cat(decoded_andMatrixOutputs_67_2_1, decoded_andMatrixOutputs_10_2_4)
node _decoded_orMatrixOutputs_T_219 = cat(decoded_orMatrixOutputs_hi_106, decoded_orMatrixOutputs_lo_100)
node _decoded_orMatrixOutputs_T_220 = orr(_decoded_orMatrixOutputs_T_219)
node decoded_orMatrixOutputs_lo_hi_89 = cat(decoded_andMatrixOutputs_10_2_4, decoded_andMatrixOutputs_44_2_3)
node decoded_orMatrixOutputs_lo_101 = cat(decoded_orMatrixOutputs_lo_hi_89, decoded_andMatrixOutputs_3_2_4)
node decoded_orMatrixOutputs_hi_hi_99 = cat(decoded_andMatrixOutputs_37_2_4, decoded_andMatrixOutputs_32_2_4)
node decoded_orMatrixOutputs_hi_107 = cat(decoded_orMatrixOutputs_hi_hi_99, decoded_andMatrixOutputs_67_2_1)
node _decoded_orMatrixOutputs_T_221 = cat(decoded_orMatrixOutputs_hi_107, decoded_orMatrixOutputs_lo_101)
node _decoded_orMatrixOutputs_T_222 = orr(_decoded_orMatrixOutputs_T_221)
node decoded_orMatrixOutputs_lo_lo_lo_19 = cat(decoded_andMatrixOutputs_56_2_1, decoded_andMatrixOutputs_36_2_4)
node decoded_orMatrixOutputs_lo_lo_hi_51 = cat(decoded_andMatrixOutputs_29_2_4, decoded_andMatrixOutputs_49_2_3)
node decoded_orMatrixOutputs_lo_lo_77 = cat(decoded_orMatrixOutputs_lo_lo_hi_51, decoded_orMatrixOutputs_lo_lo_lo_19)
node decoded_orMatrixOutputs_lo_hi_lo_31 = cat(decoded_andMatrixOutputs_13_2_4, decoded_andMatrixOutputs_25_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_45_2_3, decoded_andMatrixOutputs_34_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_56 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_8, decoded_andMatrixOutputs_57_2_1)
node decoded_orMatrixOutputs_lo_hi_90 = cat(decoded_orMatrixOutputs_lo_hi_hi_56, decoded_orMatrixOutputs_lo_hi_lo_31)
node decoded_orMatrixOutputs_lo_102 = cat(decoded_orMatrixOutputs_lo_hi_90, decoded_orMatrixOutputs_lo_lo_77)
node decoded_orMatrixOutputs_hi_lo_lo_23 = cat(decoded_andMatrixOutputs_43_2_4, decoded_andMatrixOutputs_53_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_55_2_2, decoded_andMatrixOutputs_18_2_4)
node decoded_orMatrixOutputs_hi_lo_hi_51 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_8, decoded_andMatrixOutputs_26_2_4)
node decoded_orMatrixOutputs_hi_lo_79 = cat(decoded_orMatrixOutputs_hi_lo_hi_51, decoded_orMatrixOutputs_hi_lo_lo_23)
node decoded_orMatrixOutputs_hi_hi_lo_35 = cat(decoded_andMatrixOutputs_69_2_1, decoded_andMatrixOutputs_27_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_66 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_13, decoded_andMatrixOutputs_40_2_4)
node decoded_orMatrixOutputs_hi_hi_100 = cat(decoded_orMatrixOutputs_hi_hi_hi_66, decoded_orMatrixOutputs_hi_hi_lo_35)
node decoded_orMatrixOutputs_hi_108 = cat(decoded_orMatrixOutputs_hi_hi_100, decoded_orMatrixOutputs_hi_lo_79)
node _decoded_orMatrixOutputs_T_223 = cat(decoded_orMatrixOutputs_hi_108, decoded_orMatrixOutputs_lo_102)
node _decoded_orMatrixOutputs_T_224 = orr(_decoded_orMatrixOutputs_T_223)
node decoded_orMatrixOutputs_lo_lo_lo_20 = cat(decoded_andMatrixOutputs_56_2_1, decoded_andMatrixOutputs_36_2_4)
node decoded_orMatrixOutputs_lo_lo_hi_52 = cat(decoded_andMatrixOutputs_29_2_4, decoded_andMatrixOutputs_49_2_3)
node decoded_orMatrixOutputs_lo_lo_78 = cat(decoded_orMatrixOutputs_lo_lo_hi_52, decoded_orMatrixOutputs_lo_lo_lo_20)
node decoded_orMatrixOutputs_lo_hi_lo_32 = cat(decoded_andMatrixOutputs_13_2_4, decoded_andMatrixOutputs_25_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_45_2_3, decoded_andMatrixOutputs_34_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_57 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_9, decoded_andMatrixOutputs_57_2_1)
node decoded_orMatrixOutputs_lo_hi_91 = cat(decoded_orMatrixOutputs_lo_hi_hi_57, decoded_orMatrixOutputs_lo_hi_lo_32)
node decoded_orMatrixOutputs_lo_103 = cat(decoded_orMatrixOutputs_lo_hi_91, decoded_orMatrixOutputs_lo_lo_78)
node decoded_orMatrixOutputs_hi_lo_lo_24 = cat(decoded_andMatrixOutputs_43_2_4, decoded_andMatrixOutputs_53_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_55_2_2, decoded_andMatrixOutputs_18_2_4)
node decoded_orMatrixOutputs_hi_lo_hi_52 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_9, decoded_andMatrixOutputs_26_2_4)
node decoded_orMatrixOutputs_hi_lo_80 = cat(decoded_orMatrixOutputs_hi_lo_hi_52, decoded_orMatrixOutputs_hi_lo_lo_24)
node decoded_orMatrixOutputs_hi_hi_lo_36 = cat(decoded_andMatrixOutputs_69_2_1, decoded_andMatrixOutputs_27_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_67 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_14, decoded_andMatrixOutputs_40_2_4)
node decoded_orMatrixOutputs_hi_hi_101 = cat(decoded_orMatrixOutputs_hi_hi_hi_67, decoded_orMatrixOutputs_hi_hi_lo_36)
node decoded_orMatrixOutputs_hi_109 = cat(decoded_orMatrixOutputs_hi_hi_101, decoded_orMatrixOutputs_hi_lo_80)
node _decoded_orMatrixOutputs_T_225 = cat(decoded_orMatrixOutputs_hi_109, decoded_orMatrixOutputs_lo_103)
node _decoded_orMatrixOutputs_T_226 = orr(_decoded_orMatrixOutputs_T_225)
node decoded_orMatrixOutputs_lo_lo_lo_21 = cat(decoded_andMatrixOutputs_56_2_1, decoded_andMatrixOutputs_36_2_4)
node decoded_orMatrixOutputs_lo_lo_hi_53 = cat(decoded_andMatrixOutputs_29_2_4, decoded_andMatrixOutputs_49_2_3)
node decoded_orMatrixOutputs_lo_lo_79 = cat(decoded_orMatrixOutputs_lo_lo_hi_53, decoded_orMatrixOutputs_lo_lo_lo_21)
node decoded_orMatrixOutputs_lo_hi_lo_33 = cat(decoded_andMatrixOutputs_13_2_4, decoded_andMatrixOutputs_25_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_45_2_3, decoded_andMatrixOutputs_34_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_58 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_10, decoded_andMatrixOutputs_57_2_1)
node decoded_orMatrixOutputs_lo_hi_92 = cat(decoded_orMatrixOutputs_lo_hi_hi_58, decoded_orMatrixOutputs_lo_hi_lo_33)
node decoded_orMatrixOutputs_lo_104 = cat(decoded_orMatrixOutputs_lo_hi_92, decoded_orMatrixOutputs_lo_lo_79)
node decoded_orMatrixOutputs_hi_lo_lo_25 = cat(decoded_andMatrixOutputs_43_2_4, decoded_andMatrixOutputs_53_2_3)
node decoded_orMatrixOutputs_hi_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_55_2_2, decoded_andMatrixOutputs_18_2_4)
node decoded_orMatrixOutputs_hi_lo_hi_53 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_10, decoded_andMatrixOutputs_26_2_4)
node decoded_orMatrixOutputs_hi_lo_81 = cat(decoded_orMatrixOutputs_hi_lo_hi_53, decoded_orMatrixOutputs_hi_lo_lo_25)
node decoded_orMatrixOutputs_hi_hi_lo_37 = cat(decoded_andMatrixOutputs_69_2_1, decoded_andMatrixOutputs_27_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_68 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_15, decoded_andMatrixOutputs_40_2_4)
node decoded_orMatrixOutputs_hi_hi_102 = cat(decoded_orMatrixOutputs_hi_hi_hi_68, decoded_orMatrixOutputs_hi_hi_lo_37)
node decoded_orMatrixOutputs_hi_110 = cat(decoded_orMatrixOutputs_hi_hi_102, decoded_orMatrixOutputs_hi_lo_81)
node _decoded_orMatrixOutputs_T_227 = cat(decoded_orMatrixOutputs_hi_110, decoded_orMatrixOutputs_lo_104)
node _decoded_orMatrixOutputs_T_228 = orr(_decoded_orMatrixOutputs_T_227)
node decoded_orMatrixOutputs_lo_lo_lo_22 = cat(decoded_andMatrixOutputs_20_2_4, decoded_andMatrixOutputs_66_2_1)
node decoded_orMatrixOutputs_lo_lo_hi_54 = cat(decoded_andMatrixOutputs_13_2_4, decoded_andMatrixOutputs_25_2_4)
node decoded_orMatrixOutputs_lo_lo_80 = cat(decoded_orMatrixOutputs_lo_lo_hi_54, decoded_orMatrixOutputs_lo_lo_lo_22)
node decoded_orMatrixOutputs_lo_hi_lo_34 = cat(decoded_andMatrixOutputs_34_2_4, decoded_andMatrixOutputs_57_2_1)
node decoded_orMatrixOutputs_lo_hi_hi_59 = cat(decoded_andMatrixOutputs_53_2_3, decoded_andMatrixOutputs_45_2_3)
node decoded_orMatrixOutputs_lo_hi_93 = cat(decoded_orMatrixOutputs_lo_hi_hi_59, decoded_orMatrixOutputs_lo_hi_lo_34)
node decoded_orMatrixOutputs_lo_105 = cat(decoded_orMatrixOutputs_lo_hi_93, decoded_orMatrixOutputs_lo_lo_80)
node decoded_orMatrixOutputs_hi_lo_lo_26 = cat(decoded_andMatrixOutputs_26_2_4, decoded_andMatrixOutputs_43_2_4)
node decoded_orMatrixOutputs_hi_lo_hi_54 = cat(decoded_andMatrixOutputs_55_2_2, decoded_andMatrixOutputs_18_2_4)
node decoded_orMatrixOutputs_hi_lo_82 = cat(decoded_orMatrixOutputs_hi_lo_hi_54, decoded_orMatrixOutputs_hi_lo_lo_26)
node decoded_orMatrixOutputs_hi_hi_lo_38 = cat(decoded_andMatrixOutputs_69_2_1, decoded_andMatrixOutputs_27_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_hi_69 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_16, decoded_andMatrixOutputs_40_2_4)
node decoded_orMatrixOutputs_hi_hi_103 = cat(decoded_orMatrixOutputs_hi_hi_hi_69, decoded_orMatrixOutputs_hi_hi_lo_38)
node decoded_orMatrixOutputs_hi_111 = cat(decoded_orMatrixOutputs_hi_hi_103, decoded_orMatrixOutputs_hi_lo_82)
node _decoded_orMatrixOutputs_T_229 = cat(decoded_orMatrixOutputs_hi_111, decoded_orMatrixOutputs_lo_105)
node _decoded_orMatrixOutputs_T_230 = orr(_decoded_orMatrixOutputs_T_229)
node decoded_orMatrixOutputs_lo_lo_lo_23 = cat(decoded_andMatrixOutputs_13_2_4, decoded_andMatrixOutputs_25_2_4)
node decoded_orMatrixOutputs_lo_lo_hi_55 = cat(decoded_andMatrixOutputs_34_2_4, decoded_andMatrixOutputs_57_2_1)
node decoded_orMatrixOutputs_lo_lo_81 = cat(decoded_orMatrixOutputs_lo_lo_hi_55, decoded_orMatrixOutputs_lo_lo_lo_23)
node decoded_orMatrixOutputs_lo_hi_lo_35 = cat(decoded_andMatrixOutputs_53_2_3, decoded_andMatrixOutputs_45_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_60 = cat(decoded_andMatrixOutputs_59_2_1, decoded_andMatrixOutputs_43_2_4)
node decoded_orMatrixOutputs_lo_hi_94 = cat(decoded_orMatrixOutputs_lo_hi_hi_60, decoded_orMatrixOutputs_lo_hi_lo_35)
node decoded_orMatrixOutputs_lo_106 = cat(decoded_orMatrixOutputs_lo_hi_94, decoded_orMatrixOutputs_lo_lo_81)
node decoded_orMatrixOutputs_hi_lo_lo_27 = cat(decoded_andMatrixOutputs_18_2_4, decoded_andMatrixOutputs_26_2_4)
node decoded_orMatrixOutputs_hi_lo_hi_55 = cat(decoded_andMatrixOutputs_27_2_4, decoded_andMatrixOutputs_55_2_2)
node decoded_orMatrixOutputs_hi_lo_83 = cat(decoded_orMatrixOutputs_hi_lo_hi_55, decoded_orMatrixOutputs_hi_lo_lo_27)
node decoded_orMatrixOutputs_hi_hi_lo_39 = cat(decoded_andMatrixOutputs_40_2_4, decoded_andMatrixOutputs_69_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_70 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_104 = cat(decoded_orMatrixOutputs_hi_hi_hi_70, decoded_orMatrixOutputs_hi_hi_lo_39)
node decoded_orMatrixOutputs_hi_112 = cat(decoded_orMatrixOutputs_hi_hi_104, decoded_orMatrixOutputs_hi_lo_83)
node _decoded_orMatrixOutputs_T_231 = cat(decoded_orMatrixOutputs_hi_112, decoded_orMatrixOutputs_lo_106)
node _decoded_orMatrixOutputs_T_232 = orr(_decoded_orMatrixOutputs_T_231)
node decoded_orMatrixOutputs_lo_lo_hi_56 = cat(decoded_andMatrixOutputs_34_2_4, decoded_andMatrixOutputs_57_2_1)
node decoded_orMatrixOutputs_lo_lo_82 = cat(decoded_orMatrixOutputs_lo_lo_hi_56, decoded_andMatrixOutputs_13_2_4)
node decoded_orMatrixOutputs_lo_hi_lo_36 = cat(decoded_andMatrixOutputs_53_2_3, decoded_andMatrixOutputs_45_2_3)
node decoded_orMatrixOutputs_lo_hi_hi_61 = cat(decoded_andMatrixOutputs_35_2_4, decoded_andMatrixOutputs_43_2_4)
node decoded_orMatrixOutputs_lo_hi_95 = cat(decoded_orMatrixOutputs_lo_hi_hi_61, decoded_orMatrixOutputs_lo_hi_lo_36)
node decoded_orMatrixOutputs_lo_107 = cat(decoded_orMatrixOutputs_lo_hi_95, decoded_orMatrixOutputs_lo_lo_82)
node decoded_orMatrixOutputs_hi_lo_hi_56 = cat(decoded_andMatrixOutputs_27_2_4, decoded_andMatrixOutputs_55_2_2)
node decoded_orMatrixOutputs_hi_lo_84 = cat(decoded_orMatrixOutputs_hi_lo_hi_56, decoded_andMatrixOutputs_54_2_3)
node decoded_orMatrixOutputs_hi_hi_lo_40 = cat(decoded_andMatrixOutputs_40_2_4, decoded_andMatrixOutputs_69_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_71 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_105 = cat(decoded_orMatrixOutputs_hi_hi_hi_71, decoded_orMatrixOutputs_hi_hi_lo_40)
node decoded_orMatrixOutputs_hi_113 = cat(decoded_orMatrixOutputs_hi_hi_105, decoded_orMatrixOutputs_hi_lo_84)
node _decoded_orMatrixOutputs_T_233 = cat(decoded_orMatrixOutputs_hi_113, decoded_orMatrixOutputs_lo_107)
node _decoded_orMatrixOutputs_T_234 = orr(_decoded_orMatrixOutputs_T_233)
node decoded_orMatrixOutputs_lo_lo_hi_57 = cat(decoded_andMatrixOutputs_53_2_3, decoded_andMatrixOutputs_45_2_3)
node decoded_orMatrixOutputs_lo_lo_83 = cat(decoded_orMatrixOutputs_lo_lo_hi_57, decoded_andMatrixOutputs_34_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_62 = cat(decoded_andMatrixOutputs_27_2_4, decoded_andMatrixOutputs_55_2_2)
node decoded_orMatrixOutputs_lo_hi_96 = cat(decoded_orMatrixOutputs_lo_hi_hi_62, decoded_andMatrixOutputs_43_2_4)
node decoded_orMatrixOutputs_lo_108 = cat(decoded_orMatrixOutputs_lo_hi_96, decoded_orMatrixOutputs_lo_lo_83)
node decoded_orMatrixOutputs_hi_lo_hi_57 = cat(decoded_andMatrixOutputs_48_2_3, decoded_andMatrixOutputs_40_2_4)
node decoded_orMatrixOutputs_hi_lo_85 = cat(decoded_orMatrixOutputs_hi_lo_hi_57, decoded_andMatrixOutputs_69_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_72 = cat(decoded_andMatrixOutputs_30_2_4, decoded_andMatrixOutputs_38_2_4)
node decoded_orMatrixOutputs_hi_hi_106 = cat(decoded_orMatrixOutputs_hi_hi_hi_72, decoded_andMatrixOutputs_65_2_1)
node decoded_orMatrixOutputs_hi_114 = cat(decoded_orMatrixOutputs_hi_hi_106, decoded_orMatrixOutputs_hi_lo_85)
node _decoded_orMatrixOutputs_T_235 = cat(decoded_orMatrixOutputs_hi_114, decoded_orMatrixOutputs_lo_108)
node _decoded_orMatrixOutputs_T_236 = orr(_decoded_orMatrixOutputs_T_235)
node _decoded_orMatrixOutputs_T_237 = orr(decoded_andMatrixOutputs_21_2_4)
node decoded_orMatrixOutputs_lo_lo_hi_58 = cat(decoded_andMatrixOutputs_9_2_4, decoded_andMatrixOutputs_61_2_1)
node decoded_orMatrixOutputs_lo_lo_84 = cat(decoded_orMatrixOutputs_lo_lo_hi_58, decoded_andMatrixOutputs_15_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_63 = cat(decoded_andMatrixOutputs_52_2_3, decoded_andMatrixOutputs_33_2_4)
node decoded_orMatrixOutputs_lo_hi_97 = cat(decoded_orMatrixOutputs_lo_hi_hi_63, decoded_andMatrixOutputs_1_2_4)
node decoded_orMatrixOutputs_lo_109 = cat(decoded_orMatrixOutputs_lo_hi_97, decoded_orMatrixOutputs_lo_lo_84)
node decoded_orMatrixOutputs_hi_lo_hi_58 = cat(decoded_andMatrixOutputs_7_2_4, decoded_andMatrixOutputs_8_2_4)
node decoded_orMatrixOutputs_hi_lo_86 = cat(decoded_orMatrixOutputs_hi_lo_hi_58, decoded_andMatrixOutputs_60_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_73 = cat(decoded_andMatrixOutputs_51_2_3, decoded_andMatrixOutputs_4_2_4)
node decoded_orMatrixOutputs_hi_hi_107 = cat(decoded_orMatrixOutputs_hi_hi_hi_73, decoded_andMatrixOutputs_42_2_4)
node decoded_orMatrixOutputs_hi_115 = cat(decoded_orMatrixOutputs_hi_hi_107, decoded_orMatrixOutputs_hi_lo_86)
node _decoded_orMatrixOutputs_T_238 = cat(decoded_orMatrixOutputs_hi_115, decoded_orMatrixOutputs_lo_109)
node _decoded_orMatrixOutputs_T_239 = orr(_decoded_orMatrixOutputs_T_238)
node decoded_orMatrixOutputs_lo_lo_hi_59 = cat(decoded_andMatrixOutputs_9_2_4, decoded_andMatrixOutputs_61_2_1)
node decoded_orMatrixOutputs_lo_lo_85 = cat(decoded_orMatrixOutputs_lo_lo_hi_59, decoded_andMatrixOutputs_15_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_64 = cat(decoded_andMatrixOutputs_52_2_3, decoded_andMatrixOutputs_33_2_4)
node decoded_orMatrixOutputs_lo_hi_98 = cat(decoded_orMatrixOutputs_lo_hi_hi_64, decoded_andMatrixOutputs_1_2_4)
node decoded_orMatrixOutputs_lo_110 = cat(decoded_orMatrixOutputs_lo_hi_98, decoded_orMatrixOutputs_lo_lo_85)
node decoded_orMatrixOutputs_hi_lo_hi_59 = cat(decoded_andMatrixOutputs_7_2_4, decoded_andMatrixOutputs_8_2_4)
node decoded_orMatrixOutputs_hi_lo_87 = cat(decoded_orMatrixOutputs_hi_lo_hi_59, decoded_andMatrixOutputs_60_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_74 = cat(decoded_andMatrixOutputs_51_2_3, decoded_andMatrixOutputs_4_2_4)
node decoded_orMatrixOutputs_hi_hi_108 = cat(decoded_orMatrixOutputs_hi_hi_hi_74, decoded_andMatrixOutputs_42_2_4)
node decoded_orMatrixOutputs_hi_116 = cat(decoded_orMatrixOutputs_hi_hi_108, decoded_orMatrixOutputs_hi_lo_87)
node _decoded_orMatrixOutputs_T_240 = cat(decoded_orMatrixOutputs_hi_116, decoded_orMatrixOutputs_lo_110)
node _decoded_orMatrixOutputs_T_241 = orr(_decoded_orMatrixOutputs_T_240)
node decoded_orMatrixOutputs_lo_lo_hi_60 = cat(decoded_andMatrixOutputs_9_2_4, decoded_andMatrixOutputs_61_2_1)
node decoded_orMatrixOutputs_lo_lo_86 = cat(decoded_orMatrixOutputs_lo_lo_hi_60, decoded_andMatrixOutputs_15_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_65 = cat(decoded_andMatrixOutputs_52_2_3, decoded_andMatrixOutputs_33_2_4)
node decoded_orMatrixOutputs_lo_hi_99 = cat(decoded_orMatrixOutputs_lo_hi_hi_65, decoded_andMatrixOutputs_1_2_4)
node decoded_orMatrixOutputs_lo_111 = cat(decoded_orMatrixOutputs_lo_hi_99, decoded_orMatrixOutputs_lo_lo_86)
node decoded_orMatrixOutputs_hi_lo_hi_60 = cat(decoded_andMatrixOutputs_7_2_4, decoded_andMatrixOutputs_8_2_4)
node decoded_orMatrixOutputs_hi_lo_88 = cat(decoded_orMatrixOutputs_hi_lo_hi_60, decoded_andMatrixOutputs_60_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_75 = cat(decoded_andMatrixOutputs_51_2_3, decoded_andMatrixOutputs_4_2_4)
node decoded_orMatrixOutputs_hi_hi_109 = cat(decoded_orMatrixOutputs_hi_hi_hi_75, decoded_andMatrixOutputs_42_2_4)
node decoded_orMatrixOutputs_hi_117 = cat(decoded_orMatrixOutputs_hi_hi_109, decoded_orMatrixOutputs_hi_lo_88)
node _decoded_orMatrixOutputs_T_242 = cat(decoded_orMatrixOutputs_hi_117, decoded_orMatrixOutputs_lo_111)
node _decoded_orMatrixOutputs_T_243 = orr(_decoded_orMatrixOutputs_T_242)
node decoded_orMatrixOutputs_lo_hi_100 = cat(decoded_andMatrixOutputs_7_2_4, decoded_andMatrixOutputs_8_2_4)
node decoded_orMatrixOutputs_lo_112 = cat(decoded_orMatrixOutputs_lo_hi_100, decoded_andMatrixOutputs_60_2_1)
node decoded_orMatrixOutputs_hi_hi_110 = cat(decoded_andMatrixOutputs_51_2_3, decoded_andMatrixOutputs_4_2_4)
node decoded_orMatrixOutputs_hi_118 = cat(decoded_orMatrixOutputs_hi_hi_110, decoded_andMatrixOutputs_42_2_4)
node _decoded_orMatrixOutputs_T_244 = cat(decoded_orMatrixOutputs_hi_118, decoded_orMatrixOutputs_lo_112)
node _decoded_orMatrixOutputs_T_245 = orr(_decoded_orMatrixOutputs_T_244)
node decoded_orMatrixOutputs_lo_lo_87 = cat(decoded_andMatrixOutputs_8_2_4, decoded_andMatrixOutputs_6_2_4)
node decoded_orMatrixOutputs_lo_hi_101 = cat(decoded_andMatrixOutputs_42_2_4, decoded_andMatrixOutputs_7_2_4)
node decoded_orMatrixOutputs_lo_113 = cat(decoded_orMatrixOutputs_lo_hi_101, decoded_orMatrixOutputs_lo_lo_87)
node decoded_orMatrixOutputs_hi_lo_89 = cat(decoded_andMatrixOutputs_2_2_4, decoded_andMatrixOutputs_28_2_4)
node decoded_orMatrixOutputs_hi_hi_111 = cat(decoded_andMatrixOutputs_51_2_3, decoded_andMatrixOutputs_4_2_4)
node decoded_orMatrixOutputs_hi_119 = cat(decoded_orMatrixOutputs_hi_hi_111, decoded_orMatrixOutputs_hi_lo_89)
node _decoded_orMatrixOutputs_T_246 = cat(decoded_orMatrixOutputs_hi_119, decoded_orMatrixOutputs_lo_113)
node _decoded_orMatrixOutputs_T_247 = orr(_decoded_orMatrixOutputs_T_246)
node decoded_orMatrixOutputs_lo_114 = cat(decoded_andMatrixOutputs_42_2_4, decoded_andMatrixOutputs_7_2_4)
node decoded_orMatrixOutputs_hi_120 = cat(decoded_andMatrixOutputs_51_2_3, decoded_andMatrixOutputs_4_2_4)
node _decoded_orMatrixOutputs_T_248 = cat(decoded_orMatrixOutputs_hi_120, decoded_orMatrixOutputs_lo_114)
node _decoded_orMatrixOutputs_T_249 = orr(_decoded_orMatrixOutputs_T_248)
node decoded_orMatrixOutputs_lo_hi_102 = cat(decoded_andMatrixOutputs_64_2_1, decoded_andMatrixOutputs_42_2_4)
node decoded_orMatrixOutputs_lo_115 = cat(decoded_orMatrixOutputs_lo_hi_102, decoded_andMatrixOutputs_0_2_4)
node decoded_orMatrixOutputs_hi_hi_112 = cat(decoded_andMatrixOutputs_5_2_4, decoded_andMatrixOutputs_47_2_3)
node decoded_orMatrixOutputs_hi_121 = cat(decoded_orMatrixOutputs_hi_hi_112, decoded_andMatrixOutputs_51_2_3)
node _decoded_orMatrixOutputs_T_250 = cat(decoded_orMatrixOutputs_hi_121, decoded_orMatrixOutputs_lo_115)
node _decoded_orMatrixOutputs_T_251 = orr(_decoded_orMatrixOutputs_T_250)
node decoded_orMatrixOutputs_lo_lo_88 = cat(decoded_andMatrixOutputs_62_2_1, decoded_andMatrixOutputs_22_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_66 = cat(decoded_andMatrixOutputs_24_2_4, decoded_andMatrixOutputs_11_2_4)
node decoded_orMatrixOutputs_lo_hi_103 = cat(decoded_orMatrixOutputs_lo_hi_hi_66, decoded_andMatrixOutputs_46_2_3)
node decoded_orMatrixOutputs_lo_116 = cat(decoded_orMatrixOutputs_lo_hi_103, decoded_orMatrixOutputs_lo_lo_88)
node decoded_orMatrixOutputs_hi_lo_hi_61 = cat(decoded_andMatrixOutputs_12_2_4, decoded_andMatrixOutputs_50_2_3)
node decoded_orMatrixOutputs_hi_lo_90 = cat(decoded_orMatrixOutputs_hi_lo_hi_61, decoded_andMatrixOutputs_58_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_76 = cat(decoded_andMatrixOutputs_14_2_4, decoded_andMatrixOutputs_39_2_4)
node decoded_orMatrixOutputs_hi_hi_113 = cat(decoded_orMatrixOutputs_hi_hi_hi_76, decoded_andMatrixOutputs_63_2_1)
node decoded_orMatrixOutputs_hi_122 = cat(decoded_orMatrixOutputs_hi_hi_113, decoded_orMatrixOutputs_hi_lo_90)
node _decoded_orMatrixOutputs_T_252 = cat(decoded_orMatrixOutputs_hi_122, decoded_orMatrixOutputs_lo_116)
node _decoded_orMatrixOutputs_T_253 = orr(_decoded_orMatrixOutputs_T_252)
node decoded_orMatrixOutputs_lo_lo_89 = cat(decoded_andMatrixOutputs_62_2_1, decoded_andMatrixOutputs_22_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_67 = cat(decoded_andMatrixOutputs_24_2_4, decoded_andMatrixOutputs_11_2_4)
node decoded_orMatrixOutputs_lo_hi_104 = cat(decoded_orMatrixOutputs_lo_hi_hi_67, decoded_andMatrixOutputs_46_2_3)
node decoded_orMatrixOutputs_lo_117 = cat(decoded_orMatrixOutputs_lo_hi_104, decoded_orMatrixOutputs_lo_lo_89)
node decoded_orMatrixOutputs_hi_lo_hi_62 = cat(decoded_andMatrixOutputs_12_2_4, decoded_andMatrixOutputs_50_2_3)
node decoded_orMatrixOutputs_hi_lo_91 = cat(decoded_orMatrixOutputs_hi_lo_hi_62, decoded_andMatrixOutputs_58_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_77 = cat(decoded_andMatrixOutputs_14_2_4, decoded_andMatrixOutputs_39_2_4)
node decoded_orMatrixOutputs_hi_hi_114 = cat(decoded_orMatrixOutputs_hi_hi_hi_77, decoded_andMatrixOutputs_63_2_1)
node decoded_orMatrixOutputs_hi_123 = cat(decoded_orMatrixOutputs_hi_hi_114, decoded_orMatrixOutputs_hi_lo_91)
node _decoded_orMatrixOutputs_T_254 = cat(decoded_orMatrixOutputs_hi_123, decoded_orMatrixOutputs_lo_117)
node _decoded_orMatrixOutputs_T_255 = orr(_decoded_orMatrixOutputs_T_254)
node decoded_orMatrixOutputs_lo_lo_90 = cat(decoded_andMatrixOutputs_62_2_1, decoded_andMatrixOutputs_22_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_68 = cat(decoded_andMatrixOutputs_24_2_4, decoded_andMatrixOutputs_11_2_4)
node decoded_orMatrixOutputs_lo_hi_105 = cat(decoded_orMatrixOutputs_lo_hi_hi_68, decoded_andMatrixOutputs_46_2_3)
node decoded_orMatrixOutputs_lo_118 = cat(decoded_orMatrixOutputs_lo_hi_105, decoded_orMatrixOutputs_lo_lo_90)
node decoded_orMatrixOutputs_hi_lo_hi_63 = cat(decoded_andMatrixOutputs_12_2_4, decoded_andMatrixOutputs_50_2_3)
node decoded_orMatrixOutputs_hi_lo_92 = cat(decoded_orMatrixOutputs_hi_lo_hi_63, decoded_andMatrixOutputs_58_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_78 = cat(decoded_andMatrixOutputs_14_2_4, decoded_andMatrixOutputs_39_2_4)
node decoded_orMatrixOutputs_hi_hi_115 = cat(decoded_orMatrixOutputs_hi_hi_hi_78, decoded_andMatrixOutputs_63_2_1)
node decoded_orMatrixOutputs_hi_124 = cat(decoded_orMatrixOutputs_hi_hi_115, decoded_orMatrixOutputs_hi_lo_92)
node _decoded_orMatrixOutputs_T_256 = cat(decoded_orMatrixOutputs_hi_124, decoded_orMatrixOutputs_lo_118)
node _decoded_orMatrixOutputs_T_257 = orr(_decoded_orMatrixOutputs_T_256)
node decoded_orMatrixOutputs_lo_lo_91 = cat(decoded_andMatrixOutputs_62_2_1, decoded_andMatrixOutputs_22_2_4)
node decoded_orMatrixOutputs_lo_hi_hi_69 = cat(decoded_andMatrixOutputs_24_2_4, decoded_andMatrixOutputs_11_2_4)
node decoded_orMatrixOutputs_lo_hi_106 = cat(decoded_orMatrixOutputs_lo_hi_hi_69, decoded_andMatrixOutputs_46_2_3)
node decoded_orMatrixOutputs_lo_119 = cat(decoded_orMatrixOutputs_lo_hi_106, decoded_orMatrixOutputs_lo_lo_91)
node decoded_orMatrixOutputs_hi_lo_hi_64 = cat(decoded_andMatrixOutputs_12_2_4, decoded_andMatrixOutputs_50_2_3)
node decoded_orMatrixOutputs_hi_lo_93 = cat(decoded_orMatrixOutputs_hi_lo_hi_64, decoded_andMatrixOutputs_58_2_1)
node decoded_orMatrixOutputs_hi_hi_hi_79 = cat(decoded_andMatrixOutputs_14_2_4, decoded_andMatrixOutputs_39_2_4)
node decoded_orMatrixOutputs_hi_hi_116 = cat(decoded_orMatrixOutputs_hi_hi_hi_79, decoded_andMatrixOutputs_63_2_1)
node decoded_orMatrixOutputs_hi_125 = cat(decoded_orMatrixOutputs_hi_hi_116, decoded_orMatrixOutputs_hi_lo_93)
node _decoded_orMatrixOutputs_T_258 = cat(decoded_orMatrixOutputs_hi_125, decoded_orMatrixOutputs_lo_119)
node _decoded_orMatrixOutputs_T_259 = orr(_decoded_orMatrixOutputs_T_258)
node decoded_orMatrixOutputs_lo_hi_107 = cat(decoded_andMatrixOutputs_50_2_3, decoded_andMatrixOutputs_58_2_1)
node decoded_orMatrixOutputs_lo_120 = cat(decoded_orMatrixOutputs_lo_hi_107, decoded_andMatrixOutputs_24_2_4)
node decoded_orMatrixOutputs_hi_lo_94 = cat(decoded_andMatrixOutputs_63_2_1, decoded_andMatrixOutputs_12_2_4)
node decoded_orMatrixOutputs_hi_hi_117 = cat(decoded_andMatrixOutputs_14_2_4, decoded_andMatrixOutputs_39_2_4)
node decoded_orMatrixOutputs_hi_126 = cat(decoded_orMatrixOutputs_hi_hi_117, decoded_orMatrixOutputs_hi_lo_94)
node _decoded_orMatrixOutputs_T_260 = cat(decoded_orMatrixOutputs_hi_126, decoded_orMatrixOutputs_lo_120)
node _decoded_orMatrixOutputs_T_261 = orr(_decoded_orMatrixOutputs_T_260)
node decoded_orMatrixOutputs_lo_hi_108 = cat(decoded_andMatrixOutputs_50_2_3, decoded_andMatrixOutputs_58_2_1)
node decoded_orMatrixOutputs_lo_121 = cat(decoded_orMatrixOutputs_lo_hi_108, decoded_andMatrixOutputs_24_2_4)
node decoded_orMatrixOutputs_hi_lo_95 = cat(decoded_andMatrixOutputs_63_2_1, decoded_andMatrixOutputs_12_2_4)
node decoded_orMatrixOutputs_hi_hi_118 = cat(decoded_andMatrixOutputs_14_2_4, decoded_andMatrixOutputs_39_2_4)
node decoded_orMatrixOutputs_hi_127 = cat(decoded_orMatrixOutputs_hi_hi_118, decoded_orMatrixOutputs_hi_lo_95)
node _decoded_orMatrixOutputs_T_262 = cat(decoded_orMatrixOutputs_hi_127, decoded_orMatrixOutputs_lo_121)
node _decoded_orMatrixOutputs_T_263 = orr(_decoded_orMatrixOutputs_T_262)
node _decoded_orMatrixOutputs_T_264 = orr(decoded_andMatrixOutputs_14_2_4)
node _decoded_orMatrixOutputs_T_265 = orr(decoded_andMatrixOutputs_14_2_4)
node decoded_orMatrixOutputs_lo_lo_lo_lo_4 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_lo_24 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_4, decoded_orMatrixOutputs_lo_lo_lo_lo_4)
node decoded_orMatrixOutputs_lo_lo_hi_lo_4 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_212, _decoded_orMatrixOutputs_T_210)
node decoded_orMatrixOutputs_lo_lo_hi_hi_8 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_lo_hi_61 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_8, decoded_orMatrixOutputs_lo_lo_hi_lo_4)
node decoded_orMatrixOutputs_lo_lo_92 = cat(decoded_orMatrixOutputs_lo_lo_hi_61, decoded_orMatrixOutputs_lo_lo_lo_24)
node decoded_orMatrixOutputs_lo_hi_lo_lo_4 = cat(_decoded_orMatrixOutputs_T_216, _decoded_orMatrixOutputs_T_214)
node decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_222, _decoded_orMatrixOutputs_T_220)
node decoded_orMatrixOutputs_lo_hi_lo_hi_7 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _decoded_orMatrixOutputs_T_218)
node decoded_orMatrixOutputs_lo_hi_lo_37 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_7, decoded_orMatrixOutputs_lo_hi_lo_lo_4)
node decoded_orMatrixOutputs_lo_hi_hi_lo_4 = cat(_decoded_orMatrixOutputs_T_224, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_230, _decoded_orMatrixOutputs_T_228)
node decoded_orMatrixOutputs_lo_hi_hi_hi_11 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, _decoded_orMatrixOutputs_T_226)
node decoded_orMatrixOutputs_lo_hi_hi_70 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_11, decoded_orMatrixOutputs_lo_hi_hi_lo_4)
node decoded_orMatrixOutputs_lo_hi_109 = cat(decoded_orMatrixOutputs_lo_hi_hi_70, decoded_orMatrixOutputs_lo_hi_lo_37)
node decoded_orMatrixOutputs_lo_122 = cat(decoded_orMatrixOutputs_lo_hi_109, decoded_orMatrixOutputs_lo_lo_92)
node decoded_orMatrixOutputs_hi_lo_lo_lo_4 = cat(_decoded_orMatrixOutputs_T_234, _decoded_orMatrixOutputs_T_232)
node decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_239, _decoded_orMatrixOutputs_T_237)
node decoded_orMatrixOutputs_hi_lo_lo_hi_7 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _decoded_orMatrixOutputs_T_236)
node decoded_orMatrixOutputs_hi_lo_lo_28 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_7, decoded_orMatrixOutputs_hi_lo_lo_lo_4)
node decoded_orMatrixOutputs_hi_lo_hi_lo_4 = cat(_decoded_orMatrixOutputs_T_243, _decoded_orMatrixOutputs_T_241)
node decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_249, _decoded_orMatrixOutputs_T_247)
node decoded_orMatrixOutputs_hi_lo_hi_hi_11 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, _decoded_orMatrixOutputs_T_245)
node decoded_orMatrixOutputs_hi_lo_hi_65 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_11, decoded_orMatrixOutputs_hi_lo_hi_lo_4)
node decoded_orMatrixOutputs_hi_lo_96 = cat(decoded_orMatrixOutputs_hi_lo_hi_65, decoded_orMatrixOutputs_hi_lo_lo_28)
node decoded_orMatrixOutputs_hi_hi_lo_lo_4 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_251)
node decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_257, _decoded_orMatrixOutputs_T_255)
node decoded_orMatrixOutputs_hi_hi_lo_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _decoded_orMatrixOutputs_T_253)
node decoded_orMatrixOutputs_hi_hi_lo_41 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_7, decoded_orMatrixOutputs_hi_hi_lo_lo_4)
node decoded_orMatrixOutputs_hi_hi_hi_lo_4 = cat(_decoded_orMatrixOutputs_T_261, _decoded_orMatrixOutputs_T_259)
node decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_265, _decoded_orMatrixOutputs_T_264)
node decoded_orMatrixOutputs_hi_hi_hi_hi_17 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, _decoded_orMatrixOutputs_T_263)
node decoded_orMatrixOutputs_hi_hi_hi_80 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_17, decoded_orMatrixOutputs_hi_hi_hi_lo_4)
node decoded_orMatrixOutputs_hi_hi_119 = cat(decoded_orMatrixOutputs_hi_hi_hi_80, decoded_orMatrixOutputs_hi_hi_lo_41)
node decoded_orMatrixOutputs_hi_128 = cat(decoded_orMatrixOutputs_hi_hi_119, decoded_orMatrixOutputs_hi_lo_96)
node decoded_orMatrixOutputs_4 = cat(decoded_orMatrixOutputs_hi_128, decoded_orMatrixOutputs_lo_122)
node _decoded_invMatrixOutputs_T_160 = bits(decoded_orMatrixOutputs_4, 0, 0)
node _decoded_invMatrixOutputs_T_161 = bits(decoded_orMatrixOutputs_4, 1, 1)
node _decoded_invMatrixOutputs_T_162 = bits(decoded_orMatrixOutputs_4, 2, 2)
node _decoded_invMatrixOutputs_T_163 = bits(decoded_orMatrixOutputs_4, 3, 3)
node _decoded_invMatrixOutputs_T_164 = bits(decoded_orMatrixOutputs_4, 4, 4)
node _decoded_invMatrixOutputs_T_165 = bits(decoded_orMatrixOutputs_4, 5, 5)
node _decoded_invMatrixOutputs_T_166 = bits(decoded_orMatrixOutputs_4, 6, 6)
node _decoded_invMatrixOutputs_T_167 = bits(decoded_orMatrixOutputs_4, 7, 7)
node _decoded_invMatrixOutputs_T_168 = bits(decoded_orMatrixOutputs_4, 8, 8)
node _decoded_invMatrixOutputs_T_169 = bits(decoded_orMatrixOutputs_4, 9, 9)
node _decoded_invMatrixOutputs_T_170 = bits(decoded_orMatrixOutputs_4, 10, 10)
node _decoded_invMatrixOutputs_T_171 = bits(decoded_orMatrixOutputs_4, 11, 11)
node _decoded_invMatrixOutputs_T_172 = bits(decoded_orMatrixOutputs_4, 12, 12)
node _decoded_invMatrixOutputs_T_173 = bits(decoded_orMatrixOutputs_4, 13, 13)
node _decoded_invMatrixOutputs_T_174 = bits(decoded_orMatrixOutputs_4, 14, 14)
node _decoded_invMatrixOutputs_T_175 = bits(decoded_orMatrixOutputs_4, 15, 15)
node _decoded_invMatrixOutputs_T_176 = bits(decoded_orMatrixOutputs_4, 16, 16)
node _decoded_invMatrixOutputs_T_177 = bits(decoded_orMatrixOutputs_4, 17, 17)
node _decoded_invMatrixOutputs_T_178 = bits(decoded_orMatrixOutputs_4, 18, 18)
node _decoded_invMatrixOutputs_T_179 = bits(decoded_orMatrixOutputs_4, 19, 19)
node _decoded_invMatrixOutputs_T_180 = bits(decoded_orMatrixOutputs_4, 20, 20)
node _decoded_invMatrixOutputs_T_181 = bits(decoded_orMatrixOutputs_4, 21, 21)
node _decoded_invMatrixOutputs_T_182 = bits(decoded_orMatrixOutputs_4, 22, 22)
node _decoded_invMatrixOutputs_T_183 = bits(decoded_orMatrixOutputs_4, 23, 23)
node _decoded_invMatrixOutputs_T_184 = bits(decoded_orMatrixOutputs_4, 24, 24)
node _decoded_invMatrixOutputs_T_185 = bits(decoded_orMatrixOutputs_4, 25, 25)
node _decoded_invMatrixOutputs_T_186 = bits(decoded_orMatrixOutputs_4, 26, 26)
node _decoded_invMatrixOutputs_T_187 = bits(decoded_orMatrixOutputs_4, 27, 27)
node _decoded_invMatrixOutputs_T_188 = bits(decoded_orMatrixOutputs_4, 28, 28)
node _decoded_invMatrixOutputs_T_189 = bits(decoded_orMatrixOutputs_4, 29, 29)
node _decoded_invMatrixOutputs_T_190 = bits(decoded_orMatrixOutputs_4, 30, 30)
node _decoded_invMatrixOutputs_T_191 = bits(decoded_orMatrixOutputs_4, 31, 31)
node _decoded_invMatrixOutputs_T_192 = bits(decoded_orMatrixOutputs_4, 32, 32)
node _decoded_invMatrixOutputs_T_193 = bits(decoded_orMatrixOutputs_4, 33, 33)
node _decoded_invMatrixOutputs_T_194 = bits(decoded_orMatrixOutputs_4, 34, 34)
node _decoded_invMatrixOutputs_T_195 = bits(decoded_orMatrixOutputs_4, 35, 35)
node _decoded_invMatrixOutputs_T_196 = bits(decoded_orMatrixOutputs_4, 36, 36)
node _decoded_invMatrixOutputs_T_197 = bits(decoded_orMatrixOutputs_4, 37, 37)
node _decoded_invMatrixOutputs_T_198 = bits(decoded_orMatrixOutputs_4, 38, 38)
node _decoded_invMatrixOutputs_T_199 = bits(decoded_orMatrixOutputs_4, 39, 39)
node decoded_invMatrixOutputs_lo_lo_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_161, _decoded_invMatrixOutputs_T_160)
node decoded_invMatrixOutputs_lo_lo_lo_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_164, _decoded_invMatrixOutputs_T_163)
node decoded_invMatrixOutputs_lo_lo_lo_hi_4 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_hi_4, _decoded_invMatrixOutputs_T_162)
node decoded_invMatrixOutputs_lo_lo_lo_4 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_4, decoded_invMatrixOutputs_lo_lo_lo_lo_4)
node decoded_invMatrixOutputs_lo_lo_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_166, _decoded_invMatrixOutputs_T_165)
node decoded_invMatrixOutputs_lo_lo_hi_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_169, _decoded_invMatrixOutputs_T_168)
node decoded_invMatrixOutputs_lo_lo_hi_hi_4 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_hi_4, _decoded_invMatrixOutputs_T_167)
node decoded_invMatrixOutputs_lo_lo_hi_4 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_4, decoded_invMatrixOutputs_lo_lo_hi_lo_4)
node decoded_invMatrixOutputs_lo_lo_4 = cat(decoded_invMatrixOutputs_lo_lo_hi_4, decoded_invMatrixOutputs_lo_lo_lo_4)
node decoded_invMatrixOutputs_lo_hi_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_171, _decoded_invMatrixOutputs_T_170)
node decoded_invMatrixOutputs_lo_hi_lo_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_174, _decoded_invMatrixOutputs_T_173)
node decoded_invMatrixOutputs_lo_hi_lo_hi_4 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_hi_4, _decoded_invMatrixOutputs_T_172)
node decoded_invMatrixOutputs_lo_hi_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_4, decoded_invMatrixOutputs_lo_hi_lo_lo_4)
node decoded_invMatrixOutputs_lo_hi_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_176, _decoded_invMatrixOutputs_T_175)
node decoded_invMatrixOutputs_lo_hi_hi_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_179, _decoded_invMatrixOutputs_T_178)
node decoded_invMatrixOutputs_lo_hi_hi_hi_4 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_hi_4, _decoded_invMatrixOutputs_T_177)
node decoded_invMatrixOutputs_lo_hi_hi_4 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_4, decoded_invMatrixOutputs_lo_hi_hi_lo_4)
node decoded_invMatrixOutputs_lo_hi_4 = cat(decoded_invMatrixOutputs_lo_hi_hi_4, decoded_invMatrixOutputs_lo_hi_lo_4)
node decoded_invMatrixOutputs_lo_4 = cat(decoded_invMatrixOutputs_lo_hi_4, decoded_invMatrixOutputs_lo_lo_4)
node decoded_invMatrixOutputs_hi_lo_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_181, _decoded_invMatrixOutputs_T_180)
node decoded_invMatrixOutputs_hi_lo_lo_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_184, _decoded_invMatrixOutputs_T_183)
node decoded_invMatrixOutputs_hi_lo_lo_hi_4 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_hi_4, _decoded_invMatrixOutputs_T_182)
node decoded_invMatrixOutputs_hi_lo_lo_4 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_4, decoded_invMatrixOutputs_hi_lo_lo_lo_4)
node decoded_invMatrixOutputs_hi_lo_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_186, _decoded_invMatrixOutputs_T_185)
node decoded_invMatrixOutputs_hi_lo_hi_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_189, _decoded_invMatrixOutputs_T_188)
node decoded_invMatrixOutputs_hi_lo_hi_hi_4 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_hi_4, _decoded_invMatrixOutputs_T_187)
node decoded_invMatrixOutputs_hi_lo_hi_4 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_4, decoded_invMatrixOutputs_hi_lo_hi_lo_4)
node decoded_invMatrixOutputs_hi_lo_4 = cat(decoded_invMatrixOutputs_hi_lo_hi_4, decoded_invMatrixOutputs_hi_lo_lo_4)
node decoded_invMatrixOutputs_hi_hi_lo_lo_4 = cat(_decoded_invMatrixOutputs_T_191, _decoded_invMatrixOutputs_T_190)
node decoded_invMatrixOutputs_hi_hi_lo_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_194, _decoded_invMatrixOutputs_T_193)
node decoded_invMatrixOutputs_hi_hi_lo_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_hi_4, _decoded_invMatrixOutputs_T_192)
node decoded_invMatrixOutputs_hi_hi_lo_4 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_4, decoded_invMatrixOutputs_hi_hi_lo_lo_4)
node decoded_invMatrixOutputs_hi_hi_hi_lo_4 = cat(_decoded_invMatrixOutputs_T_196, _decoded_invMatrixOutputs_T_195)
node decoded_invMatrixOutputs_hi_hi_hi_hi_hi_4 = cat(_decoded_invMatrixOutputs_T_199, _decoded_invMatrixOutputs_T_198)
node decoded_invMatrixOutputs_hi_hi_hi_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_hi_4, _decoded_invMatrixOutputs_T_197)
node decoded_invMatrixOutputs_hi_hi_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_4, decoded_invMatrixOutputs_hi_hi_hi_lo_4)
node decoded_invMatrixOutputs_hi_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_hi_4, decoded_invMatrixOutputs_hi_hi_lo_4)
node decoded_invMatrixOutputs_hi_4 = cat(decoded_invMatrixOutputs_hi_hi_4, decoded_invMatrixOutputs_hi_lo_4)
node decoded_invMatrixOutputs_4 = cat(decoded_invMatrixOutputs_hi_4, decoded_invMatrixOutputs_lo_4)
connect decoded_plaOutput_4, decoded_invMatrixOutputs_4
connect decoded_plaInput_4, addr_4
node _decoded_T_320 = bits(decoded_plaOutput_4, 31, 0)
node _decoded_T_321 = shl(UInt<16>(0hffff), 16)
node _decoded_T_322 = xor(UInt<32>(0hffffffff), _decoded_T_321)
node _decoded_T_323 = shr(_decoded_T_320, 16)
node _decoded_T_324 = and(_decoded_T_323, _decoded_T_322)
node _decoded_T_325 = bits(_decoded_T_320, 15, 0)
node _decoded_T_326 = shl(_decoded_T_325, 16)
node _decoded_T_327 = not(_decoded_T_322)
node _decoded_T_328 = and(_decoded_T_326, _decoded_T_327)
node _decoded_T_329 = or(_decoded_T_324, _decoded_T_328)
node _decoded_T_330 = bits(_decoded_T_322, 23, 0)
node _decoded_T_331 = shl(_decoded_T_330, 8)
node _decoded_T_332 = xor(_decoded_T_322, _decoded_T_331)
node _decoded_T_333 = shr(_decoded_T_329, 8)
node _decoded_T_334 = and(_decoded_T_333, _decoded_T_332)
node _decoded_T_335 = bits(_decoded_T_329, 23, 0)
node _decoded_T_336 = shl(_decoded_T_335, 8)
node _decoded_T_337 = not(_decoded_T_332)
node _decoded_T_338 = and(_decoded_T_336, _decoded_T_337)
node _decoded_T_339 = or(_decoded_T_334, _decoded_T_338)
node _decoded_T_340 = bits(_decoded_T_332, 27, 0)
node _decoded_T_341 = shl(_decoded_T_340, 4)
node _decoded_T_342 = xor(_decoded_T_332, _decoded_T_341)
node _decoded_T_343 = shr(_decoded_T_339, 4)
node _decoded_T_344 = and(_decoded_T_343, _decoded_T_342)
node _decoded_T_345 = bits(_decoded_T_339, 27, 0)
node _decoded_T_346 = shl(_decoded_T_345, 4)
node _decoded_T_347 = not(_decoded_T_342)
node _decoded_T_348 = and(_decoded_T_346, _decoded_T_347)
node _decoded_T_349 = or(_decoded_T_344, _decoded_T_348)
node _decoded_T_350 = bits(_decoded_T_342, 29, 0)
node _decoded_T_351 = shl(_decoded_T_350, 2)
node _decoded_T_352 = xor(_decoded_T_342, _decoded_T_351)
node _decoded_T_353 = shr(_decoded_T_349, 2)
node _decoded_T_354 = and(_decoded_T_353, _decoded_T_352)
node _decoded_T_355 = bits(_decoded_T_349, 29, 0)
node _decoded_T_356 = shl(_decoded_T_355, 2)
node _decoded_T_357 = not(_decoded_T_352)
node _decoded_T_358 = and(_decoded_T_356, _decoded_T_357)
node _decoded_T_359 = or(_decoded_T_354, _decoded_T_358)
node _decoded_T_360 = bits(_decoded_T_352, 30, 0)
node _decoded_T_361 = shl(_decoded_T_360, 1)
node _decoded_T_362 = xor(_decoded_T_352, _decoded_T_361)
node _decoded_T_363 = shr(_decoded_T_359, 1)
node _decoded_T_364 = and(_decoded_T_363, _decoded_T_362)
node _decoded_T_365 = bits(_decoded_T_359, 30, 0)
node _decoded_T_366 = shl(_decoded_T_365, 1)
node _decoded_T_367 = not(_decoded_T_362)
node _decoded_T_368 = and(_decoded_T_366, _decoded_T_367)
node _decoded_T_369 = or(_decoded_T_364, _decoded_T_368)
node _decoded_T_370 = bits(decoded_plaOutput_4, 39, 32)
node _decoded_T_371 = shl(UInt<4>(0hf), 4)
node _decoded_T_372 = xor(UInt<8>(0hff), _decoded_T_371)
node _decoded_T_373 = shr(_decoded_T_370, 4)
node _decoded_T_374 = and(_decoded_T_373, _decoded_T_372)
node _decoded_T_375 = bits(_decoded_T_370, 3, 0)
node _decoded_T_376 = shl(_decoded_T_375, 4)
node _decoded_T_377 = not(_decoded_T_372)
node _decoded_T_378 = and(_decoded_T_376, _decoded_T_377)
node _decoded_T_379 = or(_decoded_T_374, _decoded_T_378)
node _decoded_T_380 = bits(_decoded_T_372, 5, 0)
node _decoded_T_381 = shl(_decoded_T_380, 2)
node _decoded_T_382 = xor(_decoded_T_372, _decoded_T_381)
node _decoded_T_383 = shr(_decoded_T_379, 2)
node _decoded_T_384 = and(_decoded_T_383, _decoded_T_382)
node _decoded_T_385 = bits(_decoded_T_379, 5, 0)
node _decoded_T_386 = shl(_decoded_T_385, 2)
node _decoded_T_387 = not(_decoded_T_382)
node _decoded_T_388 = and(_decoded_T_386, _decoded_T_387)
node _decoded_T_389 = or(_decoded_T_384, _decoded_T_388)
node _decoded_T_390 = bits(_decoded_T_382, 6, 0)
node _decoded_T_391 = shl(_decoded_T_390, 1)
node _decoded_T_392 = xor(_decoded_T_382, _decoded_T_391)
node _decoded_T_393 = shr(_decoded_T_389, 1)
node _decoded_T_394 = and(_decoded_T_393, _decoded_T_392)
node _decoded_T_395 = bits(_decoded_T_389, 6, 0)
node _decoded_T_396 = shl(_decoded_T_395, 1)
node _decoded_T_397 = not(_decoded_T_392)
node _decoded_T_398 = and(_decoded_T_396, _decoded_T_397)
node _decoded_T_399 = or(_decoded_T_394, _decoded_T_398)
node decoded_4 = cat(_decoded_T_369, _decoded_T_399)
node _io_resp_4_vc_sel_0_0_T = bits(decoded_4, 0, 0)
connect io.resp.`4`.vc_sel.`0`[0], _io_resp_4_vc_sel_0_0_T
node _io_resp_4_vc_sel_0_1_T = bits(decoded_4, 1, 1)
connect io.resp.`4`.vc_sel.`0`[1], _io_resp_4_vc_sel_0_1_T
node _io_resp_4_vc_sel_0_2_T = bits(decoded_4, 2, 2)
connect io.resp.`4`.vc_sel.`0`[2], _io_resp_4_vc_sel_0_2_T
node _io_resp_4_vc_sel_0_3_T = bits(decoded_4, 3, 3)
connect io.resp.`4`.vc_sel.`0`[3], _io_resp_4_vc_sel_0_3_T
node _io_resp_4_vc_sel_0_4_T = bits(decoded_4, 4, 4)
connect io.resp.`4`.vc_sel.`0`[4], _io_resp_4_vc_sel_0_4_T
node _io_resp_4_vc_sel_0_5_T = bits(decoded_4, 5, 5)
connect io.resp.`4`.vc_sel.`0`[5], _io_resp_4_vc_sel_0_5_T
node _io_resp_4_vc_sel_0_6_T = bits(decoded_4, 6, 6)
connect io.resp.`4`.vc_sel.`0`[6], _io_resp_4_vc_sel_0_6_T
node _io_resp_4_vc_sel_0_7_T = bits(decoded_4, 7, 7)
connect io.resp.`4`.vc_sel.`0`[7], _io_resp_4_vc_sel_0_7_T
node _io_resp_4_vc_sel_1_0_T = bits(decoded_4, 8, 8)
connect io.resp.`4`.vc_sel.`1`[0], _io_resp_4_vc_sel_1_0_T
node _io_resp_4_vc_sel_1_1_T = bits(decoded_4, 9, 9)
connect io.resp.`4`.vc_sel.`1`[1], _io_resp_4_vc_sel_1_1_T
node _io_resp_4_vc_sel_1_2_T = bits(decoded_4, 10, 10)
connect io.resp.`4`.vc_sel.`1`[2], _io_resp_4_vc_sel_1_2_T
node _io_resp_4_vc_sel_1_3_T = bits(decoded_4, 11, 11)
connect io.resp.`4`.vc_sel.`1`[3], _io_resp_4_vc_sel_1_3_T
node _io_resp_4_vc_sel_1_4_T = bits(decoded_4, 12, 12)
connect io.resp.`4`.vc_sel.`1`[4], _io_resp_4_vc_sel_1_4_T
node _io_resp_4_vc_sel_1_5_T = bits(decoded_4, 13, 13)
connect io.resp.`4`.vc_sel.`1`[5], _io_resp_4_vc_sel_1_5_T
node _io_resp_4_vc_sel_1_6_T = bits(decoded_4, 14, 14)
connect io.resp.`4`.vc_sel.`1`[6], _io_resp_4_vc_sel_1_6_T
node _io_resp_4_vc_sel_1_7_T = bits(decoded_4, 15, 15)
connect io.resp.`4`.vc_sel.`1`[7], _io_resp_4_vc_sel_1_7_T
node _io_resp_4_vc_sel_2_0_T = bits(decoded_4, 16, 16)
connect io.resp.`4`.vc_sel.`2`[0], _io_resp_4_vc_sel_2_0_T
node _io_resp_4_vc_sel_2_1_T = bits(decoded_4, 17, 17)
connect io.resp.`4`.vc_sel.`2`[1], _io_resp_4_vc_sel_2_1_T
node _io_resp_4_vc_sel_2_2_T = bits(decoded_4, 18, 18)
connect io.resp.`4`.vc_sel.`2`[2], _io_resp_4_vc_sel_2_2_T
node _io_resp_4_vc_sel_2_3_T = bits(decoded_4, 19, 19)
connect io.resp.`4`.vc_sel.`2`[3], _io_resp_4_vc_sel_2_3_T
node _io_resp_4_vc_sel_2_4_T = bits(decoded_4, 20, 20)
connect io.resp.`4`.vc_sel.`2`[4], _io_resp_4_vc_sel_2_4_T
node _io_resp_4_vc_sel_2_5_T = bits(decoded_4, 21, 21)
connect io.resp.`4`.vc_sel.`2`[5], _io_resp_4_vc_sel_2_5_T
node _io_resp_4_vc_sel_2_6_T = bits(decoded_4, 22, 22)
connect io.resp.`4`.vc_sel.`2`[6], _io_resp_4_vc_sel_2_6_T
node _io_resp_4_vc_sel_2_7_T = bits(decoded_4, 23, 23)
connect io.resp.`4`.vc_sel.`2`[7], _io_resp_4_vc_sel_2_7_T
node _io_resp_4_vc_sel_3_0_T = bits(decoded_4, 24, 24)
connect io.resp.`4`.vc_sel.`3`[0], _io_resp_4_vc_sel_3_0_T
node _io_resp_4_vc_sel_3_1_T = bits(decoded_4, 25, 25)
connect io.resp.`4`.vc_sel.`3`[1], _io_resp_4_vc_sel_3_1_T
node _io_resp_4_vc_sel_3_2_T = bits(decoded_4, 26, 26)
connect io.resp.`4`.vc_sel.`3`[2], _io_resp_4_vc_sel_3_2_T
node _io_resp_4_vc_sel_3_3_T = bits(decoded_4, 27, 27)
connect io.resp.`4`.vc_sel.`3`[3], _io_resp_4_vc_sel_3_3_T
node _io_resp_4_vc_sel_3_4_T = bits(decoded_4, 28, 28)
connect io.resp.`4`.vc_sel.`3`[4], _io_resp_4_vc_sel_3_4_T
node _io_resp_4_vc_sel_3_5_T = bits(decoded_4, 29, 29)
connect io.resp.`4`.vc_sel.`3`[5], _io_resp_4_vc_sel_3_5_T
node _io_resp_4_vc_sel_3_6_T = bits(decoded_4, 30, 30)
connect io.resp.`4`.vc_sel.`3`[6], _io_resp_4_vc_sel_3_6_T
node _io_resp_4_vc_sel_3_7_T = bits(decoded_4, 31, 31)
connect io.resp.`4`.vc_sel.`3`[7], _io_resp_4_vc_sel_3_7_T
node _io_resp_4_vc_sel_4_0_T = bits(decoded_4, 32, 32)
connect io.resp.`4`.vc_sel.`4`[0], _io_resp_4_vc_sel_4_0_T
node _io_resp_4_vc_sel_4_1_T = bits(decoded_4, 33, 33)
connect io.resp.`4`.vc_sel.`4`[1], _io_resp_4_vc_sel_4_1_T
node _io_resp_4_vc_sel_4_2_T = bits(decoded_4, 34, 34)
connect io.resp.`4`.vc_sel.`4`[2], _io_resp_4_vc_sel_4_2_T
node _io_resp_4_vc_sel_4_3_T = bits(decoded_4, 35, 35)
connect io.resp.`4`.vc_sel.`4`[3], _io_resp_4_vc_sel_4_3_T
node _io_resp_4_vc_sel_4_4_T = bits(decoded_4, 36, 36)
connect io.resp.`4`.vc_sel.`4`[4], _io_resp_4_vc_sel_4_4_T
node _io_resp_4_vc_sel_4_5_T = bits(decoded_4, 37, 37)
connect io.resp.`4`.vc_sel.`4`[5], _io_resp_4_vc_sel_4_5_T
node _io_resp_4_vc_sel_4_6_T = bits(decoded_4, 38, 38)
connect io.resp.`4`.vc_sel.`4`[6], _io_resp_4_vc_sel_4_6_T
node _io_resp_4_vc_sel_4_7_T = bits(decoded_4, 39, 39)
connect io.resp.`4`.vc_sel.`4`[7], _io_resp_4_vc_sel_4_7_T
extmodule plusarg_reader_38 :
output out : UInt<20>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "noc_util_sample_rate=%d"
parameter WIDTH = 20 | module RouteComputer_20( // @[RouteComputer.scala:29:7]
input [2:0] io_req_4_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_4_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_4_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_4_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_4_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_4_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_3_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_3_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_3_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_3_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_3_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_3_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [4:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [1:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_2, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_3, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_4, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_5, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_6, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_3_7, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_2, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_3, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_4, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_5, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_6, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_2_7, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_2, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_3, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_4, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_5, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_6, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_1_7, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_4_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_2, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_3, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_4, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_5, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_6, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_4_7, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_2, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_3, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_4, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_5, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_6, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_2_7, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_3_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_2, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_3, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_4, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_5, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_6, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_4_7, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_2, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_3, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_4, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_5, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_6, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_3_7, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_2, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_3, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_4, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_5, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_6, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_1_7, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_2, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_3, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_4, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_5, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_6, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_4_7, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_3, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_4, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_5, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_6, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_2_7, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_2, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_3, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_4, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_5, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_6, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_4_7, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_2, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_3, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_4, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_5, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_6, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_3_7, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_2, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_3, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_4, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_5, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_6, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_2_7, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_1, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_2, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_3, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_4, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_5, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_6, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_1_7 // @[RouteComputer.scala:40:14]
);
wire [16:0] decoded_invInputs = ~{io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [16:0] _decoded_andMatrixOutputs_T = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_1 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_2 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_3 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_5 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_6 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_7 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_8 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_10 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_11 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_12 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_13 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_15 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_16 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_17 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_18 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_20 = {decoded_invInputs[0], decoded_invInputs[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_21 = {decoded_invInputs[0], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_23 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_24 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_25 = {decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_27 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_28 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_29 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_30 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_32 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_33 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_34 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_35 = {io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_37 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_38 = {decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_40 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_41 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_42 = {decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] decoded_invInputs_1 = ~{io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [14:0] _decoded_andMatrixOutputs_T_45 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_47 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_49 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_50 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_51 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_52 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_55 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_56 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_57 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_58 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_59 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_60 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_62 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_65 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_68 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_69 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_70 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_71 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_72 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_73 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_74 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_75 = {decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_76 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_77 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_79 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_80 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_81 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_82 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_83 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_84 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_86 = {decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_87 = {decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_92 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_93 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_94 = {decoded_invInputs_1[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_95 = {decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_96 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_97 = {decoded_invInputs_1[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_98 = {decoded_invInputs_1[0], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_99 = {decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [1:0] decoded_orMatrixOutputs_hi_hi_39 = {&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47}; // @[pla.scala:98:{53,70}, :114:19]
wire [16:0] decoded_invInputs_2 = ~{io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [14:0] _decoded_andMatrixOutputs_T_100 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_102 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [8:0] _decoded_andMatrixOutputs_T_104 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_105 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_106 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_113 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_114 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_115 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_116 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_117 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_118 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_120 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_121 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_122 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_124 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [8:0] _decoded_andMatrixOutputs_T_126 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_127 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_128 = {io_req_2_bits_flow_egress_node_id[0], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_135 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_136 = {decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_137 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_138 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_139 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_140 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_142 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_143 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_144 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_145 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_146 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_147 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [8:0] _decoded_andMatrixOutputs_T_148 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_149 = {decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_150 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_151 = {decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_152 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_154 = {decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_155 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_156 = {decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_157 = {decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_158 = {decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_164 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_165 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_166 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_167 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_168 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_169 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_170 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_171 = {decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_172 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_173 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_174 = {decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[1], io_req_2_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] decoded_invInputs_3 = ~{io_req_3_bits_flow_vnet_id, io_req_3_bits_flow_ingress_node, io_req_3_bits_flow_ingress_node_id, io_req_3_bits_flow_egress_node, io_req_3_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [14:0] _decoded_andMatrixOutputs_T_176 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [7:0] _decoded_andMatrixOutputs_T_178 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[2], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_179 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_180 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_181 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_182 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_185 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_186 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_187 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_188 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_189 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_190 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_193 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_197 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_198 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_199 = {io_req_3_bits_flow_egress_node_id[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_200 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_201 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_202 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_203 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_204 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_205 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_206 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_207 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_209 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_210 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_211 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_212 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_214 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_215 = {io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_217 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_221 = {decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_222 = {decoded_invInputs_3[0], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_223 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_224 = {decoded_invInputs_3[0], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_225 = {decoded_invInputs_3[0], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[0], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_226 = {decoded_invInputs_3[0], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [14:0] _decoded_andMatrixOutputs_T_227 = {decoded_invInputs_3[0], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_228 = {decoded_invInputs_3[0], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_229 = {decoded_invInputs_3[0], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[1], io_req_3_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [1:0] decoded_orMatrixOutputs_hi_hi_87 = {&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178}; // @[pla.scala:98:{53,70}, :114:19]
wire [16:0] decoded_invInputs_4 = ~{io_req_4_bits_flow_vnet_id, io_req_4_bits_flow_ingress_node, io_req_4_bits_flow_ingress_node_id, io_req_4_bits_flow_egress_node, io_req_4_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [2:0] _decoded_andMatrixOutputs_T_230 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_232 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_233 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_240 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_241 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_242 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_243 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_244 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_245 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_246 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_248 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [8:0] _decoded_andMatrixOutputs_T_249 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_251 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_253 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_254 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_255 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_261 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_262 = {decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], io_req_4_bits_flow_ingress_node_id[1], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_263 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_264 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_265 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_266 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_267 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_269 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [8:0] _decoded_andMatrixOutputs_T_270 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_271 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_272 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_273 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_274 = {io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_275 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_276 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_277 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_278 = {decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_280 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_282 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_284 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_286 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_289 = {decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_290 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_291 = {decoded_invInputs_4[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_292 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_293 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_294 = {decoded_invInputs_4[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_295 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_296 = {decoded_invInputs_4[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_297 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [15:0] _decoded_andMatrixOutputs_T_298 = {decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
wire [16:0] _decoded_andMatrixOutputs_T_299 = {decoded_invInputs_4[0], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[1], io_req_4_bits_src_virt_id[2]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53]
assign io_resp_4_vc_sel_3_1 = |{&{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_3_2 = |{&_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_3_3 = |{&_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_280}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_3_4 = |{&_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_280, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_3_5 = |{&_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_290, &_decoded_andMatrixOutputs_T_292, &_decoded_andMatrixOutputs_T_293, &_decoded_andMatrixOutputs_T_295, &_decoded_andMatrixOutputs_T_297, &_decoded_andMatrixOutputs_T_298}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_3_6 = |{&_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_290, &_decoded_andMatrixOutputs_T_292, &_decoded_andMatrixOutputs_T_293, &_decoded_andMatrixOutputs_T_295, &_decoded_andMatrixOutputs_T_297, &_decoded_andMatrixOutputs_T_298}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_3_7 = |{&_decoded_andMatrixOutputs_T_243, &_decoded_andMatrixOutputs_T_248, &_decoded_andMatrixOutputs_T_264, &_decoded_andMatrixOutputs_T_269, &_decoded_andMatrixOutputs_T_276, &_decoded_andMatrixOutputs_T_280, &_decoded_andMatrixOutputs_T_290, &_decoded_andMatrixOutputs_T_292, &_decoded_andMatrixOutputs_T_293, &_decoded_andMatrixOutputs_T_295, &_decoded_andMatrixOutputs_T_297, &_decoded_andMatrixOutputs_T_298}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_0 = &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node_id[1], io_req_4_bits_flow_egress_node[0], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], decoded_invInputs_4[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_4_vc_sel_2_1 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[2], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_2 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_271, &_decoded_andMatrixOutputs_T_273}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_3 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_255, &{decoded_invInputs_4[0], decoded_invInputs_4[3], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_271, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_277}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_255, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_271, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_277, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}, &{decoded_invInputs_4[0], decoded_invInputs_4[1], decoded_invInputs_4[3], io_req_4_bits_flow_egress_node[2], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], io_req_4_bits_flow_ingress_node[2], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], decoded_invInputs_4[14], decoded_invInputs_4[15], io_req_4_bits_flow_vnet_id[2], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_5 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_255, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_271, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_291, &_decoded_andMatrixOutputs_T_294, &_decoded_andMatrixOutputs_T_296, &_decoded_andMatrixOutputs_T_299}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_255, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_271, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_291, &_decoded_andMatrixOutputs_T_294, &_decoded_andMatrixOutputs_T_296, &_decoded_andMatrixOutputs_T_299}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_2_7 = |{&_decoded_andMatrixOutputs_T_232, &_decoded_andMatrixOutputs_T_233, &_decoded_andMatrixOutputs_T_240, &_decoded_andMatrixOutputs_T_241, &_decoded_andMatrixOutputs_T_244, &_decoded_andMatrixOutputs_T_246, &_decoded_andMatrixOutputs_T_254, &_decoded_andMatrixOutputs_T_255, &_decoded_andMatrixOutputs_T_261, &_decoded_andMatrixOutputs_T_262, &_decoded_andMatrixOutputs_T_265, &_decoded_andMatrixOutputs_T_267, &_decoded_andMatrixOutputs_T_271, &_decoded_andMatrixOutputs_T_273, &_decoded_andMatrixOutputs_T_277, &_decoded_andMatrixOutputs_T_291, &_decoded_andMatrixOutputs_T_294, &_decoded_andMatrixOutputs_T_296, &_decoded_andMatrixOutputs_T_299}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_1 = |{&{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_242, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_263, &{io_req_4_bits_flow_egress_node_id[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], io_req_4_bits_flow_ingress_node_id[0], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], decoded_invInputs_4[15], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_2 = |{&_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_266}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_3 = |{&_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_245, &{decoded_invInputs_4[0], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], io_req_4_bits_flow_ingress_node[0], decoded_invInputs_4[10], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &{decoded_invInputs_4[0], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[0], io_req_4_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_266, &_decoded_andMatrixOutputs_T_275, &{decoded_invInputs_4[0], decoded_invInputs_4[1], io_req_4_bits_flow_egress_node[1], decoded_invInputs_4[4], decoded_invInputs_4[5], decoded_invInputs_4[6], decoded_invInputs_4[7], decoded_invInputs_4[8], decoded_invInputs_4[9], io_req_4_bits_flow_ingress_node[1], decoded_invInputs_4[11], io_req_4_bits_flow_ingress_node[3], decoded_invInputs_4[13], io_req_4_bits_flow_vnet_id[0], io_req_4_bits_flow_vnet_id[1], decoded_invInputs_4[16], io_req_4_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_4 = |{&_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_266, &_decoded_andMatrixOutputs_T_275, &_decoded_andMatrixOutputs_T_278}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_5 = |{&_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_266, &_decoded_andMatrixOutputs_T_275, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_290, &_decoded_andMatrixOutputs_T_292, &_decoded_andMatrixOutputs_T_293, &_decoded_andMatrixOutputs_T_295, &_decoded_andMatrixOutputs_T_297, &_decoded_andMatrixOutputs_T_298}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_6 = |{&_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_266, &_decoded_andMatrixOutputs_T_275, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_290, &_decoded_andMatrixOutputs_T_292, &_decoded_andMatrixOutputs_T_293, &_decoded_andMatrixOutputs_T_295, &_decoded_andMatrixOutputs_T_297, &_decoded_andMatrixOutputs_T_298}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_1_7 = |{&_decoded_andMatrixOutputs_T_242, &_decoded_andMatrixOutputs_T_245, &_decoded_andMatrixOutputs_T_263, &_decoded_andMatrixOutputs_T_266, &_decoded_andMatrixOutputs_T_275, &_decoded_andMatrixOutputs_T_278, &_decoded_andMatrixOutputs_T_290, &_decoded_andMatrixOutputs_T_292, &_decoded_andMatrixOutputs_T_293, &_decoded_andMatrixOutputs_T_295, &_decoded_andMatrixOutputs_T_297, &_decoded_andMatrixOutputs_T_298}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_0 = &_decoded_andMatrixOutputs_T_230; // @[pla.scala:98:{53,70}]
assign io_resp_4_vc_sel_0_1 = &_decoded_andMatrixOutputs_T_230; // @[pla.scala:98:{53,70}]
assign io_resp_4_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_249, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_270, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_274}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_249, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_270, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_274}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_249, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_270, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_274, &_decoded_andMatrixOutputs_T_282, &_decoded_andMatrixOutputs_T_284, &_decoded_andMatrixOutputs_T_286, &_decoded_andMatrixOutputs_T_289}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_249, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_270, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_274, &_decoded_andMatrixOutputs_T_282, &_decoded_andMatrixOutputs_T_284, &_decoded_andMatrixOutputs_T_286, &_decoded_andMatrixOutputs_T_289}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_249, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_270, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_274, &_decoded_andMatrixOutputs_T_282, &_decoded_andMatrixOutputs_T_284, &_decoded_andMatrixOutputs_T_286, &_decoded_andMatrixOutputs_T_289}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_4_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_230, &_decoded_andMatrixOutputs_T_249, &_decoded_andMatrixOutputs_T_251, &_decoded_andMatrixOutputs_T_253, &_decoded_andMatrixOutputs_T_270, &_decoded_andMatrixOutputs_T_272, &_decoded_andMatrixOutputs_T_274, &_decoded_andMatrixOutputs_T_282, &_decoded_andMatrixOutputs_T_284, &_decoded_andMatrixOutputs_T_286, &_decoded_andMatrixOutputs_T_289}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_0 = &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], decoded_invInputs_3[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], io_req_3_bits_flow_ingress_node_id[1], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], decoded_invInputs_3[16]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_3_vc_sel_4_1 = |{&_decoded_andMatrixOutputs_T_180, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_186, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_203, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], io_req_3_bits_flow_egress_node[2], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_2 = |{&_decoded_andMatrixOutputs_T_180, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_190, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_3 = |{&_decoded_andMatrixOutputs_T_180, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_199, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_211}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_4 = |{&_decoded_andMatrixOutputs_T_180, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_199, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_211, &{decoded_invInputs_3[0], decoded_invInputs_3[1], io_req_3_bits_flow_egress_node[1], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_5 = |{&_decoded_andMatrixOutputs_T_180, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_199, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_211, &_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_227}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_6 = |{&_decoded_andMatrixOutputs_T_180, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_199, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_211, &_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_227}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_4_7 = |{&_decoded_andMatrixOutputs_T_180, &_decoded_andMatrixOutputs_T_186, &_decoded_andMatrixOutputs_T_190, &_decoded_andMatrixOutputs_T_199, &_decoded_andMatrixOutputs_T_203, &_decoded_andMatrixOutputs_T_207, &_decoded_andMatrixOutputs_T_211, &_decoded_andMatrixOutputs_T_223, &_decoded_andMatrixOutputs_T_227}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_0 = &{decoded_invInputs_3[0], io_req_3_bits_flow_egress_node_id[1], io_req_3_bits_flow_egress_node[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_3_vc_sel_2_1 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], decoded_invInputs_3[12], decoded_invInputs_3[13], io_req_3_bits_flow_vnet_id[0], decoded_invInputs_3[15], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_2 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &{io_req_3_bits_flow_egress_node_id[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], io_req_3_bits_flow_ingress_node_id[0], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], io_req_3_bits_flow_vnet_id[1], decoded_invInputs_3[16], io_req_3_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_209, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_3 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_209, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_209, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &{decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}, &{decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[3], decoded_invInputs_3[4], io_req_3_bits_flow_egress_node[3], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], io_req_3_bits_flow_ingress_node[2], decoded_invInputs_3[12], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}, &{decoded_invInputs_3[0], decoded_invInputs_3[1], decoded_invInputs_3[3], io_req_3_bits_flow_egress_node[2], decoded_invInputs_3[5], decoded_invInputs_3[6], decoded_invInputs_3[7], decoded_invInputs_3[8], io_req_3_bits_flow_ingress_node[0], io_req_3_bits_flow_ingress_node[1], decoded_invInputs_3[11], io_req_3_bits_flow_ingress_node[3], decoded_invInputs_3[13], decoded_invInputs_3[14], decoded_invInputs_3[15], io_req_3_bits_flow_vnet_id[2], io_req_3_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_5 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_209, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_222, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_225, &_decoded_andMatrixOutputs_T_226, &_decoded_andMatrixOutputs_T_228, &_decoded_andMatrixOutputs_T_229}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_209, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_222, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_225, &_decoded_andMatrixOutputs_T_226, &_decoded_andMatrixOutputs_T_228, &_decoded_andMatrixOutputs_T_229}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_2_7 = |{&_decoded_andMatrixOutputs_T_179, &_decoded_andMatrixOutputs_T_181, &_decoded_andMatrixOutputs_T_182, &_decoded_andMatrixOutputs_T_185, &_decoded_andMatrixOutputs_T_187, &_decoded_andMatrixOutputs_T_188, &_decoded_andMatrixOutputs_T_189, &_decoded_andMatrixOutputs_T_198, &_decoded_andMatrixOutputs_T_200, &_decoded_andMatrixOutputs_T_201, &_decoded_andMatrixOutputs_T_202, &_decoded_andMatrixOutputs_T_204, &_decoded_andMatrixOutputs_T_205, &_decoded_andMatrixOutputs_T_206, &_decoded_andMatrixOutputs_T_209, &_decoded_andMatrixOutputs_T_212, &_decoded_andMatrixOutputs_T_214, &_decoded_andMatrixOutputs_T_222, &_decoded_andMatrixOutputs_T_224, &_decoded_andMatrixOutputs_T_225, &_decoded_andMatrixOutputs_T_226, &_decoded_andMatrixOutputs_T_228, &_decoded_andMatrixOutputs_T_229}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_0_0 = |decoded_orMatrixOutputs_hi_hi_87; // @[pla.scala:114:{19,36}]
assign io_resp_3_vc_sel_0_1 = |decoded_orMatrixOutputs_hi_hi_87; // @[pla.scala:114:{19,36}]
assign io_resp_3_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_210, &_decoded_andMatrixOutputs_T_215}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_210, &_decoded_andMatrixOutputs_T_215}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_210, &_decoded_andMatrixOutputs_T_215, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_221}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_210, &_decoded_andMatrixOutputs_T_215, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_221}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_210, &_decoded_andMatrixOutputs_T_215, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_221}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_3_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_176, &_decoded_andMatrixOutputs_T_178, &_decoded_andMatrixOutputs_T_193, &_decoded_andMatrixOutputs_T_197, &_decoded_andMatrixOutputs_T_210, &_decoded_andMatrixOutputs_T_215, &_decoded_andMatrixOutputs_T_217, &_decoded_andMatrixOutputs_T_221}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_0 = |{&{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node_id[1], decoded_invInputs_2[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], io_req_2_bits_flow_ingress_node_id[1], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], decoded_invInputs_2[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_1 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_2 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_118, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_140, &_decoded_andMatrixOutputs_T_145, &_decoded_andMatrixOutputs_T_147}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_3 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_140, &_decoded_andMatrixOutputs_T_145, &_decoded_andMatrixOutputs_T_147, &{decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_4 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_140, &_decoded_andMatrixOutputs_T_145, &_decoded_andMatrixOutputs_T_147, &_decoded_andMatrixOutputs_T_152, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[2], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[10], decoded_invInputs_2[11], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_5 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_140, &_decoded_andMatrixOutputs_T_145, &_decoded_andMatrixOutputs_T_147, &_decoded_andMatrixOutputs_T_152, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_171}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_6 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_140, &_decoded_andMatrixOutputs_T_145, &_decoded_andMatrixOutputs_T_147, &_decoded_andMatrixOutputs_T_152, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_171}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_4_7 = |{&_decoded_andMatrixOutputs_T_105, &_decoded_andMatrixOutputs_T_106, &_decoded_andMatrixOutputs_T_113, &_decoded_andMatrixOutputs_T_114, &_decoded_andMatrixOutputs_T_118, &_decoded_andMatrixOutputs_T_127, &_decoded_andMatrixOutputs_T_128, &_decoded_andMatrixOutputs_T_135, &_decoded_andMatrixOutputs_T_136, &_decoded_andMatrixOutputs_T_140, &_decoded_andMatrixOutputs_T_145, &_decoded_andMatrixOutputs_T_147, &_decoded_andMatrixOutputs_T_152, &_decoded_andMatrixOutputs_T_165, &_decoded_andMatrixOutputs_T_166, &_decoded_andMatrixOutputs_T_170, &_decoded_andMatrixOutputs_T_171}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_1 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_2 = |{&_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_3 = |{&_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}, &{decoded_invInputs_2[0], decoded_invInputs_2[4], io_req_2_bits_flow_egress_node[3], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}, &{decoded_invInputs_2[0], io_req_2_bits_flow_egress_node[2], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_151, &_decoded_andMatrixOutputs_T_155}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_4 = |{&_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_151, &_decoded_andMatrixOutputs_T_155, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], decoded_invInputs_2[9], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}, &{decoded_invInputs_2[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], decoded_invInputs_2[14], decoded_invInputs_2[15], io_req_2_bits_flow_vnet_id[2], io_req_2_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_5 = |{&_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_151, &_decoded_andMatrixOutputs_T_155, &_decoded_andMatrixOutputs_T_167, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_169, &_decoded_andMatrixOutputs_T_172, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_174}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_6 = |{&_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_151, &_decoded_andMatrixOutputs_T_155, &_decoded_andMatrixOutputs_T_167, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_169, &_decoded_andMatrixOutputs_T_172, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_174}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_3_7 = |{&_decoded_andMatrixOutputs_T_116, &_decoded_andMatrixOutputs_T_117, &_decoded_andMatrixOutputs_T_121, &_decoded_andMatrixOutputs_T_138, &_decoded_andMatrixOutputs_T_139, &_decoded_andMatrixOutputs_T_143, &_decoded_andMatrixOutputs_T_150, &_decoded_andMatrixOutputs_T_151, &_decoded_andMatrixOutputs_T_155, &_decoded_andMatrixOutputs_T_167, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_169, &_decoded_andMatrixOutputs_T_172, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_174}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_1 = |{&{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}, &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[1], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], io_req_2_bits_flow_ingress_node_id[0], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], decoded_invInputs_2[15], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_2 = |{&_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_3 = |{&_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &{decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], io_req_2_bits_flow_ingress_node[2], decoded_invInputs_2[12], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}, &{decoded_invInputs_2[0], decoded_invInputs_2[4], decoded_invInputs_2[5], decoded_invInputs_2[6], decoded_invInputs_2[7], decoded_invInputs_2[8], io_req_2_bits_flow_ingress_node[0], decoded_invInputs_2[10], decoded_invInputs_2[11], io_req_2_bits_flow_ingress_node[3], decoded_invInputs_2[13], io_req_2_bits_flow_vnet_id[0], io_req_2_bits_flow_vnet_id[1], decoded_invInputs_2[16], io_req_2_bits_src_virt_id[0], io_req_2_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_154}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_4 = |{&_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_154}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_5 = |{&_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_154, &_decoded_andMatrixOutputs_T_167, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_169, &_decoded_andMatrixOutputs_T_172, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_174}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_6 = |{&_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_154, &_decoded_andMatrixOutputs_T_167, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_169, &_decoded_andMatrixOutputs_T_172, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_174}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_1_7 = |{&_decoded_andMatrixOutputs_T_115, &_decoded_andMatrixOutputs_T_120, &_decoded_andMatrixOutputs_T_137, &_decoded_andMatrixOutputs_T_142, &_decoded_andMatrixOutputs_T_149, &_decoded_andMatrixOutputs_T_154, &_decoded_andMatrixOutputs_T_167, &_decoded_andMatrixOutputs_T_168, &_decoded_andMatrixOutputs_T_169, &_decoded_andMatrixOutputs_T_172, &_decoded_andMatrixOutputs_T_173, &_decoded_andMatrixOutputs_T_174}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_0 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_1 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_122, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_126, &_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_122, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_126, &_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_122, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_126, &_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_156, &_decoded_andMatrixOutputs_T_157, &_decoded_andMatrixOutputs_T_158, &_decoded_andMatrixOutputs_T_164}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_122, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_126, &_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_156, &_decoded_andMatrixOutputs_T_157, &_decoded_andMatrixOutputs_T_158, &_decoded_andMatrixOutputs_T_164}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_122, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_126, &_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_156, &_decoded_andMatrixOutputs_T_157, &_decoded_andMatrixOutputs_T_158, &_decoded_andMatrixOutputs_T_164}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_2_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_100, &_decoded_andMatrixOutputs_T_102, &_decoded_andMatrixOutputs_T_104, &_decoded_andMatrixOutputs_T_122, &_decoded_andMatrixOutputs_T_124, &_decoded_andMatrixOutputs_T_126, &_decoded_andMatrixOutputs_T_144, &_decoded_andMatrixOutputs_T_146, &_decoded_andMatrixOutputs_T_148, &_decoded_andMatrixOutputs_T_156, &_decoded_andMatrixOutputs_T_157, &_decoded_andMatrixOutputs_T_158, &_decoded_andMatrixOutputs_T_164}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_0 = |{&{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}, &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], decoded_invInputs_1[16]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_1 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], io_req_1_bits_flow_egress_node[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_2 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &_decoded_andMatrixOutputs_T_60, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_80, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_3 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &_decoded_andMatrixOutputs_T_60, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_80, &_decoded_andMatrixOutputs_T_83}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_4 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &_decoded_andMatrixOutputs_T_60, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_80, &_decoded_andMatrixOutputs_T_83, &{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}, &{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[2], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[10], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_5 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &_decoded_andMatrixOutputs_T_60, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_80, &_decoded_andMatrixOutputs_T_83, &_decoded_andMatrixOutputs_T_92, &_decoded_andMatrixOutputs_T_93, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_97}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_6 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &_decoded_andMatrixOutputs_T_60, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_80, &_decoded_andMatrixOutputs_T_83, &_decoded_andMatrixOutputs_T_92, &_decoded_andMatrixOutputs_T_93, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_97}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_4_7 = |{&_decoded_andMatrixOutputs_T_49, &_decoded_andMatrixOutputs_T_51, &_decoded_andMatrixOutputs_T_55, &_decoded_andMatrixOutputs_T_57, &_decoded_andMatrixOutputs_T_60, &_decoded_andMatrixOutputs_T_68, &_decoded_andMatrixOutputs_T_70, &_decoded_andMatrixOutputs_T_72, &_decoded_andMatrixOutputs_T_74, &_decoded_andMatrixOutputs_T_77, &_decoded_andMatrixOutputs_T_80, &_decoded_andMatrixOutputs_T_83, &_decoded_andMatrixOutputs_T_92, &_decoded_andMatrixOutputs_T_93, &_decoded_andMatrixOutputs_T_96, &_decoded_andMatrixOutputs_T_97}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_0 = &{decoded_invInputs_1[0], io_req_1_bits_flow_egress_node_id[1], io_req_1_bits_flow_egress_node[0]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}]
assign io_resp_1_vc_sel_2_1 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], io_req_1_bits_flow_ingress_node[0], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[15], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[0]}, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_2 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_flow_vnet_id[1], decoded_invInputs_1[16], io_req_1_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_84}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_3 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_84}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_84, &{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[3], io_req_1_bits_flow_egress_node[2], decoded_invInputs_1[5], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}, &{decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], io_req_1_bits_flow_egress_node[3], decoded_invInputs_1[6], decoded_invInputs_1[7], decoded_invInputs_1[8], decoded_invInputs_1[9], io_req_1_bits_flow_ingress_node[1], decoded_invInputs_1[11], decoded_invInputs_1[12], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[15], io_req_1_bits_flow_vnet_id[2], io_req_1_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_5 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_84, &_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_95, &_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_99}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_84, &_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_95, &_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_99}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_2_7 = |{&_decoded_andMatrixOutputs_T_50, &_decoded_andMatrixOutputs_T_52, &_decoded_andMatrixOutputs_T_56, &_decoded_andMatrixOutputs_T_58, &_decoded_andMatrixOutputs_T_59, &_decoded_andMatrixOutputs_T_69, &_decoded_andMatrixOutputs_T_71, &_decoded_andMatrixOutputs_T_73, &_decoded_andMatrixOutputs_T_75, &_decoded_andMatrixOutputs_T_76, &_decoded_andMatrixOutputs_T_81, &_decoded_andMatrixOutputs_T_84, &_decoded_andMatrixOutputs_T_94, &_decoded_andMatrixOutputs_T_95, &_decoded_andMatrixOutputs_T_98, &_decoded_andMatrixOutputs_T_99}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_0 = |decoded_orMatrixOutputs_hi_hi_39; // @[pla.scala:114:{19,36}]
assign io_resp_1_vc_sel_0_1 = |decoded_orMatrixOutputs_hi_hi_39; // @[pla.scala:114:{19,36}]
assign io_resp_1_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_82}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_82, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_82, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_82, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_1_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_45, &_decoded_andMatrixOutputs_T_47, &_decoded_andMatrixOutputs_T_62, &_decoded_andMatrixOutputs_T_65, &_decoded_andMatrixOutputs_T_79, &_decoded_andMatrixOutputs_T_82, &_decoded_andMatrixOutputs_T_86, &_decoded_andMatrixOutputs_T_87}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_1 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_2 = |{&_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_33}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_3 = |{&_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_16, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_33, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], io_req_0_bits_flow_egress_node[2], io_req_0_bits_flow_egress_node[3], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_4 = |{&_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_24, &_decoded_andMatrixOutputs_T_33, &_decoded_andMatrixOutputs_T_41}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_5 = |{&_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_24, &_decoded_andMatrixOutputs_T_33, &_decoded_andMatrixOutputs_T_41}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_6 = |{&_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_24, &_decoded_andMatrixOutputs_T_33, &_decoded_andMatrixOutputs_T_41}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_4_7 = |{&_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_16, &_decoded_andMatrixOutputs_T_24, &_decoded_andMatrixOutputs_T_33, &_decoded_andMatrixOutputs_T_41}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_1 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_2 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_3 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34, &_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_4 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34, &_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_5 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34, &_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_6 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34, &_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_3_7 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_15, &_decoded_andMatrixOutputs_T_17, &_decoded_andMatrixOutputs_T_23, &_decoded_andMatrixOutputs_T_25, &_decoded_andMatrixOutputs_T_32, &_decoded_andMatrixOutputs_T_34, &_decoded_andMatrixOutputs_T_40, &_decoded_andMatrixOutputs_T_42}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_1 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_2 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_3 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_20, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35, &_decoded_andMatrixOutputs_T_37}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_20, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35, &_decoded_andMatrixOutputs_T_37}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_5 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_20, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35, &_decoded_andMatrixOutputs_T_37}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_20, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35, &_decoded_andMatrixOutputs_T_37}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_2_7 = |{&_decoded_andMatrixOutputs_T, &_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_8, &_decoded_andMatrixOutputs_T_10, &_decoded_andMatrixOutputs_T_11, &_decoded_andMatrixOutputs_T_13, &_decoded_andMatrixOutputs_T_18, &_decoded_andMatrixOutputs_T_20, &_decoded_andMatrixOutputs_T_27, &_decoded_andMatrixOutputs_T_28, &_decoded_andMatrixOutputs_T_30, &_decoded_andMatrixOutputs_T_35, &_decoded_andMatrixOutputs_T_37}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_1 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[1]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_2 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_29}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_3 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_12, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], io_req_0_bits_src_virt_id[1]}, &_decoded_andMatrixOutputs_T_29, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[4], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[12], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[2]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_4 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_29, &_decoded_andMatrixOutputs_T_38}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_5 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_29, &_decoded_andMatrixOutputs_T_38}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_6 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_29, &_decoded_andMatrixOutputs_T_38}; // @[pla.scala:98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_1_7 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_12, &_decoded_andMatrixOutputs_T_21, &_decoded_andMatrixOutputs_T_29, &_decoded_andMatrixOutputs_T_38}; // @[pla.scala:98:{53,70}, :114:{19,36}]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_9 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h3))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h2))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 3)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<4>(0h8))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h4))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_43
connect _source_ok_WIRE[9], _source_ok_T_44
connect _source_ok_WIRE[10], _source_ok_T_45
node _source_ok_T_46 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[2])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[3])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[4])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[5])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[6])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[7])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[8])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_54, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<2>(0h3))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_77 = shr(io.in.a.bits.source, 3)
node _T_78 = eq(_T_77, UInt<2>(0h2))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_90 = shr(io.in.a.bits.source, 3)
node _T_91 = eq(_T_90, UInt<4>(0h8))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<3>(0h4))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = or(_T_104, _T_109)
node _T_111 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_112 = eq(_T_111, UInt<1>(0h0))
node _T_113 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_114 = cvt(_T_113)
node _T_115 = and(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = asSInt(_T_115)
node _T_117 = eq(_T_116, asSInt(UInt<1>(0h0)))
node _T_118 = or(_T_112, _T_117)
node _T_119 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = or(_T_120, _T_125)
node _T_127 = and(_T_11, _T_24)
node _T_128 = and(_T_127, _T_37)
node _T_129 = and(_T_128, _T_50)
node _T_130 = and(_T_129, _T_63)
node _T_131 = and(_T_130, _T_76)
node _T_132 = and(_T_131, _T_89)
node _T_133 = and(_T_132, _T_102)
node _T_134 = and(_T_133, _T_110)
node _T_135 = and(_T_134, _T_118)
node _T_136 = and(_T_135, _T_126)
node _T_137 = asUInt(reset)
node _T_138 = eq(_T_137, UInt<1>(0h0))
when _T_138 :
node _T_139 = eq(_T_136, UInt<1>(0h0))
when _T_139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_136, UInt<1>(0h1), "") : assert_1
node _T_140 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_140 :
node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_142 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_151 = shr(io.in.a.bits.source, 2)
node _T_152 = eq(_T_151, UInt<1>(0h1))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_157 = shr(io.in.a.bits.source, 2)
node _T_158 = eq(_T_157, UInt<2>(0h2))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_162 = and(_T_160, _T_161)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_163 = shr(io.in.a.bits.source, 2)
node _T_164 = eq(_T_163, UInt<2>(0h3))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_168 = and(_T_166, _T_167)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_169 = shr(io.in.a.bits.source, 3)
node _T_170 = eq(_T_169, UInt<2>(0h3))
node _T_171 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_172 = and(_T_170, _T_171)
node _T_173 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_174 = and(_T_172, _T_173)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_175 = shr(io.in.a.bits.source, 3)
node _T_176 = eq(_T_175, UInt<2>(0h2))
node _T_177 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_178 = and(_T_176, _T_177)
node _T_179 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_180 = and(_T_178, _T_179)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_181 = shr(io.in.a.bits.source, 3)
node _T_182 = eq(_T_181, UInt<4>(0h8))
node _T_183 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_184 = and(_T_182, _T_183)
node _T_185 = leq(uncommonBits_13, UInt<3>(0h4))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_188 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_189 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_190 = or(_T_144, _T_150)
node _T_191 = or(_T_190, _T_156)
node _T_192 = or(_T_191, _T_162)
node _T_193 = or(_T_192, _T_168)
node _T_194 = or(_T_193, _T_174)
node _T_195 = or(_T_194, _T_180)
node _T_196 = or(_T_195, _T_186)
node _T_197 = or(_T_196, _T_187)
node _T_198 = or(_T_197, _T_188)
node _T_199 = or(_T_198, _T_189)
node _T_200 = and(_T_143, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = and(_T_202, _T_207)
node _T_209 = or(UInt<1>(0h0), _T_208)
node _T_210 = and(_T_201, _T_209)
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_210, UInt<1>(0h1), "") : assert_2
node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_215 = shr(io.in.a.bits.source, 2)
node _T_216 = eq(_T_215, UInt<1>(0h0))
node _T_217 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_218 = and(_T_216, _T_217)
node _T_219 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_220 = and(_T_218, _T_219)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_221 = shr(io.in.a.bits.source, 2)
node _T_222 = eq(_T_221, UInt<1>(0h1))
node _T_223 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_224 = and(_T_222, _T_223)
node _T_225 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_226 = and(_T_224, _T_225)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_227 = shr(io.in.a.bits.source, 2)
node _T_228 = eq(_T_227, UInt<2>(0h2))
node _T_229 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_230 = and(_T_228, _T_229)
node _T_231 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_232 = and(_T_230, _T_231)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_233 = shr(io.in.a.bits.source, 2)
node _T_234 = eq(_T_233, UInt<2>(0h3))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_239 = shr(io.in.a.bits.source, 3)
node _T_240 = eq(_T_239, UInt<2>(0h3))
node _T_241 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_242 = and(_T_240, _T_241)
node _T_243 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_244 = and(_T_242, _T_243)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_245 = shr(io.in.a.bits.source, 3)
node _T_246 = eq(_T_245, UInt<2>(0h2))
node _T_247 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_248 = and(_T_246, _T_247)
node _T_249 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_250 = and(_T_248, _T_249)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0)
node _T_251 = shr(io.in.a.bits.source, 3)
node _T_252 = eq(_T_251, UInt<4>(0h8))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_20, UInt<3>(0h4))
node _T_256 = and(_T_254, _T_255)
node _T_257 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_258 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_259 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_214
connect _WIRE[1], _T_220
connect _WIRE[2], _T_226
connect _WIRE[3], _T_232
connect _WIRE[4], _T_238
connect _WIRE[5], _T_244
connect _WIRE[6], _T_250
connect _WIRE[7], _T_256
connect _WIRE[8], _T_257
connect _WIRE[9], _T_258
connect _WIRE[10], _T_259
node _T_260 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_261 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_262 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_263 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_264 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_265 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_266 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_267 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_268 = mux(_WIRE[7], _T_260, UInt<1>(0h0))
node _T_269 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_272 = or(_T_261, _T_262)
node _T_273 = or(_T_272, _T_263)
node _T_274 = or(_T_273, _T_264)
node _T_275 = or(_T_274, _T_265)
node _T_276 = or(_T_275, _T_266)
node _T_277 = or(_T_276, _T_267)
node _T_278 = or(_T_277, _T_268)
node _T_279 = or(_T_278, _T_269)
node _T_280 = or(_T_279, _T_270)
node _T_281 = or(_T_280, _T_271)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_281
node _T_282 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_283 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_284 = and(_T_282, _T_283)
node _T_285 = or(UInt<1>(0h0), _T_284)
node _T_286 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = and(_T_285, _T_290)
node _T_292 = or(UInt<1>(0h0), _T_291)
node _T_293 = and(_WIRE_1, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_293, UInt<1>(0h1), "") : assert_3
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(source_ok, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_300 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(_T_300, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_300, UInt<1>(0h1), "") : assert_5
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(is_aligned, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_307 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_307, UInt<1>(0h1), "") : assert_7
node _T_311 = not(io.in.a.bits.mask)
node _T_312 = eq(_T_311, UInt<1>(0h0))
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_T_312, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_312, UInt<1>(0h1), "") : assert_8
node _T_316 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_317 = asUInt(reset)
node _T_318 = eq(_T_317, UInt<1>(0h0))
when _T_318 :
node _T_319 = eq(_T_316, UInt<1>(0h0))
when _T_319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_316, UInt<1>(0h1), "") : assert_9
node _T_320 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_320 :
node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_322 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_325 = shr(io.in.a.bits.source, 2)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_330 = and(_T_328, _T_329)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<1>(0h1))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<2>(0h2))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_343 = shr(io.in.a.bits.source, 2)
node _T_344 = eq(_T_343, UInt<2>(0h3))
node _T_345 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_346 = and(_T_344, _T_345)
node _T_347 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_348 = and(_T_346, _T_347)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_349 = shr(io.in.a.bits.source, 3)
node _T_350 = eq(_T_349, UInt<2>(0h3))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_354 = and(_T_352, _T_353)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0)
node _T_355 = shr(io.in.a.bits.source, 3)
node _T_356 = eq(_T_355, UInt<2>(0h2))
node _T_357 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_358 = and(_T_356, _T_357)
node _T_359 = leq(uncommonBits_26, UInt<3>(0h7))
node _T_360 = and(_T_358, _T_359)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0)
node _T_361 = shr(io.in.a.bits.source, 3)
node _T_362 = eq(_T_361, UInt<4>(0h8))
node _T_363 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_364 = and(_T_362, _T_363)
node _T_365 = leq(uncommonBits_27, UInt<3>(0h4))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_368 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_369 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_370 = or(_T_324, _T_330)
node _T_371 = or(_T_370, _T_336)
node _T_372 = or(_T_371, _T_342)
node _T_373 = or(_T_372, _T_348)
node _T_374 = or(_T_373, _T_354)
node _T_375 = or(_T_374, _T_360)
node _T_376 = or(_T_375, _T_366)
node _T_377 = or(_T_376, _T_367)
node _T_378 = or(_T_377, _T_368)
node _T_379 = or(_T_378, _T_369)
node _T_380 = and(_T_323, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_383 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<13>(0h1000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = and(_T_382, _T_387)
node _T_389 = or(UInt<1>(0h0), _T_388)
node _T_390 = and(_T_381, _T_389)
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_390, UInt<1>(0h1), "") : assert_10
node _T_394 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_395 = shr(io.in.a.bits.source, 2)
node _T_396 = eq(_T_395, UInt<1>(0h0))
node _T_397 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_398 = and(_T_396, _T_397)
node _T_399 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_400 = and(_T_398, _T_399)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_401 = shr(io.in.a.bits.source, 2)
node _T_402 = eq(_T_401, UInt<1>(0h1))
node _T_403 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_404 = and(_T_402, _T_403)
node _T_405 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_406 = and(_T_404, _T_405)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_407 = shr(io.in.a.bits.source, 2)
node _T_408 = eq(_T_407, UInt<2>(0h2))
node _T_409 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_410 = and(_T_408, _T_409)
node _T_411 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_413 = shr(io.in.a.bits.source, 2)
node _T_414 = eq(_T_413, UInt<2>(0h3))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_418 = and(_T_416, _T_417)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0)
node _T_419 = shr(io.in.a.bits.source, 3)
node _T_420 = eq(_T_419, UInt<2>(0h3))
node _T_421 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_422 = and(_T_420, _T_421)
node _T_423 = leq(uncommonBits_32, UInt<3>(0h7))
node _T_424 = and(_T_422, _T_423)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0)
node _T_425 = shr(io.in.a.bits.source, 3)
node _T_426 = eq(_T_425, UInt<2>(0h2))
node _T_427 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_428 = and(_T_426, _T_427)
node _T_429 = leq(uncommonBits_33, UInt<3>(0h7))
node _T_430 = and(_T_428, _T_429)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_431 = shr(io.in.a.bits.source, 3)
node _T_432 = eq(_T_431, UInt<4>(0h8))
node _T_433 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_434 = and(_T_432, _T_433)
node _T_435 = leq(uncommonBits_34, UInt<3>(0h4))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_439 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_394
connect _WIRE_2[1], _T_400
connect _WIRE_2[2], _T_406
connect _WIRE_2[3], _T_412
connect _WIRE_2[4], _T_418
connect _WIRE_2[5], _T_424
connect _WIRE_2[6], _T_430
connect _WIRE_2[7], _T_436
connect _WIRE_2[8], _T_437
connect _WIRE_2[9], _T_438
connect _WIRE_2[10], _T_439
node _T_440 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_441 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_442 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_443 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_444 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_445 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_446 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_447 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_448 = mux(_WIRE_2[7], _T_440, UInt<1>(0h0))
node _T_449 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_450 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_452 = or(_T_441, _T_442)
node _T_453 = or(_T_452, _T_443)
node _T_454 = or(_T_453, _T_444)
node _T_455 = or(_T_454, _T_445)
node _T_456 = or(_T_455, _T_446)
node _T_457 = or(_T_456, _T_447)
node _T_458 = or(_T_457, _T_448)
node _T_459 = or(_T_458, _T_449)
node _T_460 = or(_T_459, _T_450)
node _T_461 = or(_T_460, _T_451)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_461
node _T_462 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_463 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_464 = and(_T_462, _T_463)
node _T_465 = or(UInt<1>(0h0), _T_464)
node _T_466 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<13>(0h1000)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = and(_T_465, _T_470)
node _T_472 = or(UInt<1>(0h0), _T_471)
node _T_473 = and(_WIRE_3, _T_472)
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_473, UInt<1>(0h1), "") : assert_11
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(source_ok, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_480 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_480, UInt<1>(0h1), "") : assert_13
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_487 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_487, UInt<1>(0h1), "") : assert_15
node _T_491 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_491, UInt<1>(0h1), "") : assert_16
node _T_495 = not(io.in.a.bits.mask)
node _T_496 = eq(_T_495, UInt<1>(0h0))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_496, UInt<1>(0h1), "") : assert_17
node _T_500 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_500, UInt<1>(0h1), "") : assert_18
node _T_504 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_504 :
node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_509 = shr(io.in.a.bits.source, 2)
node _T_510 = eq(_T_509, UInt<1>(0h0))
node _T_511 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_512 = and(_T_510, _T_511)
node _T_513 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_514 = and(_T_512, _T_513)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_515 = shr(io.in.a.bits.source, 2)
node _T_516 = eq(_T_515, UInt<1>(0h1))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_521 = shr(io.in.a.bits.source, 2)
node _T_522 = eq(_T_521, UInt<2>(0h2))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_526 = and(_T_524, _T_525)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_527 = shr(io.in.a.bits.source, 2)
node _T_528 = eq(_T_527, UInt<2>(0h3))
node _T_529 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_530 = and(_T_528, _T_529)
node _T_531 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_532 = and(_T_530, _T_531)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_533 = shr(io.in.a.bits.source, 3)
node _T_534 = eq(_T_533, UInt<2>(0h3))
node _T_535 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_536 = and(_T_534, _T_535)
node _T_537 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_538 = and(_T_536, _T_537)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_539 = shr(io.in.a.bits.source, 3)
node _T_540 = eq(_T_539, UInt<2>(0h2))
node _T_541 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_542 = and(_T_540, _T_541)
node _T_543 = leq(uncommonBits_40, UInt<3>(0h7))
node _T_544 = and(_T_542, _T_543)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_545 = shr(io.in.a.bits.source, 3)
node _T_546 = eq(_T_545, UInt<4>(0h8))
node _T_547 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_548 = and(_T_546, _T_547)
node _T_549 = leq(uncommonBits_41, UInt<3>(0h4))
node _T_550 = and(_T_548, _T_549)
node _T_551 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_552 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_553 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_554 = or(_T_508, _T_514)
node _T_555 = or(_T_554, _T_520)
node _T_556 = or(_T_555, _T_526)
node _T_557 = or(_T_556, _T_532)
node _T_558 = or(_T_557, _T_538)
node _T_559 = or(_T_558, _T_544)
node _T_560 = or(_T_559, _T_550)
node _T_561 = or(_T_560, _T_551)
node _T_562 = or(_T_561, _T_552)
node _T_563 = or(_T_562, _T_553)
node _T_564 = and(_T_507, _T_563)
node _T_565 = or(UInt<1>(0h0), _T_564)
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_565, UInt<1>(0h1), "") : assert_19
node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_570 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_571 = and(_T_569, _T_570)
node _T_572 = or(UInt<1>(0h0), _T_571)
node _T_573 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_574 = cvt(_T_573)
node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000)))
node _T_576 = asSInt(_T_575)
node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0)))
node _T_578 = and(_T_572, _T_577)
node _T_579 = or(UInt<1>(0h0), _T_578)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_579, UInt<1>(0h1), "") : assert_20
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(source_ok, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(is_aligned, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_589 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(_T_589, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_589, UInt<1>(0h1), "") : assert_23
node _T_593 = eq(io.in.a.bits.mask, mask)
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(_T_593, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_593, UInt<1>(0h1), "") : assert_24
node _T_597 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_597, UInt<1>(0h1), "") : assert_25
node _T_601 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_601 :
node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_606 = shr(io.in.a.bits.source, 2)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_611 = and(_T_609, _T_610)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_612 = shr(io.in.a.bits.source, 2)
node _T_613 = eq(_T_612, UInt<1>(0h1))
node _T_614 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_615 = and(_T_613, _T_614)
node _T_616 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_617 = and(_T_615, _T_616)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_618 = shr(io.in.a.bits.source, 2)
node _T_619 = eq(_T_618, UInt<2>(0h2))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_624 = shr(io.in.a.bits.source, 2)
node _T_625 = eq(_T_624, UInt<2>(0h3))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_630 = shr(io.in.a.bits.source, 3)
node _T_631 = eq(_T_630, UInt<2>(0h3))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_46, UInt<3>(0h7))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_636 = shr(io.in.a.bits.source, 3)
node _T_637 = eq(_T_636, UInt<2>(0h2))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_47, UInt<3>(0h7))
node _T_641 = and(_T_639, _T_640)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_642 = shr(io.in.a.bits.source, 3)
node _T_643 = eq(_T_642, UInt<4>(0h8))
node _T_644 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_645 = and(_T_643, _T_644)
node _T_646 = leq(uncommonBits_48, UInt<3>(0h4))
node _T_647 = and(_T_645, _T_646)
node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_650 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_651 = or(_T_605, _T_611)
node _T_652 = or(_T_651, _T_617)
node _T_653 = or(_T_652, _T_623)
node _T_654 = or(_T_653, _T_629)
node _T_655 = or(_T_654, _T_635)
node _T_656 = or(_T_655, _T_641)
node _T_657 = or(_T_656, _T_647)
node _T_658 = or(_T_657, _T_648)
node _T_659 = or(_T_658, _T_649)
node _T_660 = or(_T_659, _T_650)
node _T_661 = and(_T_604, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_664 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_665 = and(_T_663, _T_664)
node _T_666 = or(UInt<1>(0h0), _T_665)
node _T_667 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_668 = cvt(_T_667)
node _T_669 = and(_T_668, asSInt(UInt<13>(0h1000)))
node _T_670 = asSInt(_T_669)
node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0)))
node _T_672 = and(_T_666, _T_671)
node _T_673 = or(UInt<1>(0h0), _T_672)
node _T_674 = and(_T_662, _T_673)
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_674, UInt<1>(0h1), "") : assert_26
node _T_678 = asUInt(reset)
node _T_679 = eq(_T_678, UInt<1>(0h0))
when _T_679 :
node _T_680 = eq(source_ok, UInt<1>(0h0))
when _T_680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(is_aligned, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_685 = asUInt(reset)
node _T_686 = eq(_T_685, UInt<1>(0h0))
when _T_686 :
node _T_687 = eq(_T_684, UInt<1>(0h0))
when _T_687 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_684, UInt<1>(0h1), "") : assert_29
node _T_688 = eq(io.in.a.bits.mask, mask)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_688, UInt<1>(0h1), "") : assert_30
node _T_692 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_692 :
node _T_693 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_694 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_695 = and(_T_693, _T_694)
node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_697 = shr(io.in.a.bits.source, 2)
node _T_698 = eq(_T_697, UInt<1>(0h0))
node _T_699 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_700 = and(_T_698, _T_699)
node _T_701 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_702 = and(_T_700, _T_701)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_703 = shr(io.in.a.bits.source, 2)
node _T_704 = eq(_T_703, UInt<1>(0h1))
node _T_705 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_706 = and(_T_704, _T_705)
node _T_707 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_708 = and(_T_706, _T_707)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_709 = shr(io.in.a.bits.source, 2)
node _T_710 = eq(_T_709, UInt<2>(0h2))
node _T_711 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_712 = and(_T_710, _T_711)
node _T_713 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_714 = and(_T_712, _T_713)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_715 = shr(io.in.a.bits.source, 2)
node _T_716 = eq(_T_715, UInt<2>(0h3))
node _T_717 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_718 = and(_T_716, _T_717)
node _T_719 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_720 = and(_T_718, _T_719)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_721 = shr(io.in.a.bits.source, 3)
node _T_722 = eq(_T_721, UInt<2>(0h3))
node _T_723 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_724 = and(_T_722, _T_723)
node _T_725 = leq(uncommonBits_53, UInt<3>(0h7))
node _T_726 = and(_T_724, _T_725)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_727 = shr(io.in.a.bits.source, 3)
node _T_728 = eq(_T_727, UInt<2>(0h2))
node _T_729 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_730 = and(_T_728, _T_729)
node _T_731 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_732 = and(_T_730, _T_731)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0)
node _T_733 = shr(io.in.a.bits.source, 3)
node _T_734 = eq(_T_733, UInt<4>(0h8))
node _T_735 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_736 = and(_T_734, _T_735)
node _T_737 = leq(uncommonBits_55, UInt<3>(0h4))
node _T_738 = and(_T_736, _T_737)
node _T_739 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_740 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_741 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_742 = or(_T_696, _T_702)
node _T_743 = or(_T_742, _T_708)
node _T_744 = or(_T_743, _T_714)
node _T_745 = or(_T_744, _T_720)
node _T_746 = or(_T_745, _T_726)
node _T_747 = or(_T_746, _T_732)
node _T_748 = or(_T_747, _T_738)
node _T_749 = or(_T_748, _T_739)
node _T_750 = or(_T_749, _T_740)
node _T_751 = or(_T_750, _T_741)
node _T_752 = and(_T_695, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_755 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_756 = and(_T_754, _T_755)
node _T_757 = or(UInt<1>(0h0), _T_756)
node _T_758 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_759 = cvt(_T_758)
node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000)))
node _T_761 = asSInt(_T_760)
node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0)))
node _T_763 = and(_T_757, _T_762)
node _T_764 = or(UInt<1>(0h0), _T_763)
node _T_765 = and(_T_753, _T_764)
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(_T_765, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_765, UInt<1>(0h1), "") : assert_31
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(source_ok, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(is_aligned, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_775 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_775, UInt<1>(0h1), "") : assert_34
node _T_779 = not(mask)
node _T_780 = and(io.in.a.bits.mask, _T_779)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_781, UInt<1>(0h1), "") : assert_35
node _T_785 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_785 :
node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_787 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_788 = and(_T_786, _T_787)
node _T_789 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_790 = shr(io.in.a.bits.source, 2)
node _T_791 = eq(_T_790, UInt<1>(0h0))
node _T_792 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_793 = and(_T_791, _T_792)
node _T_794 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_795 = and(_T_793, _T_794)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_796 = shr(io.in.a.bits.source, 2)
node _T_797 = eq(_T_796, UInt<1>(0h1))
node _T_798 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_799 = and(_T_797, _T_798)
node _T_800 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_801 = and(_T_799, _T_800)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_802 = shr(io.in.a.bits.source, 2)
node _T_803 = eq(_T_802, UInt<2>(0h2))
node _T_804 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_805 = and(_T_803, _T_804)
node _T_806 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_807 = and(_T_805, _T_806)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<2>(0h3))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0)
node _T_814 = shr(io.in.a.bits.source, 3)
node _T_815 = eq(_T_814, UInt<2>(0h3))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_60, UInt<3>(0h7))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0)
node _T_820 = shr(io.in.a.bits.source, 3)
node _T_821 = eq(_T_820, UInt<2>(0h2))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_61, UInt<3>(0h7))
node _T_825 = and(_T_823, _T_824)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0)
node _T_826 = shr(io.in.a.bits.source, 3)
node _T_827 = eq(_T_826, UInt<4>(0h8))
node _T_828 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_829 = and(_T_827, _T_828)
node _T_830 = leq(uncommonBits_62, UInt<3>(0h4))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_833 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_834 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_835 = or(_T_789, _T_795)
node _T_836 = or(_T_835, _T_801)
node _T_837 = or(_T_836, _T_807)
node _T_838 = or(_T_837, _T_813)
node _T_839 = or(_T_838, _T_819)
node _T_840 = or(_T_839, _T_825)
node _T_841 = or(_T_840, _T_831)
node _T_842 = or(_T_841, _T_832)
node _T_843 = or(_T_842, _T_833)
node _T_844 = or(_T_843, _T_834)
node _T_845 = and(_T_788, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_848 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = and(_T_847, _T_852)
node _T_854 = or(UInt<1>(0h0), _T_853)
node _T_855 = and(_T_846, _T_854)
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_855, UInt<1>(0h1), "") : assert_36
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(source_ok, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(is_aligned, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_865 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_865, UInt<1>(0h1), "") : assert_39
node _T_869 = eq(io.in.a.bits.mask, mask)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_869, UInt<1>(0h1), "") : assert_40
node _T_873 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_873 :
node _T_874 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_875 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_876 = and(_T_874, _T_875)
node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_878 = shr(io.in.a.bits.source, 2)
node _T_879 = eq(_T_878, UInt<1>(0h0))
node _T_880 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_881 = and(_T_879, _T_880)
node _T_882 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_883 = and(_T_881, _T_882)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_884 = shr(io.in.a.bits.source, 2)
node _T_885 = eq(_T_884, UInt<1>(0h1))
node _T_886 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_887 = and(_T_885, _T_886)
node _T_888 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_889 = and(_T_887, _T_888)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_890 = shr(io.in.a.bits.source, 2)
node _T_891 = eq(_T_890, UInt<2>(0h2))
node _T_892 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_893 = and(_T_891, _T_892)
node _T_894 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_895 = and(_T_893, _T_894)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_896 = shr(io.in.a.bits.source, 2)
node _T_897 = eq(_T_896, UInt<2>(0h3))
node _T_898 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_899 = and(_T_897, _T_898)
node _T_900 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_901 = and(_T_899, _T_900)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0)
node _T_902 = shr(io.in.a.bits.source, 3)
node _T_903 = eq(_T_902, UInt<2>(0h3))
node _T_904 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_905 = and(_T_903, _T_904)
node _T_906 = leq(uncommonBits_67, UInt<3>(0h7))
node _T_907 = and(_T_905, _T_906)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0)
node _T_908 = shr(io.in.a.bits.source, 3)
node _T_909 = eq(_T_908, UInt<2>(0h2))
node _T_910 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_911 = and(_T_909, _T_910)
node _T_912 = leq(uncommonBits_68, UInt<3>(0h7))
node _T_913 = and(_T_911, _T_912)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_914 = shr(io.in.a.bits.source, 3)
node _T_915 = eq(_T_914, UInt<4>(0h8))
node _T_916 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_917 = and(_T_915, _T_916)
node _T_918 = leq(uncommonBits_69, UInt<3>(0h4))
node _T_919 = and(_T_917, _T_918)
node _T_920 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_921 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_922 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_923 = or(_T_877, _T_883)
node _T_924 = or(_T_923, _T_889)
node _T_925 = or(_T_924, _T_895)
node _T_926 = or(_T_925, _T_901)
node _T_927 = or(_T_926, _T_907)
node _T_928 = or(_T_927, _T_913)
node _T_929 = or(_T_928, _T_919)
node _T_930 = or(_T_929, _T_920)
node _T_931 = or(_T_930, _T_921)
node _T_932 = or(_T_931, _T_922)
node _T_933 = and(_T_876, _T_932)
node _T_934 = or(UInt<1>(0h0), _T_933)
node _T_935 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_936 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_937 = cvt(_T_936)
node _T_938 = and(_T_937, asSInt(UInt<13>(0h1000)))
node _T_939 = asSInt(_T_938)
node _T_940 = eq(_T_939, asSInt(UInt<1>(0h0)))
node _T_941 = and(_T_935, _T_940)
node _T_942 = or(UInt<1>(0h0), _T_941)
node _T_943 = and(_T_934, _T_942)
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_943, UInt<1>(0h1), "") : assert_41
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(source_ok, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_950 = asUInt(reset)
node _T_951 = eq(_T_950, UInt<1>(0h0))
when _T_951 :
node _T_952 = eq(is_aligned, UInt<1>(0h0))
when _T_952 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_953 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_953, UInt<1>(0h1), "") : assert_44
node _T_957 = eq(io.in.a.bits.mask, mask)
node _T_958 = asUInt(reset)
node _T_959 = eq(_T_958, UInt<1>(0h0))
when _T_959 :
node _T_960 = eq(_T_957, UInt<1>(0h0))
when _T_960 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_957, UInt<1>(0h1), "") : assert_45
node _T_961 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_961 :
node _T_962 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_963 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_964 = and(_T_962, _T_963)
node _T_965 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_966 = shr(io.in.a.bits.source, 2)
node _T_967 = eq(_T_966, UInt<1>(0h0))
node _T_968 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_969 = and(_T_967, _T_968)
node _T_970 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_971 = and(_T_969, _T_970)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_972 = shr(io.in.a.bits.source, 2)
node _T_973 = eq(_T_972, UInt<1>(0h1))
node _T_974 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_975 = and(_T_973, _T_974)
node _T_976 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_977 = and(_T_975, _T_976)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_978 = shr(io.in.a.bits.source, 2)
node _T_979 = eq(_T_978, UInt<2>(0h2))
node _T_980 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_981 = and(_T_979, _T_980)
node _T_982 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_983 = and(_T_981, _T_982)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_984 = shr(io.in.a.bits.source, 2)
node _T_985 = eq(_T_984, UInt<2>(0h3))
node _T_986 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_987 = and(_T_985, _T_986)
node _T_988 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_989 = and(_T_987, _T_988)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_990 = shr(io.in.a.bits.source, 3)
node _T_991 = eq(_T_990, UInt<2>(0h3))
node _T_992 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_993 = and(_T_991, _T_992)
node _T_994 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_995 = and(_T_993, _T_994)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0)
node _T_996 = shr(io.in.a.bits.source, 3)
node _T_997 = eq(_T_996, UInt<2>(0h2))
node _T_998 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_999 = and(_T_997, _T_998)
node _T_1000 = leq(uncommonBits_75, UInt<3>(0h7))
node _T_1001 = and(_T_999, _T_1000)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0)
node _T_1002 = shr(io.in.a.bits.source, 3)
node _T_1003 = eq(_T_1002, UInt<4>(0h8))
node _T_1004 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = leq(uncommonBits_76, UInt<3>(0h4))
node _T_1007 = and(_T_1005, _T_1006)
node _T_1008 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1009 = eq(io.in.a.bits.source, UInt<7>(0h48))
node _T_1010 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1011 = or(_T_965, _T_971)
node _T_1012 = or(_T_1011, _T_977)
node _T_1013 = or(_T_1012, _T_983)
node _T_1014 = or(_T_1013, _T_989)
node _T_1015 = or(_T_1014, _T_995)
node _T_1016 = or(_T_1015, _T_1001)
node _T_1017 = or(_T_1016, _T_1007)
node _T_1018 = or(_T_1017, _T_1008)
node _T_1019 = or(_T_1018, _T_1009)
node _T_1020 = or(_T_1019, _T_1010)
node _T_1021 = and(_T_964, _T_1020)
node _T_1022 = or(UInt<1>(0h0), _T_1021)
node _T_1023 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1024 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1025 = cvt(_T_1024)
node _T_1026 = and(_T_1025, asSInt(UInt<13>(0h1000)))
node _T_1027 = asSInt(_T_1026)
node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0)))
node _T_1029 = and(_T_1023, _T_1028)
node _T_1030 = or(UInt<1>(0h0), _T_1029)
node _T_1031 = and(_T_1022, _T_1030)
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_46
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(source_ok, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(is_aligned, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1041 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_49
node _T_1045 = eq(io.in.a.bits.mask, mask)
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_50
node _T_1049 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1053 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_52
node _source_ok_T_55 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_56 = shr(io.in.d.bits.source, 2)
node _source_ok_T_57 = eq(_source_ok_T_56, UInt<1>(0h0))
node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_62 = shr(io.in.d.bits.source, 2)
node _source_ok_T_63 = eq(_source_ok_T_62, UInt<1>(0h1))
node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_68 = shr(io.in.d.bits.source, 2)
node _source_ok_T_69 = eq(_source_ok_T_68, UInt<2>(0h2))
node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_74 = shr(io.in.d.bits.source, 2)
node _source_ok_T_75 = eq(_source_ok_T_74, UInt<2>(0h3))
node _source_ok_T_76 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76)
node _source_ok_T_78 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_80 = shr(io.in.d.bits.source, 3)
node _source_ok_T_81 = eq(_source_ok_T_80, UInt<2>(0h3))
node _source_ok_T_82 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82)
node _source_ok_T_84 = leq(source_ok_uncommonBits_11, UInt<3>(0h7))
node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0)
node _source_ok_T_86 = shr(io.in.d.bits.source, 3)
node _source_ok_T_87 = eq(_source_ok_T_86, UInt<2>(0h2))
node _source_ok_T_88 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_89 = and(_source_ok_T_87, _source_ok_T_88)
node _source_ok_T_90 = leq(source_ok_uncommonBits_12, UInt<3>(0h7))
node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0)
node _source_ok_T_92 = shr(io.in.d.bits.source, 3)
node _source_ok_T_93 = eq(_source_ok_T_92, UInt<4>(0h8))
node _source_ok_T_94 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_95 = and(_source_ok_T_93, _source_ok_T_94)
node _source_ok_T_96 = leq(source_ok_uncommonBits_13, UInt<3>(0h4))
node _source_ok_T_97 = and(_source_ok_T_95, _source_ok_T_96)
node _source_ok_T_98 = eq(io.in.d.bits.source, UInt<7>(0h45))
node _source_ok_T_99 = eq(io.in.d.bits.source, UInt<7>(0h48))
node _source_ok_T_100 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_55
connect _source_ok_WIRE_1[1], _source_ok_T_61
connect _source_ok_WIRE_1[2], _source_ok_T_67
connect _source_ok_WIRE_1[3], _source_ok_T_73
connect _source_ok_WIRE_1[4], _source_ok_T_79
connect _source_ok_WIRE_1[5], _source_ok_T_85
connect _source_ok_WIRE_1[6], _source_ok_T_91
connect _source_ok_WIRE_1[7], _source_ok_T_97
connect _source_ok_WIRE_1[8], _source_ok_T_98
connect _source_ok_WIRE_1[9], _source_ok_T_99
connect _source_ok_WIRE_1[10], _source_ok_T_100
node _source_ok_T_101 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[2])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[3])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[4])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[5])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[6])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[7])
node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[8])
node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_109, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1057 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1057 :
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(source_ok_1, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1061 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_54
node _T_1065 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_55
node _T_1069 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_56
node _T_1073 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(_T_1073, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1073, UInt<1>(0h1), "") : assert_57
node _T_1077 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1077 :
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(source_ok_1, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(sink_ok, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1084 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_60
node _T_1088 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_61
node _T_1092 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_62
node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_63
node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1101 = or(UInt<1>(0h0), _T_1100)
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_64
node _T_1105 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1105 :
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(source_ok_1, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(sink_ok, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1112 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_67
node _T_1116 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_68
node _T_1120 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_69
node _T_1124 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1125 = or(_T_1124, io.in.d.bits.corrupt)
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_70
node _T_1129 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1130 = or(UInt<1>(0h0), _T_1129)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_71
node _T_1134 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(source_ok_1, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1138 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_73
node _T_1142 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_74
node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1147 = or(UInt<1>(0h0), _T_1146)
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_75
node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1151 :
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(source_ok_1, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_77
node _T_1159 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1160 = or(_T_1159, io.in.d.bits.corrupt)
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_78
node _T_1164 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1165 = or(UInt<1>(0h0), _T_1164)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_79
node _T_1169 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1169 :
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(source_ok_1, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1173 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_81
node _T_1177 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_82
node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1182 = or(UInt<1>(0h0), _T_1181)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1186 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1190 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1194 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1198 = eq(a_first, UInt<1>(0h0))
node _T_1199 = and(io.in.a.valid, _T_1198)
when _T_1199 :
node _T_1200 = eq(io.in.a.bits.opcode, opcode)
node _T_1201 = asUInt(reset)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
when _T_1202 :
node _T_1203 = eq(_T_1200, UInt<1>(0h0))
when _T_1203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1200, UInt<1>(0h1), "") : assert_87
node _T_1204 = eq(io.in.a.bits.param, param)
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(_T_1204, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1204, UInt<1>(0h1), "") : assert_88
node _T_1208 = eq(io.in.a.bits.size, size)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_89
node _T_1212 = eq(io.in.a.bits.source, source)
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_90
node _T_1216 = eq(io.in.a.bits.address, address)
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_91
node _T_1220 = and(io.in.a.ready, io.in.a.valid)
node _T_1221 = and(_T_1220, a_first)
when _T_1221 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1222 = eq(d_first, UInt<1>(0h0))
node _T_1223 = and(io.in.d.valid, _T_1222)
when _T_1223 :
node _T_1224 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92
node _T_1228 = eq(io.in.d.bits.param, param_1)
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_93
node _T_1232 = eq(io.in.d.bits.size, size_1)
node _T_1233 = asUInt(reset)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
when _T_1234 :
node _T_1235 = eq(_T_1232, UInt<1>(0h0))
when _T_1235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1232, UInt<1>(0h1), "") : assert_94
node _T_1236 = eq(io.in.d.bits.source, source_1)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_95
node _T_1240 = eq(io.in.d.bits.sink, sink)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_96
node _T_1244 = eq(io.in.d.bits.denied, denied)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_97
node _T_1248 = and(io.in.d.ready, io.in.d.valid)
node _T_1249 = and(_T_1248, d_first)
when _T_1249 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1250 = and(io.in.a.valid, a_first_1)
node _T_1251 = and(_T_1250, UInt<1>(0h1))
when _T_1251 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1252 = and(io.in.a.ready, io.in.a.valid)
node _T_1253 = and(_T_1252, a_first_1)
node _T_1254 = and(_T_1253, UInt<1>(0h1))
when _T_1254 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1255 = dshr(inflight, io.in.a.bits.source)
node _T_1256 = bits(_T_1255, 0, 0)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(_T_1257, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1257, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1261 = and(io.in.d.valid, d_first_1)
node _T_1262 = and(_T_1261, UInt<1>(0h1))
node _T_1263 = eq(d_release_ack, UInt<1>(0h0))
node _T_1264 = and(_T_1262, _T_1263)
when _T_1264 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1265 = and(io.in.d.ready, io.in.d.valid)
node _T_1266 = and(_T_1265, d_first_1)
node _T_1267 = and(_T_1266, UInt<1>(0h1))
node _T_1268 = eq(d_release_ack, UInt<1>(0h0))
node _T_1269 = and(_T_1267, _T_1268)
when _T_1269 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1270 = and(io.in.d.valid, d_first_1)
node _T_1271 = and(_T_1270, UInt<1>(0h1))
node _T_1272 = eq(d_release_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1274 = dshr(inflight, io.in.d.bits.source)
node _T_1275 = bits(_T_1274, 0, 0)
node _T_1276 = or(_T_1275, same_cycle_resp)
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(_T_1276, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1276, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1280 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1281 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1282 = or(_T_1280, _T_1281)
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_100
node _T_1286 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_101
else :
node _T_1290 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1291 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1292 = or(_T_1290, _T_1291)
node _T_1293 = asUInt(reset)
node _T_1294 = eq(_T_1293, UInt<1>(0h0))
when _T_1294 :
node _T_1295 = eq(_T_1292, UInt<1>(0h0))
when _T_1295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1292, UInt<1>(0h1), "") : assert_102
node _T_1296 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_103
node _T_1300 = and(io.in.d.valid, d_first_1)
node _T_1301 = and(_T_1300, a_first_1)
node _T_1302 = and(_T_1301, io.in.a.valid)
node _T_1303 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1304 = and(_T_1302, _T_1303)
node _T_1305 = eq(d_release_ack, UInt<1>(0h0))
node _T_1306 = and(_T_1304, _T_1305)
when _T_1306 :
node _T_1307 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1308 = or(_T_1307, io.in.a.ready)
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_18
node _T_1312 = orr(inflight)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
node _T_1314 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1315 = or(_T_1313, _T_1314)
node _T_1316 = lt(watchdog, plusarg_reader.out)
node _T_1317 = or(_T_1315, _T_1316)
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(_T_1317, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1317, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1321 = and(io.in.a.ready, io.in.a.valid)
node _T_1322 = and(io.in.d.ready, io.in.d.valid)
node _T_1323 = or(_T_1321, _T_1322)
when _T_1323 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1324 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1325 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1326 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1327 = and(_T_1325, _T_1326)
node _T_1328 = and(_T_1324, _T_1327)
when _T_1328 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1329 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1330 = and(_T_1329, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1331 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1332 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1333 = and(_T_1331, _T_1332)
node _T_1334 = and(_T_1330, _T_1333)
when _T_1334 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1335 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1336 = bits(_T_1335, 0, 0)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(_T_1337, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1337, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1341 = and(io.in.d.valid, d_first_2)
node _T_1342 = and(_T_1341, UInt<1>(0h1))
node _T_1343 = and(_T_1342, d_release_ack_1)
when _T_1343 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1344 = and(io.in.d.ready, io.in.d.valid)
node _T_1345 = and(_T_1344, d_first_2)
node _T_1346 = and(_T_1345, UInt<1>(0h1))
node _T_1347 = and(_T_1346, d_release_ack_1)
when _T_1347 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1348 = and(io.in.d.valid, d_first_2)
node _T_1349 = and(_T_1348, UInt<1>(0h1))
node _T_1350 = and(_T_1349, d_release_ack_1)
when _T_1350 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1351 = dshr(inflight_1, io.in.d.bits.source)
node _T_1352 = bits(_T_1351, 0, 0)
node _T_1353 = or(_T_1352, same_cycle_resp_1)
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1357 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1358 = asUInt(reset)
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(_T_1357, UInt<1>(0h0))
when _T_1360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1357, UInt<1>(0h1), "") : assert_108
else :
node _T_1361 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_109
node _T_1365 = and(io.in.d.valid, d_first_2)
node _T_1366 = and(_T_1365, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1367 = and(_T_1366, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1368 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1369 = and(_T_1367, _T_1368)
node _T_1370 = and(_T_1369, d_release_ack_1)
node _T_1371 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1372 = and(_T_1370, _T_1371)
when _T_1372 :
node _T_1373 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1374 = or(_T_1373, _WIRE_27.ready)
node _T_1375 = asUInt(reset)
node _T_1376 = eq(_T_1375, UInt<1>(0h0))
when _T_1376 :
node _T_1377 = eq(_T_1374, UInt<1>(0h0))
when _T_1377 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1374, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_19
node _T_1378 = orr(inflight_1)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
node _T_1380 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1381 = or(_T_1379, _T_1380)
node _T_1382 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1383 = or(_T_1381, _T_1382)
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-blocks/src/main/scala/devices/uart/UART.scala:296:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1387 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1388 = and(io.in.d.ready, io.in.d.valid)
node _T_1389 = or(_T_1387, _T_1388)
when _T_1389 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_9( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_88 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_94 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_37 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_41 = source_ok_uncommonBits_6 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_42 = _source_ok_T_40 & _source_ok_T_41; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = io_in_a_bits_source_0 == 8'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_54 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_56 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_62 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_68 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_74 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_57 = _source_ok_T_56 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_61; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_63 = _source_ok_T_62 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_69 = _source_ok_T_68 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_75 = _source_ok_T_74 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_79; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_80 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_86 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_92 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_81 = _source_ok_T_80 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_87 = _source_ok_T_86 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_89 = _source_ok_T_87; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_93 = _source_ok_T_92 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_95 = _source_ok_T_93; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_96 = source_ok_uncommonBits_13 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_97 = _source_ok_T_95 & _source_ok_T_96; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_7 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_98; // @[Parameters.scala:1138:31]
wire _source_ok_T_99 = io_in_d_bits_source_0 == 8'h48; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_99; // @[Parameters.scala:1138:31]
wire _source_ok_T_100 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_109 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1321 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1321; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1321; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1389 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1389; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1389; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1389; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1254 = _T_1321 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1254 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1254 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1254 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1254 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1254 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1300 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1300 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1269 = _T_1389 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1269 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1269 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1269 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1365 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1365 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1347 = _T_1389 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1347 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1347 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1347 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_302 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_302( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_120 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_120( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module JtagBypassChain :
input clock : Clock
input reset : Reset
output io : { flip chainIn : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}, chainOut : { shift : UInt<1>, data : UInt<1>, capture : UInt<1>, update : UInt<1>}}
connect io.chainOut.shift, io.chainIn.shift
connect io.chainOut.capture, io.chainIn.capture
connect io.chainOut.update, io.chainIn.update
reg reg : UInt<1>, clock
connect io.chainOut.data, reg
when io.chainIn.capture :
connect reg, UInt<1>(0h0)
else :
when io.chainIn.shift :
connect reg, io.chainIn.data
node _T = and(io.chainIn.capture, io.chainIn.update)
node _T_1 = eq(_T, UInt<1>(0h0))
node _T_2 = and(io.chainIn.capture, io.chainIn.shift)
node _T_3 = eq(_T_2, UInt<1>(0h0))
node _T_4 = and(_T_1, _T_3)
node _T_5 = and(io.chainIn.update, io.chainIn.shift)
node _T_6 = eq(_T_5, UInt<1>(0h0))
node _T_7 = and(_T_4, _T_6)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at JtagShifter.scala:72 assert(!(io.chainIn.capture && io.chainIn.update)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert | module JtagBypassChain( // @[JtagShifter.scala:56:7]
input clock, // @[JtagShifter.scala:56:7]
input reset, // @[JtagShifter.scala:56:7]
input io_chainIn_shift, // @[JtagShifter.scala:58:14]
input io_chainIn_data, // @[JtagShifter.scala:58:14]
input io_chainIn_capture, // @[JtagShifter.scala:58:14]
input io_chainIn_update, // @[JtagShifter.scala:58:14]
output io_chainOut_shift, // @[JtagShifter.scala:58:14]
output io_chainOut_data, // @[JtagShifter.scala:58:14]
output io_chainOut_capture, // @[JtagShifter.scala:58:14]
output io_chainOut_update // @[JtagShifter.scala:58:14]
);
wire io_chainIn_shift_0 = io_chainIn_shift; // @[JtagShifter.scala:56:7]
wire io_chainIn_data_0 = io_chainIn_data; // @[JtagShifter.scala:56:7]
wire io_chainIn_capture_0 = io_chainIn_capture; // @[JtagShifter.scala:56:7]
wire io_chainIn_update_0 = io_chainIn_update; // @[JtagShifter.scala:56:7]
wire io_chainOut_shift_0 = io_chainIn_shift_0; // @[JtagShifter.scala:56:7]
wire io_chainOut_capture_0 = io_chainIn_capture_0; // @[JtagShifter.scala:56:7]
wire io_chainOut_update_0 = io_chainIn_update_0; // @[JtagShifter.scala:56:7]
wire io_chainOut_data_0; // @[JtagShifter.scala:56:7]
reg reg_0; // @[JtagShifter.scala:61:16]
assign io_chainOut_data_0 = reg_0; // @[JtagShifter.scala:56:7, :61:16] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_227 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_227( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Atomics :
input clock : Clock
input reset : Reset
output io : { flip write : UInt<1>, flip a : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}, flip data_in : UInt<32>, data_out : UInt<32>}
node adder = bits(io.a.param, 2, 2)
node unsigned = bits(io.a.param, 1, 1)
node take_max = bits(io.a.param, 0, 0)
node _signBit_T = not(io.a.mask)
node _signBit_T_1 = shr(_signBit_T, 1)
node _signBit_T_2 = cat(UInt<1>(0h1), _signBit_T_1)
node signBit = and(io.a.mask, _signBit_T_2)
node _inv_d_T = not(io.data_in)
node inv_d = mux(adder, io.data_in, _inv_d_T)
node _sum_T = bits(io.a.mask, 0, 0)
node _sum_T_1 = bits(io.a.mask, 1, 1)
node _sum_T_2 = bits(io.a.mask, 2, 2)
node _sum_T_3 = bits(io.a.mask, 3, 3)
node _sum_T_4 = mux(_sum_T, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_5 = mux(_sum_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_6 = mux(_sum_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _sum_T_7 = mux(_sum_T_3, UInt<8>(0hff), UInt<8>(0h0))
node sum_lo = cat(_sum_T_5, _sum_T_4)
node sum_hi = cat(_sum_T_7, _sum_T_6)
node _sum_T_8 = cat(sum_hi, sum_lo)
node _sum_T_9 = and(_sum_T_8, io.a.data)
node _sum_T_10 = add(_sum_T_9, inv_d)
node sum = tail(_sum_T_10, 1)
node _sign_a_T = bits(io.a.data, 0, 0)
node _sign_a_T_1 = bits(io.a.data, 1, 1)
node _sign_a_T_2 = bits(io.a.data, 2, 2)
node _sign_a_T_3 = bits(io.a.data, 3, 3)
node _sign_a_T_4 = bits(io.a.data, 4, 4)
node _sign_a_T_5 = bits(io.a.data, 5, 5)
node _sign_a_T_6 = bits(io.a.data, 6, 6)
node _sign_a_T_7 = bits(io.a.data, 7, 7)
node _sign_a_T_8 = bits(io.a.data, 8, 8)
node _sign_a_T_9 = bits(io.a.data, 9, 9)
node _sign_a_T_10 = bits(io.a.data, 10, 10)
node _sign_a_T_11 = bits(io.a.data, 11, 11)
node _sign_a_T_12 = bits(io.a.data, 12, 12)
node _sign_a_T_13 = bits(io.a.data, 13, 13)
node _sign_a_T_14 = bits(io.a.data, 14, 14)
node _sign_a_T_15 = bits(io.a.data, 15, 15)
node _sign_a_T_16 = bits(io.a.data, 16, 16)
node _sign_a_T_17 = bits(io.a.data, 17, 17)
node _sign_a_T_18 = bits(io.a.data, 18, 18)
node _sign_a_T_19 = bits(io.a.data, 19, 19)
node _sign_a_T_20 = bits(io.a.data, 20, 20)
node _sign_a_T_21 = bits(io.a.data, 21, 21)
node _sign_a_T_22 = bits(io.a.data, 22, 22)
node _sign_a_T_23 = bits(io.a.data, 23, 23)
node _sign_a_T_24 = bits(io.a.data, 24, 24)
node _sign_a_T_25 = bits(io.a.data, 25, 25)
node _sign_a_T_26 = bits(io.a.data, 26, 26)
node _sign_a_T_27 = bits(io.a.data, 27, 27)
node _sign_a_T_28 = bits(io.a.data, 28, 28)
node _sign_a_T_29 = bits(io.a.data, 29, 29)
node _sign_a_T_30 = bits(io.a.data, 30, 30)
node _sign_a_T_31 = bits(io.a.data, 31, 31)
node sign_a_lo = cat(_sign_a_T_15, _sign_a_T_7)
node sign_a_hi = cat(_sign_a_T_31, _sign_a_T_23)
node _sign_a_T_32 = cat(sign_a_hi, sign_a_lo)
node _sign_a_T_33 = and(_sign_a_T_32, signBit)
node sign_a = orr(_sign_a_T_33)
node _sign_d_T = bits(io.data_in, 0, 0)
node _sign_d_T_1 = bits(io.data_in, 1, 1)
node _sign_d_T_2 = bits(io.data_in, 2, 2)
node _sign_d_T_3 = bits(io.data_in, 3, 3)
node _sign_d_T_4 = bits(io.data_in, 4, 4)
node _sign_d_T_5 = bits(io.data_in, 5, 5)
node _sign_d_T_6 = bits(io.data_in, 6, 6)
node _sign_d_T_7 = bits(io.data_in, 7, 7)
node _sign_d_T_8 = bits(io.data_in, 8, 8)
node _sign_d_T_9 = bits(io.data_in, 9, 9)
node _sign_d_T_10 = bits(io.data_in, 10, 10)
node _sign_d_T_11 = bits(io.data_in, 11, 11)
node _sign_d_T_12 = bits(io.data_in, 12, 12)
node _sign_d_T_13 = bits(io.data_in, 13, 13)
node _sign_d_T_14 = bits(io.data_in, 14, 14)
node _sign_d_T_15 = bits(io.data_in, 15, 15)
node _sign_d_T_16 = bits(io.data_in, 16, 16)
node _sign_d_T_17 = bits(io.data_in, 17, 17)
node _sign_d_T_18 = bits(io.data_in, 18, 18)
node _sign_d_T_19 = bits(io.data_in, 19, 19)
node _sign_d_T_20 = bits(io.data_in, 20, 20)
node _sign_d_T_21 = bits(io.data_in, 21, 21)
node _sign_d_T_22 = bits(io.data_in, 22, 22)
node _sign_d_T_23 = bits(io.data_in, 23, 23)
node _sign_d_T_24 = bits(io.data_in, 24, 24)
node _sign_d_T_25 = bits(io.data_in, 25, 25)
node _sign_d_T_26 = bits(io.data_in, 26, 26)
node _sign_d_T_27 = bits(io.data_in, 27, 27)
node _sign_d_T_28 = bits(io.data_in, 28, 28)
node _sign_d_T_29 = bits(io.data_in, 29, 29)
node _sign_d_T_30 = bits(io.data_in, 30, 30)
node _sign_d_T_31 = bits(io.data_in, 31, 31)
node sign_d_lo = cat(_sign_d_T_15, _sign_d_T_7)
node sign_d_hi = cat(_sign_d_T_31, _sign_d_T_23)
node _sign_d_T_32 = cat(sign_d_hi, sign_d_lo)
node _sign_d_T_33 = and(_sign_d_T_32, signBit)
node sign_d = orr(_sign_d_T_33)
node _sign_s_T = bits(sum, 0, 0)
node _sign_s_T_1 = bits(sum, 1, 1)
node _sign_s_T_2 = bits(sum, 2, 2)
node _sign_s_T_3 = bits(sum, 3, 3)
node _sign_s_T_4 = bits(sum, 4, 4)
node _sign_s_T_5 = bits(sum, 5, 5)
node _sign_s_T_6 = bits(sum, 6, 6)
node _sign_s_T_7 = bits(sum, 7, 7)
node _sign_s_T_8 = bits(sum, 8, 8)
node _sign_s_T_9 = bits(sum, 9, 9)
node _sign_s_T_10 = bits(sum, 10, 10)
node _sign_s_T_11 = bits(sum, 11, 11)
node _sign_s_T_12 = bits(sum, 12, 12)
node _sign_s_T_13 = bits(sum, 13, 13)
node _sign_s_T_14 = bits(sum, 14, 14)
node _sign_s_T_15 = bits(sum, 15, 15)
node _sign_s_T_16 = bits(sum, 16, 16)
node _sign_s_T_17 = bits(sum, 17, 17)
node _sign_s_T_18 = bits(sum, 18, 18)
node _sign_s_T_19 = bits(sum, 19, 19)
node _sign_s_T_20 = bits(sum, 20, 20)
node _sign_s_T_21 = bits(sum, 21, 21)
node _sign_s_T_22 = bits(sum, 22, 22)
node _sign_s_T_23 = bits(sum, 23, 23)
node _sign_s_T_24 = bits(sum, 24, 24)
node _sign_s_T_25 = bits(sum, 25, 25)
node _sign_s_T_26 = bits(sum, 26, 26)
node _sign_s_T_27 = bits(sum, 27, 27)
node _sign_s_T_28 = bits(sum, 28, 28)
node _sign_s_T_29 = bits(sum, 29, 29)
node _sign_s_T_30 = bits(sum, 30, 30)
node _sign_s_T_31 = bits(sum, 31, 31)
node sign_s_lo = cat(_sign_s_T_15, _sign_s_T_7)
node sign_s_hi = cat(_sign_s_T_31, _sign_s_T_23)
node _sign_s_T_32 = cat(sign_s_hi, sign_s_lo)
node _sign_s_T_33 = and(_sign_s_T_32, signBit)
node sign_s = orr(_sign_s_T_33)
node a_bigger_uneq = eq(unsigned, sign_a)
node _a_bigger_T = eq(sign_a, sign_d)
node _a_bigger_T_1 = eq(sign_s, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T, _a_bigger_T_1, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
wire _lut_WIRE : UInt<4>[4]
connect _lut_WIRE[0], UInt<3>(0h6)
connect _lut_WIRE[1], UInt<4>(0he)
connect _lut_WIRE[2], UInt<4>(0h8)
connect _lut_WIRE[3], UInt<4>(0hc)
node _lut_T = bits(io.a.param, 1, 0)
node _logical_T = bits(io.a.data, 0, 0)
node _logical_T_1 = bits(io.a.data, 1, 1)
node _logical_T_2 = bits(io.a.data, 2, 2)
node _logical_T_3 = bits(io.a.data, 3, 3)
node _logical_T_4 = bits(io.a.data, 4, 4)
node _logical_T_5 = bits(io.a.data, 5, 5)
node _logical_T_6 = bits(io.a.data, 6, 6)
node _logical_T_7 = bits(io.a.data, 7, 7)
node _logical_T_8 = bits(io.a.data, 8, 8)
node _logical_T_9 = bits(io.a.data, 9, 9)
node _logical_T_10 = bits(io.a.data, 10, 10)
node _logical_T_11 = bits(io.a.data, 11, 11)
node _logical_T_12 = bits(io.a.data, 12, 12)
node _logical_T_13 = bits(io.a.data, 13, 13)
node _logical_T_14 = bits(io.a.data, 14, 14)
node _logical_T_15 = bits(io.a.data, 15, 15)
node _logical_T_16 = bits(io.a.data, 16, 16)
node _logical_T_17 = bits(io.a.data, 17, 17)
node _logical_T_18 = bits(io.a.data, 18, 18)
node _logical_T_19 = bits(io.a.data, 19, 19)
node _logical_T_20 = bits(io.a.data, 20, 20)
node _logical_T_21 = bits(io.a.data, 21, 21)
node _logical_T_22 = bits(io.a.data, 22, 22)
node _logical_T_23 = bits(io.a.data, 23, 23)
node _logical_T_24 = bits(io.a.data, 24, 24)
node _logical_T_25 = bits(io.a.data, 25, 25)
node _logical_T_26 = bits(io.a.data, 26, 26)
node _logical_T_27 = bits(io.a.data, 27, 27)
node _logical_T_28 = bits(io.a.data, 28, 28)
node _logical_T_29 = bits(io.a.data, 29, 29)
node _logical_T_30 = bits(io.a.data, 30, 30)
node _logical_T_31 = bits(io.a.data, 31, 31)
node _logical_T_32 = bits(io.data_in, 0, 0)
node _logical_T_33 = bits(io.data_in, 1, 1)
node _logical_T_34 = bits(io.data_in, 2, 2)
node _logical_T_35 = bits(io.data_in, 3, 3)
node _logical_T_36 = bits(io.data_in, 4, 4)
node _logical_T_37 = bits(io.data_in, 5, 5)
node _logical_T_38 = bits(io.data_in, 6, 6)
node _logical_T_39 = bits(io.data_in, 7, 7)
node _logical_T_40 = bits(io.data_in, 8, 8)
node _logical_T_41 = bits(io.data_in, 9, 9)
node _logical_T_42 = bits(io.data_in, 10, 10)
node _logical_T_43 = bits(io.data_in, 11, 11)
node _logical_T_44 = bits(io.data_in, 12, 12)
node _logical_T_45 = bits(io.data_in, 13, 13)
node _logical_T_46 = bits(io.data_in, 14, 14)
node _logical_T_47 = bits(io.data_in, 15, 15)
node _logical_T_48 = bits(io.data_in, 16, 16)
node _logical_T_49 = bits(io.data_in, 17, 17)
node _logical_T_50 = bits(io.data_in, 18, 18)
node _logical_T_51 = bits(io.data_in, 19, 19)
node _logical_T_52 = bits(io.data_in, 20, 20)
node _logical_T_53 = bits(io.data_in, 21, 21)
node _logical_T_54 = bits(io.data_in, 22, 22)
node _logical_T_55 = bits(io.data_in, 23, 23)
node _logical_T_56 = bits(io.data_in, 24, 24)
node _logical_T_57 = bits(io.data_in, 25, 25)
node _logical_T_58 = bits(io.data_in, 26, 26)
node _logical_T_59 = bits(io.data_in, 27, 27)
node _logical_T_60 = bits(io.data_in, 28, 28)
node _logical_T_61 = bits(io.data_in, 29, 29)
node _logical_T_62 = bits(io.data_in, 30, 30)
node _logical_T_63 = bits(io.data_in, 31, 31)
node _logical_T_64 = cat(_logical_T, _logical_T_32)
node _logical_T_65 = dshr(_lut_WIRE[_lut_T], _logical_T_64)
node _logical_T_66 = bits(_logical_T_65, 0, 0)
node _logical_T_67 = cat(_logical_T_1, _logical_T_33)
node _logical_T_68 = dshr(_lut_WIRE[_lut_T], _logical_T_67)
node _logical_T_69 = bits(_logical_T_68, 0, 0)
node _logical_T_70 = cat(_logical_T_2, _logical_T_34)
node _logical_T_71 = dshr(_lut_WIRE[_lut_T], _logical_T_70)
node _logical_T_72 = bits(_logical_T_71, 0, 0)
node _logical_T_73 = cat(_logical_T_3, _logical_T_35)
node _logical_T_74 = dshr(_lut_WIRE[_lut_T], _logical_T_73)
node _logical_T_75 = bits(_logical_T_74, 0, 0)
node _logical_T_76 = cat(_logical_T_4, _logical_T_36)
node _logical_T_77 = dshr(_lut_WIRE[_lut_T], _logical_T_76)
node _logical_T_78 = bits(_logical_T_77, 0, 0)
node _logical_T_79 = cat(_logical_T_5, _logical_T_37)
node _logical_T_80 = dshr(_lut_WIRE[_lut_T], _logical_T_79)
node _logical_T_81 = bits(_logical_T_80, 0, 0)
node _logical_T_82 = cat(_logical_T_6, _logical_T_38)
node _logical_T_83 = dshr(_lut_WIRE[_lut_T], _logical_T_82)
node _logical_T_84 = bits(_logical_T_83, 0, 0)
node _logical_T_85 = cat(_logical_T_7, _logical_T_39)
node _logical_T_86 = dshr(_lut_WIRE[_lut_T], _logical_T_85)
node _logical_T_87 = bits(_logical_T_86, 0, 0)
node _logical_T_88 = cat(_logical_T_8, _logical_T_40)
node _logical_T_89 = dshr(_lut_WIRE[_lut_T], _logical_T_88)
node _logical_T_90 = bits(_logical_T_89, 0, 0)
node _logical_T_91 = cat(_logical_T_9, _logical_T_41)
node _logical_T_92 = dshr(_lut_WIRE[_lut_T], _logical_T_91)
node _logical_T_93 = bits(_logical_T_92, 0, 0)
node _logical_T_94 = cat(_logical_T_10, _logical_T_42)
node _logical_T_95 = dshr(_lut_WIRE[_lut_T], _logical_T_94)
node _logical_T_96 = bits(_logical_T_95, 0, 0)
node _logical_T_97 = cat(_logical_T_11, _logical_T_43)
node _logical_T_98 = dshr(_lut_WIRE[_lut_T], _logical_T_97)
node _logical_T_99 = bits(_logical_T_98, 0, 0)
node _logical_T_100 = cat(_logical_T_12, _logical_T_44)
node _logical_T_101 = dshr(_lut_WIRE[_lut_T], _logical_T_100)
node _logical_T_102 = bits(_logical_T_101, 0, 0)
node _logical_T_103 = cat(_logical_T_13, _logical_T_45)
node _logical_T_104 = dshr(_lut_WIRE[_lut_T], _logical_T_103)
node _logical_T_105 = bits(_logical_T_104, 0, 0)
node _logical_T_106 = cat(_logical_T_14, _logical_T_46)
node _logical_T_107 = dshr(_lut_WIRE[_lut_T], _logical_T_106)
node _logical_T_108 = bits(_logical_T_107, 0, 0)
node _logical_T_109 = cat(_logical_T_15, _logical_T_47)
node _logical_T_110 = dshr(_lut_WIRE[_lut_T], _logical_T_109)
node _logical_T_111 = bits(_logical_T_110, 0, 0)
node _logical_T_112 = cat(_logical_T_16, _logical_T_48)
node _logical_T_113 = dshr(_lut_WIRE[_lut_T], _logical_T_112)
node _logical_T_114 = bits(_logical_T_113, 0, 0)
node _logical_T_115 = cat(_logical_T_17, _logical_T_49)
node _logical_T_116 = dshr(_lut_WIRE[_lut_T], _logical_T_115)
node _logical_T_117 = bits(_logical_T_116, 0, 0)
node _logical_T_118 = cat(_logical_T_18, _logical_T_50)
node _logical_T_119 = dshr(_lut_WIRE[_lut_T], _logical_T_118)
node _logical_T_120 = bits(_logical_T_119, 0, 0)
node _logical_T_121 = cat(_logical_T_19, _logical_T_51)
node _logical_T_122 = dshr(_lut_WIRE[_lut_T], _logical_T_121)
node _logical_T_123 = bits(_logical_T_122, 0, 0)
node _logical_T_124 = cat(_logical_T_20, _logical_T_52)
node _logical_T_125 = dshr(_lut_WIRE[_lut_T], _logical_T_124)
node _logical_T_126 = bits(_logical_T_125, 0, 0)
node _logical_T_127 = cat(_logical_T_21, _logical_T_53)
node _logical_T_128 = dshr(_lut_WIRE[_lut_T], _logical_T_127)
node _logical_T_129 = bits(_logical_T_128, 0, 0)
node _logical_T_130 = cat(_logical_T_22, _logical_T_54)
node _logical_T_131 = dshr(_lut_WIRE[_lut_T], _logical_T_130)
node _logical_T_132 = bits(_logical_T_131, 0, 0)
node _logical_T_133 = cat(_logical_T_23, _logical_T_55)
node _logical_T_134 = dshr(_lut_WIRE[_lut_T], _logical_T_133)
node _logical_T_135 = bits(_logical_T_134, 0, 0)
node _logical_T_136 = cat(_logical_T_24, _logical_T_56)
node _logical_T_137 = dshr(_lut_WIRE[_lut_T], _logical_T_136)
node _logical_T_138 = bits(_logical_T_137, 0, 0)
node _logical_T_139 = cat(_logical_T_25, _logical_T_57)
node _logical_T_140 = dshr(_lut_WIRE[_lut_T], _logical_T_139)
node _logical_T_141 = bits(_logical_T_140, 0, 0)
node _logical_T_142 = cat(_logical_T_26, _logical_T_58)
node _logical_T_143 = dshr(_lut_WIRE[_lut_T], _logical_T_142)
node _logical_T_144 = bits(_logical_T_143, 0, 0)
node _logical_T_145 = cat(_logical_T_27, _logical_T_59)
node _logical_T_146 = dshr(_lut_WIRE[_lut_T], _logical_T_145)
node _logical_T_147 = bits(_logical_T_146, 0, 0)
node _logical_T_148 = cat(_logical_T_28, _logical_T_60)
node _logical_T_149 = dshr(_lut_WIRE[_lut_T], _logical_T_148)
node _logical_T_150 = bits(_logical_T_149, 0, 0)
node _logical_T_151 = cat(_logical_T_29, _logical_T_61)
node _logical_T_152 = dshr(_lut_WIRE[_lut_T], _logical_T_151)
node _logical_T_153 = bits(_logical_T_152, 0, 0)
node _logical_T_154 = cat(_logical_T_30, _logical_T_62)
node _logical_T_155 = dshr(_lut_WIRE[_lut_T], _logical_T_154)
node _logical_T_156 = bits(_logical_T_155, 0, 0)
node _logical_T_157 = cat(_logical_T_31, _logical_T_63)
node _logical_T_158 = dshr(_lut_WIRE[_lut_T], _logical_T_157)
node _logical_T_159 = bits(_logical_T_158, 0, 0)
node logical_lo_lo_lo_lo = cat(_logical_T_69, _logical_T_66)
node logical_lo_lo_lo_hi = cat(_logical_T_75, _logical_T_72)
node logical_lo_lo_lo = cat(logical_lo_lo_lo_hi, logical_lo_lo_lo_lo)
node logical_lo_lo_hi_lo = cat(_logical_T_81, _logical_T_78)
node logical_lo_lo_hi_hi = cat(_logical_T_87, _logical_T_84)
node logical_lo_lo_hi = cat(logical_lo_lo_hi_hi, logical_lo_lo_hi_lo)
node logical_lo_lo = cat(logical_lo_lo_hi, logical_lo_lo_lo)
node logical_lo_hi_lo_lo = cat(_logical_T_93, _logical_T_90)
node logical_lo_hi_lo_hi = cat(_logical_T_99, _logical_T_96)
node logical_lo_hi_lo = cat(logical_lo_hi_lo_hi, logical_lo_hi_lo_lo)
node logical_lo_hi_hi_lo = cat(_logical_T_105, _logical_T_102)
node logical_lo_hi_hi_hi = cat(_logical_T_111, _logical_T_108)
node logical_lo_hi_hi = cat(logical_lo_hi_hi_hi, logical_lo_hi_hi_lo)
node logical_lo_hi = cat(logical_lo_hi_hi, logical_lo_hi_lo)
node logical_lo = cat(logical_lo_hi, logical_lo_lo)
node logical_hi_lo_lo_lo = cat(_logical_T_117, _logical_T_114)
node logical_hi_lo_lo_hi = cat(_logical_T_123, _logical_T_120)
node logical_hi_lo_lo = cat(logical_hi_lo_lo_hi, logical_hi_lo_lo_lo)
node logical_hi_lo_hi_lo = cat(_logical_T_129, _logical_T_126)
node logical_hi_lo_hi_hi = cat(_logical_T_135, _logical_T_132)
node logical_hi_lo_hi = cat(logical_hi_lo_hi_hi, logical_hi_lo_hi_lo)
node logical_hi_lo = cat(logical_hi_lo_hi, logical_hi_lo_lo)
node logical_hi_hi_lo_lo = cat(_logical_T_141, _logical_T_138)
node logical_hi_hi_lo_hi = cat(_logical_T_147, _logical_T_144)
node logical_hi_hi_lo = cat(logical_hi_hi_lo_hi, logical_hi_hi_lo_lo)
node logical_hi_hi_hi_lo = cat(_logical_T_153, _logical_T_150)
node logical_hi_hi_hi_hi = cat(_logical_T_159, _logical_T_156)
node logical_hi_hi_hi = cat(logical_hi_hi_hi_hi, logical_hi_hi_hi_lo)
node logical_hi_hi = cat(logical_hi_hi_hi, logical_hi_hi_lo)
node logical_hi = cat(logical_hi_hi, logical_hi_lo)
node logical = cat(logical_hi, logical_lo)
node _select_T = mux(pick_a, UInt<1>(0h1), UInt<1>(0h0))
node _select_T_1 = mux(adder, UInt<2>(0h2), _select_T)
wire _select_WIRE : UInt<2>[8]
connect _select_WIRE[0], UInt<1>(0h1)
connect _select_WIRE[1], UInt<1>(0h1)
connect _select_WIRE[2], _select_T_1
connect _select_WIRE[3], UInt<2>(0h3)
connect _select_WIRE[4], UInt<1>(0h0)
connect _select_WIRE[5], UInt<1>(0h0)
connect _select_WIRE[6], UInt<1>(0h0)
connect _select_WIRE[7], UInt<1>(0h0)
node select = mux(io.write, UInt<1>(0h1), _select_WIRE[io.a.opcode])
node _selects_T = bits(io.a.mask, 0, 0)
node _selects_T_1 = bits(io.a.mask, 1, 1)
node _selects_T_2 = bits(io.a.mask, 2, 2)
node _selects_T_3 = bits(io.a.mask, 3, 3)
node selects_0 = mux(_selects_T, select, UInt<1>(0h0))
node selects_1 = mux(_selects_T_1, select, UInt<1>(0h0))
node selects_2 = mux(_selects_T_2, select, UInt<1>(0h0))
node selects_3 = mux(_selects_T_3, select, UInt<1>(0h0))
node _io_data_out_T = bits(io.data_in, 7, 0)
node _io_data_out_T_1 = bits(io.a.data, 7, 0)
node _io_data_out_T_2 = bits(sum, 7, 0)
node _io_data_out_T_3 = bits(logical, 7, 0)
wire _io_data_out_WIRE : UInt<8>[4]
connect _io_data_out_WIRE[0], _io_data_out_T
connect _io_data_out_WIRE[1], _io_data_out_T_1
connect _io_data_out_WIRE[2], _io_data_out_T_2
connect _io_data_out_WIRE[3], _io_data_out_T_3
node _io_data_out_T_4 = bits(io.data_in, 15, 8)
node _io_data_out_T_5 = bits(io.a.data, 15, 8)
node _io_data_out_T_6 = bits(sum, 15, 8)
node _io_data_out_T_7 = bits(logical, 15, 8)
wire _io_data_out_WIRE_1 : UInt<8>[4]
connect _io_data_out_WIRE_1[0], _io_data_out_T_4
connect _io_data_out_WIRE_1[1], _io_data_out_T_5
connect _io_data_out_WIRE_1[2], _io_data_out_T_6
connect _io_data_out_WIRE_1[3], _io_data_out_T_7
node _io_data_out_T_8 = bits(io.data_in, 23, 16)
node _io_data_out_T_9 = bits(io.a.data, 23, 16)
node _io_data_out_T_10 = bits(sum, 23, 16)
node _io_data_out_T_11 = bits(logical, 23, 16)
wire _io_data_out_WIRE_2 : UInt<8>[4]
connect _io_data_out_WIRE_2[0], _io_data_out_T_8
connect _io_data_out_WIRE_2[1], _io_data_out_T_9
connect _io_data_out_WIRE_2[2], _io_data_out_T_10
connect _io_data_out_WIRE_2[3], _io_data_out_T_11
node _io_data_out_T_12 = bits(io.data_in, 31, 24)
node _io_data_out_T_13 = bits(io.a.data, 31, 24)
node _io_data_out_T_14 = bits(sum, 31, 24)
node _io_data_out_T_15 = bits(logical, 31, 24)
wire _io_data_out_WIRE_3 : UInt<8>[4]
connect _io_data_out_WIRE_3[0], _io_data_out_T_12
connect _io_data_out_WIRE_3[1], _io_data_out_T_13
connect _io_data_out_WIRE_3[2], _io_data_out_T_14
connect _io_data_out_WIRE_3[3], _io_data_out_T_15
node io_data_out_lo = cat(_io_data_out_WIRE_1[selects_1], _io_data_out_WIRE[selects_0])
node io_data_out_hi = cat(_io_data_out_WIRE_3[selects_3], _io_data_out_WIRE_2[selects_2])
node _io_data_out_T_16 = cat(io_data_out_hi, io_data_out_lo)
connect io.data_out, _io_data_out_T_16 | module Atomics( // @[Atomics.scala:8:7]
input clock, // @[Atomics.scala:8:7]
input reset, // @[Atomics.scala:8:7]
input io_write, // @[Atomics.scala:10:14]
input [2:0] io_a_opcode, // @[Atomics.scala:10:14]
input [2:0] io_a_param, // @[Atomics.scala:10:14]
input [3:0] io_a_mask, // @[Atomics.scala:10:14]
input [31:0] io_a_data, // @[Atomics.scala:10:14]
input [31:0] io_data_in, // @[Atomics.scala:10:14]
output [31:0] io_data_out // @[Atomics.scala:10:14]
);
wire io_write_0 = io_write; // @[Atomics.scala:8:7]
wire [2:0] io_a_opcode_0 = io_a_opcode; // @[Atomics.scala:8:7]
wire [2:0] io_a_param_0 = io_a_param; // @[Atomics.scala:8:7]
wire [3:0] io_a_mask_0 = io_a_mask; // @[Atomics.scala:8:7]
wire [31:0] io_a_data_0 = io_a_data; // @[Atomics.scala:8:7]
wire [31:0] io_data_in_0 = io_data_in; // @[Atomics.scala:8:7]
wire [3:0][3:0] _GEN = '{4'hC, 4'h8, 4'hE, 4'h6};
wire [3:0] _lut_WIRE_0 = 4'h6; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_1 = 4'hE; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_2 = 4'h8; // @[Atomics.scala:34:20]
wire [3:0] _lut_WIRE_3 = 4'hC; // @[Atomics.scala:34:20]
wire [1:0] _select_WIRE_0 = 2'h1; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_1 = 2'h1; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_3 = 2'h3; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_4 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_5 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_6 = 2'h0; // @[Atomics.scala:45:42]
wire [1:0] _select_WIRE_7 = 2'h0; // @[Atomics.scala:45:42]
wire io_a_corrupt = 1'h0; // @[Atomics.scala:8:7, :10:14]
wire [31:0] io_a_address = 32'h0; // @[Atomics.scala:8:7, :10:14]
wire [5:0] io_a_source = 6'h0; // @[Atomics.scala:8:7, :10:14]
wire [2:0] io_a_size = 3'h0; // @[Atomics.scala:8:7, :10:14]
wire [31:0] _io_data_out_T_16; // @[Atomics.scala:58:21]
wire [31:0] io_data_out_0; // @[Atomics.scala:8:7]
wire adder = io_a_param_0[2]; // @[Atomics.scala:8:7, :18:28]
wire unsigned_0 = io_a_param_0[1]; // @[Atomics.scala:8:7, :19:28]
wire take_max = io_a_param_0[0]; // @[Atomics.scala:8:7, :20:28]
wire [3:0] _signBit_T = ~io_a_mask_0; // @[Atomics.scala:8:7, :22:38]
wire [2:0] _signBit_T_1 = _signBit_T[3:1]; // @[Atomics.scala:22:{38,49}]
wire [3:0] _signBit_T_2 = {1'h1, _signBit_T_1}; // @[Atomics.scala:22:{32,49}]
wire [3:0] signBit = io_a_mask_0 & _signBit_T_2; // @[Atomics.scala:8:7, :22:{27,32}]
wire [31:0] _inv_d_T = ~io_data_in_0; // @[Atomics.scala:8:7, :23:38]
wire [31:0] inv_d = adder ? io_data_in_0 : _inv_d_T; // @[Atomics.scala:8:7, :18:28, :23:{18,38}]
wire _sum_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T = io_a_mask_0[0]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_1 = io_a_mask_0[1]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_2 = io_a_mask_0[2]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire _sum_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29]
wire _selects_T_3 = io_a_mask_0[3]; // @[Atomics.scala:8:7, :24:29, :57:27]
wire [7:0] _sum_T_4 = {8{_sum_T}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_5 = {8{_sum_T_1}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_6 = {8{_sum_T_2}}; // @[Atomics.scala:24:29]
wire [7:0] _sum_T_7 = {8{_sum_T_3}}; // @[Atomics.scala:24:29]
wire [15:0] sum_lo = {_sum_T_5, _sum_T_4}; // @[Atomics.scala:24:29]
wire [15:0] sum_hi = {_sum_T_7, _sum_T_6}; // @[Atomics.scala:24:29]
wire [31:0] _sum_T_8 = {sum_hi, sum_lo}; // @[Atomics.scala:24:29]
wire [31:0] _sum_T_9 = _sum_T_8 & io_a_data_0; // @[Atomics.scala:8:7, :24:{29,44}]
wire [32:0] _sum_T_10 = {1'h0, _sum_T_9} + {1'h0, inv_d}; // @[Atomics.scala:8:7, :10:14, :23:18, :24:{44,57}]
wire [31:0] sum = _sum_T_10[31:0]; // @[Atomics.scala:24:57]
wire _sign_a_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T = io_a_data_0[0]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_1 = io_a_data_0[1]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_2 = io_a_data_0[2]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_3 = io_a_data_0[3]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_4 = io_a_data_0[4]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_5 = io_a_data_0[5]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_6 = io_a_data_0[6]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_7 = io_a_data_0[7]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_8 = io_a_data_0[8]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_9 = io_a_data_0[9]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_10 = io_a_data_0[10]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_11 = io_a_data_0[11]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_12 = io_a_data_0[12]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_13 = io_a_data_0[13]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_14 = io_a_data_0[14]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_15 = io_a_data_0[15]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_16 = io_a_data_0[16]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_17 = io_a_data_0[17]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_18 = io_a_data_0[18]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_19 = io_a_data_0[19]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_20 = io_a_data_0[20]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_21 = io_a_data_0[21]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_22 = io_a_data_0[22]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_23 = io_a_data_0[23]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_24 = io_a_data_0[24]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_25 = io_a_data_0[25]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_26 = io_a_data_0[26]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_27 = io_a_data_0[27]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_28 = io_a_data_0[28]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_29 = io_a_data_0[29]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_30 = io_a_data_0[30]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire _sign_a_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_31 = io_a_data_0[31]; // @[Atomics.scala:8:7, :25:36, :40:32]
wire [1:0] sign_a_lo = {_sign_a_T_15, _sign_a_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_a_hi = {_sign_a_T_31, _sign_a_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] _sign_a_T_32 = {sign_a_hi, sign_a_lo}; // @[Atomics.scala:25:33]
wire [3:0] _sign_a_T_33 = _sign_a_T_32 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_a = |_sign_a_T_33; // @[Atomics.scala:25:{83,94}]
wire _sign_d_T = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_32 = io_data_in_0[0]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_1 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_33 = io_data_in_0[1]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_2 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_34 = io_data_in_0[2]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_3 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_35 = io_data_in_0[3]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_4 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_36 = io_data_in_0[4]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_5 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_37 = io_data_in_0[5]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_6 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_38 = io_data_in_0[6]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_7 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_39 = io_data_in_0[7]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_8 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_40 = io_data_in_0[8]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_9 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_41 = io_data_in_0[9]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_10 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_42 = io_data_in_0[10]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_11 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_43 = io_data_in_0[11]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_12 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_44 = io_data_in_0[12]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_13 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_45 = io_data_in_0[13]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_14 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_46 = io_data_in_0[14]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_15 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_47 = io_data_in_0[15]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_16 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_48 = io_data_in_0[16]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_17 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_49 = io_data_in_0[17]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_18 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_50 = io_data_in_0[18]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_19 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_51 = io_data_in_0[19]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_20 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_52 = io_data_in_0[20]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_21 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_53 = io_data_in_0[21]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_22 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_54 = io_data_in_0[22]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_23 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_55 = io_data_in_0[23]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_24 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_56 = io_data_in_0[24]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_25 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_57 = io_data_in_0[25]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_26 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_58 = io_data_in_0[26]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_27 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_59 = io_data_in_0[27]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_28 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_60 = io_data_in_0[28]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_29 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_61 = io_data_in_0[29]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_30 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_62 = io_data_in_0[30]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire _sign_d_T_31 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36]
wire _logical_T_63 = io_data_in_0[31]; // @[Atomics.scala:8:7, :25:36, :40:55]
wire [1:0] sign_d_lo = {_sign_d_T_15, _sign_d_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_d_hi = {_sign_d_T_31, _sign_d_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] _sign_d_T_32 = {sign_d_hi, sign_d_lo}; // @[Atomics.scala:25:33]
wire [3:0] _sign_d_T_33 = _sign_d_T_32 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_d = |_sign_d_T_33; // @[Atomics.scala:25:{83,94}]
wire _sign_s_T = sum[0]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_1 = sum[1]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_2 = sum[2]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_3 = sum[3]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_4 = sum[4]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_5 = sum[5]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_6 = sum[6]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_7 = sum[7]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_8 = sum[8]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_9 = sum[9]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_10 = sum[10]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_11 = sum[11]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_12 = sum[12]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_13 = sum[13]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_14 = sum[14]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_15 = sum[15]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_16 = sum[16]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_17 = sum[17]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_18 = sum[18]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_19 = sum[19]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_20 = sum[20]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_21 = sum[21]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_22 = sum[22]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_23 = sum[23]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_24 = sum[24]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_25 = sum[25]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_26 = sum[26]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_27 = sum[27]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_28 = sum[28]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_29 = sum[29]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_30 = sum[30]; // @[Atomics.scala:24:57, :25:36]
wire _sign_s_T_31 = sum[31]; // @[Atomics.scala:24:57, :25:36]
wire [1:0] sign_s_lo = {_sign_s_T_15, _sign_s_T_7}; // @[Atomics.scala:25:{33,36}]
wire [1:0] sign_s_hi = {_sign_s_T_31, _sign_s_T_23}; // @[Atomics.scala:25:{33,36}]
wire [3:0] _sign_s_T_32 = {sign_s_hi, sign_s_lo}; // @[Atomics.scala:25:33]
wire [3:0] _sign_s_T_33 = _sign_s_T_32 & signBit; // @[Atomics.scala:22:27, :25:{33,83}]
wire sign_s = |_sign_s_T_33; // @[Atomics.scala:25:{83,94}]
wire a_bigger_uneq = unsigned_0 == sign_a; // @[Atomics.scala:19:28, :25:94, :29:32]
wire _a_bigger_T = sign_a == sign_d; // @[Atomics.scala:25:94, :30:29]
wire _a_bigger_T_1 = ~sign_s; // @[Atomics.scala:25:94, :30:41]
wire a_bigger = _a_bigger_T ? _a_bigger_T_1 : a_bigger_uneq; // @[Atomics.scala:29:32, :30:{21,29,41}]
wire pick_a = take_max == a_bigger; // @[Atomics.scala:20:28, :30:21, :31:25]
wire _select_T = pick_a; // @[Atomics.scala:31:25, :48:24]
wire [1:0] _lut_T = io_a_param_0[1:0]; // @[Atomics.scala:8:7, :39:15]
wire [1:0] _logical_T_64 = {_logical_T, _logical_T_32}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_65 = _GEN[_lut_T] >> _logical_T_64; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_66 = _logical_T_65[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_67 = {_logical_T_1, _logical_T_33}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_68 = _GEN[_lut_T] >> _logical_T_67; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_69 = _logical_T_68[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_70 = {_logical_T_2, _logical_T_34}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_71 = _GEN[_lut_T] >> _logical_T_70; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_72 = _logical_T_71[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_73 = {_logical_T_3, _logical_T_35}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_74 = _GEN[_lut_T] >> _logical_T_73; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_75 = _logical_T_74[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_76 = {_logical_T_4, _logical_T_36}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_77 = _GEN[_lut_T] >> _logical_T_76; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_78 = _logical_T_77[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_79 = {_logical_T_5, _logical_T_37}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_80 = _GEN[_lut_T] >> _logical_T_79; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_81 = _logical_T_80[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_82 = {_logical_T_6, _logical_T_38}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_83 = _GEN[_lut_T] >> _logical_T_82; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_84 = _logical_T_83[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_85 = {_logical_T_7, _logical_T_39}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_86 = _GEN[_lut_T] >> _logical_T_85; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_87 = _logical_T_86[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_88 = {_logical_T_8, _logical_T_40}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_89 = _GEN[_lut_T] >> _logical_T_88; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_90 = _logical_T_89[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_91 = {_logical_T_9, _logical_T_41}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_92 = _GEN[_lut_T] >> _logical_T_91; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_93 = _logical_T_92[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_94 = {_logical_T_10, _logical_T_42}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_95 = _GEN[_lut_T] >> _logical_T_94; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_96 = _logical_T_95[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_97 = {_logical_T_11, _logical_T_43}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_98 = _GEN[_lut_T] >> _logical_T_97; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_99 = _logical_T_98[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_100 = {_logical_T_12, _logical_T_44}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_101 = _GEN[_lut_T] >> _logical_T_100; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_102 = _logical_T_101[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_103 = {_logical_T_13, _logical_T_45}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_104 = _GEN[_lut_T] >> _logical_T_103; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_105 = _logical_T_104[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_106 = {_logical_T_14, _logical_T_46}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_107 = _GEN[_lut_T] >> _logical_T_106; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_108 = _logical_T_107[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_109 = {_logical_T_15, _logical_T_47}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_110 = _GEN[_lut_T] >> _logical_T_109; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_111 = _logical_T_110[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_112 = {_logical_T_16, _logical_T_48}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_113 = _GEN[_lut_T] >> _logical_T_112; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_114 = _logical_T_113[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_115 = {_logical_T_17, _logical_T_49}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_116 = _GEN[_lut_T] >> _logical_T_115; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_117 = _logical_T_116[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_118 = {_logical_T_18, _logical_T_50}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_119 = _GEN[_lut_T] >> _logical_T_118; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_120 = _logical_T_119[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_121 = {_logical_T_19, _logical_T_51}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_122 = _GEN[_lut_T] >> _logical_T_121; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_123 = _logical_T_122[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_124 = {_logical_T_20, _logical_T_52}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_125 = _GEN[_lut_T] >> _logical_T_124; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_126 = _logical_T_125[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_127 = {_logical_T_21, _logical_T_53}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_128 = _GEN[_lut_T] >> _logical_T_127; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_129 = _logical_T_128[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_130 = {_logical_T_22, _logical_T_54}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_131 = _GEN[_lut_T] >> _logical_T_130; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_132 = _logical_T_131[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_133 = {_logical_T_23, _logical_T_55}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_134 = _GEN[_lut_T] >> _logical_T_133; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_135 = _logical_T_134[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_136 = {_logical_T_24, _logical_T_56}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_137 = _GEN[_lut_T] >> _logical_T_136; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_138 = _logical_T_137[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_139 = {_logical_T_25, _logical_T_57}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_140 = _GEN[_lut_T] >> _logical_T_139; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_141 = _logical_T_140[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_142 = {_logical_T_26, _logical_T_58}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_143 = _GEN[_lut_T] >> _logical_T_142; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_144 = _logical_T_143[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_145 = {_logical_T_27, _logical_T_59}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_146 = _GEN[_lut_T] >> _logical_T_145; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_147 = _logical_T_146[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_148 = {_logical_T_28, _logical_T_60}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_149 = _GEN[_lut_T] >> _logical_T_148; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_150 = _logical_T_149[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_151 = {_logical_T_29, _logical_T_61}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_152 = _GEN[_lut_T] >> _logical_T_151; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_153 = _logical_T_152[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_154 = {_logical_T_30, _logical_T_62}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_155 = _GEN[_lut_T] >> _logical_T_154; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_156 = _logical_T_155[0]; // @[Atomics.scala:41:8]
wire [1:0] _logical_T_157 = {_logical_T_31, _logical_T_63}; // @[Atomics.scala:40:{32,55}, :41:12]
wire [3:0] _logical_T_158 = _GEN[_lut_T] >> _logical_T_157; // @[Atomics.scala:39:15, :41:{8,12}]
wire _logical_T_159 = _logical_T_158[0]; // @[Atomics.scala:41:8]
wire [1:0] logical_lo_lo_lo_lo = {_logical_T_69, _logical_T_66}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_lo_hi = {_logical_T_75, _logical_T_72}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_lo = {logical_lo_lo_lo_hi, logical_lo_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_lo_hi_lo = {_logical_T_81, _logical_T_78}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_lo_hi_hi = {_logical_T_87, _logical_T_84}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_lo_hi = {logical_lo_lo_hi_hi, logical_lo_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_lo = {logical_lo_lo_hi, logical_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_lo_lo = {_logical_T_93, _logical_T_90}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_lo_hi = {_logical_T_99, _logical_T_96}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_lo = {logical_lo_hi_lo_hi, logical_lo_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_lo_hi_hi_lo = {_logical_T_105, _logical_T_102}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_lo_hi_hi_hi = {_logical_T_111, _logical_T_108}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_lo_hi_hi = {logical_lo_hi_hi_hi, logical_lo_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_lo_hi = {logical_lo_hi_hi, logical_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_lo = {logical_lo_hi, logical_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_lo_lo = {_logical_T_117, _logical_T_114}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_lo_hi = {_logical_T_123, _logical_T_120}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_lo = {logical_hi_lo_lo_hi, logical_hi_lo_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_lo_hi_lo = {_logical_T_129, _logical_T_126}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_lo_hi_hi = {_logical_T_135, _logical_T_132}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_lo_hi = {logical_hi_lo_hi_hi, logical_hi_lo_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_lo = {logical_hi_lo_hi, logical_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_lo_lo = {_logical_T_141, _logical_T_138}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_lo_hi = {_logical_T_147, _logical_T_144}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_lo = {logical_hi_hi_lo_hi, logical_hi_hi_lo_lo}; // @[Atomics.scala:40:20]
wire [1:0] logical_hi_hi_hi_lo = {_logical_T_153, _logical_T_150}; // @[Atomics.scala:40:20, :41:8]
wire [1:0] logical_hi_hi_hi_hi = {_logical_T_159, _logical_T_156}; // @[Atomics.scala:40:20, :41:8]
wire [3:0] logical_hi_hi_hi = {logical_hi_hi_hi_hi, logical_hi_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [7:0] logical_hi_hi = {logical_hi_hi_hi, logical_hi_hi_lo}; // @[Atomics.scala:40:20]
wire [15:0] logical_hi = {logical_hi_hi, logical_hi_lo}; // @[Atomics.scala:40:20]
wire [31:0] logical = {logical_hi, logical_lo}; // @[Atomics.scala:40:20]
wire [1:0] _select_T_1 = adder ? 2'h2 : {1'h0, _select_T}; // @[Atomics.scala:8:7, :10:14, :18:28, :48:{8,24}]
wire [1:0] _select_WIRE_2 = _select_T_1; // @[Atomics.scala:45:42, :48:8]
wire [7:0][1:0] _GEN_0 = {{2'h0}, {2'h0}, {2'h0}, {2'h0}, {2'h3}, {_select_WIRE_2}, {2'h1}, {2'h1}}; // @[Atomics.scala:45:{19,42}]
wire [1:0] select = io_write_0 ? 2'h1 : _GEN_0[io_a_opcode_0]; // @[Atomics.scala:8:7, :45:19]
wire [1:0] selects_0 = _selects_T ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_1 = _selects_T_1 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_2 = _selects_T_2 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [1:0] selects_3 = _selects_T_3 ? select : 2'h0; // @[Atomics.scala:45:19, :57:{27,47}]
wire [7:0] _io_data_out_T = io_data_in_0[7:0]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_0 = _io_data_out_T; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_1 = io_a_data_0[7:0]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1 = _io_data_out_T_1; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_2 = sum[7:0]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_2 = _io_data_out_T_2; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_3 = logical[7:0]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_3 = _io_data_out_T_3; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_4 = io_data_in_0[15:8]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1_0 = _io_data_out_T_4; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_5 = io_a_data_0[15:8]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_1_1 = _io_data_out_T_5; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_6 = sum[15:8]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_1_2 = _io_data_out_T_6; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_7 = logical[15:8]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_1_3 = _io_data_out_T_7; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_8 = io_data_in_0[23:16]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_2_0 = _io_data_out_T_8; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_9 = io_a_data_0[23:16]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_2_1 = _io_data_out_T_9; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_10 = sum[23:16]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_2_2 = _io_data_out_T_10; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_11 = logical[23:16]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_2_3 = _io_data_out_T_11; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_12 = io_data_in_0[31:24]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_3_0 = _io_data_out_T_12; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_13 = io_a_data_0[31:24]; // @[Atomics.scala:8:7, :59:59]
wire [7:0] _io_data_out_WIRE_3_1 = _io_data_out_T_13; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_14 = sum[31:24]; // @[Atomics.scala:24:57, :59:59]
wire [7:0] _io_data_out_WIRE_3_2 = _io_data_out_T_14; // @[Atomics.scala:59:{12,59}]
wire [7:0] _io_data_out_T_15 = logical[31:24]; // @[Atomics.scala:40:20, :59:59]
wire [7:0] _io_data_out_WIRE_3_3 = _io_data_out_T_15; // @[Atomics.scala:59:{12,59}]
wire [3:0][7:0] _GEN_1 = {{_io_data_out_WIRE_1_3}, {_io_data_out_WIRE_1_2}, {_io_data_out_WIRE_1_1}, {_io_data_out_WIRE_1_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_2 = {{_io_data_out_WIRE_3}, {_io_data_out_WIRE_2}, {_io_data_out_WIRE_1}, {_io_data_out_WIRE_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_lo = {_GEN_1[selects_1], _GEN_2[selects_0]}; // @[Atomics.scala:57:47, :58:21]
wire [3:0][7:0] _GEN_3 = {{_io_data_out_WIRE_3_3}, {_io_data_out_WIRE_3_2}, {_io_data_out_WIRE_3_1}, {_io_data_out_WIRE_3_0}}; // @[Atomics.scala:58:21, :59:12]
wire [3:0][7:0] _GEN_4 = {{_io_data_out_WIRE_2_3}, {_io_data_out_WIRE_2_2}, {_io_data_out_WIRE_2_1}, {_io_data_out_WIRE_2_0}}; // @[Atomics.scala:58:21, :59:12]
wire [15:0] io_data_out_hi = {_GEN_3[selects_3], _GEN_4[selects_2]}; // @[Atomics.scala:57:47, :58:21]
assign _io_data_out_T_16 = {io_data_out_hi, io_data_out_lo}; // @[Atomics.scala:58:21]
assign io_data_out_0 = _io_data_out_T_16; // @[Atomics.scala:8:7, :58:21]
assign io_data_out = io_data_out_0; // @[Atomics.scala:8:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_18 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T = shr(io.in.a.bits.source, 3)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 3)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_4 = shr(io.in.a.bits.source, 3)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<3>(0h7))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_17 = shr(io.in.a.bits.source, 3)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _T_30 = and(_T_16, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_30, UInt<1>(0h1), "") : assert_1
node _T_34 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_34 :
node _T_35 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_36 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_37 = and(_T_35, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0)
node _T_38 = shr(io.in.a.bits.source, 3)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<3>(0h7))
node _T_43 = and(_T_41, _T_42)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0)
node _T_44 = shr(io.in.a.bits.source, 3)
node _T_45 = eq(_T_44, UInt<1>(0h1))
node _T_46 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_47 = and(_T_45, _T_46)
node _T_48 = leq(uncommonBits_3, UInt<3>(0h7))
node _T_49 = and(_T_47, _T_48)
node _T_50 = or(_T_43, _T_49)
node _T_51 = and(_T_37, _T_50)
node _T_52 = or(UInt<1>(0h0), _T_51)
node _T_53 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_54 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<14>(0h2000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<18>(0h2f000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<17>(0h10000)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<27>(0h4000000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<13>(0h1000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<30>(0h20000000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_95 = cvt(_T_94)
node _T_96 = and(_T_95, asSInt(UInt<15>(0h4000)))
node _T_97 = asSInt(_T_96)
node _T_98 = eq(_T_97, asSInt(UInt<1>(0h0)))
node _T_99 = or(_T_58, _T_63)
node _T_100 = or(_T_99, _T_68)
node _T_101 = or(_T_100, _T_73)
node _T_102 = or(_T_101, _T_78)
node _T_103 = or(_T_102, _T_83)
node _T_104 = or(_T_103, _T_88)
node _T_105 = or(_T_104, _T_93)
node _T_106 = or(_T_105, _T_98)
node _T_107 = and(_T_53, _T_106)
node _T_108 = or(UInt<1>(0h0), _T_107)
node _T_109 = and(_T_52, _T_108)
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_109, UInt<1>(0h1), "") : assert_2
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<14>(0h2000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<13>(0h1000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<18>(0h2f000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<27>(0h4000000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<13>(0h1000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_153 = cvt(_T_152)
node _T_154 = and(_T_153, asSInt(UInt<30>(0h20000000)))
node _T_155 = asSInt(_T_154)
node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<15>(0h4000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = or(_T_121, _T_126)
node _T_163 = or(_T_162, _T_131)
node _T_164 = or(_T_163, _T_136)
node _T_165 = or(_T_164, _T_141)
node _T_166 = or(_T_165, _T_146)
node _T_167 = or(_T_166, _T_151)
node _T_168 = or(_T_167, _T_156)
node _T_169 = or(_T_168, _T_161)
node _T_170 = and(_T_116, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = and(UInt<1>(0h0), _T_171)
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_172, UInt<1>(0h1), "") : assert_3
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(source_ok, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_179 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_179, UInt<1>(0h1), "") : assert_5
node _T_183 = asUInt(reset)
node _T_184 = eq(_T_183, UInt<1>(0h0))
when _T_184 :
node _T_185 = eq(is_aligned, UInt<1>(0h0))
when _T_185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_186 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_T_186, UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_186, UInt<1>(0h1), "") : assert_7
node _T_190 = not(io.in.a.bits.mask)
node _T_191 = eq(_T_190, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_191, UInt<1>(0h1), "") : assert_8
node _T_195 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(_T_195, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_195, UInt<1>(0h1), "") : assert_9
node _T_199 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_199 :
node _T_200 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_201 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_202 = and(_T_200, _T_201)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_203 = shr(io.in.a.bits.source, 3)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_206 = and(_T_204, _T_205)
node _T_207 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_208 = and(_T_206, _T_207)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_209 = shr(io.in.a.bits.source, 3)
node _T_210 = eq(_T_209, UInt<1>(0h1))
node _T_211 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_212 = and(_T_210, _T_211)
node _T_213 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_214 = and(_T_212, _T_213)
node _T_215 = or(_T_208, _T_214)
node _T_216 = and(_T_202, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_219 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_220 = cvt(_T_219)
node _T_221 = and(_T_220, asSInt(UInt<14>(0h2000)))
node _T_222 = asSInt(_T_221)
node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0)))
node _T_224 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_225 = cvt(_T_224)
node _T_226 = and(_T_225, asSInt(UInt<13>(0h1000)))
node _T_227 = asSInt(_T_226)
node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0)))
node _T_229 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_230 = cvt(_T_229)
node _T_231 = and(_T_230, asSInt(UInt<17>(0h10000)))
node _T_232 = asSInt(_T_231)
node _T_233 = eq(_T_232, asSInt(UInt<1>(0h0)))
node _T_234 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<18>(0h2f000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<17>(0h10000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<27>(0h4000000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<13>(0h1000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<30>(0h20000000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<15>(0h4000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = or(_T_223, _T_228)
node _T_265 = or(_T_264, _T_233)
node _T_266 = or(_T_265, _T_238)
node _T_267 = or(_T_266, _T_243)
node _T_268 = or(_T_267, _T_248)
node _T_269 = or(_T_268, _T_253)
node _T_270 = or(_T_269, _T_258)
node _T_271 = or(_T_270, _T_263)
node _T_272 = and(_T_218, _T_271)
node _T_273 = or(UInt<1>(0h0), _T_272)
node _T_274 = and(_T_217, _T_273)
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_274, UInt<1>(0h1), "") : assert_10
node _T_278 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_279 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_280 = and(_T_278, _T_279)
node _T_281 = or(UInt<1>(0h0), _T_280)
node _T_282 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<14>(0h2000)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_288 = cvt(_T_287)
node _T_289 = and(_T_288, asSInt(UInt<13>(0h1000)))
node _T_290 = asSInt(_T_289)
node _T_291 = eq(_T_290, asSInt(UInt<1>(0h0)))
node _T_292 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_298 = cvt(_T_297)
node _T_299 = and(_T_298, asSInt(UInt<18>(0h2f000)))
node _T_300 = asSInt(_T_299)
node _T_301 = eq(_T_300, asSInt(UInt<1>(0h0)))
node _T_302 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<17>(0h10000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<27>(0h4000000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<13>(0h1000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<30>(0h20000000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<15>(0h4000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = or(_T_286, _T_291)
node _T_328 = or(_T_327, _T_296)
node _T_329 = or(_T_328, _T_301)
node _T_330 = or(_T_329, _T_306)
node _T_331 = or(_T_330, _T_311)
node _T_332 = or(_T_331, _T_316)
node _T_333 = or(_T_332, _T_321)
node _T_334 = or(_T_333, _T_326)
node _T_335 = and(_T_281, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(UInt<1>(0h0), _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_337, UInt<1>(0h1), "") : assert_11
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(source_ok, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_344 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_345 = asUInt(reset)
node _T_346 = eq(_T_345, UInt<1>(0h0))
when _T_346 :
node _T_347 = eq(_T_344, UInt<1>(0h0))
when _T_347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_344, UInt<1>(0h1), "") : assert_13
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(is_aligned, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_351 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_351, UInt<1>(0h1), "") : assert_15
node _T_355 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_355, UInt<1>(0h1), "") : assert_16
node _T_359 = not(io.in.a.bits.mask)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_360, UInt<1>(0h1), "") : assert_17
node _T_364 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_365 = asUInt(reset)
node _T_366 = eq(_T_365, UInt<1>(0h0))
when _T_366 :
node _T_367 = eq(_T_364, UInt<1>(0h0))
when _T_367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_364, UInt<1>(0h1), "") : assert_18
node _T_368 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_368 :
node _T_369 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_370 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_371 = and(_T_369, _T_370)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_372 = shr(io.in.a.bits.source, 3)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_375 = and(_T_373, _T_374)
node _T_376 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_377 = and(_T_375, _T_376)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_378 = shr(io.in.a.bits.source, 3)
node _T_379 = eq(_T_378, UInt<1>(0h1))
node _T_380 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_381 = and(_T_379, _T_380)
node _T_382 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_383 = and(_T_381, _T_382)
node _T_384 = or(_T_377, _T_383)
node _T_385 = and(_T_371, _T_384)
node _T_386 = or(UInt<1>(0h0), _T_385)
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_386, UInt<1>(0h1), "") : assert_19
node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_392 = and(_T_390, _T_391)
node _T_393 = or(UInt<1>(0h0), _T_392)
node _T_394 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<13>(0h1000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = and(_T_393, _T_398)
node _T_400 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_401 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_402 = and(_T_400, _T_401)
node _T_403 = or(UInt<1>(0h0), _T_402)
node _T_404 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<14>(0h2000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<17>(0h10000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<18>(0h2f000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<17>(0h10000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<27>(0h4000000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<13>(0h1000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<30>(0h20000000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<15>(0h4000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_408, _T_413)
node _T_445 = or(_T_444, _T_418)
node _T_446 = or(_T_445, _T_423)
node _T_447 = or(_T_446, _T_428)
node _T_448 = or(_T_447, _T_433)
node _T_449 = or(_T_448, _T_438)
node _T_450 = or(_T_449, _T_443)
node _T_451 = and(_T_403, _T_450)
node _T_452 = or(UInt<1>(0h0), _T_399)
node _T_453 = or(_T_452, _T_451)
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_453, UInt<1>(0h1), "") : assert_20
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(source_ok, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(is_aligned, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_463 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_463, UInt<1>(0h1), "") : assert_23
node _T_467 = eq(io.in.a.bits.mask, mask)
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_467, UInt<1>(0h1), "") : assert_24
node _T_471 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_471, UInt<1>(0h1), "") : assert_25
node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_475 :
node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_478 = and(_T_476, _T_477)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0)
node _T_479 = shr(io.in.a.bits.source, 3)
node _T_480 = eq(_T_479, UInt<1>(0h0))
node _T_481 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_482 = and(_T_480, _T_481)
node _T_483 = leq(uncommonBits_8, UInt<3>(0h7))
node _T_484 = and(_T_482, _T_483)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0)
node _T_485 = shr(io.in.a.bits.source, 3)
node _T_486 = eq(_T_485, UInt<1>(0h1))
node _T_487 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_488 = and(_T_486, _T_487)
node _T_489 = leq(uncommonBits_9, UInt<3>(0h7))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(_T_484, _T_490)
node _T_492 = and(_T_478, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_492)
node _T_494 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_495 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_496 = and(_T_494, _T_495)
node _T_497 = or(UInt<1>(0h0), _T_496)
node _T_498 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_499 = cvt(_T_498)
node _T_500 = and(_T_499, asSInt(UInt<13>(0h1000)))
node _T_501 = asSInt(_T_500)
node _T_502 = eq(_T_501, asSInt(UInt<1>(0h0)))
node _T_503 = and(_T_497, _T_502)
node _T_504 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_505 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_506 = and(_T_504, _T_505)
node _T_507 = or(UInt<1>(0h0), _T_506)
node _T_508 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_509 = cvt(_T_508)
node _T_510 = and(_T_509, asSInt(UInt<14>(0h2000)))
node _T_511 = asSInt(_T_510)
node _T_512 = eq(_T_511, asSInt(UInt<1>(0h0)))
node _T_513 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_514 = cvt(_T_513)
node _T_515 = and(_T_514, asSInt(UInt<18>(0h2f000)))
node _T_516 = asSInt(_T_515)
node _T_517 = eq(_T_516, asSInt(UInt<1>(0h0)))
node _T_518 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_519 = cvt(_T_518)
node _T_520 = and(_T_519, asSInt(UInt<17>(0h10000)))
node _T_521 = asSInt(_T_520)
node _T_522 = eq(_T_521, asSInt(UInt<1>(0h0)))
node _T_523 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_524 = cvt(_T_523)
node _T_525 = and(_T_524, asSInt(UInt<27>(0h4000000)))
node _T_526 = asSInt(_T_525)
node _T_527 = eq(_T_526, asSInt(UInt<1>(0h0)))
node _T_528 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_529 = cvt(_T_528)
node _T_530 = and(_T_529, asSInt(UInt<13>(0h1000)))
node _T_531 = asSInt(_T_530)
node _T_532 = eq(_T_531, asSInt(UInt<1>(0h0)))
node _T_533 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_534 = cvt(_T_533)
node _T_535 = and(_T_534, asSInt(UInt<15>(0h4000)))
node _T_536 = asSInt(_T_535)
node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0)))
node _T_538 = or(_T_512, _T_517)
node _T_539 = or(_T_538, _T_522)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_532)
node _T_542 = or(_T_541, _T_537)
node _T_543 = and(_T_507, _T_542)
node _T_544 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_546 = cvt(_T_545)
node _T_547 = and(_T_546, asSInt(UInt<17>(0h10000)))
node _T_548 = asSInt(_T_547)
node _T_549 = eq(_T_548, asSInt(UInt<1>(0h0)))
node _T_550 = and(_T_544, _T_549)
node _T_551 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_552 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_553 = and(_T_551, _T_552)
node _T_554 = or(UInt<1>(0h0), _T_553)
node _T_555 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<30>(0h20000000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = and(_T_554, _T_559)
node _T_561 = or(UInt<1>(0h0), _T_503)
node _T_562 = or(_T_561, _T_543)
node _T_563 = or(_T_562, _T_550)
node _T_564 = or(_T_563, _T_560)
node _T_565 = and(_T_493, _T_564)
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(_T_565, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_565, UInt<1>(0h1), "") : assert_26
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(source_ok, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(is_aligned, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_575 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_576 = asUInt(reset)
node _T_577 = eq(_T_576, UInt<1>(0h0))
when _T_577 :
node _T_578 = eq(_T_575, UInt<1>(0h0))
when _T_578 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_575, UInt<1>(0h1), "") : assert_29
node _T_579 = eq(io.in.a.bits.mask, mask)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_579, UInt<1>(0h1), "") : assert_30
node _T_583 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_583 :
node _T_584 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_585 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_587 = shr(io.in.a.bits.source, 3)
node _T_588 = eq(_T_587, UInt<1>(0h0))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_10, UInt<3>(0h7))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_593 = shr(io.in.a.bits.source, 3)
node _T_594 = eq(_T_593, UInt<1>(0h1))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_598 = and(_T_596, _T_597)
node _T_599 = or(_T_592, _T_598)
node _T_600 = and(_T_586, _T_599)
node _T_601 = or(UInt<1>(0h0), _T_600)
node _T_602 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_603 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_604 = and(_T_602, _T_603)
node _T_605 = or(UInt<1>(0h0), _T_604)
node _T_606 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_607 = cvt(_T_606)
node _T_608 = and(_T_607, asSInt(UInt<13>(0h1000)))
node _T_609 = asSInt(_T_608)
node _T_610 = eq(_T_609, asSInt(UInt<1>(0h0)))
node _T_611 = and(_T_605, _T_610)
node _T_612 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_613 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_614 = and(_T_612, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_617 = cvt(_T_616)
node _T_618 = and(_T_617, asSInt(UInt<14>(0h2000)))
node _T_619 = asSInt(_T_618)
node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0)))
node _T_621 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_622 = cvt(_T_621)
node _T_623 = and(_T_622, asSInt(UInt<18>(0h2f000)))
node _T_624 = asSInt(_T_623)
node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0)))
node _T_626 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_627 = cvt(_T_626)
node _T_628 = and(_T_627, asSInt(UInt<17>(0h10000)))
node _T_629 = asSInt(_T_628)
node _T_630 = eq(_T_629, asSInt(UInt<1>(0h0)))
node _T_631 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_632 = cvt(_T_631)
node _T_633 = and(_T_632, asSInt(UInt<27>(0h4000000)))
node _T_634 = asSInt(_T_633)
node _T_635 = eq(_T_634, asSInt(UInt<1>(0h0)))
node _T_636 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_637 = cvt(_T_636)
node _T_638 = and(_T_637, asSInt(UInt<13>(0h1000)))
node _T_639 = asSInt(_T_638)
node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0)))
node _T_641 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_642 = cvt(_T_641)
node _T_643 = and(_T_642, asSInt(UInt<15>(0h4000)))
node _T_644 = asSInt(_T_643)
node _T_645 = eq(_T_644, asSInt(UInt<1>(0h0)))
node _T_646 = or(_T_620, _T_625)
node _T_647 = or(_T_646, _T_630)
node _T_648 = or(_T_647, _T_635)
node _T_649 = or(_T_648, _T_640)
node _T_650 = or(_T_649, _T_645)
node _T_651 = and(_T_615, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<30>(0h20000000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = and(_T_662, _T_667)
node _T_669 = or(UInt<1>(0h0), _T_611)
node _T_670 = or(_T_669, _T_651)
node _T_671 = or(_T_670, _T_658)
node _T_672 = or(_T_671, _T_668)
node _T_673 = and(_T_601, _T_672)
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_673, UInt<1>(0h1), "") : assert_31
node _T_677 = asUInt(reset)
node _T_678 = eq(_T_677, UInt<1>(0h0))
when _T_678 :
node _T_679 = eq(source_ok, UInt<1>(0h0))
when _T_679 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(is_aligned, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_683 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_684 = asUInt(reset)
node _T_685 = eq(_T_684, UInt<1>(0h0))
when _T_685 :
node _T_686 = eq(_T_683, UInt<1>(0h0))
when _T_686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_683, UInt<1>(0h1), "") : assert_34
node _T_687 = not(mask)
node _T_688 = and(io.in.a.bits.mask, _T_687)
node _T_689 = eq(_T_688, UInt<1>(0h0))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_689, UInt<1>(0h1), "") : assert_35
node _T_693 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_693 :
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_696 = and(_T_694, _T_695)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_697 = shr(io.in.a.bits.source, 3)
node _T_698 = eq(_T_697, UInt<1>(0h0))
node _T_699 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_700 = and(_T_698, _T_699)
node _T_701 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_702 = and(_T_700, _T_701)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_703 = shr(io.in.a.bits.source, 3)
node _T_704 = eq(_T_703, UInt<1>(0h1))
node _T_705 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_706 = and(_T_704, _T_705)
node _T_707 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_708 = and(_T_706, _T_707)
node _T_709 = or(_T_702, _T_708)
node _T_710 = and(_T_696, _T_709)
node _T_711 = or(UInt<1>(0h0), _T_710)
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_714 = and(_T_712, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<14>(0h2000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<13>(0h1000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<18>(0h2f000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<17>(0h10000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<27>(0h4000000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<15>(0h4000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = or(_T_720, _T_725)
node _T_752 = or(_T_751, _T_730)
node _T_753 = or(_T_752, _T_735)
node _T_754 = or(_T_753, _T_740)
node _T_755 = or(_T_754, _T_745)
node _T_756 = or(_T_755, _T_750)
node _T_757 = and(_T_715, _T_756)
node _T_758 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_759 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<17>(0h10000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<30>(0h20000000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = or(_T_763, _T_768)
node _T_770 = and(_T_758, _T_769)
node _T_771 = or(UInt<1>(0h0), _T_757)
node _T_772 = or(_T_771, _T_770)
node _T_773 = and(_T_711, _T_772)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_773, UInt<1>(0h1), "") : assert_36
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(source_ok, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(is_aligned, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_783 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_784 = asUInt(reset)
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(_T_783, UInt<1>(0h0))
when _T_786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_783, UInt<1>(0h1), "") : assert_39
node _T_787 = eq(io.in.a.bits.mask, mask)
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_787, UInt<1>(0h1), "") : assert_40
node _T_791 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_791 :
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_794 = and(_T_792, _T_793)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0)
node _T_795 = shr(io.in.a.bits.source, 3)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_798 = and(_T_796, _T_797)
node _T_799 = leq(uncommonBits_14, UInt<3>(0h7))
node _T_800 = and(_T_798, _T_799)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0)
node _T_801 = shr(io.in.a.bits.source, 3)
node _T_802 = eq(_T_801, UInt<1>(0h1))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_15, UInt<3>(0h7))
node _T_806 = and(_T_804, _T_805)
node _T_807 = or(_T_800, _T_806)
node _T_808 = and(_T_794, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_811 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _T_813 = or(UInt<1>(0h0), _T_812)
node _T_814 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_815 = cvt(_T_814)
node _T_816 = and(_T_815, asSInt(UInt<14>(0h2000)))
node _T_817 = asSInt(_T_816)
node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0)))
node _T_819 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_820 = cvt(_T_819)
node _T_821 = and(_T_820, asSInt(UInt<13>(0h1000)))
node _T_822 = asSInt(_T_821)
node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0)))
node _T_824 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_825 = cvt(_T_824)
node _T_826 = and(_T_825, asSInt(UInt<18>(0h2f000)))
node _T_827 = asSInt(_T_826)
node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0)))
node _T_829 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_830 = cvt(_T_829)
node _T_831 = and(_T_830, asSInt(UInt<17>(0h10000)))
node _T_832 = asSInt(_T_831)
node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0)))
node _T_834 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_835 = cvt(_T_834)
node _T_836 = and(_T_835, asSInt(UInt<27>(0h4000000)))
node _T_837 = asSInt(_T_836)
node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0)))
node _T_839 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<15>(0h4000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = or(_T_818, _T_823)
node _T_850 = or(_T_849, _T_828)
node _T_851 = or(_T_850, _T_833)
node _T_852 = or(_T_851, _T_838)
node _T_853 = or(_T_852, _T_843)
node _T_854 = or(_T_853, _T_848)
node _T_855 = and(_T_813, _T_854)
node _T_856 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_857 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<17>(0h10000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<30>(0h20000000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = or(_T_861, _T_866)
node _T_868 = and(_T_856, _T_867)
node _T_869 = or(UInt<1>(0h0), _T_855)
node _T_870 = or(_T_869, _T_868)
node _T_871 = and(_T_809, _T_870)
node _T_872 = asUInt(reset)
node _T_873 = eq(_T_872, UInt<1>(0h0))
when _T_873 :
node _T_874 = eq(_T_871, UInt<1>(0h0))
when _T_874 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_871, UInt<1>(0h1), "") : assert_41
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(source_ok, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(is_aligned, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_881 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_881, UInt<1>(0h1), "") : assert_44
node _T_885 = eq(io.in.a.bits.mask, mask)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_885, UInt<1>(0h1), "") : assert_45
node _T_889 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_889 :
node _T_890 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_891 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_892 = and(_T_890, _T_891)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0)
node _T_893 = shr(io.in.a.bits.source, 3)
node _T_894 = eq(_T_893, UInt<1>(0h0))
node _T_895 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_896 = and(_T_894, _T_895)
node _T_897 = leq(uncommonBits_16, UInt<3>(0h7))
node _T_898 = and(_T_896, _T_897)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0)
node _T_899 = shr(io.in.a.bits.source, 3)
node _T_900 = eq(_T_899, UInt<1>(0h1))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_17, UInt<3>(0h7))
node _T_904 = and(_T_902, _T_903)
node _T_905 = or(_T_898, _T_904)
node _T_906 = and(_T_892, _T_905)
node _T_907 = or(UInt<1>(0h0), _T_906)
node _T_908 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_909 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_910 = and(_T_908, _T_909)
node _T_911 = or(UInt<1>(0h0), _T_910)
node _T_912 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_913 = cvt(_T_912)
node _T_914 = and(_T_913, asSInt(UInt<13>(0h1000)))
node _T_915 = asSInt(_T_914)
node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0)))
node _T_917 = and(_T_911, _T_916)
node _T_918 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_919 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<14>(0h2000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<18>(0h2f000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<17>(0h10000)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<27>(0h4000000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_945 = cvt(_T_944)
node _T_946 = and(_T_945, asSInt(UInt<13>(0h1000)))
node _T_947 = asSInt(_T_946)
node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0)))
node _T_949 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_950 = cvt(_T_949)
node _T_951 = and(_T_950, asSInt(UInt<30>(0h20000000)))
node _T_952 = asSInt(_T_951)
node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0)))
node _T_954 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_955 = cvt(_T_954)
node _T_956 = and(_T_955, asSInt(UInt<15>(0h4000)))
node _T_957 = asSInt(_T_956)
node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0)))
node _T_959 = or(_T_923, _T_928)
node _T_960 = or(_T_959, _T_933)
node _T_961 = or(_T_960, _T_938)
node _T_962 = or(_T_961, _T_943)
node _T_963 = or(_T_962, _T_948)
node _T_964 = or(_T_963, _T_953)
node _T_965 = or(_T_964, _T_958)
node _T_966 = and(_T_918, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_917)
node _T_968 = or(_T_967, _T_966)
node _T_969 = and(_T_907, _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_969, UInt<1>(0h1), "") : assert_46
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(source_ok, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(is_aligned, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_979 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(_T_979, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_979, UInt<1>(0h1), "") : assert_49
node _T_983 = eq(io.in.a.bits.mask, mask)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_983, UInt<1>(0h1), "") : assert_50
node _T_987 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_988 = asUInt(reset)
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(_T_987, UInt<1>(0h0))
when _T_990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_987, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_991 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_991, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0)
node _source_ok_T_12 = shr(io.in.d.bits.source, 3)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<3>(0h7))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 2, 0)
node _source_ok_T_18 = shr(io.in.d.bits.source, 3)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h1))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<3>(0h7))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_17
connect _source_ok_WIRE_1[1], _source_ok_T_23
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_995 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_995 :
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(source_ok_1, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_999 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_999, UInt<1>(0h1), "") : assert_54
node _T_1003 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_55
node _T_1007 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_56
node _T_1011 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_57
node _T_1015 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1015 :
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(source_ok_1, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(sink_ok, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1022 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_60
node _T_1026 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_61
node _T_1030 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_62
node _T_1034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_63
node _T_1038 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1039 = or(UInt<1>(0h1), _T_1038)
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_64
node _T_1043 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1043 :
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok_1, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(sink_ok, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1050 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_67
node _T_1054 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_68
node _T_1058 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_69
node _T_1062 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1063 = or(_T_1062, io.in.d.bits.corrupt)
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_70
node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1068 = or(UInt<1>(0h1), _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_71
node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(source_ok_1, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_73
node _T_1080 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_74
node _T_1084 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1085 = or(UInt<1>(0h1), _T_1084)
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_75
node _T_1089 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1089 :
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(source_ok_1, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1093 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_77
node _T_1097 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1098 = or(_T_1097, io.in.d.bits.corrupt)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_78
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(UInt<1>(0h1), _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_79
node _T_1107 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1107 :
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(source_ok_1, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1111 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_81
node _T_1115 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_82
node _T_1119 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1120 = or(UInt<1>(0h1), _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1124 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1128 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1132 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1136 = eq(a_first, UInt<1>(0h0))
node _T_1137 = and(io.in.a.valid, _T_1136)
when _T_1137 :
node _T_1138 = eq(io.in.a.bits.opcode, opcode)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_87
node _T_1142 = eq(io.in.a.bits.param, param)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_88
node _T_1146 = eq(io.in.a.bits.size, size)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_89
node _T_1150 = eq(io.in.a.bits.source, source)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_90
node _T_1154 = eq(io.in.a.bits.address, address)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_91
node _T_1158 = and(io.in.a.ready, io.in.a.valid)
node _T_1159 = and(_T_1158, a_first)
when _T_1159 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1160 = eq(d_first, UInt<1>(0h0))
node _T_1161 = and(io.in.d.valid, _T_1160)
when _T_1161 :
node _T_1162 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_92
node _T_1166 = eq(io.in.d.bits.param, param_1)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_93
node _T_1170 = eq(io.in.d.bits.size, size_1)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_94
node _T_1174 = eq(io.in.d.bits.source, source_1)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_95
node _T_1178 = eq(io.in.d.bits.sink, sink)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_96
node _T_1182 = eq(io.in.d.bits.denied, denied)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_97
node _T_1186 = and(io.in.d.ready, io.in.d.valid)
node _T_1187 = and(_T_1186, d_first)
when _T_1187 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1188 = and(io.in.a.valid, a_first_1)
node _T_1189 = and(_T_1188, UInt<1>(0h1))
when _T_1189 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1190 = and(io.in.a.ready, io.in.a.valid)
node _T_1191 = and(_T_1190, a_first_1)
node _T_1192 = and(_T_1191, UInt<1>(0h1))
when _T_1192 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1193 = dshr(inflight, io.in.a.bits.source)
node _T_1194 = bits(_T_1193, 0, 0)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1203 = and(io.in.d.ready, io.in.d.valid)
node _T_1204 = and(_T_1203, d_first_1)
node _T_1205 = and(_T_1204, UInt<1>(0h1))
node _T_1206 = eq(d_release_ack, UInt<1>(0h0))
node _T_1207 = and(_T_1205, _T_1206)
when _T_1207 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1208 = and(io.in.d.valid, d_first_1)
node _T_1209 = and(_T_1208, UInt<1>(0h1))
node _T_1210 = eq(d_release_ack, UInt<1>(0h0))
node _T_1211 = and(_T_1209, _T_1210)
when _T_1211 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1212 = dshr(inflight, io.in.d.bits.source)
node _T_1213 = bits(_T_1212, 0, 0)
node _T_1214 = or(_T_1213, same_cycle_resp)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1218 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1219 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1220 = or(_T_1218, _T_1219)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_100
node _T_1224 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_101
else :
node _T_1228 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1229 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1230 = or(_T_1228, _T_1229)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_102
node _T_1234 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(_T_1234, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1234, UInt<1>(0h1), "") : assert_103
node _T_1238 = and(io.in.d.valid, d_first_1)
node _T_1239 = and(_T_1238, a_first_1)
node _T_1240 = and(_T_1239, io.in.a.valid)
node _T_1241 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1242 = and(_T_1240, _T_1241)
node _T_1243 = eq(d_release_ack, UInt<1>(0h0))
node _T_1244 = and(_T_1242, _T_1243)
when _T_1244 :
node _T_1245 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1246 = or(_T_1245, io.in.a.ready)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_104
node _T_1250 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1251 = orr(a_set_wo_ready)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
node _T_1253 = or(_T_1250, _T_1252)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_36
node _T_1257 = orr(inflight)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1260 = or(_T_1258, _T_1259)
node _T_1261 = lt(watchdog, plusarg_reader.out)
node _T_1262 = or(_T_1260, _T_1261)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1266 = and(io.in.a.ready, io.in.a.valid)
node _T_1267 = and(io.in.d.ready, io.in.d.valid)
node _T_1268 = or(_T_1266, _T_1267)
when _T_1268 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1269 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1270 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1271 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1272 = and(_T_1270, _T_1271)
node _T_1273 = and(_T_1269, _T_1272)
when _T_1273 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1274 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1275 = and(_T_1274, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1276 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1277 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1278 = and(_T_1276, _T_1277)
node _T_1279 = and(_T_1275, _T_1278)
when _T_1279 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1280 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1281 = bits(_T_1280, 0, 0)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1286 = and(io.in.d.valid, d_first_2)
node _T_1287 = and(_T_1286, UInt<1>(0h1))
node _T_1288 = and(_T_1287, d_release_ack_1)
when _T_1288 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1289 = and(io.in.d.ready, io.in.d.valid)
node _T_1290 = and(_T_1289, d_first_2)
node _T_1291 = and(_T_1290, UInt<1>(0h1))
node _T_1292 = and(_T_1291, d_release_ack_1)
when _T_1292 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1296 = dshr(inflight_1, io.in.d.bits.source)
node _T_1297 = bits(_T_1296, 0, 0)
node _T_1298 = or(_T_1297, same_cycle_resp_1)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1302 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_109
else :
node _T_1306 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_110
node _T_1310 = and(io.in.d.valid, d_first_2)
node _T_1311 = and(_T_1310, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1312 = and(_T_1311, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1313 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1314 = and(_T_1312, _T_1313)
node _T_1315 = and(_T_1314, d_release_ack_1)
node _T_1316 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1317 = and(_T_1315, _T_1316)
when _T_1317 :
node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1319 = or(_T_1318, _WIRE_23.ready)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_111
node _T_1323 = orr(c_set_wo_ready)
when _T_1323 :
node _T_1324 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_37
node _T_1328 = orr(inflight_1)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
node _T_1330 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1333 = or(_T_1331, _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:173:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1337 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1338 = and(io.in.d.ready, io.in.d.valid)
node _T_1339 = or(_T_1337, _T_1338)
when _T_1339 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_18( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_bufferable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_modifiable, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_readalloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_writealloc, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_privileged, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_secure, // @[Monitor.scala:20:14]
input io_in_a_bits_user_amba_prot_fetch, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_bufferable_0 = io_in_a_bits_user_amba_prot_bufferable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_modifiable_0 = io_in_a_bits_user_amba_prot_modifiable; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_readalloc_0 = io_in_a_bits_user_amba_prot_readalloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_writealloc_0 = io_in_a_bits_user_amba_prot_writealloc; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_privileged_0 = io_in_a_bits_user_amba_prot_privileged; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_secure_0 = io_in_a_bits_user_amba_prot_secure; // @[Monitor.scala:36:7]
wire io_in_a_bits_user_amba_prot_fetch_0 = io_in_a_bits_user_amba_prot_fetch; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = ~_source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = _source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1339 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1339; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1339; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1339; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1192 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1192 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1207 = _T_1339 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1207 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1292 = _T_1339 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1292 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_49 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_49( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_418 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_162
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_418( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_162 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s2k4z4c_3 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_48
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d128s2k4z4c_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d128s2k4z4c_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d128s2k4z4c_1
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d128s2k4z4c_1
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d128s2k4z4c_1
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d128s2k4z4c_3( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21]
wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21]
wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21]
wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_48 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d128s2k4z4c_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s2k4z4c_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d128s2k4z4c_1 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d128s2k4z4c_1 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d128s2k4z4c_1 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = or(_T_17, _T_24)
node _T_47 = or(_T_46, _T_31)
node _T_48 = or(_T_47, _T_38)
node _T_49 = or(_T_48, _T_45)
node _T_50 = or(_T_10, _T_49)
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_50, UInt<1>(0h1), "") : assert_2
node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_61, _T_68)
node _T_91 = or(_T_90, _T_75)
node _T_92 = or(_T_91, _T_82)
node _T_93 = or(_T_92, _T_89)
node _T_94 = or(_T_54, _T_93)
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_94, UInt<1>(0h1), "") : assert_3
node _T_98 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_105 = and(_T_103, _T_104)
node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(_T_105, _T_112)
node _T_163 = or(_T_162, _T_119)
node _T_164 = or(_T_163, _T_126)
node _T_165 = or(_T_164, _T_133)
node _T_166 = or(_T_165, _T_140)
node _T_167 = or(_T_166, _T_147)
node _T_168 = or(_T_167, _T_154)
node _T_169 = or(_T_168, _T_161)
node _T_170 = or(_T_98, _T_169)
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_170, UInt<1>(0h1), "") : assert_4
node _T_174 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_176 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_183 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_190 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_197 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_200 = and(_T_198, _T_199)
node _T_201 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_237 = and(_T_235, _T_236)
node _T_238 = or(_T_181, _T_188)
node _T_239 = or(_T_238, _T_195)
node _T_240 = or(_T_239, _T_202)
node _T_241 = or(_T_240, _T_209)
node _T_242 = or(_T_241, _T_216)
node _T_243 = or(_T_242, _T_223)
node _T_244 = or(_T_243, _T_230)
node _T_245 = or(_T_244, _T_237)
node _T_246 = or(_T_174, _T_245)
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_246, UInt<1>(0h1), "") : assert_5
node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_313 = and(_T_311, _T_312)
node _T_314 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_315 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_316 = and(_T_314, _T_315)
node _T_317 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_322 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_329 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_330 = and(_T_328, _T_329)
node _T_331 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_332 = and(_T_330, _T_331)
node _T_333 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_336 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_339 = and(_T_337, _T_338)
node _T_340 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_341 = and(_T_339, _T_340)
node _T_342 = or(_T_257, _T_264)
node _T_343 = or(_T_342, _T_271)
node _T_344 = or(_T_343, _T_278)
node _T_345 = or(_T_344, _T_285)
node _T_346 = or(_T_345, _T_292)
node _T_347 = or(_T_346, _T_299)
node _T_348 = or(_T_347, _T_306)
node _T_349 = or(_T_348, _T_313)
node _T_350 = or(_T_349, _T_320)
node _T_351 = or(_T_350, _T_327)
node _T_352 = or(_T_351, _T_334)
node _T_353 = or(_T_352, _T_341)
node _T_354 = or(_T_250, _T_353)
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_354, UInt<1>(0h1), "") : assert_6
node _T_358 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_359 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_360 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_367 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_370 = and(_T_368, _T_369)
node _T_371 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_374 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_377 = and(_T_375, _T_376)
node _T_378 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_384 = and(_T_382, _T_383)
node _T_385 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_395 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_400 = and(_T_398, _T_399)
node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_402 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_409 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_416 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_423 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_430 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_437 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_444 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_449 = and(_T_447, _T_448)
node _T_450 = or(_T_365, _T_372)
node _T_451 = or(_T_450, _T_379)
node _T_452 = or(_T_451, _T_386)
node _T_453 = or(_T_452, _T_393)
node _T_454 = or(_T_453, _T_400)
node _T_455 = or(_T_454, _T_407)
node _T_456 = or(_T_455, _T_414)
node _T_457 = or(_T_456, _T_421)
node _T_458 = or(_T_457, _T_428)
node _T_459 = or(_T_458, _T_435)
node _T_460 = or(_T_459, _T_442)
node _T_461 = or(_T_460, _T_449)
node _T_462 = or(_T_358, _T_461)
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_462, UInt<1>(0h1), "") : assert_7
node _T_466 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_468 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_469 = and(_T_467, _T_468)
node _T_470 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_475 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_476 = and(_T_474, _T_475)
node _T_477 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_482 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_483 = and(_T_481, _T_482)
node _T_484 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_489 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_490 = and(_T_488, _T_489)
node _T_491 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_492 = and(_T_490, _T_491)
node _T_493 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_496 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_497 = and(_T_495, _T_496)
node _T_498 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_499 = and(_T_497, _T_498)
node _T_500 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_503 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_504 = and(_T_502, _T_503)
node _T_505 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_506 = and(_T_504, _T_505)
node _T_507 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_510 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_511 = and(_T_509, _T_510)
node _T_512 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_513 = and(_T_511, _T_512)
node _T_514 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_517 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_520 = and(_T_518, _T_519)
node _T_521 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_522 = and(_T_520, _T_521)
node _T_523 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_524 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_525 = and(_T_523, _T_524)
node _T_526 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_527 = and(_T_525, _T_526)
node _T_528 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_529 = and(_T_527, _T_528)
node _T_530 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_531 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_532 = and(_T_530, _T_531)
node _T_533 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_538 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_539 = and(_T_537, _T_538)
node _T_540 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
node _T_542 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_545 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_546 = and(_T_544, _T_545)
node _T_547 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_548 = and(_T_546, _T_547)
node _T_549 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_550 = and(_T_548, _T_549)
node _T_551 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_552 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_553 = and(_T_551, _T_552)
node _T_554 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
node _T_556 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_557 = and(_T_555, _T_556)
node _T_558 = or(_T_473, _T_480)
node _T_559 = or(_T_558, _T_487)
node _T_560 = or(_T_559, _T_494)
node _T_561 = or(_T_560, _T_501)
node _T_562 = or(_T_561, _T_508)
node _T_563 = or(_T_562, _T_515)
node _T_564 = or(_T_563, _T_522)
node _T_565 = or(_T_564, _T_529)
node _T_566 = or(_T_565, _T_536)
node _T_567 = or(_T_566, _T_543)
node _T_568 = or(_T_567, _T_550)
node _T_569 = or(_T_568, _T_557)
node _T_570 = or(_T_466, _T_569)
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_570, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_47( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_28 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_28(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [8:0] _roundMask_T = 9'hFF; // @[RoundAnyRawFNToRecFN.scala:156:37]
wire [6:0] roundMask_lsbs_1 = 7'h0; // @[primitives.scala:59:26]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [7:0] roundMask_lsbs = 8'h0; // @[primitives.scala:59:26, :77:20]
wire [7:0] _roundMask_T_6 = 8'h0; // @[primitives.scala:59:26, :77:20]
wire [7:0] _roundMask_T_8 = 8'h0; // @[primitives.scala:59:26, :77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = 12'h0; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = 12'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = 14'h0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = 14'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = 15'h0; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = 15'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_3 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = 16'h0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = 16'h0; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = 22'h3FFFFF; // @[primitives.scala:73:{21,32}]
wire [21:0] _roundMask_T_61 = 22'h3FFFFF; // @[primitives.scala:73:{21,32}]
wire [21:0] _roundMask_T_2 = 22'h0; // @[primitives.scala:73:17, :77:20, :78:22]
wire [21:0] _roundMask_T_59 = 22'h0; // @[primitives.scala:73:17, :77:20, :78:22]
wire [21:0] _roundMask_T_62 = 22'h0; // @[primitives.scala:73:17, :77:20, :78:22]
wire [24:0] _roundMask_T_63 = 25'h7; // @[primitives.scala:68:58]
wire [5:0] roundMask_lsbs_2 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [5:0] _roundMask_T_43 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [5:0] _roundMask_T_58 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [5:0] roundMask_lsbs_3 = 6'h0; // @[primitives.scala:59:26, :77:20]
wire [64:0] roundMask_shift = 65'h10000000000000000; // @[primitives.scala:76:56]
wire [64:0] roundMask_shift_1 = 65'h10000000000000000; // @[primitives.scala:76:56]
wire [24:0] _roundMask_T_72 = 25'h0; // @[primitives.scala:62:24, :67:24]
wire [24:0] _roundMask_T_73 = 25'h0; // @[primitives.scala:62:24, :67:24]
wire [24:0] _roundMask_T_74 = 25'h1; // @[RoundAnyRawFNToRecFN.scala:159:23]
wire [26:0] roundMask = 27'h7; // @[RoundAnyRawFNToRecFN.scala:159:42]
wire [27:0] _shiftedRoundMask_T = 28'h7; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [26:0] shiftedRoundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [26:0] _roundPosMask_T = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [26:0] roundPosMask = 27'h4; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [26:0] _roundPosBit_T = 27'h0; // @[RoundAnyRawFNToRecFN.scala:164:40, :165:42]
wire [26:0] _anyRoundExtra_T = 27'h0; // @[RoundAnyRawFNToRecFN.scala:164:40, :165:42]
wire [26:0] _roundedSig_T = 27'h4000007; // @[RoundAnyRawFNToRecFN.scala:174:32]
wire [24:0] _roundedSig_T_1 = 25'h1000001; // @[RoundAnyRawFNToRecFN.scala:174:44]
wire [25:0] _roundedSig_T_6 = 26'h3; // @[RoundAnyRawFNToRecFN.scala:177:35]
wire [25:0] _roundedSig_T_8 = 26'h3FFFFFF; // @[RoundAnyRawFNToRecFN.scala:175:21]
wire [25:0] _roundedSig_T_2 = 26'h1000002; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}]
wire [25:0] _roundedSig_T_9 = 26'h1000002; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}]
wire [26:0] _roundedSig_T_10 = 27'h7FFFFF8; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [24:0] _roundedSig_T_12 = 25'h1000000; // @[RoundAnyRawFNToRecFN.scala:180:43]
wire [25:0] _roundedSig_T_14 = 26'h2; // @[RoundAnyRawFNToRecFN.scala:181:67]
wire [25:0] _roundedSig_T_7 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:25, :181:24]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:25, :181:24]
wire [25:0] _roundedSig_T_16 = 26'h1000000; // @[RoundAnyRawFNToRecFN.scala:173:16, :180:47]
wire [25:0] roundedSig = 26'h1000000; // @[RoundAnyRawFNToRecFN.scala:173:16, :180:47]
wire [1:0] _sRoundedExp_T = 2'h1; // @[RoundAnyRawFNToRecFN.scala:185:54]
wire [2:0] _sRoundedExp_T_1 = 3'h1; // @[RoundAnyRawFNToRecFN.scala:185:76]
wire [10:0] sRoundedExp = 11'h100; // @[RoundAnyRawFNToRecFN.scala:185:40]
wire [3:0] _common_overflow_T = 4'h2; // @[RoundAnyRawFNToRecFN.scala:196:30]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] common_expOut = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _roundMask_T_1 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _common_expOut_T = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_3 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_7 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_10 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_13 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_15 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_17 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] _expOut_T_19 = 9'h100; // @[primitives.scala:52:21]
wire [8:0] expOut = 9'h100; // @[primitives.scala:52:21]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16, :190:27, :191:27, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _io_out_T = 10'h300; // @[RoundAnyRawFNToRecFN.scala:286:23]
wire [1:0] _roundMask_T_45 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_65 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _unboundedRange_anyRound_T_2 = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _common_underflow_T = 2'h0; // @[primitives.scala:77:20]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_44 = 4'h0; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = 4'h0; // @[primitives.scala:77:20]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[primitives.scala:77:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h180000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h180000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [2:0] io_roundingMode = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _roundMask_T_64 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _roundMask_T_70 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _roundMask_T_71 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[primitives.scala:62:24, :77:20, :78:22]
wire [26:0] io_in_sig = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :114:22, :180:30]
wire [26:0] adjustedSig = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :114:22, :180:30]
wire [26:0] _roundedSig_T_11 = 27'h4000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :114:22, :180:30]
wire [9:0] io_in_sExp = 10'hFF; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_in_sign = 1'h1; // @[primitives.scala:58:25]
wire io_detectTininess = 1'h1; // @[primitives.scala:58:25]
wire roundingMode_near_even = 1'h1; // @[primitives.scala:58:25]
wire doShiftSigDown1 = 1'h1; // @[primitives.scala:58:25]
wire roundMask_msb = 1'h1; // @[primitives.scala:58:25]
wire _roundIncr_T = 1'h1; // @[primitives.scala:58:25]
wire _roundedSig_T_4 = 1'h1; // @[primitives.scala:58:25]
wire _unboundedRange_roundIncr_T = 1'h1; // @[primitives.scala:58:25]
wire _roundCarry_T_1 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_1 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_4 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_7 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_11 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_12 = 1'h1; // @[primitives.scala:58:25]
wire _common_underflow_T_16 = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T_1 = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T_2 = 1'h1; // @[primitives.scala:58:25]
wire _commonCase_T_3 = 1'h1; // @[primitives.scala:58:25]
wire commonCase = 1'h1; // @[primitives.scala:58:25]
wire _overflow_roundMagUp_T = 1'h1; // @[primitives.scala:58:25]
wire overflow_roundMagUp = 1'h1; // @[primitives.scala:58:25]
wire signOut = 1'h1; // @[primitives.scala:58:25]
wire io_invalidExc = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_infiniteExc = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_in_isNaN = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_in_isInf = 1'h0; // @[primitives.scala:58:25, :77:20]
wire io_in_isZero = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_minMag = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_min = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_max = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_near_maxMag = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundingMode_odd = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMagUp_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMagUp_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMagUp_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMagUp = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_overflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_totalUnderflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_underflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire common_inexact = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMask_msb_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMask_msb_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_46 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_47 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_50 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_51 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_55 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_56 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundMask_msb_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_66 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_67 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundMask_T_69 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundPosBit = 1'h0; // @[primitives.scala:58:25, :77:20]
wire anyRoundExtra = 1'h0; // @[primitives.scala:58:25, :77:20]
wire anyRound = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundIncr_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundIncr_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundIncr = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundedSig_T_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundedSig_T_5 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundedSig_T_13 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_overflow_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_totalUnderflow_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundPosBit_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundPosBit_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire unboundedRange_roundPosBit = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_anyRound_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_anyRound_T_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire unboundedRange_anyRound = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundIncr_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire unboundedRange_roundIncr = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _roundCarry_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire roundCarry = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_2 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_3 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_5 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_6 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_8 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_9 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_10 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_13 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_14 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_15 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_17 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_underflow_T_18 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _common_inexact_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire isNaNOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire notNaN_isSpecialInfOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire overflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire underflow = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _inexact_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire inexact = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
wire pegMinNonzeroMagOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire pegMaxFiniteMagOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _notNaN_isInfOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire notNaN_isInfOut = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _expOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _fractOut_T = 1'h0; // @[primitives.scala:58:25, :77:20]
wire _fractOut_T_1 = 1'h0; // @[primitives.scala:58:25, :77:20]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_18 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_18( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_fbus_i3_o1_a32d64s6k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.user.amba_prot.fetch
invalidate anonIn.a.bits.user.amba_prot.secure
invalidate anonIn.a.bits.user.amba_prot.privileged
invalidate anonIn.a.bits.user.amba_prot.writealloc
invalidate anonIn.a.bits.user.amba_prot.readalloc
invalidate anonIn.a.bits.user.amba_prot.modifiable
invalidate anonIn.a.bits.user.amba_prot.bufferable
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.user.amba_prot.fetch
invalidate anonIn_1.a.bits.user.amba_prot.secure
invalidate anonIn_1.a.bits.user.amba_prot.privileged
invalidate anonIn_1.a.bits.user.amba_prot.writealloc
invalidate anonIn_1.a.bits.user.amba_prot.readalloc
invalidate anonIn_1.a.bits.user.amba_prot.modifiable
invalidate anonIn_1.a.bits.user.amba_prot.bufferable
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_2.d.bits.corrupt
invalidate anonIn_2.d.bits.data
invalidate anonIn_2.d.bits.denied
invalidate anonIn_2.d.bits.sink
invalidate anonIn_2.d.bits.source
invalidate anonIn_2.d.bits.size
invalidate anonIn_2.d.bits.param
invalidate anonIn_2.d.bits.opcode
invalidate anonIn_2.d.valid
invalidate anonIn_2.d.ready
invalidate anonIn_2.a.bits.corrupt
invalidate anonIn_2.a.bits.data
invalidate anonIn_2.a.bits.mask
invalidate anonIn_2.a.bits.address
invalidate anonIn_2.a.bits.source
invalidate anonIn_2.a.bits.size
invalidate anonIn_2.a.bits.param
invalidate anonIn_2.a.bits.opcode
invalidate anonIn_2.a.valid
invalidate anonIn_2.a.ready
inst monitor of TLMonitor_13
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_14
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch
connect monitor_1.io.in.a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure
connect monitor_1.io.in.a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged
connect monitor_1.io.in.a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc
connect monitor_1.io.in.a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc
connect monitor_1.io.in.a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable
connect monitor_1.io.in.a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
inst monitor_2 of TLMonitor_15
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, anonIn_2.d.valid
connect monitor_2.io.in.d.ready, anonIn_2.d.ready
connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, anonIn_2.a.valid
connect monitor_2.io.in.a.ready, anonIn_2.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.user.amba_prot.fetch
invalidate anonOut.a.bits.user.amba_prot.secure
invalidate anonOut.a.bits.user.amba_prot.privileged
invalidate anonOut.a.bits.user.amba_prot.writealloc
invalidate anonOut.a.bits.user.amba_prot.readalloc
invalidate anonOut.a.bits.user.amba_prot.modifiable
invalidate anonOut.a.bits.user.amba_prot.bufferable
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonIn_2, auto.anon_in_2
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[3]
invalidate in[0].a.bits.user.amba_prot.fetch
invalidate in[0].a.bits.user.amba_prot.secure
invalidate in[0].a.bits.user.amba_prot.privileged
invalidate in[0].a.bits.user.amba_prot.writealloc
invalidate in[0].a.bits.user.amba_prot.readalloc
invalidate in[0].a.bits.user.amba_prot.modifiable
invalidate in[0].a.bits.user.amba_prot.bufferable
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.user.amba_prot.fetch, anonIn.a.bits.user.amba_prot.fetch
connect in[0].a.bits.user.amba_prot.secure, anonIn.a.bits.user.amba_prot.secure
connect in[0].a.bits.user.amba_prot.privileged, anonIn.a.bits.user.amba_prot.privileged
connect in[0].a.bits.user.amba_prot.writealloc, anonIn.a.bits.user.amba_prot.writealloc
connect in[0].a.bits.user.amba_prot.readalloc, anonIn.a.bits.user.amba_prot.readalloc
connect in[0].a.bits.user.amba_prot.modifiable, anonIn.a.bits.user.amba_prot.modifiable
connect in[0].a.bits.user.amba_prot.bufferable, anonIn.a.bits.user.amba_prot.bufferable
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<6>(0h20))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<6>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.user.amba_prot.fetch
invalidate _WIRE_9.bits.user.amba_prot.secure
invalidate _WIRE_9.bits.user.amba_prot.privileged
invalidate _WIRE_9.bits.user.amba_prot.writealloc
invalidate _WIRE_9.bits.user.amba_prot.readalloc
invalidate _WIRE_9.bits.user.amba_prot.modifiable
invalidate _WIRE_9.bits.user.amba_prot.bufferable
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.user.amba_prot.fetch
invalidate _WIRE_11.bits.user.amba_prot.secure
invalidate _WIRE_11.bits.user.amba_prot.privileged
invalidate _WIRE_11.bits.user.amba_prot.writealloc
invalidate _WIRE_11.bits.user.amba_prot.readalloc
invalidate _WIRE_11.bits.user.amba_prot.modifiable
invalidate _WIRE_11.bits.user.amba_prot.bufferable
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
connect anonIn.d.bits.source, UInt<1>(0h0)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
invalidate in[1].a.bits.user.amba_prot.fetch
invalidate in[1].a.bits.user.amba_prot.secure
invalidate in[1].a.bits.user.amba_prot.privileged
invalidate in[1].a.bits.user.amba_prot.writealloc
invalidate in[1].a.bits.user.amba_prot.readalloc
invalidate in[1].a.bits.user.amba_prot.modifiable
invalidate in[1].a.bits.user.amba_prot.bufferable
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.user.amba_prot.fetch, anonIn_1.a.bits.user.amba_prot.fetch
connect in[1].a.bits.user.amba_prot.secure, anonIn_1.a.bits.user.amba_prot.secure
connect in[1].a.bits.user.amba_prot.privileged, anonIn_1.a.bits.user.amba_prot.privileged
connect in[1].a.bits.user.amba_prot.writealloc, anonIn_1.a.bits.user.amba_prot.writealloc
connect in[1].a.bits.user.amba_prot.readalloc, anonIn_1.a.bits.user.amba_prot.readalloc
connect in[1].a.bits.user.amba_prot.modifiable, anonIn_1.a.bits.user.amba_prot.modifiable
connect in[1].a.bits.user.amba_prot.bufferable, anonIn_1.a.bits.user.amba_prot.bufferable
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<5>(0h10))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<4>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<6>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<4>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_32.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<6>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.user.amba_prot.fetch
invalidate _WIRE_33.bits.user.amba_prot.secure
invalidate _WIRE_33.bits.user.amba_prot.privileged
invalidate _WIRE_33.bits.user.amba_prot.writealloc
invalidate _WIRE_33.bits.user.amba_prot.readalloc
invalidate _WIRE_33.bits.user.amba_prot.modifiable
invalidate _WIRE_33.bits.user.amba_prot.bufferable
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_34.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_34.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_34.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_34.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_34.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_34.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<4>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.user.amba_prot.fetch
invalidate _WIRE_35.bits.user.amba_prot.secure
invalidate _WIRE_35.bits.user.amba_prot.privileged
invalidate _WIRE_35.bits.user.amba_prot.writealloc
invalidate _WIRE_35.bits.user.amba_prot.readalloc
invalidate _WIRE_35.bits.user.amba_prot.modifiable
invalidate _WIRE_35.bits.user.amba_prot.bufferable
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_36.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<6>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_38.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_38.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_38.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_38.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_38.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_38.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<4>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T = bits(in[1].d.bits.source, 3, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
invalidate in[2].a.bits.user.amba_prot.fetch
invalidate in[2].a.bits.user.amba_prot.secure
invalidate in[2].a.bits.user.amba_prot.privileged
invalidate in[2].a.bits.user.amba_prot.writealloc
invalidate in[2].a.bits.user.amba_prot.readalloc
invalidate in[2].a.bits.user.amba_prot.modifiable
invalidate in[2].a.bits.user.amba_prot.bufferable
connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt
connect in[2].a.bits.data, anonIn_2.a.bits.data
connect in[2].a.bits.mask, anonIn_2.a.bits.mask
connect in[2].a.bits.address, anonIn_2.a.bits.address
connect in[2].a.bits.source, anonIn_2.a.bits.source
connect in[2].a.bits.size, anonIn_2.a.bits.size
connect in[2].a.bits.param, anonIn_2.a.bits.param
connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode
connect in[2].a.valid, anonIn_2.a.valid
connect anonIn_2.a.ready, in[2].a.ready
node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<1>(0h0))
connect in[2].a.bits.source, _in_2_a_bits_source_T
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<6>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<4>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<6>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.ready, UInt<1>(0h1)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<4>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.valid, UInt<1>(0h0)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_56.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<6>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.user.amba_prot.fetch
invalidate _WIRE_57.bits.user.amba_prot.secure
invalidate _WIRE_57.bits.user.amba_prot.privileged
invalidate _WIRE_57.bits.user.amba_prot.writealloc
invalidate _WIRE_57.bits.user.amba_prot.readalloc
invalidate _WIRE_57.bits.user.amba_prot.modifiable
invalidate _WIRE_57.bits.user.amba_prot.bufferable
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<4>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_60.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<6>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.valid, UInt<1>(0h0)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<4>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.ready, UInt<1>(0h1)
connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt
connect anonIn_2.d.bits.data, in[2].d.bits.data
connect anonIn_2.d.bits.denied, in[2].d.bits.denied
connect anonIn_2.d.bits.sink, in[2].d.bits.sink
connect anonIn_2.d.bits.source, in[2].d.bits.source
connect anonIn_2.d.bits.size, in[2].d.bits.size
connect anonIn_2.d.bits.param, in[2].d.bits.param
connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode
connect anonIn_2.d.valid, in[2].d.valid
connect in[2].d.ready, anonIn_2.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[2].d.bits.source, 3, 0)
connect anonIn_2.d.bits.source, _anonIn_d_bits_source_T_1
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.valid, UInt<1>(0h0)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[1]
invalidate out[0].a.bits.user.amba_prot.fetch
invalidate out[0].a.bits.user.amba_prot.secure
invalidate out[0].a.bits.user.amba_prot.privileged
invalidate out[0].a.bits.user.amba_prot.writealloc
invalidate out[0].a.bits.user.amba_prot.readalloc
invalidate out[0].a.bits.user.amba_prot.modifiable
invalidate out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.user.amba_prot.fetch, out[0].a.bits.user.amba_prot.fetch
connect anonOut.a.bits.user.amba_prot.secure, out[0].a.bits.user.amba_prot.secure
connect anonOut.a.bits.user.amba_prot.privileged, out[0].a.bits.user.amba_prot.privileged
connect anonOut.a.bits.user.amba_prot.writealloc, out[0].a.bits.user.amba_prot.writealloc
connect anonOut.a.bits.user.amba_prot.readalloc, out[0].a.bits.user.amba_prot.readalloc
connect anonOut.a.bits.user.amba_prot.modifiable, out[0].a.bits.user.amba_prot.modifiable
connect anonOut.a.bits.user.amba_prot.bufferable, out[0].a.bits.user.amba_prot.bufferable
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.mask, UInt<8>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<6>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<2>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.mask
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
invalidate _WIRE_73.valid
invalidate _WIRE_73.ready
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_74.bits.corrupt, UInt<1>(0h0)
connect _WIRE_74.bits.data, UInt<64>(0h0)
connect _WIRE_74.bits.mask, UInt<8>(0h0)
connect _WIRE_74.bits.address, UInt<32>(0h0)
connect _WIRE_74.bits.source, UInt<6>(0h0)
connect _WIRE_74.bits.size, UInt<4>(0h0)
connect _WIRE_74.bits.param, UInt<2>(0h0)
connect _WIRE_74.bits.opcode, UInt<3>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.corrupt
invalidate _WIRE_75.bits.data
invalidate _WIRE_75.bits.mask
invalidate _WIRE_75.bits.address
invalidate _WIRE_75.bits.source
invalidate _WIRE_75.bits.size
invalidate _WIRE_75.bits.param
invalidate _WIRE_75.bits.opcode
invalidate _WIRE_75.valid
invalidate _WIRE_75.ready
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<6>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
connect _WIRE_77.valid, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<6>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
connect _WIRE_79.ready, UInt<1>(0h1)
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_80.bits.corrupt, UInt<1>(0h0)
connect _WIRE_80.bits.data, UInt<64>(0h0)
connect _WIRE_80.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_80.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_80.bits.address, UInt<32>(0h0)
connect _WIRE_80.bits.source, UInt<6>(0h0)
connect _WIRE_80.bits.size, UInt<4>(0h0)
connect _WIRE_80.bits.param, UInt<3>(0h0)
connect _WIRE_80.bits.opcode, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.corrupt
invalidate _WIRE_81.bits.data
invalidate _WIRE_81.bits.user.amba_prot.fetch
invalidate _WIRE_81.bits.user.amba_prot.secure
invalidate _WIRE_81.bits.user.amba_prot.privileged
invalidate _WIRE_81.bits.user.amba_prot.writealloc
invalidate _WIRE_81.bits.user.amba_prot.readalloc
invalidate _WIRE_81.bits.user.amba_prot.modifiable
invalidate _WIRE_81.bits.user.amba_prot.bufferable
invalidate _WIRE_81.bits.address
invalidate _WIRE_81.bits.source
invalidate _WIRE_81.bits.size
invalidate _WIRE_81.bits.param
invalidate _WIRE_81.bits.opcode
invalidate _WIRE_81.valid
invalidate _WIRE_81.ready
wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_82.bits.corrupt, UInt<1>(0h0)
connect _WIRE_82.bits.data, UInt<64>(0h0)
connect _WIRE_82.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_82.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_82.bits.address, UInt<32>(0h0)
connect _WIRE_82.bits.source, UInt<6>(0h0)
connect _WIRE_82.bits.size, UInt<4>(0h0)
connect _WIRE_82.bits.param, UInt<3>(0h0)
connect _WIRE_82.bits.opcode, UInt<3>(0h0)
connect _WIRE_82.valid, UInt<1>(0h0)
connect _WIRE_82.ready, UInt<1>(0h0)
wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_83.bits, _WIRE_82.bits
connect _WIRE_83.valid, _WIRE_82.valid
connect _WIRE_83.ready, _WIRE_82.ready
invalidate _WIRE_83.bits.corrupt
invalidate _WIRE_83.bits.data
invalidate _WIRE_83.bits.user.amba_prot.fetch
invalidate _WIRE_83.bits.user.amba_prot.secure
invalidate _WIRE_83.bits.user.amba_prot.privileged
invalidate _WIRE_83.bits.user.amba_prot.writealloc
invalidate _WIRE_83.bits.user.amba_prot.readalloc
invalidate _WIRE_83.bits.user.amba_prot.modifiable
invalidate _WIRE_83.bits.user.amba_prot.bufferable
invalidate _WIRE_83.bits.address
invalidate _WIRE_83.bits.source
invalidate _WIRE_83.bits.size
invalidate _WIRE_83.bits.param
invalidate _WIRE_83.bits.opcode
invalidate _WIRE_83.valid
invalidate _WIRE_83.ready
wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_84.bits.corrupt, UInt<1>(0h0)
connect _WIRE_84.bits.data, UInt<64>(0h0)
connect _WIRE_84.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_84.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_84.bits.address, UInt<32>(0h0)
connect _WIRE_84.bits.source, UInt<6>(0h0)
connect _WIRE_84.bits.size, UInt<4>(0h0)
connect _WIRE_84.bits.param, UInt<3>(0h0)
connect _WIRE_84.bits.opcode, UInt<3>(0h0)
connect _WIRE_84.valid, UInt<1>(0h0)
connect _WIRE_84.ready, UInt<1>(0h0)
wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_85.bits, _WIRE_84.bits
connect _WIRE_85.valid, _WIRE_84.valid
connect _WIRE_85.ready, _WIRE_84.ready
connect _WIRE_85.ready, UInt<1>(0h1)
wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_86.bits.corrupt, UInt<1>(0h0)
connect _WIRE_86.bits.data, UInt<64>(0h0)
connect _WIRE_86.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_86.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_86.bits.address, UInt<32>(0h0)
connect _WIRE_86.bits.source, UInt<6>(0h0)
connect _WIRE_86.bits.size, UInt<4>(0h0)
connect _WIRE_86.bits.param, UInt<3>(0h0)
connect _WIRE_86.bits.opcode, UInt<3>(0h0)
connect _WIRE_86.valid, UInt<1>(0h0)
connect _WIRE_86.ready, UInt<1>(0h0)
wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_87.bits, _WIRE_86.bits
connect _WIRE_87.valid, _WIRE_86.valid
connect _WIRE_87.ready, _WIRE_86.ready
connect _WIRE_87.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_88.bits.sink, UInt<1>(0h0)
connect _WIRE_88.valid, UInt<1>(0h0)
connect _WIRE_88.ready, UInt<1>(0h0)
wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_89.bits, _WIRE_88.bits
connect _WIRE_89.valid, _WIRE_88.valid
connect _WIRE_89.ready, _WIRE_88.ready
invalidate _WIRE_89.bits.sink
invalidate _WIRE_89.valid
invalidate _WIRE_89.ready
wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_90.bits.sink, UInt<1>(0h0)
connect _WIRE_90.valid, UInt<1>(0h0)
connect _WIRE_90.ready, UInt<1>(0h0)
wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_91.bits, _WIRE_90.bits
connect _WIRE_91.valid, _WIRE_90.valid
connect _WIRE_91.ready, _WIRE_90.ready
invalidate _WIRE_91.bits.sink
invalidate _WIRE_91.valid
invalidate _WIRE_91.ready
wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_92.bits.sink, UInt<1>(0h0)
connect _WIRE_92.valid, UInt<1>(0h0)
connect _WIRE_92.ready, UInt<1>(0h0)
wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_93.bits, _WIRE_92.bits
connect _WIRE_93.valid, _WIRE_92.valid
connect _WIRE_93.ready, _WIRE_92.ready
connect _WIRE_93.ready, UInt<1>(0h1)
wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_94.bits.sink, UInt<1>(0h0)
connect _WIRE_94.valid, UInt<1>(0h0)
connect _WIRE_94.ready, UInt<1>(0h0)
wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_95.bits, _WIRE_94.bits
connect _WIRE_95.valid, _WIRE_94.valid
connect _WIRE_95.ready, _WIRE_94.ready
connect _WIRE_95.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE.bits.address, UInt<32>(0h0)
connect _addressC_WIRE.bits.source, UInt<6>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<6>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
wire _addressC_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_4.bits.source, UInt<6>(0h0)
connect _addressC_WIRE_4.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_4.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_4.valid, UInt<1>(0h0)
connect _addressC_WIRE_4.ready, UInt<1>(0h0)
wire _addressC_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_5.bits, _addressC_WIRE_4.bits
connect _addressC_WIRE_5.valid, _addressC_WIRE_4.valid
connect _addressC_WIRE_5.ready, _addressC_WIRE_4.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestAIO_T_10 = xor(in[2].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<1>(0h0)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node requestAIO_2_0 = or(UInt<1>(0h1), _requestAIO_T_14)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(_addressC_WIRE_5.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_14)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<6>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node requestBOI_0_0 = eq(_requestBOI_WIRE_1.bits.source, UInt<6>(0h20))
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<6>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_3.bits.source, UInt<4>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 3, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_3.bits.source, 4)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h1))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<4>(0hf))
node requestBOI_0_1 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_4.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_4.bits.source, UInt<6>(0h0)
connect _requestBOI_WIRE_4.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_4.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_4.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits
connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid
connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_5.bits.source, UInt<4>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 3, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_5.bits.source, 4)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<4>(0hf))
node requestBOI_0_2 = and(_requestBOI_T_8, _requestBOI_T_9)
node requestDOI_0_0 = eq(out[0].d.bits.source, UInt<6>(0h20))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<4>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 3, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 4)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h1))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<4>(0hf))
node requestDOI_0_1 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<4>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 3, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 4)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<4>(0hf))
node requestDOI_0_2 = and(_requestDOI_T_8, _requestDOI_T_9)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_4.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_4.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits
connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid
connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsAI_decode_T_6 = dshl(UInt<12>(0hfff), in[2].a.bits.size)
node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 11, 0)
node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7)
node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 3)
node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2)
node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0))
node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<6>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<6>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<6>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
wire _beatsCI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_4.bits.source, UInt<6>(0h0)
connect _beatsCI_WIRE_4.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_4.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_4.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_4.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_5.bits, _beatsCI_WIRE_4.bits
connect _beatsCI_WIRE_5.valid, _beatsCI_WIRE_4.valid
connect _beatsCI_WIRE_5.ready, _beatsCI_WIRE_4.ready
node _beatsCI_decode_T_6 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_5.bits.size)
node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 11, 0)
node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7)
node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 3)
node beatsCI_opdata_2 = bits(_beatsCI_WIRE_5.bits.opcode, 0, 0)
node beatsCI_2 = mux(UInt<1>(0h0), beatsCI_decode_2, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire _beatsEI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_4.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_4.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_4.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_5.bits, _beatsEI_WIRE_4.bits
connect _beatsEI_WIRE_5.valid, _beatsEI_WIRE_4.valid
connect _beatsEI_WIRE_5.ready, _beatsEI_WIRE_4.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_2[0].bits, in[2].a.bits
node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4)
connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5
connect in[2].a.ready, portsAOI_filtered_2[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<6>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[3]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
connect portsBIO_filtered[2].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0))
node _portsBIO_filtered_2_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_2_valid_T)
connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0))
node _portsBIO_T_3 = or(_portsBIO_T, _portsBIO_T_1)
node _portsBIO_T_4 = or(_portsBIO_T_3, _portsBIO_T_2)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_4
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<6>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<6>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire _portsCOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _portsCOI_WIRE_4.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_4.bits.source, UInt<6>(0h0)
connect _portsCOI_WIRE_4.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_4.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_4.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_4.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_5.bits, _portsCOI_WIRE_4.bits
connect _portsCOI_WIRE_5.valid, _portsCOI_WIRE_4.valid
connect _portsCOI_WIRE_5.ready, _portsCOI_WIRE_4.ready
wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_2[0].bits, _portsCOI_WIRE_5.bits
node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_5 = and(_portsCOI_WIRE_5.valid, _portsCOI_filtered_0_valid_T_4)
connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5
connect _portsCOI_WIRE_5.ready, portsCOI_filtered_2[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[3]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[2].bits.data, out[0].d.bits.data
connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[2].bits.source, out[0].d.bits.source
connect portsDIO_filtered[2].bits.size, out[0].d.bits.size
connect portsDIO_filtered[2].bits.param, out[0].d.bits.param
connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0))
node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T)
connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_3 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
node _portsDIO_out_0_d_ready_T_4 = or(_portsDIO_out_0_d_ready_T_3, _portsDIO_out_0_d_ready_T_2)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_4
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
wire _portsEOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_4.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_4.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_4.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_5.bits, _portsEOI_WIRE_4.bits
connect _portsEOI_WIRE_5.valid, _portsEOI_WIRE_4.valid
connect _portsEOI_WIRE_5.ready, _portsEOI_WIRE_4.ready
wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_2[0].bits, _portsEOI_WIRE_5.bits
node _portsEOI_filtered_0_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_5 = and(_portsEOI_WIRE_5.valid, _portsEOI_filtered_0_valid_T_4)
connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5
connect _portsEOI_WIRE_5.ready, portsEOI_filtered_2[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node readys_hi = cat(portsAOI_filtered_2[0].valid, portsAOI_filtered_1[0].valid)
node _readys_T = cat(readys_hi, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 2, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<3>, clock, reset, UInt<3>(0h7)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = bits(_readys_unready_T_3, 5, 0)
node _readys_unready_T_5 = shr(_readys_unready_T_4, 1)
node _readys_unready_T_6 = shl(readys_mask, 3)
node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6)
node _readys_readys_T = shr(readys_unready, 3)
node _readys_readys_T_1 = bits(readys_unready, 2, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 2, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 2, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 2, 0)
connect readys_mask, _readys_mask_T_7
node _readys_T_7 = bits(readys_readys, 2, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
wire readys : UInt<1>[3]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid)
wire winner : UInt<1>[3]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node _prefixOR_T = or(prefixOR_2, winner[2])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = and(_T_2, _T_5)
node _T_10 = and(_T_9, _T_8)
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _T_14 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_15 = or(_T_14, portsAOI_filtered_2[0].valid)
node _T_16 = eq(_T_15, UInt<1>(0h0))
node _T_17 = or(winner[0], winner[1])
node _T_18 = or(_T_17, winner[2])
node _T_19 = or(_T_16, _T_18)
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node initBeats = or(_initBeats_T, maskedBeats_2)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[3]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
regreset state : UInt<1>[3], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2])
connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid)
node _out_0_a_valid_T_2 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_4 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_5 = or(_out_0_a_valid_T_2, _out_0_a_valid_T_3)
node _out_0_a_valid_T_6 = or(_out_0_a_valid_T_5, _out_0_a_valid_T_4)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_6
node _out_0_a_valid_T_7 = mux(idle, _out_0_a_valid_T_1, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_7
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_3 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
node _out_0_a_bits_T_4 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_2)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_4
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_5 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_6 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_5, _out_0_a_bits_T_6)
node _out_0_a_bits_T_9 = or(_out_0_a_bits_T_8, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_9
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_10 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_11 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_12 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_13 = or(_out_0_a_bits_T_10, _out_0_a_bits_T_11)
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_13, _out_0_a_bits_T_12)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}
wire _out_0_a_bits_WIRE_6 : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_17 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.fetch, UInt<1>(0h0))
node _out_0_a_bits_T_18 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
node _out_0_a_bits_T_19 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_17)
wire _out_0_a_bits_WIRE_7 : UInt<1>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_19
connect _out_0_a_bits_WIRE_6.fetch, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_20 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_21 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.secure, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_20, _out_0_a_bits_T_21)
node _out_0_a_bits_T_24 = or(_out_0_a_bits_T_23, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_8 : UInt<1>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_24
connect _out_0_a_bits_WIRE_6.secure, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_25 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_26 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_27 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.privileged, UInt<1>(0h0))
node _out_0_a_bits_T_28 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_26)
node _out_0_a_bits_T_29 = or(_out_0_a_bits_T_28, _out_0_a_bits_T_27)
wire _out_0_a_bits_WIRE_9 : UInt<1>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_29
connect _out_0_a_bits_WIRE_6.privileged, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_30 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_31 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_32 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.writealloc, UInt<1>(0h0))
node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_30, _out_0_a_bits_T_31)
node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_32)
wire _out_0_a_bits_WIRE_10 : UInt<1>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_34
connect _out_0_a_bits_WIRE_6.writealloc, _out_0_a_bits_WIRE_10
node _out_0_a_bits_T_35 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_36 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_37 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.readalloc, UInt<1>(0h0))
node _out_0_a_bits_T_38 = or(_out_0_a_bits_T_35, _out_0_a_bits_T_36)
node _out_0_a_bits_T_39 = or(_out_0_a_bits_T_38, _out_0_a_bits_T_37)
wire _out_0_a_bits_WIRE_11 : UInt<1>
connect _out_0_a_bits_WIRE_11, _out_0_a_bits_T_39
connect _out_0_a_bits_WIRE_6.readalloc, _out_0_a_bits_WIRE_11
node _out_0_a_bits_T_40 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_41 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_42 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.modifiable, UInt<1>(0h0))
node _out_0_a_bits_T_43 = or(_out_0_a_bits_T_40, _out_0_a_bits_T_41)
node _out_0_a_bits_T_44 = or(_out_0_a_bits_T_43, _out_0_a_bits_T_42)
wire _out_0_a_bits_WIRE_12 : UInt<1>
connect _out_0_a_bits_WIRE_12, _out_0_a_bits_T_44
connect _out_0_a_bits_WIRE_6.modifiable, _out_0_a_bits_WIRE_12
node _out_0_a_bits_T_45 = mux(muxState[0], portsAOI_filtered[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_46 = mux(muxState[1], portsAOI_filtered_1[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_47 = mux(muxState[2], portsAOI_filtered_2[0].bits.user.amba_prot.bufferable, UInt<1>(0h0))
node _out_0_a_bits_T_48 = or(_out_0_a_bits_T_45, _out_0_a_bits_T_46)
node _out_0_a_bits_T_49 = or(_out_0_a_bits_T_48, _out_0_a_bits_T_47)
wire _out_0_a_bits_WIRE_13 : UInt<1>
connect _out_0_a_bits_WIRE_13, _out_0_a_bits_T_49
connect _out_0_a_bits_WIRE_6.bufferable, _out_0_a_bits_WIRE_13
connect _out_0_a_bits_WIRE_5.amba_prot, _out_0_a_bits_WIRE_6
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_50 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_51 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_52 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_53 = or(_out_0_a_bits_T_50, _out_0_a_bits_T_51)
node _out_0_a_bits_T_54 = or(_out_0_a_bits_T_53, _out_0_a_bits_T_52)
wire _out_0_a_bits_WIRE_14 : UInt<32>
connect _out_0_a_bits_WIRE_14, _out_0_a_bits_T_54
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_14
node _out_0_a_bits_T_55 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_56 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_57 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_58 = or(_out_0_a_bits_T_55, _out_0_a_bits_T_56)
node _out_0_a_bits_T_59 = or(_out_0_a_bits_T_58, _out_0_a_bits_T_57)
wire _out_0_a_bits_WIRE_15 : UInt<6>
connect _out_0_a_bits_WIRE_15, _out_0_a_bits_T_59
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_15
node _out_0_a_bits_T_60 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_61 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_62 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_63 = or(_out_0_a_bits_T_60, _out_0_a_bits_T_61)
node _out_0_a_bits_T_64 = or(_out_0_a_bits_T_63, _out_0_a_bits_T_62)
wire _out_0_a_bits_WIRE_16 : UInt<4>
connect _out_0_a_bits_WIRE_16, _out_0_a_bits_T_64
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_16
node _out_0_a_bits_T_65 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_66 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_67 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_68 = or(_out_0_a_bits_T_65, _out_0_a_bits_T_66)
node _out_0_a_bits_T_69 = or(_out_0_a_bits_T_68, _out_0_a_bits_T_67)
wire _out_0_a_bits_WIRE_17 : UInt<3>
connect _out_0_a_bits_WIRE_17, _out_0_a_bits_T_69
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_17
node _out_0_a_bits_T_70 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_71 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_72 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_73 = or(_out_0_a_bits_T_70, _out_0_a_bits_T_71)
node _out_0_a_bits_T_74 = or(_out_0_a_bits_T_73, _out_0_a_bits_T_72)
wire _out_0_a_bits_WIRE_18 : UInt<3>
connect _out_0_a_bits_WIRE_18, _out_0_a_bits_T_74
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_18
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.user.amba_prot.fetch, _out_0_a_bits_WIRE.user.amba_prot.fetch
connect out[0].a.bits.user.amba_prot.secure, _out_0_a_bits_WIRE.user.amba_prot.secure
connect out[0].a.bits.user.amba_prot.privileged, _out_0_a_bits_WIRE.user.amba_prot.privileged
connect out[0].a.bits.user.amba_prot.writealloc, _out_0_a_bits_WIRE.user.amba_prot.writealloc
connect out[0].a.bits.user.amba_prot.readalloc, _out_0_a_bits_WIRE.user.amba_prot.readalloc
connect out[0].a.bits.user.amba_prot.modifiable, _out_0_a_bits_WIRE.user.amba_prot.modifiable
connect out[0].a.bits.user.amba_prot.bufferable, _out_0_a_bits_WIRE.user.amba_prot.bufferable
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_96.bits.corrupt, UInt<1>(0h0)
connect _WIRE_96.bits.data, UInt<64>(0h0)
connect _WIRE_96.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_96.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_96.bits.address, UInt<32>(0h0)
connect _WIRE_96.bits.source, UInt<6>(0h0)
connect _WIRE_96.bits.size, UInt<4>(0h0)
connect _WIRE_96.bits.param, UInt<3>(0h0)
connect _WIRE_96.bits.opcode, UInt<3>(0h0)
connect _WIRE_96.valid, UInt<1>(0h0)
connect _WIRE_96.ready, UInt<1>(0h0)
wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_97.bits, _WIRE_96.bits
connect _WIRE_97.valid, _WIRE_96.valid
connect _WIRE_97.ready, _WIRE_96.ready
invalidate _WIRE_97.bits.corrupt
invalidate _WIRE_97.bits.data
invalidate _WIRE_97.bits.user.amba_prot.fetch
invalidate _WIRE_97.bits.user.amba_prot.secure
invalidate _WIRE_97.bits.user.amba_prot.privileged
invalidate _WIRE_97.bits.user.amba_prot.writealloc
invalidate _WIRE_97.bits.user.amba_prot.readalloc
invalidate _WIRE_97.bits.user.amba_prot.modifiable
invalidate _WIRE_97.bits.user.amba_prot.bufferable
invalidate _WIRE_97.bits.address
invalidate _WIRE_97.bits.source
invalidate _WIRE_97.bits.size
invalidate _WIRE_97.bits.param
invalidate _WIRE_97.bits.opcode
wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_98.bits.sink, UInt<1>(0h0)
connect _WIRE_98.valid, UInt<1>(0h0)
connect _WIRE_98.ready, UInt<1>(0h0)
wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_99.bits, _WIRE_98.bits
connect _WIRE_99.valid, _WIRE_98.valid
connect _WIRE_99.ready, _WIRE_98.ready
invalidate _WIRE_99.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_2[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_2[0].ready, UInt<1>(0h0)
wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_100.bits.corrupt, UInt<1>(0h0)
connect _WIRE_100.bits.data, UInt<64>(0h0)
connect _WIRE_100.bits.mask, UInt<8>(0h0)
connect _WIRE_100.bits.address, UInt<32>(0h0)
connect _WIRE_100.bits.source, UInt<6>(0h0)
connect _WIRE_100.bits.size, UInt<4>(0h0)
connect _WIRE_100.bits.param, UInt<2>(0h0)
connect _WIRE_100.bits.opcode, UInt<3>(0h0)
connect _WIRE_100.valid, UInt<1>(0h0)
connect _WIRE_100.ready, UInt<1>(0h0)
wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_101.bits, _WIRE_100.bits
connect _WIRE_101.valid, _WIRE_100.valid
connect _WIRE_101.ready, _WIRE_100.ready
invalidate _WIRE_101.bits.corrupt
invalidate _WIRE_101.bits.data
invalidate _WIRE_101.bits.mask
invalidate _WIRE_101.bits.address
invalidate _WIRE_101.bits.source
invalidate _WIRE_101.bits.size
invalidate _WIRE_101.bits.param
invalidate _WIRE_101.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_102.bits.corrupt, UInt<1>(0h0)
connect _WIRE_102.bits.data, UInt<64>(0h0)
connect _WIRE_102.bits.mask, UInt<8>(0h0)
connect _WIRE_102.bits.address, UInt<32>(0h0)
connect _WIRE_102.bits.source, UInt<6>(0h0)
connect _WIRE_102.bits.size, UInt<4>(0h0)
connect _WIRE_102.bits.param, UInt<2>(0h0)
connect _WIRE_102.bits.opcode, UInt<3>(0h0)
connect _WIRE_102.valid, UInt<1>(0h0)
connect _WIRE_102.ready, UInt<1>(0h0)
wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_103.bits, _WIRE_102.bits
connect _WIRE_103.valid, _WIRE_102.valid
connect _WIRE_103.ready, _WIRE_102.ready
invalidate _WIRE_103.bits.corrupt
invalidate _WIRE_103.bits.data
invalidate _WIRE_103.bits.mask
invalidate _WIRE_103.bits.address
invalidate _WIRE_103.bits.source
invalidate _WIRE_103.bits.size
invalidate _WIRE_103.bits.param
invalidate _WIRE_103.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_104.bits.corrupt, UInt<1>(0h0)
connect _WIRE_104.bits.data, UInt<64>(0h0)
connect _WIRE_104.bits.mask, UInt<8>(0h0)
connect _WIRE_104.bits.address, UInt<32>(0h0)
connect _WIRE_104.bits.source, UInt<6>(0h0)
connect _WIRE_104.bits.size, UInt<4>(0h0)
connect _WIRE_104.bits.param, UInt<2>(0h0)
connect _WIRE_104.bits.opcode, UInt<3>(0h0)
connect _WIRE_104.valid, UInt<1>(0h0)
connect _WIRE_104.ready, UInt<1>(0h0)
wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_105.bits, _WIRE_104.bits
connect _WIRE_105.valid, _WIRE_104.valid
connect _WIRE_105.ready, _WIRE_104.ready
invalidate _WIRE_105.bits.corrupt
invalidate _WIRE_105.bits.data
invalidate _WIRE_105.bits.mask
invalidate _WIRE_105.bits.address
invalidate _WIRE_105.bits.source
invalidate _WIRE_105.bits.size
invalidate _WIRE_105.bits.param
invalidate _WIRE_105.bits.opcode
connect in[2].d, portsDIO_filtered[2]
connect portsBIO_filtered[2].ready, UInt<1>(0h0)
extmodule plusarg_reader_32 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_33 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLXbar_fbus_i3_o1_a32d64s6k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [5:0] in_2_a_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_2_a_valid_0 = auto_anon_in_2_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_a_bits_opcode_0 = auto_anon_in_2_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_a_bits_param_0 = auto_anon_in_2_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_a_bits_size_0 = auto_anon_in_2_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_a_bits_source_0 = auto_anon_in_2_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_2_a_bits_address_0 = auto_anon_in_2_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_2_a_bits_mask_0 = auto_anon_in_2_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_2_a_bits_data_0 = auto_anon_in_2_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_2_a_bits_corrupt_0 = auto_anon_in_2_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_ready_0 = auto_anon_in_2_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_bufferable_0 = auto_anon_in_1_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_modifiable_0 = auto_anon_in_1_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_readalloc_0 = auto_anon_in_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_writealloc_0 = auto_anon_in_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_privileged_0 = auto_anon_in_1_a_bits_user_amba_prot_privileged; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_secure_0 = auto_anon_in_1_a_bits_user_amba_prot_secure; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_user_amba_prot_fetch_0 = auto_anon_in_1_a_bits_user_amba_prot_fetch; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire [2:0] auto_anon_in_0_a_bits_param = 3'h0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] in_0_a_bits_param = 3'h0; // @[Xbar.scala:159:18]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsAOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_2_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_2_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_2_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _out_0_a_bits_T_65 = 3'h0; // @[Mux.scala:30:73]
wire auto_anon_in_0_a_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_user_amba_prot_bufferable = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_user_amba_prot_modifiable = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_user_amba_prot_readalloc = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_user_amba_prot_writealloc = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_user_amba_prot_fetch = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire in_0_a_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:159:18]
wire in_0_a_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:159:18]
wire in_0_a_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:159:18]
wire in_0_a_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:159:18]
wire in_0_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:159:18]
wire in_2_a_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:159:18]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:46:9]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_1 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_3 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_4_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_5_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_2 = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_4_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_5_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsAOI_filtered_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24]
wire portsAOI_filtered_2_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_2_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_2_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_4 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_bufferable = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_modifiable = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_readalloc = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_writealloc = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_privileged = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_secure = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_user_amba_prot_fetch = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_2_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_4_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_4_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_4_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_5_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_5_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_5_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_2_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_2_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_5 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_2 = 1'h0; // @[Arbiter.scala:88:34]
wire _out_0_a_bits_T_15 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_17 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_22 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_27 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_30 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_32 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_37 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_40 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_42 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_45 = 1'h0; // @[Mux.scala:30:73]
wire _out_0_a_bits_T_47 = 1'h0; // @[Mux.scala:30:73]
wire auto_anon_in_0_a_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:74:9]
wire anonIn_a_bits_user_amba_prot_privileged = 1'h1; // @[MixedNode.scala:551:17]
wire anonIn_a_bits_user_amba_prot_secure = 1'h1; // @[MixedNode.scala:551:17]
wire in_0_a_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:159:18]
wire in_0_a_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:159:18]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_2_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_2_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_2 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire portsAOI_filtered_0_bits_user_amba_prot_privileged = 1'h1; // @[Xbar.scala:352:24]
wire portsAOI_filtered_0_bits_user_amba_prot_secure = 1'h1; // @[Xbar.scala:352:24]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_2_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_4 = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _addressC_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _addressC_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _addressC_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _requestBOI_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _requestBOI_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _beatsCI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _beatsCI_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _beatsCI_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] portsBIO_filtered_2_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] _portsCOI_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _portsCOI_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] portsCOI_filtered_2_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_10 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_2_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_2_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [5:0] _addressC_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _addressC_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _addressC_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _addressC_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _addressC_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _addressC_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _requestBOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29]
wire [5:0] _requestBOI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _requestBOI_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _requestBOI_uncommonBits_T_1 = 6'h0; // @[Parameters.scala:52:29]
wire [5:0] _beatsBO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _beatsCI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _beatsCI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _beatsCI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _beatsCI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _beatsCI_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _portsBIO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsBIO_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsBIO_filtered_2_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] _portsCOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] _portsCOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _portsCOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] portsCOI_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] _portsCOI_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _portsCOI_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] portsCOI_filtered_2_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _requestBOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] requestBOI_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_2_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_2_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _requestBOI_WIRE_4_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _requestBOI_WIRE_5_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_1_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] portsBIO_filtered_2_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_T = 2'h0; // @[Parameters.scala:54:10]
wire [1:0] _requestBOI_WIRE_4_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_5_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_T_5 = 2'h0; // @[Parameters.scala:54:10]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_2_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [5:0] in_0_a_bits_source = 6'h20; // @[Xbar.scala:159:18]
wire [5:0] _in_0_a_bits_source_T = 6'h20; // @[Xbar.scala:166:55]
wire [5:0] portsAOI_filtered_0_bits_source = 6'h20; // @[Xbar.scala:352:24]
wire [8:0] beatsBO_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_0 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] beatsCI_decode_2 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] beatsCI_2 = 9'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_8 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_7 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_6 = 27'hFFF; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_11 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_2_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_2_a_valid = auto_anon_in_2_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_2_a_bits_opcode = auto_anon_in_2_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_2_a_bits_param = auto_anon_in_2_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_2_a_bits_size = auto_anon_in_2_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_2_a_bits_source = auto_anon_in_2_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_2_a_bits_address = auto_anon_in_2_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_2_a_bits_mask = auto_anon_in_2_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_2_a_bits_data = auto_anon_in_2_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_2_a_bits_corrupt = auto_anon_in_2_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_2_d_ready = auto_anon_in_2_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_2_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_2_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_2_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_2_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_2_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_bufferable = auto_anon_in_1_a_bits_user_amba_prot_bufferable_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_modifiable = auto_anon_in_1_a_bits_user_amba_prot_modifiable_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_readalloc = auto_anon_in_1_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_writealloc = auto_anon_in_1_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_privileged = auto_anon_in_1_a_bits_user_amba_prot_privileged_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_secure = auto_anon_in_1_a_bits_user_amba_prot_secure_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_user_amba_prot_fetch = auto_anon_in_1_a_bits_user_amba_prot_fetch_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_secure; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_user_amba_prot_fetch; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_2_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_2_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_2_d_bits_source_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_2_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_2_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_bufferable_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_modifiable_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_readalloc_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_writealloc_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_privileged_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_secure_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_user_amba_prot_fetch_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_bufferable = anonIn_1_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_modifiable = anonIn_1_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_readalloc = anonIn_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_writealloc = anonIn_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_privileged = anonIn_1_a_bits_user_amba_prot_privileged; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_secure = anonIn_1_a_bits_user_amba_prot_secure; // @[Xbar.scala:159:18]
wire in_1_a_bits_user_amba_prot_fetch = anonIn_1_a_bits_user_amba_prot_fetch; // @[Xbar.scala:159:18]
wire [7:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_2_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_2_a_ready_0 = anonIn_2_a_ready; // @[Xbar.scala:74:9]
wire in_2_a_valid = anonIn_2_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_2_a_bits_opcode = anonIn_2_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_2_a_bits_param = anonIn_2_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_2_a_bits_size = anonIn_2_a_bits_size; // @[Xbar.scala:159:18]
wire [3:0] _in_2_a_bits_source_T = anonIn_2_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_2_a_bits_address = anonIn_2_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] in_2_a_bits_mask = anonIn_2_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] in_2_a_bits_data = anonIn_2_a_bits_data; // @[Xbar.scala:159:18]
wire in_2_a_bits_corrupt = anonIn_2_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_2_d_ready = anonIn_2_d_ready; // @[Xbar.scala:159:18]
wire in_2_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_valid_0 = anonIn_2_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_2_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_opcode_0 = anonIn_2_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_2_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_param_0 = anonIn_2_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_2_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_size_0 = anonIn_2_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
assign auto_anon_in_2_d_bits_source_0 = anonIn_2_d_bits_source; // @[Xbar.scala:74:9]
wire in_2_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_sink_0 = anonIn_2_d_bits_sink; // @[Xbar.scala:74:9]
wire in_2_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_denied_0 = anonIn_2_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] in_2_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_data_0 = anonIn_2_d_bits_data; // @[Xbar.scala:74:9]
wire in_2_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_2_d_bits_corrupt_0 = anonIn_2_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_bufferable_0 = anonOut_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_modifiable_0 = anonOut_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_readalloc_0 = anonOut_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_writealloc_0 = anonOut_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_privileged_0 = anonOut_a_bits_user_amba_prot_privileged; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_secure; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_secure_0 = anonOut_a_bits_user_amba_prot_secure; // @[Xbar.scala:74:9]
wire out_0_a_bits_user_amba_prot_fetch; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_user_amba_prot_fetch_0 = anonOut_a_bits_user_amba_prot_fetch; // @[Xbar.scala:74:9]
wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_bufferable = in_1_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_modifiable = in_1_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_readalloc = in_1_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_writealloc = in_1_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_privileged = in_1_a_bits_user_amba_prot_privileged; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_secure = in_1_a_bits_user_amba_prot_secure; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_user_amba_prot_fetch = in_1_a_bits_user_amba_prot_fetch; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_2_0_ready; // @[Xbar.scala:352:24]
assign anonIn_2_a_ready = in_2_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_5 = in_2_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_2_0_bits_opcode = in_2_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_2_0_bits_param = in_2_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_2_0_bits_size = in_2_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_2_0_bits_source = in_2_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_10 = in_2_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_2_0_bits_address = in_2_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] portsAOI_filtered_2_0_bits_mask = in_2_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] portsAOI_filtered_2_0_bits_data = in_2_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_2_0_bits_corrupt = in_2_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_2_ready = in_2_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_2_valid; // @[Xbar.scala:352:24]
assign anonIn_2_d_valid = in_2_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_2_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_opcode = in_2_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_2_bits_param; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_param = in_2_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_2_bits_size; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_size = in_2_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_2_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_2_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_sink = in_2_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_2_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_denied = in_2_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] portsDIO_filtered_2_bits_data; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_data = in_2_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_2_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_2_d_bits_corrupt = in_2_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_2_d_bits_source; // @[Xbar.scala:159:18]
wire [4:0] _in_1_a_bits_source_T = {1'h1, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55]
assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T = in_1_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_2_a_bits_source = {2'h0, _in_2_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_1 = in_2_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_2_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_7; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_bufferable; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_bufferable = out_0_a_bits_user_amba_prot_bufferable; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_modifiable; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_modifiable = out_0_a_bits_user_amba_prot_modifiable; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_readalloc; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_readalloc = out_0_a_bits_user_amba_prot_readalloc; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_writealloc; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_writealloc = out_0_a_bits_user_amba_prot_writealloc; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_privileged; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_privileged = out_0_a_bits_user_amba_prot_privileged; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_secure; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_secure = out_0_a_bits_user_amba_prot_secure; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_user_amba_prot_fetch; // @[Mux.scala:30:73]
assign anonOut_a_bits_user_amba_prot_fetch = out_0_a_bits_user_amba_prot_fetch; // @[Xbar.scala:216:19]
wire [7:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [5:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_2_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_11 = {1'h0, _requestAIO_T_10}; // @[Parameters.scala:137:{31,41}]
wire requestDOI_0_0 = out_0_d_bits_source == 6'h20; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [3:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _requestDOI_T = out_0_d_bits_source[5:4]; // @[Xbar.scala:216:19]
wire [1:0] _requestDOI_T_5 = out_0_d_bits_source[5:4]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = _requestDOI_T == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [3:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_6 = _requestDOI_T_5 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_2 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_2_valid_T = requestDOI_0_2; // @[Xbar.scala:355:54]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode = _beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_6 = 27'hFFF << in_2_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_7 = _beatsAI_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_8 = ~_beatsAI_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] beatsAI_decode_2 = _beatsAI_decode_T_8[11:3]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_2 = in_2_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_2 = ~_beatsAI_opdata_T_2; // @[Edges.scala:92:{28,37}]
wire [8:0] beatsAI_2 = beatsAI_opdata_2 ? beatsAI_decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] beatsDO_decode = _beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_2; // @[Arbiter.scala:94:31]
assign in_2_a_ready = portsAOI_filtered_2_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_2_0_valid = _portsAOI_filtered_0_valid_T_5; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:355:40]
assign in_2_d_valid = portsDIO_filtered_2_valid; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_opcode = portsDIO_filtered_2_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_param = portsDIO_filtered_2_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_size = portsDIO_filtered_2_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_source = portsDIO_filtered_2_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_sink = portsDIO_filtered_2_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_denied = portsDIO_filtered_2_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_data = portsDIO_filtered_2_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_2_d_bits_corrupt = portsDIO_filtered_2_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_2_valid_T_1 = out_0_d_valid & _portsDIO_filtered_2_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_2_valid = _portsDIO_filtered_2_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = requestDOI_0_2 & portsDIO_filtered_2_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_3 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_4 = _portsDIO_out_0_d_ready_T_3 | _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_4; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] readys_hi = {portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] _readys_T = {readys_hi, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [2:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [2:0] readys_mask; // @[Arbiter.scala:23:23]
wire [2:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [2:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [5:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [4:0] _readys_unready_T = readys_filter[5:1]; // @[package.scala:262:48]
wire [5:0] _readys_unready_T_1 = {readys_filter[5], readys_filter[4:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1[5:2]; // @[package.scala:262:{43,48}]
wire [5:0] _readys_unready_T_3 = {_readys_unready_T_1[5:4], _readys_unready_T_1[3:0] | _readys_unready_T_2}; // @[package.scala:262:{43,48}]
wire [5:0] _readys_unready_T_4 = _readys_unready_T_3; // @[package.scala:262:43, :263:17]
wire [4:0] _readys_unready_T_5 = _readys_unready_T_4[5:1]; // @[package.scala:263:17]
wire [5:0] _readys_unready_T_6 = {readys_mask, 3'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [5:0] readys_unready = {1'h0, _readys_unready_T_5} | _readys_unready_T_6; // @[Arbiter.scala:25:{52,58,66}]
wire [2:0] _readys_readys_T = readys_unready[5:3]; // @[Arbiter.scala:25:58, :26:29]
wire [2:0] _readys_readys_T_1 = readys_unready[2:0]; // @[Arbiter.scala:25:58, :26:48]
wire [2:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [2:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [2:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [2:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [3:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [2:0] _readys_mask_T_2 = _readys_mask_T_1[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [4:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [2:0] _readys_mask_T_5 = _readys_mask_T_4[2:0]; // @[package.scala:253:{48,53}]
wire [2:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_5; // @[package.scala:253:{43,53}]
wire [2:0] _readys_mask_T_7 = _readys_mask_T_6; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_10 = _readys_T_7[2]; // @[Arbiter.scala:30:11, :68:76]
wire readys_2 = _readys_T_10; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_2 = readys_2 & portsAOI_filtered_2_0_valid; // @[Xbar.scala:352:24]
wire winner_2 = _winner_T_2; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire prefixOR_2 = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_2 | winner_2; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_19 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_19( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ScratchpadBank :
input clock : Clock
input reset : Reset
output io : { flip read : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<12>, fromDMA : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<128>, fromDMA : UInt<1>}}}, flip write : { en : UInt<1>, addr : UInt<12>, mask : UInt<1>[16], data : UInt<128>}}
smem mem : UInt<8>[16] [4096]
node singleport_busy_with_write = and(UInt<1>(0h1), io.write.en)
when io.write.en :
wire _WIRE : UInt<8>[16]
wire _WIRE_1 : UInt<128>
connect _WIRE_1, io.write.data
node _T = bits(_WIRE_1, 7, 0)
connect _WIRE[0], _T
node _T_1 = bits(_WIRE_1, 15, 8)
connect _WIRE[1], _T_1
node _T_2 = bits(_WIRE_1, 23, 16)
connect _WIRE[2], _T_2
node _T_3 = bits(_WIRE_1, 31, 24)
connect _WIRE[3], _T_3
node _T_4 = bits(_WIRE_1, 39, 32)
connect _WIRE[4], _T_4
node _T_5 = bits(_WIRE_1, 47, 40)
connect _WIRE[5], _T_5
node _T_6 = bits(_WIRE_1, 55, 48)
connect _WIRE[6], _T_6
node _T_7 = bits(_WIRE_1, 63, 56)
connect _WIRE[7], _T_7
node _T_8 = bits(_WIRE_1, 71, 64)
connect _WIRE[8], _T_8
node _T_9 = bits(_WIRE_1, 79, 72)
connect _WIRE[9], _T_9
node _T_10 = bits(_WIRE_1, 87, 80)
connect _WIRE[10], _T_10
node _T_11 = bits(_WIRE_1, 95, 88)
connect _WIRE[11], _T_11
node _T_12 = bits(_WIRE_1, 103, 96)
connect _WIRE[12], _T_12
node _T_13 = bits(_WIRE_1, 111, 104)
connect _WIRE[13], _T_13
node _T_14 = bits(_WIRE_1, 119, 112)
connect _WIRE[14], _T_14
node _T_15 = bits(_WIRE_1, 127, 120)
connect _WIRE[15], _T_15
write mport MPORT = mem[io.write.addr], clock
when io.write.mask[0] :
connect MPORT[0], _WIRE[0]
when io.write.mask[1] :
connect MPORT[1], _WIRE[1]
when io.write.mask[2] :
connect MPORT[2], _WIRE[2]
when io.write.mask[3] :
connect MPORT[3], _WIRE[3]
when io.write.mask[4] :
connect MPORT[4], _WIRE[4]
when io.write.mask[5] :
connect MPORT[5], _WIRE[5]
when io.write.mask[6] :
connect MPORT[6], _WIRE[6]
when io.write.mask[7] :
connect MPORT[7], _WIRE[7]
when io.write.mask[8] :
connect MPORT[8], _WIRE[8]
when io.write.mask[9] :
connect MPORT[9], _WIRE[9]
when io.write.mask[10] :
connect MPORT[10], _WIRE[10]
when io.write.mask[11] :
connect MPORT[11], _WIRE[11]
when io.write.mask[12] :
connect MPORT[12], _WIRE[12]
when io.write.mask[13] :
connect MPORT[13], _WIRE[13]
when io.write.mask[14] :
connect MPORT[14], _WIRE[14]
when io.write.mask[15] :
connect MPORT[15], _WIRE[15]
node ren = and(io.read.req.ready, io.read.req.valid)
node _rdata_T = and(ren, io.write.en)
node _rdata_T_1 = eq(_rdata_T, UInt<1>(0h0))
node _rdata_T_2 = asUInt(reset)
node _rdata_T_3 = eq(_rdata_T_2, UInt<1>(0h0))
when _rdata_T_3 :
node _rdata_T_4 = eq(_rdata_T_1, UInt<1>(0h0))
when _rdata_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scratchpad.scala:151 assert(!(ren && io.write.en))\n") : rdata_printf
assert(clock, _rdata_T_1, UInt<1>(0h1), "") : rdata_assert
node _rdata_T_5 = eq(io.write.en, UInt<1>(0h0))
node _rdata_T_6 = and(ren, _rdata_T_5)
wire _rdata_WIRE : UInt<12>
invalidate _rdata_WIRE
when _rdata_T_6 :
connect _rdata_WIRE, io.read.req.bits.addr
read mport rdata_MPORT = mem[_rdata_WIRE], clock
node rdata_lo_lo_lo = cat(rdata_MPORT[1], rdata_MPORT[0])
node rdata_lo_lo_hi = cat(rdata_MPORT[3], rdata_MPORT[2])
node rdata_lo_lo = cat(rdata_lo_lo_hi, rdata_lo_lo_lo)
node rdata_lo_hi_lo = cat(rdata_MPORT[5], rdata_MPORT[4])
node rdata_lo_hi_hi = cat(rdata_MPORT[7], rdata_MPORT[6])
node rdata_lo_hi = cat(rdata_lo_hi_hi, rdata_lo_hi_lo)
node rdata_lo = cat(rdata_lo_hi, rdata_lo_lo)
node rdata_hi_lo_lo = cat(rdata_MPORT[9], rdata_MPORT[8])
node rdata_hi_lo_hi = cat(rdata_MPORT[11], rdata_MPORT[10])
node rdata_hi_lo = cat(rdata_hi_lo_hi, rdata_hi_lo_lo)
node rdata_hi_hi_lo = cat(rdata_MPORT[13], rdata_MPORT[12])
node rdata_hi_hi_hi = cat(rdata_MPORT[15], rdata_MPORT[14])
node rdata_hi_hi = cat(rdata_hi_hi_hi, rdata_hi_hi_lo)
node rdata_hi = cat(rdata_hi_hi, rdata_hi_lo)
node rdata = cat(rdata_hi, rdata_lo)
inst q of Queue1_ScratchpadReadResp
connect q.clock, clock
connect q.reset, reset
reg q_io_enq_valid_REG : UInt<1>, clock
connect q_io_enq_valid_REG, ren
connect q.io.enq.valid, q_io_enq_valid_REG
connect q.io.enq.bits.data, rdata
reg q_io_enq_bits_fromDMA_REG : UInt<1>, clock
connect q_io_enq_bits_fromDMA_REG, io.read.req.bits.fromDMA
connect q.io.enq.bits.fromDMA, q_io_enq_bits_fromDMA_REG
node _q_will_be_empty_T = and(q.io.enq.ready, q.io.enq.valid)
node _q_will_be_empty_T_1 = add(q.io.count, _q_will_be_empty_T)
node _q_will_be_empty_T_2 = and(q.io.deq.ready, q.io.deq.valid)
node _q_will_be_empty_T_3 = sub(_q_will_be_empty_T_1, _q_will_be_empty_T_2)
node _q_will_be_empty_T_4 = tail(_q_will_be_empty_T_3, 1)
node q_will_be_empty = eq(_q_will_be_empty_T_4, UInt<1>(0h0))
node _io_read_req_ready_T = eq(singleport_busy_with_write, UInt<1>(0h0))
node _io_read_req_ready_T_1 = and(q_will_be_empty, _io_read_req_ready_T)
connect io.read.req.ready, _io_read_req_ready_T_1
connect io.read.resp.bits, q.io.deq.bits
connect io.read.resp.valid, q.io.deq.valid
connect q.io.deq.ready, io.read.resp.ready | module ScratchpadBank( // @[Scratchpad.scala:97:7]
input clock, // @[Scratchpad.scala:97:7]
input reset, // @[Scratchpad.scala:97:7]
output io_read_req_ready, // @[Scratchpad.scala:104:14]
input io_read_req_valid, // @[Scratchpad.scala:104:14]
input [11:0] io_read_req_bits_addr, // @[Scratchpad.scala:104:14]
input io_read_req_bits_fromDMA, // @[Scratchpad.scala:104:14]
input io_read_resp_ready, // @[Scratchpad.scala:104:14]
output io_read_resp_valid, // @[Scratchpad.scala:104:14]
output [127:0] io_read_resp_bits_data, // @[Scratchpad.scala:104:14]
output io_read_resp_bits_fromDMA, // @[Scratchpad.scala:104:14]
input io_write_en, // @[Scratchpad.scala:104:14]
input [11:0] io_write_addr, // @[Scratchpad.scala:104:14]
input io_write_mask_0, // @[Scratchpad.scala:104:14]
input io_write_mask_1, // @[Scratchpad.scala:104:14]
input io_write_mask_2, // @[Scratchpad.scala:104:14]
input io_write_mask_3, // @[Scratchpad.scala:104:14]
input io_write_mask_4, // @[Scratchpad.scala:104:14]
input io_write_mask_5, // @[Scratchpad.scala:104:14]
input io_write_mask_6, // @[Scratchpad.scala:104:14]
input io_write_mask_7, // @[Scratchpad.scala:104:14]
input io_write_mask_8, // @[Scratchpad.scala:104:14]
input io_write_mask_9, // @[Scratchpad.scala:104:14]
input io_write_mask_10, // @[Scratchpad.scala:104:14]
input io_write_mask_11, // @[Scratchpad.scala:104:14]
input io_write_mask_12, // @[Scratchpad.scala:104:14]
input io_write_mask_13, // @[Scratchpad.scala:104:14]
input io_write_mask_14, // @[Scratchpad.scala:104:14]
input io_write_mask_15, // @[Scratchpad.scala:104:14]
input [127:0] io_write_data // @[Scratchpad.scala:104:14]
);
wire _q_io_enq_ready; // @[Scratchpad.scala:160:17]
wire _q_io_deq_valid; // @[Scratchpad.scala:160:17]
wire _q_io_count; // @[Scratchpad.scala:160:17]
wire [127:0] _mem_RW0_rdata; // @[Scratchpad.scala:132:26]
wire io_read_req_valid_0 = io_read_req_valid; // @[Scratchpad.scala:97:7]
wire [11:0] io_read_req_bits_addr_0 = io_read_req_bits_addr; // @[Scratchpad.scala:97:7]
wire io_read_req_bits_fromDMA_0 = io_read_req_bits_fromDMA; // @[Scratchpad.scala:97:7]
wire io_read_resp_ready_0 = io_read_resp_ready; // @[Scratchpad.scala:97:7]
wire io_write_en_0 = io_write_en; // @[Scratchpad.scala:97:7]
wire [11:0] io_write_addr_0 = io_write_addr; // @[Scratchpad.scala:97:7]
wire io_write_mask_0_0 = io_write_mask_0; // @[Scratchpad.scala:97:7]
wire io_write_mask_1_0 = io_write_mask_1; // @[Scratchpad.scala:97:7]
wire io_write_mask_2_0 = io_write_mask_2; // @[Scratchpad.scala:97:7]
wire io_write_mask_3_0 = io_write_mask_3; // @[Scratchpad.scala:97:7]
wire io_write_mask_4_0 = io_write_mask_4; // @[Scratchpad.scala:97:7]
wire io_write_mask_5_0 = io_write_mask_5; // @[Scratchpad.scala:97:7]
wire io_write_mask_6_0 = io_write_mask_6; // @[Scratchpad.scala:97:7]
wire io_write_mask_7_0 = io_write_mask_7; // @[Scratchpad.scala:97:7]
wire io_write_mask_8_0 = io_write_mask_8; // @[Scratchpad.scala:97:7]
wire io_write_mask_9_0 = io_write_mask_9; // @[Scratchpad.scala:97:7]
wire io_write_mask_10_0 = io_write_mask_10; // @[Scratchpad.scala:97:7]
wire io_write_mask_11_0 = io_write_mask_11; // @[Scratchpad.scala:97:7]
wire io_write_mask_12_0 = io_write_mask_12; // @[Scratchpad.scala:97:7]
wire io_write_mask_13_0 = io_write_mask_13; // @[Scratchpad.scala:97:7]
wire io_write_mask_14_0 = io_write_mask_14; // @[Scratchpad.scala:97:7]
wire io_write_mask_15_0 = io_write_mask_15; // @[Scratchpad.scala:97:7]
wire [127:0] io_write_data_0 = io_write_data; // @[Scratchpad.scala:97:7]
wire _rdata_T_2 = reset; // @[Scratchpad.scala:151:11]
wire _io_read_req_ready_T_1; // @[Scratchpad.scala:166:40]
wire [11:0] _rdata_WIRE = io_read_req_bits_addr_0; // @[Scratchpad.scala:97:7, :133:53]
wire singleport_busy_with_write = io_write_en_0; // @[Scratchpad.scala:97:7, :139:52]
wire io_read_req_ready_0; // @[Scratchpad.scala:97:7]
wire [127:0] io_read_resp_bits_data_0; // @[Scratchpad.scala:97:7]
wire io_read_resp_bits_fromDMA_0; // @[Scratchpad.scala:97:7]
wire io_read_resp_valid_0; // @[Scratchpad.scala:97:7]
wire _rdata_T_6; // @[Scratchpad.scala:152:21]
wire ren = io_read_req_ready_0 & io_read_req_valid_0; // @[Decoupled.scala:51:35]
wire _rdata_T = ren & io_write_en_0; // @[Decoupled.scala:51:35]
wire _rdata_T_1 = ~_rdata_T; // @[Scratchpad.scala:151:{12,18}]
wire _rdata_T_3 = ~_rdata_T_2; // @[Scratchpad.scala:151:11]
wire _rdata_T_4 = ~_rdata_T_1; // @[Scratchpad.scala:151:{11,12}] |
Generate the Verilog code corresponding to this FIRRTL code module PE_249 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_249( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ScratchpadBank_4 :
output auto : { flip xbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst xbar of TLXbar_i1_o1_a28d64s5k1z3u
connect xbar.clock, childClock
connect xbar.reset, childReset
inst ram of TLRAM_ScratchpadBank
connect ram.clock, childClock
connect ram.reset, childReset
inst fragmenter of TLFragmenter_ScratchpadBank
connect fragmenter.clock, childClock
connect fragmenter.reset, childReset
inst buffer of TLBuffer_a28d64s5k1z3u_1
connect buffer.clock, childClock
connect buffer.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect buffer.auto.in, xbar.auto.anon_out
connect ram.auto.in, fragmenter.auto.anon_out
connect fragmenter.auto.anon_in, buffer.auto.out
connect clockNodeIn, auto.clock_in
connect xbar.auto.anon_in, auto.xbar_anon_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module ScratchpadBank_4( // @[ClockDomain.scala:14:9]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_xbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [4:0] xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [4:0] xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire [4:0] xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [4:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [27:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [4:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [8:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [27:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _ram_auto_in_a_ready; // @[Scratchpad.scala:33:25]
wire _ram_auto_in_d_valid; // @[Scratchpad.scala:33:25]
wire [2:0] _ram_auto_in_d_bits_opcode; // @[Scratchpad.scala:33:25]
wire [1:0] _ram_auto_in_d_bits_size; // @[Scratchpad.scala:33:25]
wire [8:0] _ram_auto_in_d_bits_source; // @[Scratchpad.scala:33:25]
wire [63:0] _ram_auto_in_d_bits_data; // @[Scratchpad.scala:33:25]
wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [4:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [27:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__addressC_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__addressC_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__requestCIO_T = 28'h0; // @[Parameters.scala:137:31]
wire [27:0] xbar__requestBOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__requestBOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsBO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__beatsBO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsCI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__beatsCI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__portsBIO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__portsBIO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar_portsBIO_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__portsCOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__portsCOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar_portsCOI_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [4:0] xbar__addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] xbar__addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] xbar__requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] xbar__requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] xbar__requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29]
wire [4:0] xbar_requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56]
wire [4:0] xbar__beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] xbar__beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] xbar__beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] xbar__beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] xbar__portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] xbar__portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] xbar_portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] xbar__portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] xbar__portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] xbar_portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [28:0] xbar__requestAIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestAIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_1 = 29'h0; // @[Parameters.scala:137:41]
wire [28:0] xbar__requestCIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire xbar_auto_anon_in_a_valid = auto_xbar_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_opcode = auto_xbar_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_param = auto_xbar_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_size = auto_xbar_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] xbar_auto_anon_in_a_bits_source = auto_xbar_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_in_a_bits_address = auto_xbar_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_a_bits_mask = auto_xbar_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_a_bits_data = auto_xbar_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_bits_corrupt = auto_xbar_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_ready = auto_xbar_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [4:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_a_ready_0 = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_valid_0 = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_opcode_0 = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_param_0 = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_size_0 = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_source_0 = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_sink_0 = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_denied_0 = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_data_0 = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_corrupt_0 = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [4:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [4:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [27:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [4:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [27:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [27:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [4:0] xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [4:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [28:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [4:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLRAM_ScratchpadBank ram ( // @[Scratchpad.scala:33:25]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_ram_auto_in_a_ready),
.auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_in_d_valid (_ram_auto_in_d_valid),
.auto_in_d_bits_opcode (_ram_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_ram_auto_in_d_bits_size),
.auto_in_d_bits_source (_ram_auto_in_d_bits_source),
.auto_in_d_bits_data (_ram_auto_in_d_bits_data)
); // @[Scratchpad.scala:33:25]
TLFragmenter_ScratchpadBank fragmenter ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_ram_auto_in_a_ready), // @[Scratchpad.scala:33:25]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_ram_auto_in_d_valid), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_opcode (_ram_auto_in_d_bits_opcode), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_size (_ram_auto_in_d_bits_size), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_source (_ram_auto_in_d_bits_source), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_data (_ram_auto_in_d_bits_data) // @[Scratchpad.scala:33:25]
); // @[Fragmenter.scala:345:34]
TLBuffer_a28d64s5k1z3u_1 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (xbar_auto_anon_out_a_ready),
.auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9]
.auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt),
.auto_out_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Buffer.scala:75:28]
assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_param = auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_sink = auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_denied = auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_corrupt = auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FPUFMAPipe_l4_f64_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}}
reg valid : UInt<1>, clock
connect valid, io.in.valid
reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
when io.in.valid :
node one = shl(UInt<1>(0h1), 63)
node _zero_T = xor(io.in.bits.in1, io.in.bits.in2)
node _zero_T_1 = shl(UInt<1>(0h1), 64)
node zero = and(_zero_T, _zero_T_1)
connect in, io.in.bits
when io.in.bits.swap23 :
connect in.in2, one
node _T = or(io.in.bits.ren3, io.in.bits.swap23)
node _T_1 = eq(_T, UInt<1>(0h0))
when _T_1 :
connect in.in3, zero
inst fma of MulAddRecFNPipe_l2_e11_s53_3
connect fma.clock, clock
connect fma.reset, reset
connect fma.io.validin, valid
connect fma.io.op, in.fmaCmd
connect fma.io.roundingMode, in.rm
connect fma.io.detectTininess, UInt<1>(0h1)
connect fma.io.a, in.in1
connect fma.io.b, in.in2
connect fma.io.c, in.in3
wire res : { data : UInt<65>, exc : UInt<5>}
node _res_data_maskedNaN_T = not(UInt<65>(0h1010000000000000))
node res_data_maskedNaN = and(fma.io.out, _res_data_maskedNaN_T)
node _res_data_T = bits(fma.io.out, 63, 61)
node _res_data_T_1 = andr(_res_data_T)
node _res_data_T_2 = mux(_res_data_T_1, res_data_maskedNaN, fma.io.out)
connect res.data, _res_data_T_2
connect res.exc, fma.io.exceptionFlags
regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_v, fma.io.validout
reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock
when fma.io.validout :
connect io_out_pipe_b, res
wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}
connect io_out_pipe_out.valid, io_out_pipe_v
connect io_out_pipe_out.bits, io_out_pipe_b
connect io.out, io_out_pipe_out | module FPUFMAPipe_l4_f64_3( // @[FPU.scala:697:7]
input clock, // @[FPU.scala:697:7]
input reset, // @[FPU.scala:697:7]
input io_in_valid, // @[FPU.scala:702:14]
input io_in_bits_ldst, // @[FPU.scala:702:14]
input io_in_bits_wen, // @[FPU.scala:702:14]
input io_in_bits_ren1, // @[FPU.scala:702:14]
input io_in_bits_ren2, // @[FPU.scala:702:14]
input io_in_bits_ren3, // @[FPU.scala:702:14]
input io_in_bits_swap12, // @[FPU.scala:702:14]
input io_in_bits_swap23, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14]
input io_in_bits_fromint, // @[FPU.scala:702:14]
input io_in_bits_toint, // @[FPU.scala:702:14]
input io_in_bits_fastpipe, // @[FPU.scala:702:14]
input io_in_bits_fma, // @[FPU.scala:702:14]
input io_in_bits_div, // @[FPU.scala:702:14]
input io_in_bits_sqrt, // @[FPU.scala:702:14]
input io_in_bits_wflags, // @[FPU.scala:702:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:702:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:702:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:702:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:702:14]
output io_out_valid, // @[FPU.scala:702:14]
output [64:0] io_out_bits_data, // @[FPU.scala:702:14]
output [4:0] io_out_bits_exc // @[FPU.scala:702:14]
);
wire [64:0] _fma_io_out; // @[FPU.scala:719:19]
wire _fma_io_validout; // @[FPU.scala:719:19]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7]
wire [63:0] one = 64'h8000000000000000; // @[FPU.scala:710:19]
wire [64:0] _zero_T_1 = 65'h10000000000000000; // @[FPU.scala:711:57]
wire [64:0] _res_data_maskedNaN_T = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27]
wire io_in_bits_vec = 1'h0; // @[FPU.scala:697:7]
wire io_out_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7]
wire io_out_valid_0; // @[FPU.scala:697:7]
reg valid; // @[FPU.scala:707:22]
reg in_ldst; // @[FPU.scala:708:15]
reg in_wen; // @[FPU.scala:708:15]
reg in_ren1; // @[FPU.scala:708:15]
reg in_ren2; // @[FPU.scala:708:15]
reg in_ren3; // @[FPU.scala:708:15]
reg in_swap12; // @[FPU.scala:708:15]
reg in_swap23; // @[FPU.scala:708:15]
reg [1:0] in_typeTagIn; // @[FPU.scala:708:15]
reg [1:0] in_typeTagOut; // @[FPU.scala:708:15]
reg in_fromint; // @[FPU.scala:708:15]
reg in_toint; // @[FPU.scala:708:15]
reg in_fastpipe; // @[FPU.scala:708:15]
reg in_fma; // @[FPU.scala:708:15]
reg in_div; // @[FPU.scala:708:15]
reg in_sqrt; // @[FPU.scala:708:15]
reg in_wflags; // @[FPU.scala:708:15]
reg [2:0] in_rm; // @[FPU.scala:708:15]
reg [1:0] in_fmaCmd; // @[FPU.scala:708:15]
reg [1:0] in_typ; // @[FPU.scala:708:15]
reg [1:0] in_fmt; // @[FPU.scala:708:15]
reg [64:0] in_in1; // @[FPU.scala:708:15]
reg [64:0] in_in2; // @[FPU.scala:708:15]
reg [64:0] in_in3; // @[FPU.scala:708:15]
wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32]
wire [64:0] zero = _zero_T & 65'h10000000000000000; // @[FPU.scala:711:{32,50}]
wire [64:0] _res_data_T_2; // @[FPU.scala:414:10]
wire [64:0] res_data; // @[FPU.scala:728:17]
wire [4:0] res_exc; // @[FPU.scala:728:17]
wire [64:0] res_data_maskedNaN = _fma_io_out & 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:25, :719:19]
wire [2:0] _res_data_T = _fma_io_out[63:61]; // @[FPU.scala:249:25, :719:19]
wire _res_data_T_1 = &_res_data_T; // @[FPU.scala:249:{25,56}]
assign _res_data_T_2 = _res_data_T_1 ? res_data_maskedNaN : _fma_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :719:19]
assign res_data = _res_data_T_2; // @[FPU.scala:414:10, :728:17]
reg io_out_pipe_v; // @[Valid.scala:141:24]
assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26]
reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26]
assign io_out_valid_0 = io_out_pipe_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:697:7]
valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22]
if (io_in_valid_0) begin // @[FPU.scala:697:7]
in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15]
in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15]
in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15]
in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15]
in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15]
in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15]
in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15]
in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15]
in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15]
in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15]
in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15]
in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15]
in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15]
in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15]
in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15]
in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15]
in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15]
in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15]
in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15]
in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15]
in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15]
in_in2 <= io_in_bits_swap23_0 ? 65'h8000000000000000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}]
in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}]
end
if (_fma_io_validout) begin // @[FPU.scala:719:19]
io_out_pipe_b_data <= res_data; // @[Valid.scala:142:26]
io_out_pipe_b_exc <= res_exc; // @[Valid.scala:142:26]
end
if (reset) // @[FPU.scala:697:7]
io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
else // @[FPU.scala:697:7]
io_out_pipe_v <= _fma_io_validout; // @[Valid.scala:141:24]
always @(posedge)
MulAddRecFNPipe_l2_e11_s53_3 fma ( // @[FPU.scala:719:19]
.clock (clock),
.reset (reset),
.io_validin (valid), // @[FPU.scala:707:22]
.io_op (in_fmaCmd), // @[FPU.scala:708:15]
.io_a (in_in1), // @[FPU.scala:708:15]
.io_b (in_in2), // @[FPU.scala:708:15]
.io_c (in_in3), // @[FPU.scala:708:15]
.io_roundingMode (in_rm), // @[FPU.scala:708:15]
.io_out (_fma_io_out),
.io_exceptionFlags (res_exc),
.io_validout (_fma_io_validout)
); // @[FPU.scala:719:19]
assign io_out_valid = io_out_valid_0; // @[FPU.scala:697:7]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DigitalTop :
output auto : { flip chipyard_prcictrl_domain_reset_setter_clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, mbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}, cbus_fixedClockNode_anon_out : { clock : Clock, reset : Reset}}
output psd : { }
output resetctrl : { flip hartIsInReset : UInt<1>[1]}
output debug : { flip clock : Clock, flip reset : Reset, systemjtag : { flip jtag : { TCK : Clock, TMS : UInt<1>, TDI : UInt<1>, flip TDO : { data : UInt<1>, driven : UInt<1>}}, flip reset : Reset, flip mfr_id : UInt<11>, flip part_number : UInt<16>, flip version : UInt<4>}, ndreset : UInt<1>, dmactive : UInt<1>, flip dmactiveAck : UInt<1>}
output mem_tl : { }
output mem_axi4 : { `0` : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}}
output mmio_axi4 : { }
input l2_frontend_bus_axi4 : { }
input custom_boot : UInt<1>
output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock}
output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>}
output uart_0 : { txd : UInt<1>, flip rxd : UInt<1>}
output clock_tap : Clock
input interrupts : UInt<0>
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst ibus of ClockSinkDomain
inst sbus of SystemBus
inst pbus of PeripheryBus_pbus
inst fbus of FrontBus
inst cbus of PeripheryBus_cbus
inst mbus of MemoryBus
inst coh_wrapper of CoherenceManagerWrapper
inst tile_prci_domain of TilePRCIDomain
inst xbar of IntXbar_i1_o1_1
inst xbar_1 of IntXbar_i1_o1_2
inst xbar_2 of IntXbar_i1_o1_3
inst tileHartIdNexusNode of BundleBridgeNexus_UInt1_1
inst broadcast of BundleBridgeNexus_UInt32_1
inst clint_domain of CLINTClockSinkDomain
inst plic_domain of PLICClockSinkDomain
inst tlDM of TLDebugModule
inst debugCustomXbarOpt of DebugCustomXbar
inst nexus of BundleBridgeNexus_TraceBundle
inst nexus_1 of BundleBridgeNexus_TraceCoreInterface
inst bootrom_domain of BootROMClockSinkDomain
inst bank of ScratchpadBank
inst serial_tl_domain of SerialTL0ClockSinkDomain
inst uartClockDomainWrapper of TLUARTClockSinkDomain
inst intsink of IntSyncSyncCrossingSink_n1x1_5
inst streaming_passthrough_domain of ClockSinkDomain_1
inst chipyard_prcictrl_domain of ChipyardPRCICtrlClockSinkDomain
inst aggregator of ClockGroupAggregator_allClocks
inst clockNamePrefixer of ClockGroupParameterModifier
inst frequencySpecifier of ClockGroupParameterModifier_1
inst clockGroupCombiner of ClockGroupCombiner
inst clockTapNode of ClockGroup_6
inst globalNoCDomain of ClockSinkDomain_2
inst reRoCCManagerIdNexusNode of BundleBridgeNexus_NoOutput_8
wire allClockGroupsNodeOut : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}
invalidate allClockGroupsNodeOut.member.sbus_0.reset
invalidate allClockGroupsNodeOut.member.sbus_0.clock
invalidate allClockGroupsNodeOut.member.sbus_1.reset
invalidate allClockGroupsNodeOut.member.sbus_1.clock
wire x1_allClockGroupsNodeOut : { member : { pbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut.member.pbus_0.reset
invalidate x1_allClockGroupsNodeOut.member.pbus_0.clock
wire x1_allClockGroupsNodeOut_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.reset
invalidate x1_allClockGroupsNodeOut_1.member.fbus_0.clock
wire x1_allClockGroupsNodeOut_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.reset
invalidate x1_allClockGroupsNodeOut_2.member.mbus_0.clock
wire x1_allClockGroupsNodeOut_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.reset
invalidate x1_allClockGroupsNodeOut_3.member.cbus_0.clock
wire x1_allClockGroupsNodeOut_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.reset
invalidate x1_allClockGroupsNodeOut_4.member.clockTapNode_clock_tap.clock
wire allClockGroupsNodeIn : { member : { sbus_1 : { clock : Clock, reset : Reset}, sbus_0 : { clock : Clock, reset : Reset}}}
invalidate allClockGroupsNodeIn.member.sbus_0.reset
invalidate allClockGroupsNodeIn.member.sbus_0.clock
invalidate allClockGroupsNodeIn.member.sbus_1.reset
invalidate allClockGroupsNodeIn.member.sbus_1.clock
wire x1_allClockGroupsNodeIn : { member : { pbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn.member.pbus_0.reset
invalidate x1_allClockGroupsNodeIn.member.pbus_0.clock
wire x1_allClockGroupsNodeIn_1 : { member : { fbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.reset
invalidate x1_allClockGroupsNodeIn_1.member.fbus_0.clock
wire x1_allClockGroupsNodeIn_2 : { member : { mbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.reset
invalidate x1_allClockGroupsNodeIn_2.member.mbus_0.clock
wire x1_allClockGroupsNodeIn_3 : { member : { cbus_0 : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.reset
invalidate x1_allClockGroupsNodeIn_3.member.cbus_0.clock
wire x1_allClockGroupsNodeIn_4 : { member : { clockTapNode_clock_tap : { clock : Clock, reset : Reset}}}
invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.reset
invalidate x1_allClockGroupsNodeIn_4.member.clockTapNode_clock_tap.clock
connect allClockGroupsNodeOut, allClockGroupsNodeIn
connect x1_allClockGroupsNodeOut, x1_allClockGroupsNodeIn
connect x1_allClockGroupsNodeOut_1, x1_allClockGroupsNodeIn_1
connect x1_allClockGroupsNodeOut_2, x1_allClockGroupsNodeIn_2
connect x1_allClockGroupsNodeOut_3, x1_allClockGroupsNodeIn_3
connect x1_allClockGroupsNodeOut_4, x1_allClockGroupsNodeIn_4
wire tileHaltSinkNodeIn : UInt<1>[1]
invalidate tileHaltSinkNodeIn[0]
wire tileWFISinkNodeIn : UInt<1>[1]
invalidate tileWFISinkNodeIn[0]
wire tileCeaseSinkNodeIn : UInt<1>[1]
invalidate tileCeaseSinkNodeIn[0]
wire domainIn : { clock : Clock, reset : Reset}
invalidate domainIn.reset
invalidate domainIn.clock
wire debugNodesOut : { sync : UInt<1>[1]}
invalidate debugNodesOut.sync[0]
wire debugNodesIn : { sync : UInt<1>[1]}
invalidate debugNodesIn.sync[0]
connect debugNodesOut, debugNodesIn
wire traceCoreNodesIn : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreNodesIn.cause
invalidate traceCoreNodesIn.tval
invalidate traceCoreNodesIn.priv
invalidate traceCoreNodesIn.group[0].ilastsize
invalidate traceCoreNodesIn.group[0].itype
invalidate traceCoreNodesIn.group[0].iaddr
invalidate traceCoreNodesIn.group[0].iretire
wire traceNodesIn : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}
invalidate traceNodesIn.time
invalidate traceNodesIn.insns[0].tval
invalidate traceNodesIn.insns[0].cause
invalidate traceNodesIn.insns[0].interrupt
invalidate traceNodesIn.insns[0].exception
invalidate traceNodesIn.insns[0].priv
invalidate traceNodesIn.insns[0].insn
invalidate traceNodesIn.insns[0].iaddr
invalidate traceNodesIn.insns[0].valid
wire memAXI4NodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate memAXI4NodeIn.r.bits.last
invalidate memAXI4NodeIn.r.bits.resp
invalidate memAXI4NodeIn.r.bits.data
invalidate memAXI4NodeIn.r.bits.id
invalidate memAXI4NodeIn.r.valid
invalidate memAXI4NodeIn.r.ready
invalidate memAXI4NodeIn.ar.bits.qos
invalidate memAXI4NodeIn.ar.bits.prot
invalidate memAXI4NodeIn.ar.bits.cache
invalidate memAXI4NodeIn.ar.bits.lock
invalidate memAXI4NodeIn.ar.bits.burst
invalidate memAXI4NodeIn.ar.bits.size
invalidate memAXI4NodeIn.ar.bits.len
invalidate memAXI4NodeIn.ar.bits.addr
invalidate memAXI4NodeIn.ar.bits.id
invalidate memAXI4NodeIn.ar.valid
invalidate memAXI4NodeIn.ar.ready
invalidate memAXI4NodeIn.b.bits.resp
invalidate memAXI4NodeIn.b.bits.id
invalidate memAXI4NodeIn.b.valid
invalidate memAXI4NodeIn.b.ready
invalidate memAXI4NodeIn.w.bits.last
invalidate memAXI4NodeIn.w.bits.strb
invalidate memAXI4NodeIn.w.bits.data
invalidate memAXI4NodeIn.w.valid
invalidate memAXI4NodeIn.w.ready
invalidate memAXI4NodeIn.aw.bits.qos
invalidate memAXI4NodeIn.aw.bits.prot
invalidate memAXI4NodeIn.aw.bits.cache
invalidate memAXI4NodeIn.aw.bits.lock
invalidate memAXI4NodeIn.aw.bits.burst
invalidate memAXI4NodeIn.aw.bits.size
invalidate memAXI4NodeIn.aw.bits.len
invalidate memAXI4NodeIn.aw.bits.addr
invalidate memAXI4NodeIn.aw.bits.id
invalidate memAXI4NodeIn.aw.valid
invalidate memAXI4NodeIn.aw.ready
wire bootROMResetVectorSourceNodeOut : UInt<32>
invalidate bootROMResetVectorSourceNodeOut
wire intXingOut : { sync : UInt<1>[1]}
invalidate intXingOut.sync[0]
wire intXingIn : { sync : UInt<1>[1]}
invalidate intXingIn.sync[0]
connect intXingOut, intXingIn
wire ioNodeIn : { txd : UInt<1>, flip rxd : UInt<1>}
invalidate ioNodeIn.rxd
invalidate ioNodeIn.txd
wire clockTapIn : { clock : Clock, reset : Reset}
invalidate clockTapIn.reset
invalidate clockTapIn.clock
connect plic_domain.auto.plic_int_in[0], ibus.auto.int_bus_anon_out[0]
connect sbus.auto.sbus_clock_groups_in, allClockGroupsNodeOut
connect pbus.auto.pbus_clock_groups_in, x1_allClockGroupsNodeOut
connect fbus.auto.fbus_clock_groups_in, x1_allClockGroupsNodeOut_1
connect mbus.auto.mbus_clock_groups_in, x1_allClockGroupsNodeOut_2
connect cbus.auto.cbus_clock_groups_in, x1_allClockGroupsNodeOut_3
connect clockTapNode.auto.in, x1_allClockGroupsNodeOut_4
connect coh_wrapper.auto.coh_clock_groups_in, sbus.auto.sbus_clock_groups_out
connect ibus.auto.clock_in, sbus.auto.fixedClockNode_anon_out_0
connect tile_prci_domain.auto.tap_clock_in, sbus.auto.fixedClockNode_anon_out_1
connect globalNoCDomain.auto.clock_in, sbus.auto.fixedClockNode_anon_out_2
connect uartClockDomainWrapper.auto.clock_in, pbus.auto.fixedClockNode_anon_out_0
connect streaming_passthrough_domain.auto.clock_in, pbus.auto.fixedClockNode_anon_out_1
connect serial_tl_domain.auto.clock_in, fbus.auto.fixedClockNode_anon_out
connect clint_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_0
connect plic_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_1
connect domainIn, cbus.auto.fixedClockNode_anon_out_2
connect bootrom_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_3
connect chipyard_prcictrl_domain.auto.clock_in, cbus.auto.fixedClockNode_anon_out_4
connect bank.auto.clock_in, mbus.auto.fixedClockNode_anon_out_0
connect coh_wrapper.auto.l2_ctrls_ctrl_in, cbus.auto.coupler_to_l2_ctrl_buffer_out
connect cbus.auto.bus_xing_in, sbus.auto.coupler_to_bus_named_cbus_bus_xing_out
connect pbus.auto.bus_xing_in, cbus.auto.coupler_to_bus_named_pbus_bus_xing_out
connect sbus.auto.coupler_from_bus_named_fbus_bus_xing_in, fbus.auto.bus_xing_out
connect coh_wrapper.auto.coherent_jbar_anon_in, sbus.auto.coupler_to_bus_named_coh_widget_anon_out
connect mbus.auto.bus_xing_in, coh_wrapper.auto.coupler_to_bus_named_mbus_bus_xing_out
connect nexus.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_source_out
connect nexus_1.auto.in, tile_prci_domain.auto.element_reset_domain_rockettile_trace_core_source_out
connect tileHaltSinkNodeIn, xbar.auto.anon_out
connect tileWFISinkNodeIn, xbar_1.auto.anon_out
connect tileCeaseSinkNodeIn, xbar_2.auto.anon_out
connect tile_prci_domain.auto.element_reset_domain_rockettile_hartid_in, tileHartIdNexusNode.auto.out
connect tile_prci_domain.auto.element_reset_domain_rockettile_reset_vector_in, broadcast.auto.out
connect clint_domain.auto.clint_in, cbus.auto.coupler_to_clint_fragmenter_anon_out
connect plic_domain.auto.plic_in, cbus.auto.coupler_to_plic_fragmenter_anon_out
connect debugNodesIn, tlDM.auto.dmOuter_int_out
connect fbus.auto.coupler_from_debug_sb_widget_anon_in, tlDM.auto.dmInner_dmInner_sb2tlOpt_out
connect tlDM.auto.dmInner_dmInner_tl_in, cbus.auto.coupler_to_debug_fragmenter_anon_out
connect tlDM.auto.dmInner_dmInner_custom_in, debugCustomXbarOpt.auto.out
connect tile_prci_domain.auto.intsink_in.sync[0], debugNodesOut.sync[0]
connect sbus.auto.coupler_from_rockettile_tl_master_clock_xing_in, tile_prci_domain.auto.tl_master_clock_xing_out
connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[0], clint_domain.auto.int_in_clock_xing_out.sync[0]
connect tile_prci_domain.auto.int_in_clock_xing_in_0.sync[1], clint_domain.auto.int_in_clock_xing_out.sync[1]
connect tile_prci_domain.auto.int_in_clock_xing_in_1.sync[0], plic_domain.auto.int_in_clock_xing_out_0.sync[0]
connect tile_prci_domain.auto.int_in_clock_xing_in_2.sync[0], plic_domain.auto.int_in_clock_xing_out_1.sync[0]
connect xbar.auto.anon_in[0], tile_prci_domain.auto.intsink_out_0[0]
connect xbar_1.auto.anon_in[0], tile_prci_domain.auto.intsink_out_1[0]
connect xbar_2.auto.anon_in[0], tile_prci_domain.auto.intsink_out_2[0]
connect traceNodesIn, nexus.auto.out
connect traceCoreNodesIn, nexus_1.auto.out
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.r, memAXI4NodeIn.r
connect memAXI4NodeIn.ar.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.bits
connect memAXI4NodeIn.ar.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.ar.ready, memAXI4NodeIn.ar.ready
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.b, memAXI4NodeIn.b
connect memAXI4NodeIn.w.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.bits
connect memAXI4NodeIn.w.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.w.ready, memAXI4NodeIn.w.ready
connect memAXI4NodeIn.aw.bits, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.bits
connect memAXI4NodeIn.aw.valid, mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.valid
connect mbus.auto.coupler_to_memory_controller_port_named_axi4_axi4yank_out.aw.ready, memAXI4NodeIn.aw.ready
connect broadcast.auto.in, bootROMResetVectorSourceNodeOut
connect bootrom_domain.auto.bootrom_in, cbus.auto.coupler_to_bootrom_fragmenter_anon_out
connect bank.auto.xbar_anon_in, mbus.auto.buffer_out
connect fbus.auto.coupler_from_port_named_serial_tl_0_in_buffer_in, serial_tl_domain.auto.serdesser_client_out
connect uartClockDomainWrapper.auto.uart_0_io_out.rxd, ioNodeIn.rxd
connect ioNodeIn.txd, uartClockDomainWrapper.auto.uart_0_io_out.txd
connect uartClockDomainWrapper.auto.uart_0_control_xing_in, pbus.auto.coupler_to_device_named_uart_0_control_xing_out
connect ibus.auto.int_bus_anon_in[0], intsink.auto.out[0]
connect intsink.auto.in.sync[0], intXingOut.sync[0]
connect intXingIn, uartClockDomainWrapper.auto.uart_0_int_xing_out
connect streaming_passthrough_domain.auto.fragmenter_anon_in, pbus.auto.coupler_to_streamingPassthrough_tl_out
connect chipyard_prcictrl_domain.auto.xbar_anon_in, cbus.auto.coupler_to_prci_ctrl_fixer_anon_out
connect clockNamePrefixer.auto.clock_name_prefixer_in_0, aggregator.auto.out_0
connect clockNamePrefixer.auto.clock_name_prefixer_in_1, aggregator.auto.out_1
connect clockNamePrefixer.auto.clock_name_prefixer_in_2, aggregator.auto.out_2
connect clockNamePrefixer.auto.clock_name_prefixer_in_3, aggregator.auto.out_3
connect clockNamePrefixer.auto.clock_name_prefixer_in_4, aggregator.auto.out_4
connect clockNamePrefixer.auto.clock_name_prefixer_in_5, aggregator.auto.out_5
connect allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_0
connect x1_allClockGroupsNodeIn, clockNamePrefixer.auto.clock_name_prefixer_out_1
connect x1_allClockGroupsNodeIn_1, clockNamePrefixer.auto.clock_name_prefixer_out_2
connect x1_allClockGroupsNodeIn_2, clockNamePrefixer.auto.clock_name_prefixer_out_3
connect x1_allClockGroupsNodeIn_3, clockNamePrefixer.auto.clock_name_prefixer_out_4
connect x1_allClockGroupsNodeIn_4, clockNamePrefixer.auto.clock_name_prefixer_out_5
connect aggregator.auto.in, frequencySpecifier.auto.frequency_specifier_out
connect frequencySpecifier.auto.frequency_specifier_in, clockGroupCombiner.auto.clock_group_combiner_out
connect clockGroupCombiner.auto.clock_group_combiner_in, chipyard_prcictrl_domain.auto.resetSynchronizer_out
connect clockTapIn, clockTapNode.auto.out
connect auto.cbus_fixedClockNode_anon_out, cbus.auto.fixedClockNode_anon_out_5
connect auto.mbus_fixedClockNode_anon_out, mbus.auto.fixedClockNode_anon_out_1
connect chipyard_prcictrl_domain.auto.reset_setter_clock_in, auto.chipyard_prcictrl_domain_reset_setter_clock_in
connect tlDM.io.tl_reset, domainIn.reset
connect tlDM.io.tl_clock, domainIn.clock
connect tlDM.io.hartIsInReset[0], resetctrl.hartIsInReset[0]
connect tlDM.io.debug_reset, debug.reset
connect tlDM.io.debug_clock, debug.clock
connect debug.ndreset, tlDM.io.ctrl.ndreset
connect debug.dmactive, tlDM.io.ctrl.dmactive
connect tlDM.io.ctrl.dmactiveAck, debug.dmactiveAck
connect tlDM.io.ctrl.debugUnavail[0], UInt<1>(0h0)
inst dtm of DebugTransportModuleJTAG
connect dtm.io.jtag, debug.systemjtag.jtag
connect dtm.io.jtag_clock, debug.systemjtag.jtag.TCK
connect dtm.io.jtag_reset, debug.systemjtag.reset
connect dtm.io.jtag_mfr_id, debug.systemjtag.mfr_id
connect dtm.io.jtag_part_number, debug.systemjtag.part_number
connect dtm.io.jtag_version, debug.systemjtag.version
connect dtm.rf_reset, debug.systemjtag.reset
connect tlDM.io.dmi.dmi, dtm.io.dmi
connect tlDM.io.dmi.dmiClock, debug.systemjtag.jtag.TCK
connect tlDM.io.dmi.dmiReset, debug.systemjtag.reset
connect mem_axi4.`0`, memAXI4NodeIn
connect bootROMResetVectorSourceNodeOut, UInt<17>(0h10000)
connect cbus.custom_boot, custom_boot
connect serial_tl_domain.serial_tl_0.clock_in, serial_tl_0.clock_in
connect serial_tl_0.out.bits, serial_tl_domain.serial_tl_0.out.bits
connect serial_tl_0.out.valid, serial_tl_domain.serial_tl_0.out.valid
connect serial_tl_domain.serial_tl_0.out.ready, serial_tl_0.out.ready
connect serial_tl_domain.serial_tl_0.in, serial_tl_0.in
connect serial_tl_0_debug, serial_tl_domain.serial_tl_0_debug
connect uart_0, ioNodeIn
connect clock_tap, clockTapIn.clock
regreset int_rtc_tick_c_value : UInt<10>, clint_domain.clock, clint_domain.reset, UInt<10>(0h0)
wire int_rtc_tick : UInt<1>
connect int_rtc_tick, UInt<1>(0h0)
when UInt<1>(0h1) :
node int_rtc_tick_wrap_wrap = eq(int_rtc_tick_c_value, UInt<10>(0h3e7))
node _int_rtc_tick_wrap_value_T = add(int_rtc_tick_c_value, UInt<1>(0h1))
node _int_rtc_tick_wrap_value_T_1 = tail(_int_rtc_tick_wrap_value_T, 1)
connect int_rtc_tick_c_value, _int_rtc_tick_wrap_value_T_1
when int_rtc_tick_wrap_wrap :
connect int_rtc_tick_c_value, UInt<1>(0h0)
connect int_rtc_tick, int_rtc_tick_wrap_wrap
connect clint_domain.tick, int_rtc_tick
extmodule GenericDigitalInIOCell :
input pad : UInt<1>
output i : UInt<1>
input ie : UInt<1>
defname = GenericDigitalInIOCell
extmodule GenericDigitalOutIOCell :
output pad : UInt<1>
input o : UInt<1>
input oe : UInt<1>
defname = GenericDigitalOutIOCell
extmodule GenericDigitalInIOCell_1 :
input pad : UInt<1>
output i : UInt<1>
input ie : UInt<1>
defname = GenericDigitalInIOCell | module DigitalTop( // @[DigitalTop.scala:47:7]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25]
input debug_clock, // @[Periphery.scala:125:19]
input debug_reset, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19]
output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19]
input debug_systemjtag_reset, // @[Periphery.scala:125:19]
output debug_dmactive, // @[Periphery.scala:125:19]
input debug_dmactiveAck, // @[Periphery.scala:125:19]
input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21]
output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21]
output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21]
output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21]
input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21]
output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21]
output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21]
output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21]
input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21]
input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21]
input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21]
input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21]
output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21]
output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21]
output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21]
output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21]
output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21]
output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21]
output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21]
output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21]
input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21]
input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21]
input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21]
input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21]
input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21]
input custom_boot, // @[CustomBootPin.scala:73:27]
output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24]
input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24]
output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24]
output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24]
output uart_0_txd, // @[BundleBridgeSink.scala:25:19]
input uart_0_rxd, // @[BundleBridgeSink.scala:25:19]
output clock_tap // @[CanHaveClockTap.scala:23:23]
);
wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21]
wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21]
wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21]
wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21]
wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15]
wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15]
wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30]
wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _streaming_passthrough_domain_auto_fragmenter_anon_in_a_ready; // @[BusWrapper.scala:89:28]
wire _streaming_passthrough_domain_auto_fragmenter_anon_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _streaming_passthrough_domain_auto_fragmenter_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [2:0] _streaming_passthrough_domain_auto_fragmenter_anon_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [6:0] _streaming_passthrough_domain_auto_fragmenter_anon_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _streaming_passthrough_domain_auto_fragmenter_anon_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _intsink_auto_out_0; // @[Crossing.scala:109:29]
wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44]
wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44]
wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44]
wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44]
wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44]
wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38]
wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38]
wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38]
wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38]
wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28]
wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28]
wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28]
wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28]
wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28]
wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28]
wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28]
wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28]
wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28]
wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26]
wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26]
wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26]
wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26]
wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmOuter_int_out_sync_0; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26]
wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28]
wire _clint_domain_clock; // @[BusWrapper.scala:89:28]
wire _clint_domain_reset; // @[BusWrapper.scala:89:28]
wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38]
wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38]
wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38]
wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38]
wire [1:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38]
wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31]
wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [5:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31]
wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31]
wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31]
wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31]
wire [10:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31]
wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31]
wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26]
wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26]
wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26]
wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26]
wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26]
wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26]
wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26]
wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26]
wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26]
wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26]
wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26]
wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26]
wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26]
wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26]
wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26]
wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26]
wire _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [13:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_streamingPassthrough_tl_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_streamingPassthrough_tl_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26]
wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26]
wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27]
reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40]
wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24]
always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28]
if (_clint_domain_reset) // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40]
else // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 :
input clock : Clock
input reset : Reset
output auto : { flip widget_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, axi4yank_out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst axi4yank of AXI4UserYanker
connect axi4yank.clock, clock
connect axi4yank.reset, reset
inst axi4index of AXI4IdIndexer
connect axi4index.clock, clock
connect axi4index.reset, reset
inst tl2axi4 of TLToAXI4
connect tl2axi4.clock, clock
connect tl2axi4.reset, reset
inst widget of TLWidthWidget8_6
connect widget.clock, clock
connect widget.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect axi4yank.auto.in, axi4index.auto.out
connect axi4index.auto.in, tl2axi4.auto.out
connect tl2axi4.auto.in, widget.auto.anon_out
connect auto.tl_out, tlOut
connect tlIn, auto.tl_in
connect axi4yank.auto.out.r, auto.axi4yank_out.r
connect auto.axi4yank_out.ar.bits, axi4yank.auto.out.ar.bits
connect auto.axi4yank_out.ar.valid, axi4yank.auto.out.ar.valid
connect axi4yank.auto.out.ar.ready, auto.axi4yank_out.ar.ready
connect axi4yank.auto.out.b, auto.axi4yank_out.b
connect auto.axi4yank_out.w.bits, axi4yank.auto.out.w.bits
connect auto.axi4yank_out.w.valid, axi4yank.auto.out.w.valid
connect axi4yank.auto.out.w.ready, auto.axi4yank_out.w.ready
connect auto.axi4yank_out.aw.bits, axi4yank.auto.out.aw.bits
connect auto.axi4yank_out.aw.valid, axi4yank.auto.out.aw.valid
connect axi4yank.auto.out.aw.ready, auto.axi4yank_out.aw.ready
connect widget.auto.anon_in, auto.widget_anon_in | module TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_widget_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_widget_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_widget_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_widget_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_widget_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_widget_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_widget_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_widget_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_widget_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_widget_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_widget_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire _tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala:301:29]
wire [31:0] _tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_aw_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_w_valid; // @[ToAXI4.scala:301:29]
wire [63:0] _tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_b_ready; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala:301:29]
wire [31:0] _tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala:301:29]
wire [7:0] _tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala:301:29]
wire [1:0] _tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala:301:29]
wire [2:0] _tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_size; // @[ToAXI4.scala:301:29]
wire [3:0] _tl2axi4_auto_out_ar_bits_echo_tl_state_source; // @[ToAXI4.scala:301:29]
wire _tl2axi4_auto_out_r_ready; // @[ToAXI4.scala:301:29]
wire _axi4index_auto_in_aw_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_w_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_b_valid; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_b_bits_id; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_b_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_b_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_ar_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_r_valid; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_r_bits_id; // @[IdIndexer.scala:108:31]
wire [63:0] _axi4index_auto_in_r_bits_data; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_r_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_in_r_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_in_r_bits_last; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_aw_valid; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala:108:31]
wire [31:0] _axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_aw_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_w_valid; // @[IdIndexer.scala:108:31]
wire [63:0] _axi4index_auto_out_w_bits_data; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_w_bits_last; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_b_ready; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_ar_valid; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala:108:31]
wire [31:0] _axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala:108:31]
wire [7:0] _axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala:108:31]
wire [1:0] _axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala:108:31]
wire [2:0] _axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_echo_tl_state_size; // @[IdIndexer.scala:108:31]
wire [3:0] _axi4index_auto_out_ar_bits_echo_tl_state_source; // @[IdIndexer.scala:108:31]
wire _axi4index_auto_out_r_ready; // @[IdIndexer.scala:108:31]
wire _axi4yank_auto_in_aw_ready; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_w_ready; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_b_valid; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_b_bits_id; // @[UserYanker.scala:125:30]
wire [1:0] _axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_b_bits_echo_tl_state_size; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_b_bits_echo_tl_state_source; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_ar_ready; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_r_valid; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_r_bits_id; // @[UserYanker.scala:125:30]
wire [63:0] _axi4yank_auto_in_r_bits_data; // @[UserYanker.scala:125:30]
wire [1:0] _axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_r_bits_echo_tl_state_size; // @[UserYanker.scala:125:30]
wire [3:0] _axi4yank_auto_in_r_bits_echo_tl_state_source; // @[UserYanker.scala:125:30]
wire _axi4yank_auto_in_r_bits_last; // @[UserYanker.scala:125:30]
wire auto_widget_anon_in_a_valid_0 = auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_opcode_0 = auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_param_0 = auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_a_bits_size_0 = auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_in_a_bits_source_0 = auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_widget_anon_in_a_bits_address_0 = auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_widget_anon_in_a_bits_mask_0 = auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_widget_anon_in_a_bits_data_0 = auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_a_bits_corrupt_0 = auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_ready_0 = auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_aw_ready_0 = auto_axi4yank_out_aw_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_w_ready_0 = auto_axi4yank_out_w_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_b_valid_0 = auto_axi4yank_out_b_valid; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_b_bits_id_0 = auto_axi4yank_out_b_bits_id; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_b_bits_resp_0 = auto_axi4yank_out_b_bits_resp; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_ar_ready_0 = auto_axi4yank_out_ar_ready; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_r_valid_0 = auto_axi4yank_out_r_valid; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_r_bits_id_0 = auto_axi4yank_out_r_bits_id; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_axi4yank_out_r_bits_data_0 = auto_axi4yank_out_r_bits_data; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_r_bits_resp_0 = auto_axi4yank_out_r_bits_resp; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_r_bits_last_0 = auto_axi4yank_out_r_bits_last; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_source_0 = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire auto_tl_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire auto_tl_out_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_out_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_anonOut_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_anonIn_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire tlOut_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire tlIn_d_bits_sink = 1'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] auto_widget_anon_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] auto_tl_out_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] widget_auto_anon_out_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] widget_anonOut_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] widget_anonIn_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] tlOut_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire [1:0] tlIn_d_bits_param = 2'h0; // @[WidthWidget.scala:27:9, :230:28]
wire widget_auto_anon_in_a_valid = auto_widget_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode = auto_widget_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param = auto_widget_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_size = auto_widget_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_source = auto_widget_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address = auto_widget_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_a_bits_mask = auto_widget_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_a_bits_data = auto_widget_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_bits_corrupt = auto_widget_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready = auto_widget_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire tlIn_a_ready; // @[MixedNode.scala:551:17]
wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [3:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [31:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_source = auto_tl_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_aw_bits_id_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_axi4yank_out_aw_bits_addr_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_axi4yank_out_aw_bits_len_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_aw_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_aw_bits_burst_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_aw_bits_lock_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_aw_bits_cache_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_aw_bits_prot_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_aw_bits_qos_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_aw_valid_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_axi4yank_out_w_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_axi4yank_out_w_bits_strb_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_w_bits_last_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_w_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_b_ready_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_ar_bits_id_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_axi4yank_out_ar_bits_addr_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_axi4yank_out_ar_bits_len_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_ar_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_axi4yank_out_ar_bits_burst_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_ar_bits_lock_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_ar_bits_cache_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_axi4yank_out_ar_bits_prot_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_axi4yank_out_ar_bits_qos_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_ar_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_axi4yank_out_r_ready_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_a_ready_0 = widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_bits_corrupt = widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_valid_0 = widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_opcode_0 = widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_size_0 = widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_source_0 = widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_denied_0 = widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_data_0 = widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_widget_anon_in_d_bits_corrupt_0 = widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_corrupt = widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_corrupt = widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_param_0 = tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_source_0 = tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17]
assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
AXI4UserYanker axi4yank ( // @[UserYanker.scala:125:30]
.clock (clock),
.reset (reset),
.auto_in_aw_ready (_axi4yank_auto_in_aw_ready),
.auto_in_aw_valid (_axi4index_auto_out_aw_valid), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_id (_axi4index_auto_out_aw_bits_id), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_addr (_axi4index_auto_out_aw_bits_addr), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_len (_axi4index_auto_out_aw_bits_len), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_size (_axi4index_auto_out_aw_bits_size), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_burst (_axi4index_auto_out_aw_bits_burst), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_lock (_axi4index_auto_out_aw_bits_lock), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_cache (_axi4index_auto_out_aw_bits_cache), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_prot (_axi4index_auto_out_aw_bits_prot), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_qos (_axi4index_auto_out_aw_bits_qos), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_in_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_in_w_ready (_axi4yank_auto_in_w_ready),
.auto_in_w_valid (_axi4index_auto_out_w_valid), // @[IdIndexer.scala:108:31]
.auto_in_w_bits_data (_axi4index_auto_out_w_bits_data), // @[IdIndexer.scala:108:31]
.auto_in_w_bits_strb (_axi4index_auto_out_w_bits_strb), // @[IdIndexer.scala:108:31]
.auto_in_w_bits_last (_axi4index_auto_out_w_bits_last), // @[IdIndexer.scala:108:31]
.auto_in_b_ready (_axi4index_auto_out_b_ready), // @[IdIndexer.scala:108:31]
.auto_in_b_valid (_axi4yank_auto_in_b_valid),
.auto_in_b_bits_id (_axi4yank_auto_in_b_bits_id),
.auto_in_b_bits_resp (_axi4yank_auto_in_b_bits_resp),
.auto_in_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size),
.auto_in_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source),
.auto_in_ar_ready (_axi4yank_auto_in_ar_ready),
.auto_in_ar_valid (_axi4index_auto_out_ar_valid), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_id (_axi4index_auto_out_ar_bits_id), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_addr (_axi4index_auto_out_ar_bits_addr), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_len (_axi4index_auto_out_ar_bits_len), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_size (_axi4index_auto_out_ar_bits_size), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_burst (_axi4index_auto_out_ar_bits_burst), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_lock (_axi4index_auto_out_ar_bits_lock), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_cache (_axi4index_auto_out_ar_bits_cache), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_prot (_axi4index_auto_out_ar_bits_prot), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_qos (_axi4index_auto_out_ar_bits_qos), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_in_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_in_r_ready (_axi4index_auto_out_r_ready), // @[IdIndexer.scala:108:31]
.auto_in_r_valid (_axi4yank_auto_in_r_valid),
.auto_in_r_bits_id (_axi4yank_auto_in_r_bits_id),
.auto_in_r_bits_data (_axi4yank_auto_in_r_bits_data),
.auto_in_r_bits_resp (_axi4yank_auto_in_r_bits_resp),
.auto_in_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size),
.auto_in_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source),
.auto_in_r_bits_last (_axi4yank_auto_in_r_bits_last),
.auto_out_aw_ready (auto_axi4yank_out_aw_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_out_aw_valid (auto_axi4yank_out_aw_valid_0),
.auto_out_aw_bits_id (auto_axi4yank_out_aw_bits_id_0),
.auto_out_aw_bits_addr (auto_axi4yank_out_aw_bits_addr_0),
.auto_out_aw_bits_len (auto_axi4yank_out_aw_bits_len_0),
.auto_out_aw_bits_size (auto_axi4yank_out_aw_bits_size_0),
.auto_out_aw_bits_burst (auto_axi4yank_out_aw_bits_burst_0),
.auto_out_aw_bits_lock (auto_axi4yank_out_aw_bits_lock_0),
.auto_out_aw_bits_cache (auto_axi4yank_out_aw_bits_cache_0),
.auto_out_aw_bits_prot (auto_axi4yank_out_aw_bits_prot_0),
.auto_out_aw_bits_qos (auto_axi4yank_out_aw_bits_qos_0),
.auto_out_w_ready (auto_axi4yank_out_w_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_out_w_valid (auto_axi4yank_out_w_valid_0),
.auto_out_w_bits_data (auto_axi4yank_out_w_bits_data_0),
.auto_out_w_bits_strb (auto_axi4yank_out_w_bits_strb_0),
.auto_out_w_bits_last (auto_axi4yank_out_w_bits_last_0),
.auto_out_b_ready (auto_axi4yank_out_b_ready_0),
.auto_out_b_valid (auto_axi4yank_out_b_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_out_b_bits_id (auto_axi4yank_out_b_bits_id_0), // @[LazyModuleImp.scala:138:7]
.auto_out_b_bits_resp (auto_axi4yank_out_b_bits_resp_0), // @[LazyModuleImp.scala:138:7]
.auto_out_ar_ready (auto_axi4yank_out_ar_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_out_ar_valid (auto_axi4yank_out_ar_valid_0),
.auto_out_ar_bits_id (auto_axi4yank_out_ar_bits_id_0),
.auto_out_ar_bits_addr (auto_axi4yank_out_ar_bits_addr_0),
.auto_out_ar_bits_len (auto_axi4yank_out_ar_bits_len_0),
.auto_out_ar_bits_size (auto_axi4yank_out_ar_bits_size_0),
.auto_out_ar_bits_burst (auto_axi4yank_out_ar_bits_burst_0),
.auto_out_ar_bits_lock (auto_axi4yank_out_ar_bits_lock_0),
.auto_out_ar_bits_cache (auto_axi4yank_out_ar_bits_cache_0),
.auto_out_ar_bits_prot (auto_axi4yank_out_ar_bits_prot_0),
.auto_out_ar_bits_qos (auto_axi4yank_out_ar_bits_qos_0),
.auto_out_r_ready (auto_axi4yank_out_r_ready_0),
.auto_out_r_valid (auto_axi4yank_out_r_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_id (auto_axi4yank_out_r_bits_id_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_data (auto_axi4yank_out_r_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_resp (auto_axi4yank_out_r_bits_resp_0), // @[LazyModuleImp.scala:138:7]
.auto_out_r_bits_last (auto_axi4yank_out_r_bits_last_0) // @[LazyModuleImp.scala:138:7]
); // @[UserYanker.scala:125:30]
AXI4IdIndexer axi4index ( // @[IdIndexer.scala:108:31]
.clock (clock),
.reset (reset),
.auto_in_aw_ready (_axi4index_auto_in_aw_ready),
.auto_in_aw_valid (_tl2axi4_auto_out_aw_valid), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_id (_tl2axi4_auto_out_aw_bits_id), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_len (_tl2axi4_auto_out_aw_bits_len), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_size (_tl2axi4_auto_out_aw_bits_size), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29]
.auto_in_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29]
.auto_in_w_ready (_axi4index_auto_in_w_ready),
.auto_in_w_valid (_tl2axi4_auto_out_w_valid), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_data (_tl2axi4_auto_out_w_bits_data), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_strb (_tl2axi4_auto_out_w_bits_strb), // @[ToAXI4.scala:301:29]
.auto_in_w_bits_last (_tl2axi4_auto_out_w_bits_last), // @[ToAXI4.scala:301:29]
.auto_in_b_ready (_tl2axi4_auto_out_b_ready), // @[ToAXI4.scala:301:29]
.auto_in_b_valid (_axi4index_auto_in_b_valid),
.auto_in_b_bits_id (_axi4index_auto_in_b_bits_id),
.auto_in_b_bits_resp (_axi4index_auto_in_b_bits_resp),
.auto_in_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size),
.auto_in_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source),
.auto_in_ar_ready (_axi4index_auto_in_ar_ready),
.auto_in_ar_valid (_tl2axi4_auto_out_ar_valid), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_id (_tl2axi4_auto_out_ar_bits_id), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_len (_tl2axi4_auto_out_ar_bits_len), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_size (_tl2axi4_auto_out_ar_bits_size), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size), // @[ToAXI4.scala:301:29]
.auto_in_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source), // @[ToAXI4.scala:301:29]
.auto_in_r_ready (_tl2axi4_auto_out_r_ready), // @[ToAXI4.scala:301:29]
.auto_in_r_valid (_axi4index_auto_in_r_valid),
.auto_in_r_bits_id (_axi4index_auto_in_r_bits_id),
.auto_in_r_bits_data (_axi4index_auto_in_r_bits_data),
.auto_in_r_bits_resp (_axi4index_auto_in_r_bits_resp),
.auto_in_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size),
.auto_in_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source),
.auto_in_r_bits_last (_axi4index_auto_in_r_bits_last),
.auto_out_aw_ready (_axi4yank_auto_in_aw_ready), // @[UserYanker.scala:125:30]
.auto_out_aw_valid (_axi4index_auto_out_aw_valid),
.auto_out_aw_bits_id (_axi4index_auto_out_aw_bits_id),
.auto_out_aw_bits_addr (_axi4index_auto_out_aw_bits_addr),
.auto_out_aw_bits_len (_axi4index_auto_out_aw_bits_len),
.auto_out_aw_bits_size (_axi4index_auto_out_aw_bits_size),
.auto_out_aw_bits_burst (_axi4index_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock (_axi4index_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache (_axi4index_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot (_axi4index_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos (_axi4index_auto_out_aw_bits_qos),
.auto_out_aw_bits_echo_tl_state_size (_axi4index_auto_out_aw_bits_echo_tl_state_size),
.auto_out_aw_bits_echo_tl_state_source (_axi4index_auto_out_aw_bits_echo_tl_state_source),
.auto_out_w_ready (_axi4yank_auto_in_w_ready), // @[UserYanker.scala:125:30]
.auto_out_w_valid (_axi4index_auto_out_w_valid),
.auto_out_w_bits_data (_axi4index_auto_out_w_bits_data),
.auto_out_w_bits_strb (_axi4index_auto_out_w_bits_strb),
.auto_out_w_bits_last (_axi4index_auto_out_w_bits_last),
.auto_out_b_ready (_axi4index_auto_out_b_ready),
.auto_out_b_valid (_axi4yank_auto_in_b_valid), // @[UserYanker.scala:125:30]
.auto_out_b_bits_id (_axi4yank_auto_in_b_bits_id), // @[UserYanker.scala:125:30]
.auto_out_b_bits_resp (_axi4yank_auto_in_b_bits_resp), // @[UserYanker.scala:125:30]
.auto_out_b_bits_echo_tl_state_size (_axi4yank_auto_in_b_bits_echo_tl_state_size), // @[UserYanker.scala:125:30]
.auto_out_b_bits_echo_tl_state_source (_axi4yank_auto_in_b_bits_echo_tl_state_source), // @[UserYanker.scala:125:30]
.auto_out_ar_ready (_axi4yank_auto_in_ar_ready), // @[UserYanker.scala:125:30]
.auto_out_ar_valid (_axi4index_auto_out_ar_valid),
.auto_out_ar_bits_id (_axi4index_auto_out_ar_bits_id),
.auto_out_ar_bits_addr (_axi4index_auto_out_ar_bits_addr),
.auto_out_ar_bits_len (_axi4index_auto_out_ar_bits_len),
.auto_out_ar_bits_size (_axi4index_auto_out_ar_bits_size),
.auto_out_ar_bits_burst (_axi4index_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock (_axi4index_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache (_axi4index_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot (_axi4index_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos (_axi4index_auto_out_ar_bits_qos),
.auto_out_ar_bits_echo_tl_state_size (_axi4index_auto_out_ar_bits_echo_tl_state_size),
.auto_out_ar_bits_echo_tl_state_source (_axi4index_auto_out_ar_bits_echo_tl_state_source),
.auto_out_r_ready (_axi4index_auto_out_r_ready),
.auto_out_r_valid (_axi4yank_auto_in_r_valid), // @[UserYanker.scala:125:30]
.auto_out_r_bits_id (_axi4yank_auto_in_r_bits_id), // @[UserYanker.scala:125:30]
.auto_out_r_bits_data (_axi4yank_auto_in_r_bits_data), // @[UserYanker.scala:125:30]
.auto_out_r_bits_resp (_axi4yank_auto_in_r_bits_resp), // @[UserYanker.scala:125:30]
.auto_out_r_bits_echo_tl_state_size (_axi4yank_auto_in_r_bits_echo_tl_state_size), // @[UserYanker.scala:125:30]
.auto_out_r_bits_echo_tl_state_source (_axi4yank_auto_in_r_bits_echo_tl_state_source), // @[UserYanker.scala:125:30]
.auto_out_r_bits_last (_axi4yank_auto_in_r_bits_last) // @[UserYanker.scala:125:30]
); // @[IdIndexer.scala:108:31]
TLToAXI4 tl2axi4 ( // @[ToAXI4.scala:301:29]
.clock (clock),
.reset (reset),
.auto_in_a_ready (widget_auto_anon_out_a_ready),
.auto_in_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9]
.auto_in_a_bits_corrupt (widget_auto_anon_out_a_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_in_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9]
.auto_in_d_valid (widget_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (widget_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_size (widget_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (widget_auto_anon_out_d_bits_source),
.auto_in_d_bits_denied (widget_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (widget_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt),
.auto_out_aw_ready (_axi4index_auto_in_aw_ready), // @[IdIndexer.scala:108:31]
.auto_out_aw_valid (_tl2axi4_auto_out_aw_valid),
.auto_out_aw_bits_id (_tl2axi4_auto_out_aw_bits_id),
.auto_out_aw_bits_addr (_tl2axi4_auto_out_aw_bits_addr),
.auto_out_aw_bits_len (_tl2axi4_auto_out_aw_bits_len),
.auto_out_aw_bits_size (_tl2axi4_auto_out_aw_bits_size),
.auto_out_aw_bits_burst (_tl2axi4_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock (_tl2axi4_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache (_tl2axi4_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot (_tl2axi4_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos (_tl2axi4_auto_out_aw_bits_qos),
.auto_out_aw_bits_echo_tl_state_size (_tl2axi4_auto_out_aw_bits_echo_tl_state_size),
.auto_out_aw_bits_echo_tl_state_source (_tl2axi4_auto_out_aw_bits_echo_tl_state_source),
.auto_out_w_ready (_axi4index_auto_in_w_ready), // @[IdIndexer.scala:108:31]
.auto_out_w_valid (_tl2axi4_auto_out_w_valid),
.auto_out_w_bits_data (_tl2axi4_auto_out_w_bits_data),
.auto_out_w_bits_strb (_tl2axi4_auto_out_w_bits_strb),
.auto_out_w_bits_last (_tl2axi4_auto_out_w_bits_last),
.auto_out_b_ready (_tl2axi4_auto_out_b_ready),
.auto_out_b_valid (_axi4index_auto_in_b_valid), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_id (_axi4index_auto_in_b_bits_id), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_resp (_axi4index_auto_in_b_bits_resp), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_echo_tl_state_size (_axi4index_auto_in_b_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_out_b_bits_echo_tl_state_source (_axi4index_auto_in_b_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_out_ar_ready (_axi4index_auto_in_ar_ready), // @[IdIndexer.scala:108:31]
.auto_out_ar_valid (_tl2axi4_auto_out_ar_valid),
.auto_out_ar_bits_id (_tl2axi4_auto_out_ar_bits_id),
.auto_out_ar_bits_addr (_tl2axi4_auto_out_ar_bits_addr),
.auto_out_ar_bits_len (_tl2axi4_auto_out_ar_bits_len),
.auto_out_ar_bits_size (_tl2axi4_auto_out_ar_bits_size),
.auto_out_ar_bits_burst (_tl2axi4_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock (_tl2axi4_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache (_tl2axi4_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot (_tl2axi4_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos (_tl2axi4_auto_out_ar_bits_qos),
.auto_out_ar_bits_echo_tl_state_size (_tl2axi4_auto_out_ar_bits_echo_tl_state_size),
.auto_out_ar_bits_echo_tl_state_source (_tl2axi4_auto_out_ar_bits_echo_tl_state_source),
.auto_out_r_ready (_tl2axi4_auto_out_r_ready),
.auto_out_r_valid (_axi4index_auto_in_r_valid), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_id (_axi4index_auto_in_r_bits_id), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_data (_axi4index_auto_in_r_bits_data), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_resp (_axi4index_auto_in_r_bits_resp), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_echo_tl_state_size (_axi4index_auto_in_r_bits_echo_tl_state_size), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_echo_tl_state_source (_axi4index_auto_in_r_bits_echo_tl_state_source), // @[IdIndexer.scala:108:31]
.auto_out_r_bits_last (_axi4index_auto_in_r_bits_last) // @[IdIndexer.scala:108:31]
); // @[ToAXI4.scala:301:29]
assign auto_widget_anon_in_a_ready = auto_widget_anon_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_valid = auto_widget_anon_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_opcode = auto_widget_anon_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_size = auto_widget_anon_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_source = auto_widget_anon_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_denied = auto_widget_anon_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_data = auto_widget_anon_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_widget_anon_in_d_bits_corrupt = auto_widget_anon_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_valid = auto_axi4yank_out_aw_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_id = auto_axi4yank_out_aw_bits_id_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_addr = auto_axi4yank_out_aw_bits_addr_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_len = auto_axi4yank_out_aw_bits_len_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_size = auto_axi4yank_out_aw_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_burst = auto_axi4yank_out_aw_bits_burst_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_lock = auto_axi4yank_out_aw_bits_lock_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_cache = auto_axi4yank_out_aw_bits_cache_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_prot = auto_axi4yank_out_aw_bits_prot_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_aw_bits_qos = auto_axi4yank_out_aw_bits_qos_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_valid = auto_axi4yank_out_w_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_bits_data = auto_axi4yank_out_w_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_bits_strb = auto_axi4yank_out_w_bits_strb_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_w_bits_last = auto_axi4yank_out_w_bits_last_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_b_ready = auto_axi4yank_out_b_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_valid = auto_axi4yank_out_ar_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_id = auto_axi4yank_out_ar_bits_id_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_addr = auto_axi4yank_out_ar_bits_addr_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_len = auto_axi4yank_out_ar_bits_len_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_size = auto_axi4yank_out_ar_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_burst = auto_axi4yank_out_ar_bits_burst_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_lock = auto_axi4yank_out_ar_bits_lock_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_cache = auto_axi4yank_out_ar_bits_cache_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_prot = auto_axi4yank_out_ar_bits_prot_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_ar_bits_qos = auto_axi4yank_out_ar_bits_qos_0; // @[LazyModuleImp.scala:138:7]
assign auto_axi4yank_out_r_ready = auto_axi4yank_out_r_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_param = auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_source = auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RocketTile :
input clock : Clock
input reset : Reset
output auto : { buffer_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, buffer_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, wfi_out : UInt<1>[1], cease_out : UInt<1>[1], halt_out : UInt<1>[1], flip int_local_in_3 : UInt<1>[1], flip int_local_in_2 : UInt<1>[1], flip int_local_in_1 : UInt<1>[2], flip int_local_in_0 : UInt<1>[1], trace_core_source_out : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}, trace_source_out : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}, flip reset_vector_in : UInt<32>, flip hartid_in : UInt<1>}
inst tlMasterXbar of TLXbar_MasterXbar_RocketTile_i2_o1_a32d128s2k4z4c
connect tlMasterXbar.clock, clock
connect tlMasterXbar.reset, reset
inst tlSlaveXbar of TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u
connect tlSlaveXbar.clock, clock
connect tlSlaveXbar.reset, reset
inst intXbar of IntXbar_i4_o1
inst broadcast of BundleBridgeNexus_UInt1
inst broadcast_1 of BundleBridgeNexus_UInt32
inst nexus of BundleBridgeNexus_NoOutput_6
inst nexus_1 of BundleBridgeNexus_TraceAux
inst broadcast_2 of BundleBridgeNexus_NoOutput_7
inst widget of TLWidthWidget16_2
connect widget.clock, clock
connect widget.reset, reset
inst dcache of DCache
connect dcache.clock, clock
connect dcache.reset, reset
inst gemmini of Gemmini
connect gemmini.clock, clock
connect gemmini.reset, reset
inst frontend of Frontend
connect frontend.clock, clock
connect frontend.reset, reset
inst widget_1 of TLWidthWidget16_4
connect widget_1.clock, clock
connect widget_1.reset, reset
inst fragmenter of TLFragmenter
connect fragmenter.clock, clock
connect fragmenter.reset, reset
inst widget_2 of TLWidthWidget8_6
connect widget_2.clock, clock
connect widget_2.reset, reset
inst buffer of TLBuffer_a32d128s7k4z4u_1
connect buffer.clock, clock
connect buffer.reset, reset
inst buffer_1 of TLBuffer_1
connect buffer_1.clock, clock
connect buffer_1.reset, reset
wire tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate tlOtherMastersNodeOut.d.bits.corrupt
invalidate tlOtherMastersNodeOut.d.bits.data
invalidate tlOtherMastersNodeOut.d.bits.denied
invalidate tlOtherMastersNodeOut.d.bits.sink
invalidate tlOtherMastersNodeOut.d.bits.source
invalidate tlOtherMastersNodeOut.d.bits.size
invalidate tlOtherMastersNodeOut.d.bits.param
invalidate tlOtherMastersNodeOut.d.bits.opcode
invalidate tlOtherMastersNodeOut.d.valid
invalidate tlOtherMastersNodeOut.d.ready
invalidate tlOtherMastersNodeOut.a.bits.corrupt
invalidate tlOtherMastersNodeOut.a.bits.data
invalidate tlOtherMastersNodeOut.a.bits.mask
invalidate tlOtherMastersNodeOut.a.bits.address
invalidate tlOtherMastersNodeOut.a.bits.source
invalidate tlOtherMastersNodeOut.a.bits.size
invalidate tlOtherMastersNodeOut.a.bits.param
invalidate tlOtherMastersNodeOut.a.bits.opcode
invalidate tlOtherMastersNodeOut.a.valid
invalidate tlOtherMastersNodeOut.a.ready
wire x1_tlOtherMastersNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate x1_tlOtherMastersNodeOut.e.bits.sink
invalidate x1_tlOtherMastersNodeOut.e.valid
invalidate x1_tlOtherMastersNodeOut.e.ready
invalidate x1_tlOtherMastersNodeOut.d.bits.corrupt
invalidate x1_tlOtherMastersNodeOut.d.bits.data
invalidate x1_tlOtherMastersNodeOut.d.bits.denied
invalidate x1_tlOtherMastersNodeOut.d.bits.sink
invalidate x1_tlOtherMastersNodeOut.d.bits.source
invalidate x1_tlOtherMastersNodeOut.d.bits.size
invalidate x1_tlOtherMastersNodeOut.d.bits.param
invalidate x1_tlOtherMastersNodeOut.d.bits.opcode
invalidate x1_tlOtherMastersNodeOut.d.valid
invalidate x1_tlOtherMastersNodeOut.d.ready
invalidate x1_tlOtherMastersNodeOut.c.bits.corrupt
invalidate x1_tlOtherMastersNodeOut.c.bits.data
invalidate x1_tlOtherMastersNodeOut.c.bits.address
invalidate x1_tlOtherMastersNodeOut.c.bits.source
invalidate x1_tlOtherMastersNodeOut.c.bits.size
invalidate x1_tlOtherMastersNodeOut.c.bits.param
invalidate x1_tlOtherMastersNodeOut.c.bits.opcode
invalidate x1_tlOtherMastersNodeOut.c.valid
invalidate x1_tlOtherMastersNodeOut.c.ready
invalidate x1_tlOtherMastersNodeOut.b.bits.corrupt
invalidate x1_tlOtherMastersNodeOut.b.bits.data
invalidate x1_tlOtherMastersNodeOut.b.bits.mask
invalidate x1_tlOtherMastersNodeOut.b.bits.address
invalidate x1_tlOtherMastersNodeOut.b.bits.source
invalidate x1_tlOtherMastersNodeOut.b.bits.size
invalidate x1_tlOtherMastersNodeOut.b.bits.param
invalidate x1_tlOtherMastersNodeOut.b.bits.opcode
invalidate x1_tlOtherMastersNodeOut.b.valid
invalidate x1_tlOtherMastersNodeOut.b.ready
invalidate x1_tlOtherMastersNodeOut.a.bits.corrupt
invalidate x1_tlOtherMastersNodeOut.a.bits.data
invalidate x1_tlOtherMastersNodeOut.a.bits.mask
invalidate x1_tlOtherMastersNodeOut.a.bits.address
invalidate x1_tlOtherMastersNodeOut.a.bits.source
invalidate x1_tlOtherMastersNodeOut.a.bits.size
invalidate x1_tlOtherMastersNodeOut.a.bits.param
invalidate x1_tlOtherMastersNodeOut.a.bits.opcode
invalidate x1_tlOtherMastersNodeOut.a.valid
invalidate x1_tlOtherMastersNodeOut.a.ready
wire tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate tlOtherMastersNodeIn.d.bits.corrupt
invalidate tlOtherMastersNodeIn.d.bits.data
invalidate tlOtherMastersNodeIn.d.bits.denied
invalidate tlOtherMastersNodeIn.d.bits.sink
invalidate tlOtherMastersNodeIn.d.bits.source
invalidate tlOtherMastersNodeIn.d.bits.size
invalidate tlOtherMastersNodeIn.d.bits.param
invalidate tlOtherMastersNodeIn.d.bits.opcode
invalidate tlOtherMastersNodeIn.d.valid
invalidate tlOtherMastersNodeIn.d.ready
invalidate tlOtherMastersNodeIn.a.bits.corrupt
invalidate tlOtherMastersNodeIn.a.bits.data
invalidate tlOtherMastersNodeIn.a.bits.mask
invalidate tlOtherMastersNodeIn.a.bits.address
invalidate tlOtherMastersNodeIn.a.bits.source
invalidate tlOtherMastersNodeIn.a.bits.size
invalidate tlOtherMastersNodeIn.a.bits.param
invalidate tlOtherMastersNodeIn.a.bits.opcode
invalidate tlOtherMastersNodeIn.a.valid
invalidate tlOtherMastersNodeIn.a.ready
wire x1_tlOtherMastersNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate x1_tlOtherMastersNodeIn.e.bits.sink
invalidate x1_tlOtherMastersNodeIn.e.valid
invalidate x1_tlOtherMastersNodeIn.e.ready
invalidate x1_tlOtherMastersNodeIn.d.bits.corrupt
invalidate x1_tlOtherMastersNodeIn.d.bits.data
invalidate x1_tlOtherMastersNodeIn.d.bits.denied
invalidate x1_tlOtherMastersNodeIn.d.bits.sink
invalidate x1_tlOtherMastersNodeIn.d.bits.source
invalidate x1_tlOtherMastersNodeIn.d.bits.size
invalidate x1_tlOtherMastersNodeIn.d.bits.param
invalidate x1_tlOtherMastersNodeIn.d.bits.opcode
invalidate x1_tlOtherMastersNodeIn.d.valid
invalidate x1_tlOtherMastersNodeIn.d.ready
invalidate x1_tlOtherMastersNodeIn.c.bits.corrupt
invalidate x1_tlOtherMastersNodeIn.c.bits.data
invalidate x1_tlOtherMastersNodeIn.c.bits.address
invalidate x1_tlOtherMastersNodeIn.c.bits.source
invalidate x1_tlOtherMastersNodeIn.c.bits.size
invalidate x1_tlOtherMastersNodeIn.c.bits.param
invalidate x1_tlOtherMastersNodeIn.c.bits.opcode
invalidate x1_tlOtherMastersNodeIn.c.valid
invalidate x1_tlOtherMastersNodeIn.c.ready
invalidate x1_tlOtherMastersNodeIn.b.bits.corrupt
invalidate x1_tlOtherMastersNodeIn.b.bits.data
invalidate x1_tlOtherMastersNodeIn.b.bits.mask
invalidate x1_tlOtherMastersNodeIn.b.bits.address
invalidate x1_tlOtherMastersNodeIn.b.bits.source
invalidate x1_tlOtherMastersNodeIn.b.bits.size
invalidate x1_tlOtherMastersNodeIn.b.bits.param
invalidate x1_tlOtherMastersNodeIn.b.bits.opcode
invalidate x1_tlOtherMastersNodeIn.b.valid
invalidate x1_tlOtherMastersNodeIn.b.ready
invalidate x1_tlOtherMastersNodeIn.a.bits.corrupt
invalidate x1_tlOtherMastersNodeIn.a.bits.data
invalidate x1_tlOtherMastersNodeIn.a.bits.mask
invalidate x1_tlOtherMastersNodeIn.a.bits.address
invalidate x1_tlOtherMastersNodeIn.a.bits.source
invalidate x1_tlOtherMastersNodeIn.a.bits.size
invalidate x1_tlOtherMastersNodeIn.a.bits.param
invalidate x1_tlOtherMastersNodeIn.a.bits.opcode
invalidate x1_tlOtherMastersNodeIn.a.valid
invalidate x1_tlOtherMastersNodeIn.a.ready
connect tlOtherMastersNodeOut, tlOtherMastersNodeIn
connect x1_tlOtherMastersNodeOut, x1_tlOtherMastersNodeIn
wire hartIdSinkNodeIn : UInt<1>
invalidate hartIdSinkNodeIn
wire hartidOut : UInt<1>
invalidate hartidOut
wire hartidIn : UInt<1>
invalidate hartidIn
connect hartidOut, hartidIn
wire resetVectorSinkNodeIn : UInt<32>
invalidate resetVectorSinkNodeIn
wire reset_vectorOut : UInt<32>
invalidate reset_vectorOut
wire reset_vectorIn : UInt<32>
invalidate reset_vectorIn
connect reset_vectorOut, reset_vectorIn
wire traceSourceNodeOut : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], time : UInt<64>}
invalidate traceSourceNodeOut.time
invalidate traceSourceNodeOut.insns[0].tval
invalidate traceSourceNodeOut.insns[0].cause
invalidate traceSourceNodeOut.insns[0].interrupt
invalidate traceSourceNodeOut.insns[0].exception
invalidate traceSourceNodeOut.insns[0].priv
invalidate traceSourceNodeOut.insns[0].insn
invalidate traceSourceNodeOut.insns[0].iaddr
invalidate traceSourceNodeOut.insns[0].valid
wire traceCoreSourceNodeOut : { group : { iretire : UInt<1>, iaddr : UInt<32>, itype : UInt<4>, ilastsize : UInt<1>}[1], priv : UInt<4>, tval : UInt<32>, cause : UInt<32>}
invalidate traceCoreSourceNodeOut.cause
invalidate traceCoreSourceNodeOut.tval
invalidate traceCoreSourceNodeOut.priv
invalidate traceCoreSourceNodeOut.group[0].ilastsize
invalidate traceCoreSourceNodeOut.group[0].itype
invalidate traceCoreSourceNodeOut.group[0].iaddr
invalidate traceCoreSourceNodeOut.group[0].iretire
wire bundleIn_x_sourceOpt : { enable : UInt<1>, stall : UInt<1>}
connect bundleIn_x_sourceOpt.stall, UInt<1>(0h0)
connect bundleIn_x_sourceOpt.enable, UInt<1>(0h0)
wire traceAuxSinkNodeIn : { enable : UInt<1>, stall : UInt<1>}
invalidate traceAuxSinkNodeIn.stall
invalidate traceAuxSinkNodeIn.enable
wire bpwatchSourceNodeOut : { valid : UInt<1>[1], rvalid : UInt<1>[1], wvalid : UInt<1>[1], ivalid : UInt<1>[1], action : UInt<3>}[1]
invalidate bpwatchSourceNodeOut[0].action
invalidate bpwatchSourceNodeOut[0].ivalid[0]
invalidate bpwatchSourceNodeOut[0].wvalid[0]
invalidate bpwatchSourceNodeOut[0].rvalid[0]
invalidate bpwatchSourceNodeOut[0].valid[0]
wire int_localOut : UInt<1>[1]
invalidate int_localOut[0]
wire x1_int_localOut : UInt<1>[2]
invalidate x1_int_localOut[0]
invalidate x1_int_localOut[1]
wire x1_int_localOut_1 : UInt<1>[1]
invalidate x1_int_localOut_1[0]
wire x1_int_localOut_2 : UInt<1>[1]
invalidate x1_int_localOut_2[0]
wire int_localIn : UInt<1>[1]
invalidate int_localIn[0]
wire x1_int_localIn : UInt<1>[2]
invalidate x1_int_localIn[0]
invalidate x1_int_localIn[1]
wire x1_int_localIn_1 : UInt<1>[1]
invalidate x1_int_localIn_1[0]
wire x1_int_localIn_2 : UInt<1>[1]
invalidate x1_int_localIn_2[0]
connect int_localOut, int_localIn
connect x1_int_localOut, x1_int_localIn
connect x1_int_localOut_1, x1_int_localIn_1
connect x1_int_localOut_2, x1_int_localIn_2
wire intSinkNodeIn : UInt<1>[5]
invalidate intSinkNodeIn[0]
invalidate intSinkNodeIn[1]
invalidate intSinkNodeIn[2]
invalidate intSinkNodeIn[3]
invalidate intSinkNodeIn[4]
wire haltNodeOut : UInt<1>[1]
invalidate haltNodeOut[0]
wire ceaseNodeOut : UInt<1>[1]
invalidate ceaseNodeOut[0]
wire wfiNodeOut : UInt<1>[1]
invalidate wfiNodeOut[0]
connect buffer.auto.in_0, tlOtherMastersNodeOut
connect buffer.auto.in_1, x1_tlOtherMastersNodeOut
connect x1_tlOtherMastersNodeIn.e.bits, tlMasterXbar.auto.anon_out.e.bits
connect x1_tlOtherMastersNodeIn.e.valid, tlMasterXbar.auto.anon_out.e.valid
connect tlMasterXbar.auto.anon_out.e.ready, x1_tlOtherMastersNodeIn.e.ready
connect tlMasterXbar.auto.anon_out.d, x1_tlOtherMastersNodeIn.d
connect x1_tlOtherMastersNodeIn.c.bits, tlMasterXbar.auto.anon_out.c.bits
connect x1_tlOtherMastersNodeIn.c.valid, tlMasterXbar.auto.anon_out.c.valid
connect tlMasterXbar.auto.anon_out.c.ready, x1_tlOtherMastersNodeIn.c.ready
connect tlMasterXbar.auto.anon_out.b, x1_tlOtherMastersNodeIn.b
connect x1_tlOtherMastersNodeIn.a.bits, tlMasterXbar.auto.anon_out.a.bits
connect x1_tlOtherMastersNodeIn.a.valid, tlMasterXbar.auto.anon_out.a.valid
connect tlMasterXbar.auto.anon_out.a.ready, x1_tlOtherMastersNodeIn.a.ready
connect intSinkNodeIn, intXbar.auto.anon_out
connect hartIdSinkNodeIn, broadcast.auto.out
connect broadcast.auto.in, hartidOut
connect resetVectorSinkNodeIn, broadcast_1.auto.out_0
connect frontend.auto.reset_vector_sink_in, broadcast_1.auto.out_1
connect broadcast_1.auto.in, reset_vectorOut
connect traceAuxSinkNodeIn, nexus_1.auto.out
connect broadcast_2.auto.in[0], bpwatchSourceNodeOut[0]
connect intXbar.auto.anon_in_0[0], int_localOut[0]
connect intXbar.auto.anon_in_1[0], x1_int_localOut[0]
connect intXbar.auto.anon_in_1[1], x1_int_localOut[1]
connect intXbar.auto.anon_in_2[0], x1_int_localOut_1[0]
connect intXbar.auto.anon_in_3[0], x1_int_localOut_2[0]
connect tlMasterXbar.auto.anon_in_0, widget.auto.anon_out
connect widget.auto.anon_in, dcache.auto.out
connect gemmini.auto.spad_id_out.d, tlOtherMastersNodeIn.d
connect tlOtherMastersNodeIn.a.bits, gemmini.auto.spad_id_out.a.bits
connect tlOtherMastersNodeIn.a.valid, gemmini.auto.spad_id_out.a.valid
connect gemmini.auto.spad_id_out.a.ready, tlOtherMastersNodeIn.a.ready
connect widget_1.auto.anon_in, frontend.auto.icache_master_out
connect tlMasterXbar.auto.anon_in_1, widget_1.auto.anon_out
connect hartidIn, auto.hartid_in
connect reset_vectorIn, auto.reset_vector_in
connect auto.trace_source_out, traceSourceNodeOut
connect auto.trace_core_source_out, traceCoreSourceNodeOut
connect int_localIn, auto.int_local_in_0
connect x1_int_localIn, auto.int_local_in_1
connect x1_int_localIn_1, auto.int_local_in_2
connect x1_int_localIn_2, auto.int_local_in_3
connect auto.halt_out, haltNodeOut
connect auto.cease_out, ceaseNodeOut
connect auto.wfi_out, wfiNodeOut
connect buffer.auto.out_0.d, auto.buffer_out_0.d
connect auto.buffer_out_0.a.bits, buffer.auto.out_0.a.bits
connect auto.buffer_out_0.a.valid, buffer.auto.out_0.a.valid
connect buffer.auto.out_0.a.ready, auto.buffer_out_0.a.ready
connect auto.buffer_out_1.e.bits, buffer.auto.out_1.e.bits
connect auto.buffer_out_1.e.valid, buffer.auto.out_1.e.valid
connect buffer.auto.out_1.e.ready, auto.buffer_out_1.e.ready
connect buffer.auto.out_1.d, auto.buffer_out_1.d
connect auto.buffer_out_1.c.bits, buffer.auto.out_1.c.bits
connect auto.buffer_out_1.c.valid, buffer.auto.out_1.c.valid
connect buffer.auto.out_1.c.ready, auto.buffer_out_1.c.ready
connect buffer.auto.out_1.b, auto.buffer_out_1.b
connect auto.buffer_out_1.a.bits, buffer.auto.out_1.a.bits
connect auto.buffer_out_1.a.valid, buffer.auto.out_1.a.valid
connect buffer.auto.out_1.a.ready, auto.buffer_out_1.a.ready
invalidate dcache.io.tlb_port.s2_kill
invalidate dcache.io.tlb_port.s1_resp.cmd
invalidate dcache.io.tlb_port.s1_resp.size
invalidate dcache.io.tlb_port.s1_resp.prefetchable
invalidate dcache.io.tlb_port.s1_resp.must_alloc
invalidate dcache.io.tlb_port.s1_resp.cacheable
invalidate dcache.io.tlb_port.s1_resp.ma.inst
invalidate dcache.io.tlb_port.s1_resp.ma.st
invalidate dcache.io.tlb_port.s1_resp.ma.ld
invalidate dcache.io.tlb_port.s1_resp.ae.inst
invalidate dcache.io.tlb_port.s1_resp.ae.st
invalidate dcache.io.tlb_port.s1_resp.ae.ld
invalidate dcache.io.tlb_port.s1_resp.gf.inst
invalidate dcache.io.tlb_port.s1_resp.gf.st
invalidate dcache.io.tlb_port.s1_resp.gf.ld
invalidate dcache.io.tlb_port.s1_resp.pf.inst
invalidate dcache.io.tlb_port.s1_resp.pf.st
invalidate dcache.io.tlb_port.s1_resp.pf.ld
invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte
invalidate dcache.io.tlb_port.s1_resp.gpa
invalidate dcache.io.tlb_port.s1_resp.paddr
invalidate dcache.io.tlb_port.s1_resp.miss
invalidate dcache.io.tlb_port.req.bits.v
invalidate dcache.io.tlb_port.req.bits.prv
invalidate dcache.io.tlb_port.req.bits.cmd
invalidate dcache.io.tlb_port.req.bits.size
invalidate dcache.io.tlb_port.req.bits.passthrough
invalidate dcache.io.tlb_port.req.bits.vaddr
invalidate dcache.io.tlb_port.req.valid
invalidate dcache.io.tlb_port.req.ready
inst fpuOpt of FPU
connect fpuOpt.clock, clock
connect fpuOpt.reset, reset
connect fpuOpt.io.cp_req.valid, UInt<1>(0h0)
invalidate fpuOpt.io.cp_req.bits.in3
invalidate fpuOpt.io.cp_req.bits.in2
invalidate fpuOpt.io.cp_req.bits.in1
invalidate fpuOpt.io.cp_req.bits.fmt
invalidate fpuOpt.io.cp_req.bits.typ
invalidate fpuOpt.io.cp_req.bits.fmaCmd
invalidate fpuOpt.io.cp_req.bits.rm
invalidate fpuOpt.io.cp_req.bits.vec
invalidate fpuOpt.io.cp_req.bits.wflags
invalidate fpuOpt.io.cp_req.bits.sqrt
invalidate fpuOpt.io.cp_req.bits.div
invalidate fpuOpt.io.cp_req.bits.fma
invalidate fpuOpt.io.cp_req.bits.fastpipe
invalidate fpuOpt.io.cp_req.bits.toint
invalidate fpuOpt.io.cp_req.bits.fromint
invalidate fpuOpt.io.cp_req.bits.typeTagOut
invalidate fpuOpt.io.cp_req.bits.typeTagIn
invalidate fpuOpt.io.cp_req.bits.swap23
invalidate fpuOpt.io.cp_req.bits.swap12
invalidate fpuOpt.io.cp_req.bits.ren3
invalidate fpuOpt.io.cp_req.bits.ren2
invalidate fpuOpt.io.cp_req.bits.ren1
invalidate fpuOpt.io.cp_req.bits.wen
invalidate fpuOpt.io.cp_req.bits.ldst
connect fpuOpt.io.cp_resp.ready, UInt<1>(0h0)
inst dcacheArb of HellaCacheArbiter
connect dcacheArb.clock, clock
connect dcacheArb.reset, reset
connect dcache.io.cpu, dcacheArb.io.mem
inst ptw of PTW
connect ptw.clock, clock
connect ptw.reset, reset
invalidate ptw.io.mem.clock_enabled
invalidate ptw.io.mem.keep_clock_enabled
invalidate ptw.io.mem.perf.storeBufferEmptyAfterStore
invalidate ptw.io.mem.perf.storeBufferEmptyAfterLoad
invalidate ptw.io.mem.perf.canAcceptLoadThenLoad
invalidate ptw.io.mem.perf.canAcceptStoreThenRMW
invalidate ptw.io.mem.perf.canAcceptStoreThenLoad
invalidate ptw.io.mem.perf.blocked
invalidate ptw.io.mem.perf.tlbMiss
invalidate ptw.io.mem.perf.grant
invalidate ptw.io.mem.perf.release
invalidate ptw.io.mem.perf.acquire
invalidate ptw.io.mem.store_pending
invalidate ptw.io.mem.ordered
invalidate ptw.io.mem.s2_gpa_is_pte
invalidate ptw.io.mem.s2_gpa
invalidate ptw.io.mem.s2_xcpt.ae.st
invalidate ptw.io.mem.s2_xcpt.ae.ld
invalidate ptw.io.mem.s2_xcpt.gf.st
invalidate ptw.io.mem.s2_xcpt.gf.ld
invalidate ptw.io.mem.s2_xcpt.pf.st
invalidate ptw.io.mem.s2_xcpt.pf.ld
invalidate ptw.io.mem.s2_xcpt.ma.st
invalidate ptw.io.mem.s2_xcpt.ma.ld
invalidate ptw.io.mem.replay_next
invalidate ptw.io.mem.resp.bits.store_data
invalidate ptw.io.mem.resp.bits.data_raw
invalidate ptw.io.mem.resp.bits.data_word_bypass
invalidate ptw.io.mem.resp.bits.has_data
invalidate ptw.io.mem.resp.bits.replay
invalidate ptw.io.mem.resp.bits.mask
invalidate ptw.io.mem.resp.bits.data
invalidate ptw.io.mem.resp.bits.dv
invalidate ptw.io.mem.resp.bits.dprv
invalidate ptw.io.mem.resp.bits.signed
invalidate ptw.io.mem.resp.bits.size
invalidate ptw.io.mem.resp.bits.cmd
invalidate ptw.io.mem.resp.bits.tag
invalidate ptw.io.mem.resp.bits.addr
invalidate ptw.io.mem.resp.valid
invalidate ptw.io.mem.s2_paddr
invalidate ptw.io.mem.s2_uncached
invalidate ptw.io.mem.s2_kill
invalidate ptw.io.mem.s2_nack_cause_raw
invalidate ptw.io.mem.s2_nack
invalidate ptw.io.mem.s1_data.mask
invalidate ptw.io.mem.s1_data.data
invalidate ptw.io.mem.s1_kill
invalidate ptw.io.mem.req.bits.mask
invalidate ptw.io.mem.req.bits.data
invalidate ptw.io.mem.req.bits.no_xcpt
invalidate ptw.io.mem.req.bits.no_alloc
invalidate ptw.io.mem.req.bits.no_resp
invalidate ptw.io.mem.req.bits.phys
invalidate ptw.io.mem.req.bits.dv
invalidate ptw.io.mem.req.bits.dprv
invalidate ptw.io.mem.req.bits.signed
invalidate ptw.io.mem.req.bits.size
invalidate ptw.io.mem.req.bits.cmd
invalidate ptw.io.mem.req.bits.tag
invalidate ptw.io.mem.req.bits.addr
invalidate ptw.io.mem.req.valid
invalidate ptw.io.mem.req.ready
inst respArb of RRArbiter_5
connect respArb.clock, clock
connect respArb.reset, reset
inst cmdRouter of RoccCommandRouter
connect cmdRouter.clock, clock
connect cmdRouter.reset, reset
connect gemmini.io.cmd, cmdRouter.io.out[0]
inst dcIF of SimpleHellaCacheIF
connect dcIF.clock, clock
connect dcIF.reset, reset
connect dcIF.io.requestor, gemmini.io.mem
inst respArb_io_in_0_q of Queue2_RoCCResponse
connect respArb_io_in_0_q.clock, clock
connect respArb_io_in_0_q.reset, reset
connect respArb_io_in_0_q.io.enq.valid, gemmini.io.resp.valid
connect respArb_io_in_0_q.io.enq.bits.data, gemmini.io.resp.bits.data
connect respArb_io_in_0_q.io.enq.bits.rd, gemmini.io.resp.bits.rd
connect gemmini.io.resp.ready, respArb_io_in_0_q.io.enq.ready
connect respArb.io.in[0], respArb_io_in_0_q.io.deq
inst core of Rocket
connect core.clock, clock
connect core.reset, reset
invalidate core.io.reset_vector
connect haltNodeOut[0], UInt<1>(0h0)
connect ceaseNodeOut[0], UInt<1>(0h0)
regreset wfiNodeOut_0_REG : UInt<1>, clock, reset, UInt<1>(0h0)
connect wfiNodeOut_0_REG, core.io.wfi
connect wfiNodeOut[0], wfiNodeOut_0_REG
connect core.io.interrupts.debug, intSinkNodeIn[0]
connect core.io.interrupts.msip, intSinkNodeIn[1]
connect core.io.interrupts.mtip, intSinkNodeIn[2]
connect core.io.interrupts.meip, intSinkNodeIn[3]
connect core.io.interrupts.seip, intSinkNodeIn[4]
connect traceSourceNodeOut, core.io.trace
connect core.io.traceStall, traceAuxSinkNodeIn.stall
connect bpwatchSourceNodeOut, core.io.bpwatch
connect core.io.hartid, hartIdSinkNodeIn
connect frontend.io.cpu, core.io.imem
connect fpuOpt.io.keep_clock_enabled, core.io.fpu.keep_clock_enabled
connect core.io.fpu.sboard_clra, fpuOpt.io.sboard_clra
connect core.io.fpu.sboard_clr, fpuOpt.io.sboard_clr
connect core.io.fpu.sboard_set, fpuOpt.io.sboard_set
connect core.io.fpu.dec.vec, fpuOpt.io.dec.vec
connect core.io.fpu.dec.wflags, fpuOpt.io.dec.wflags
connect core.io.fpu.dec.sqrt, fpuOpt.io.dec.sqrt
connect core.io.fpu.dec.div, fpuOpt.io.dec.div
connect core.io.fpu.dec.fma, fpuOpt.io.dec.fma
connect core.io.fpu.dec.fastpipe, fpuOpt.io.dec.fastpipe
connect core.io.fpu.dec.toint, fpuOpt.io.dec.toint
connect core.io.fpu.dec.fromint, fpuOpt.io.dec.fromint
connect core.io.fpu.dec.typeTagOut, fpuOpt.io.dec.typeTagOut
connect core.io.fpu.dec.typeTagIn, fpuOpt.io.dec.typeTagIn
connect core.io.fpu.dec.swap23, fpuOpt.io.dec.swap23
connect core.io.fpu.dec.swap12, fpuOpt.io.dec.swap12
connect core.io.fpu.dec.ren3, fpuOpt.io.dec.ren3
connect core.io.fpu.dec.ren2, fpuOpt.io.dec.ren2
connect core.io.fpu.dec.ren1, fpuOpt.io.dec.ren1
connect core.io.fpu.dec.wen, fpuOpt.io.dec.wen
connect core.io.fpu.dec.ldst, fpuOpt.io.dec.ldst
connect fpuOpt.io.killm, core.io.fpu.killm
connect fpuOpt.io.killx, core.io.fpu.killx
connect core.io.fpu.illegal_rm, fpuOpt.io.illegal_rm
connect core.io.fpu.nack_mem, fpuOpt.io.nack_mem
connect core.io.fpu.fcsr_rdy, fpuOpt.io.fcsr_rdy
connect fpuOpt.io.valid, core.io.fpu.valid
connect fpuOpt.io.ll_resp_data, core.io.fpu.ll_resp_data
connect fpuOpt.io.ll_resp_tag, core.io.fpu.ll_resp_tag
connect fpuOpt.io.ll_resp_type, core.io.fpu.ll_resp_type
connect fpuOpt.io.ll_resp_val, core.io.fpu.ll_resp_val
connect core.io.fpu.toint_data, fpuOpt.io.toint_data
connect core.io.fpu.store_data, fpuOpt.io.store_data
connect fpuOpt.io.v_sew, core.io.fpu.v_sew
connect core.io.fpu.fcsr_flags.bits, fpuOpt.io.fcsr_flags.bits
connect core.io.fpu.fcsr_flags.valid, fpuOpt.io.fcsr_flags.valid
connect fpuOpt.io.fcsr_rm, core.io.fpu.fcsr_rm
connect fpuOpt.io.fromint_data, core.io.fpu.fromint_data
connect fpuOpt.io.inst, core.io.fpu.inst
connect fpuOpt.io.time, core.io.fpu.time
connect fpuOpt.io.hartid, core.io.fpu.hartid
connect core.io.ptw, ptw.io.dpath
connect cmdRouter.io.in, core.io.rocc.cmd
connect gemmini.io.exception, core.io.rocc.exception
invalidate gemmini.io.fpu_req.ready
invalidate gemmini.io.fpu_resp.valid
invalidate gemmini.io.fpu_resp.bits.data
invalidate gemmini.io.fpu_resp.bits.exc
connect core.io.rocc.resp, respArb.io.out
node _core_io_rocc_busy_T = or(cmdRouter.io.busy, gemmini.io.busy)
connect core.io.rocc.busy, _core_io_rocc_busy_T
connect core.io.rocc.interrupt, gemmini.io.interrupt
invalidate core.io.rocc.mem.clock_enabled
invalidate core.io.rocc.mem.keep_clock_enabled
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterStore
invalidate core.io.rocc.mem.perf.storeBufferEmptyAfterLoad
invalidate core.io.rocc.mem.perf.canAcceptLoadThenLoad
invalidate core.io.rocc.mem.perf.canAcceptStoreThenRMW
invalidate core.io.rocc.mem.perf.canAcceptStoreThenLoad
invalidate core.io.rocc.mem.perf.blocked
invalidate core.io.rocc.mem.perf.tlbMiss
invalidate core.io.rocc.mem.perf.grant
invalidate core.io.rocc.mem.perf.release
invalidate core.io.rocc.mem.perf.acquire
invalidate core.io.rocc.mem.store_pending
invalidate core.io.rocc.mem.ordered
invalidate core.io.rocc.mem.s2_gpa_is_pte
invalidate core.io.rocc.mem.s2_gpa
invalidate core.io.rocc.mem.s2_xcpt.ae.st
invalidate core.io.rocc.mem.s2_xcpt.ae.ld
invalidate core.io.rocc.mem.s2_xcpt.gf.st
invalidate core.io.rocc.mem.s2_xcpt.gf.ld
invalidate core.io.rocc.mem.s2_xcpt.pf.st
invalidate core.io.rocc.mem.s2_xcpt.pf.ld
invalidate core.io.rocc.mem.s2_xcpt.ma.st
invalidate core.io.rocc.mem.s2_xcpt.ma.ld
invalidate core.io.rocc.mem.replay_next
invalidate core.io.rocc.mem.resp.bits.store_data
invalidate core.io.rocc.mem.resp.bits.data_raw
invalidate core.io.rocc.mem.resp.bits.data_word_bypass
invalidate core.io.rocc.mem.resp.bits.has_data
invalidate core.io.rocc.mem.resp.bits.replay
invalidate core.io.rocc.mem.resp.bits.mask
invalidate core.io.rocc.mem.resp.bits.data
invalidate core.io.rocc.mem.resp.bits.dv
invalidate core.io.rocc.mem.resp.bits.dprv
invalidate core.io.rocc.mem.resp.bits.signed
invalidate core.io.rocc.mem.resp.bits.size
invalidate core.io.rocc.mem.resp.bits.cmd
invalidate core.io.rocc.mem.resp.bits.tag
invalidate core.io.rocc.mem.resp.bits.addr
invalidate core.io.rocc.mem.resp.valid
invalidate core.io.rocc.mem.s2_paddr
invalidate core.io.rocc.mem.s2_uncached
invalidate core.io.rocc.mem.s2_kill
invalidate core.io.rocc.mem.s2_nack_cause_raw
invalidate core.io.rocc.mem.s2_nack
invalidate core.io.rocc.mem.s1_data.mask
invalidate core.io.rocc.mem.s1_data.data
invalidate core.io.rocc.mem.s1_kill
invalidate core.io.rocc.mem.req.bits.mask
invalidate core.io.rocc.mem.req.bits.data
invalidate core.io.rocc.mem.req.bits.no_xcpt
invalidate core.io.rocc.mem.req.bits.no_alloc
invalidate core.io.rocc.mem.req.bits.no_resp
invalidate core.io.rocc.mem.req.bits.phys
invalidate core.io.rocc.mem.req.bits.dv
invalidate core.io.rocc.mem.req.bits.dprv
invalidate core.io.rocc.mem.req.bits.signed
invalidate core.io.rocc.mem.req.bits.size
invalidate core.io.rocc.mem.req.bits.cmd
invalidate core.io.rocc.mem.req.bits.tag
invalidate core.io.rocc.mem.req.bits.addr
invalidate core.io.rocc.mem.req.valid
invalidate core.io.rocc.mem.req.ready
connect dcacheArb.io.requestor[0], ptw.io.mem
connect dcacheArb.io.requestor[1], dcIF.io.cache
connect dcacheArb.io.requestor[2], core.io.dmem
connect ptw.io.requestor[0], gemmini.io.ptw[0]
connect ptw.io.requestor[1], dcache.io.ptw
connect ptw.io.requestor[2], frontend.io.ptw | module RocketTile( // @[RocketTile.scala:141:7]
input clock, // @[RocketTile.scala:141:7]
input reset, // @[RocketTile.scala:141:7]
input auto_buffer_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_buffer_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_1_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_out_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_buffer_out_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_1_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_out_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_1_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_1_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_buffer_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_buffer_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_buffer_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_wfi_out_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_insns_0_valid, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_trace_source_out_insns_0_iaddr, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_trace_source_out_insns_0_insn, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_trace_source_out_insns_0_priv, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_insns_0_exception, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_insns_0_interrupt, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_insns_0_cause, // @[LazyModuleImp.scala:107:25]
output [39:0] auto_trace_source_out_insns_0_tval, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
input auto_hartid_in // @[LazyModuleImp.scala:107:25]
);
wire buffer_auto_in_0_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_0_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_0_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_0_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_in_0_d_bits_denied; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_0_d_bits_sink; // @[Buffer.scala:40:9]
wire [6:0] buffer_auto_in_0_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_0_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_0_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_0_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_0_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_0_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_0_a_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_0_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_0_a_bits_address; // @[Buffer.scala:40:9]
wire [6:0] buffer_auto_in_0_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_0_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_0_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_e_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_e_ready; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_1_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_1_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_d_bits_denied; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_1_d_bits_sink; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_1_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_1_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_1_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_1_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_c_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_c_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_1_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_1_c_bits_address; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_1_c_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_1_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_1_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_1_c_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_b_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_b_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_1_b_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_1_b_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_1_b_bits_address; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_1_b_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_1_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_1_b_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_1_b_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_a_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_1_a_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_1_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_1_a_bits_address; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_1_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_1_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_1_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9]
wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] broadcast_2_auto_in_0_action; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_auto_in_0_valid_0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9]
wire _core_io_imem_might_request; // @[RocketTile.scala:147:20]
wire _core_io_imem_req_valid; // @[RocketTile.scala:147:20]
wire [39:0] _core_io_imem_req_bits_pc; // @[RocketTile.scala:147:20]
wire _core_io_imem_req_bits_speculative; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_valid; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_rs1; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_rs2; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_sfence_bits_addr; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_asid; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_hv; // @[RocketTile.scala:147:20]
wire _core_io_imem_sfence_bits_hg; // @[RocketTile.scala:147:20]
wire _core_io_imem_resp_ready; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_valid; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_imem_btb_update_bits_prediction_cfiType; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_prediction_taken; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_imem_btb_update_bits_prediction_mask; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_prediction_bridx; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_prediction_target; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_imem_btb_update_bits_prediction_bht_history; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_prediction_bht_value; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_pc; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_target; // @[RocketTile.scala:147:20]
wire _core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_valid; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_prediction_value; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_imem_bht_update_bits_pc; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_branch; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_taken; // @[RocketTile.scala:147:20]
wire _core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala:147:20]
wire _core_io_imem_flush_icache; // @[RocketTile.scala:147:20]
wire _core_io_imem_progress; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_valid; // @[RocketTile.scala:147:20]
wire [39:0] _core_io_dmem_req_bits_addr; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_dmem_req_bits_tag; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_dmem_req_bits_cmd; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_dmem_req_bits_size; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_bits_signed; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_dmem_req_bits_dprv; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_bits_dv; // @[RocketTile.scala:147:20]
wire _core_io_dmem_req_bits_no_resp; // @[RocketTile.scala:147:20]
wire _core_io_dmem_s1_kill; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_dmem_s1_data_data; // @[RocketTile.scala:147:20]
wire _core_io_dmem_keep_clock_enabled; // @[RocketTile.scala:147:20]
wire [3:0] _core_io_ptw_ptbr_mode; // @[RocketTile.scala:147:20]
wire [43:0] _core_io_ptw_ptbr_ppn; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_valid; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_rs1; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_rs2; // @[RocketTile.scala:147:20]
wire [38:0] _core_io_ptw_sfence_bits_addr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_asid; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_hv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_sfence_bits_hg; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_debug; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_cease; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_wfi; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_status_isa; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_dprv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_dv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_prv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_v; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mpv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_gva; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_tsr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_tw; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_tvm; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mxr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_sum; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mprv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_fs; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_status_mpp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_spp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mpie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_spie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_mie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_status_sie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_hstatus_spvp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_hstatus_spv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_hstatus_gva; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_debug; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_cease; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_wfi; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_gstatus_isa; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_dprv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_dv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_prv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_v; // @[RocketTile.scala:147:20]
wire [22:0] _core_io_ptw_gstatus_zero2; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mpv; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_gva; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mbe; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sbe; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_sxl; // @[RocketTile.scala:147:20]
wire [7:0] _core_io_ptw_gstatus_zero1; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_tsr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_tw; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_tvm; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mxr; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sum; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mprv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_fs; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_mpp; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_gstatus_vs; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_spp; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mpie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_ube; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_spie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_upie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_mie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_hie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_sie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_gstatus_uie; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_0_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_0_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_1_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_1_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_2_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_2_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_3_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_3_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_4_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_4_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_5_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_5_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_6_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_6_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala:147:20]
wire _core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala:147:20]
wire [29:0] _core_io_ptw_pmp_7_addr; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_ptw_pmp_7_mask; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_0_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_0_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_0_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_1_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_1_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_1_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_1_value; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_2_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_2_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_2_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_2_value; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_3_ren; // @[RocketTile.scala:147:20]
wire _core_io_ptw_customCSRs_csrs_3_wen; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_3_wdata; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_ptw_customCSRs_csrs_3_value; // @[RocketTile.scala:147:20]
wire _core_io_fpu_hartid; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_fpu_time; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_fpu_inst; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_fpu_fromint_data; // @[RocketTile.scala:147:20]
wire [2:0] _core_io_fpu_fcsr_rm; // @[RocketTile.scala:147:20]
wire _core_io_fpu_ll_resp_val; // @[RocketTile.scala:147:20]
wire [2:0] _core_io_fpu_ll_resp_type; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_fpu_ll_resp_tag; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_fpu_ll_resp_data; // @[RocketTile.scala:147:20]
wire _core_io_fpu_valid; // @[RocketTile.scala:147:20]
wire _core_io_fpu_killx; // @[RocketTile.scala:147:20]
wire _core_io_fpu_killm; // @[RocketTile.scala:147:20]
wire _core_io_fpu_keep_clock_enabled; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_valid; // @[RocketTile.scala:147:20]
wire [6:0] _core_io_rocc_cmd_bits_inst_funct; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_rocc_cmd_bits_inst_rs2; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_rocc_cmd_bits_inst_rs1; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_inst_xd; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_inst_xs1; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_inst_xs2; // @[RocketTile.scala:147:20]
wire [4:0] _core_io_rocc_cmd_bits_inst_rd; // @[RocketTile.scala:147:20]
wire [6:0] _core_io_rocc_cmd_bits_inst_opcode; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_rocc_cmd_bits_rs1; // @[RocketTile.scala:147:20]
wire [63:0] _core_io_rocc_cmd_bits_rs2; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_debug; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_cease; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_wfi; // @[RocketTile.scala:147:20]
wire [31:0] _core_io_rocc_cmd_bits_status_isa; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_rocc_cmd_bits_status_dprv; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_dv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_rocc_cmd_bits_status_prv; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_v; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_mpv; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_gva; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_tsr; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_tw; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_tvm; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_mxr; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_sum; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_mprv; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_rocc_cmd_bits_status_fs; // @[RocketTile.scala:147:20]
wire [1:0] _core_io_rocc_cmd_bits_status_mpp; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_spp; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_mpie; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_spie; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_mie; // @[RocketTile.scala:147:20]
wire _core_io_rocc_cmd_bits_status_sie; // @[RocketTile.scala:147:20]
wire _core_io_rocc_resp_ready; // @[RocketTile.scala:147:20]
wire _core_io_rocc_exception; // @[RocketTile.scala:147:20]
wire _core_io_wfi; // @[RocketTile.scala:147:20]
wire _respArb_io_in_0_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _respArb_io_in_0_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [4:0] _respArb_io_in_0_q_io_deq_bits_rd; // @[Decoupled.scala:362:21]
wire [63:0] _respArb_io_in_0_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _dcIF_io_requestor_req_ready; // @[LazyRoCC.scala:106:24]
wire _dcIF_io_requestor_resp_valid; // @[LazyRoCC.scala:106:24]
wire [39:0] _dcIF_io_requestor_resp_bits_addr; // @[LazyRoCC.scala:106:24]
wire [7:0] _dcIF_io_requestor_resp_bits_tag; // @[LazyRoCC.scala:106:24]
wire [4:0] _dcIF_io_requestor_resp_bits_cmd; // @[LazyRoCC.scala:106:24]
wire [1:0] _dcIF_io_requestor_resp_bits_size; // @[LazyRoCC.scala:106:24]
wire _dcIF_io_requestor_resp_bits_signed; // @[LazyRoCC.scala:106:24]
wire [1:0] _dcIF_io_requestor_resp_bits_dprv; // @[LazyRoCC.scala:106:24]
wire _dcIF_io_requestor_resp_bits_dv; // @[LazyRoCC.scala:106:24]
wire [63:0] _dcIF_io_requestor_resp_bits_data; // @[LazyRoCC.scala:106:24]
wire [7:0] _dcIF_io_requestor_resp_bits_mask; // @[LazyRoCC.scala:106:24]
wire _dcIF_io_requestor_resp_bits_replay; // @[LazyRoCC.scala:106:24]
wire _dcIF_io_requestor_resp_bits_has_data; // @[LazyRoCC.scala:106:24]
wire [63:0] _dcIF_io_requestor_resp_bits_data_word_bypass; // @[LazyRoCC.scala:106:24]
wire [63:0] _dcIF_io_requestor_resp_bits_data_raw; // @[LazyRoCC.scala:106:24]
wire [63:0] _dcIF_io_requestor_resp_bits_store_data; // @[LazyRoCC.scala:106:24]
wire _dcIF_io_cache_req_valid; // @[LazyRoCC.scala:106:24]
wire [63:0] _dcIF_io_cache_s1_data_data; // @[LazyRoCC.scala:106:24]
wire [7:0] _dcIF_io_cache_s1_data_mask; // @[LazyRoCC.scala:106:24]
wire _cmdRouter_io_in_ready; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_valid; // @[LazyRoCC.scala:102:27]
wire [6:0] _cmdRouter_io_out_0_bits_inst_funct; // @[LazyRoCC.scala:102:27]
wire [4:0] _cmdRouter_io_out_0_bits_inst_rs2; // @[LazyRoCC.scala:102:27]
wire [4:0] _cmdRouter_io_out_0_bits_inst_rs1; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_inst_xd; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_inst_xs1; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_inst_xs2; // @[LazyRoCC.scala:102:27]
wire [4:0] _cmdRouter_io_out_0_bits_inst_rd; // @[LazyRoCC.scala:102:27]
wire [6:0] _cmdRouter_io_out_0_bits_inst_opcode; // @[LazyRoCC.scala:102:27]
wire [63:0] _cmdRouter_io_out_0_bits_rs1; // @[LazyRoCC.scala:102:27]
wire [63:0] _cmdRouter_io_out_0_bits_rs2; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_debug; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_cease; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_wfi; // @[LazyRoCC.scala:102:27]
wire [31:0] _cmdRouter_io_out_0_bits_status_isa; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_dprv; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_dv; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_prv; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_v; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_sd; // @[LazyRoCC.scala:102:27]
wire [22:0] _cmdRouter_io_out_0_bits_status_zero2; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_mpv; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_gva; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_mbe; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_sbe; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_sxl; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_uxl; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_sd_rv32; // @[LazyRoCC.scala:102:27]
wire [7:0] _cmdRouter_io_out_0_bits_status_zero1; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_tsr; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_tw; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_tvm; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_mxr; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_sum; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_mprv; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_xs; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_fs; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_mpp; // @[LazyRoCC.scala:102:27]
wire [1:0] _cmdRouter_io_out_0_bits_status_vs; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_spp; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_mpie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_ube; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_spie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_upie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_mie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_hie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_sie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_out_0_bits_status_uie; // @[LazyRoCC.scala:102:27]
wire _cmdRouter_io_busy; // @[LazyRoCC.scala:102:27]
wire _respArb_io_in_0_ready; // @[LazyRoCC.scala:101:25]
wire _respArb_io_out_valid; // @[LazyRoCC.scala:101:25]
wire [4:0] _respArb_io_out_bits_rd; // @[LazyRoCC.scala:101:25]
wire [63:0] _respArb_io_out_bits_data; // @[LazyRoCC.scala:101:25]
wire _ptw_io_requestor_0_req_ready; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_valid; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_ae_final; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_gf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_hr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_hw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_hx; // @[PTW.scala:802:19]
wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_d; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_g; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_u; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_r; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_pte_v; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[PTW.scala:802:19]
wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[PTW.scala:802:19]
wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_status_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_status_mpp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_status_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_hstatus_spvp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_hstatus_spv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_hstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_gstatus_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_v; // @[PTW.scala:802:19]
wire [22:0] _ptw_io_requestor_0_gstatus_zero2; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mbe; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sbe; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_sxl; // @[PTW.scala:802:19]
wire [7:0] _ptw_io_requestor_0_gstatus_zero1; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_mpp; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_gstatus_vs; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_ube; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_upie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_hie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_gstatus_uie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_0_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_0_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_0_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_1_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_1_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_1_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_2_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_2_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_2_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_3_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_0_customCSRs_csrs_3_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_0_customCSRs_csrs_3_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_req_ready; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_valid; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_ae_final; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_gf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_hr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_hw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_hx; // @[PTW.scala:802:19]
wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_d; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_g; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_u; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_r; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_pte_v; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[PTW.scala:802:19]
wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[PTW.scala:802:19]
wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_status_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_status_mpp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_status_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_hstatus_spvp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_hstatus_spv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_hstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_gstatus_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_v; // @[PTW.scala:802:19]
wire [22:0] _ptw_io_requestor_1_gstatus_zero2; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mbe; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sbe; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_sxl; // @[PTW.scala:802:19]
wire [7:0] _ptw_io_requestor_1_gstatus_zero1; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_mpp; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_gstatus_vs; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_ube; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_upie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_hie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_gstatus_uie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_0_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_0_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_1_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_1_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_1_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_2_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_2_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_2_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_3_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_1_customCSRs_csrs_3_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_1_customCSRs_csrs_3_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_req_ready; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_valid; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_ae_final; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_gf; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_hr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_hw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_hx; // @[PTW.scala:802:19]
wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_d; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_g; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_u; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_r; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_pte_v; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[PTW.scala:802:19]
wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[PTW.scala:802:19]
wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[PTW.scala:802:19]
wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_status_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_status_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_status_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_v; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_status_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_status_mpp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_status_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_hstatus_spvp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_hstatus_spv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_hstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_debug; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_cease; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_wfi; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_gstatus_isa; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_gstatus_dprv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_dv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_gstatus_prv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_v; // @[PTW.scala:802:19]
wire [22:0] _ptw_io_requestor_2_gstatus_zero2; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_mpv; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_gva; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_mbe; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_sbe; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_gstatus_sxl; // @[PTW.scala:802:19]
wire [7:0] _ptw_io_requestor_2_gstatus_zero1; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_tsr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_tw; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_tvm; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_mxr; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_sum; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_mprv; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_gstatus_fs; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_gstatus_mpp; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_gstatus_vs; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_spp; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_mpie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_ube; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_spie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_upie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_mie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_hie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_sie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_gstatus_uie; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[PTW.scala:802:19]
wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[PTW.scala:802:19]
wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[PTW.scala:802:19]
wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_0_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_0_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_0_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_0_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_1_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_1_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_1_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_1_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_2_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_2_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_2_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_2_value; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_3_ren; // @[PTW.scala:802:19]
wire _ptw_io_requestor_2_customCSRs_csrs_3_wen; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_3_wdata; // @[PTW.scala:802:19]
wire [63:0] _ptw_io_requestor_2_customCSRs_csrs_3_value; // @[PTW.scala:802:19]
wire _ptw_io_mem_req_valid; // @[PTW.scala:802:19]
wire [39:0] _ptw_io_mem_req_bits_addr; // @[PTW.scala:802:19]
wire _ptw_io_mem_req_bits_dv; // @[PTW.scala:802:19]
wire _ptw_io_mem_s1_kill; // @[PTW.scala:802:19]
wire _ptw_io_dpath_perf_pte_miss; // @[PTW.scala:802:19]
wire _ptw_io_dpath_perf_pte_hit; // @[PTW.scala:802:19]
wire _ptw_io_dpath_clock_enabled; // @[PTW.scala:802:19]
wire _dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_uncached; // @[HellaCache.scala:292:25]
wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_store_pending; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_acquire; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_blocked; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_req_ready; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_nack; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_uncached; // @[HellaCache.scala:292:25]
wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_replay_next; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_ordered; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_store_pending; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_acquire; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_release; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_grant; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_blocked; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_req_ready; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_nack; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_nack_cause_raw; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_uncached; // @[HellaCache.scala:292:25]
wire [31:0] _dcacheArb_io_requestor_2_s2_paddr; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_resp_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_2_resp_bits_addr; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_2_resp_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_requestor_2_resp_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_2_resp_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_resp_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_requestor_2_resp_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_resp_bits_dv; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_requestor_2_resp_bits_mask; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_resp_bits_replay; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_resp_bits_has_data; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_word_bypass; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_2_resp_bits_data_raw; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_requestor_2_resp_bits_store_data; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_replay_next; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_xcpt_ma_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_xcpt_ma_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_xcpt_pf_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_xcpt_pf_st; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_xcpt_ae_ld; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_s2_xcpt_ae_st; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_requestor_2_s2_gpa; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_ordered; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_store_pending; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_acquire; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_release; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_grant; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_tlbMiss; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_blocked; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_valid; // @[HellaCache.scala:292:25]
wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala:292:25]
wire [4:0] _dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala:292:25]
wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_dv; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_phys; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_req_bits_no_resp; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_s1_kill; // @[HellaCache.scala:292:25]
wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala:292:25]
wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[HellaCache.scala:292:25]
wire _dcacheArb_io_mem_keep_clock_enabled; // @[HellaCache.scala:292:25]
wire _fpuOpt_io_fcsr_flags_valid; // @[RocketTile.scala:242:62]
wire [4:0] _fpuOpt_io_fcsr_flags_bits; // @[RocketTile.scala:242:62]
wire [63:0] _fpuOpt_io_store_data; // @[RocketTile.scala:242:62]
wire [63:0] _fpuOpt_io_toint_data; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_fcsr_rdy; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_nack_mem; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_illegal_rm; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ldst; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_wen; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ren1; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ren2; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_ren3; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_swap12; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_swap23; // @[RocketTile.scala:242:62]
wire [1:0] _fpuOpt_io_dec_typeTagIn; // @[RocketTile.scala:242:62]
wire [1:0] _fpuOpt_io_dec_typeTagOut; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_fromint; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_toint; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_fastpipe; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_fma; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_div; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_sqrt; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_wflags; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_dec_vec; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_sboard_set; // @[RocketTile.scala:242:62]
wire _fpuOpt_io_sboard_clr; // @[RocketTile.scala:242:62]
wire [4:0] _fpuOpt_io_sboard_clra; // @[RocketTile.scala:242:62]
wire _frontend_io_cpu_resp_valid; // @[Frontend.scala:393:28]
wire [1:0] _frontend_io_cpu_resp_bits_btb_cfiType; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala:393:28]
wire [1:0] _frontend_io_cpu_resp_bits_btb_mask; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala:393:28]
wire [38:0] _frontend_io_cpu_resp_bits_btb_target; // @[Frontend.scala:393:28]
wire [4:0] _frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala:393:28]
wire [7:0] _frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_btb_bht_value; // @[Frontend.scala:393:28]
wire [39:0] _frontend_io_cpu_resp_bits_pc; // @[Frontend.scala:393:28]
wire [31:0] _frontend_io_cpu_resp_bits_data; // @[Frontend.scala:393:28]
wire [1:0] _frontend_io_cpu_resp_bits_mask; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_xcpt_pf_inst; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_xcpt_gf_inst; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_resp_bits_replay; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_gpa_valid; // @[Frontend.scala:393:28]
wire [39:0] _frontend_io_cpu_gpa_bits; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_gpa_is_pte; // @[Frontend.scala:393:28]
wire [39:0] _frontend_io_cpu_npc; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_perf_acquire; // @[Frontend.scala:393:28]
wire _frontend_io_cpu_perf_tlbMiss; // @[Frontend.scala:393:28]
wire _frontend_io_ptw_req_valid; // @[Frontend.scala:393:28]
wire _frontend_io_ptw_req_bits_valid; // @[Frontend.scala:393:28]
wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[Frontend.scala:393:28]
wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[Frontend.scala:393:28]
wire _gemmini_io_cmd_ready; // @[Configs.scala:282:31]
wire _gemmini_io_resp_valid; // @[Configs.scala:282:31]
wire [4:0] _gemmini_io_resp_bits_rd; // @[Configs.scala:282:31]
wire [63:0] _gemmini_io_resp_bits_data; // @[Configs.scala:282:31]
wire _gemmini_io_busy; // @[Configs.scala:282:31]
wire _gemmini_io_interrupt; // @[Configs.scala:282:31]
wire _gemmini_io_ptw_0_req_valid; // @[Configs.scala:282:31]
wire [26:0] _gemmini_io_ptw_0_req_bits_bits_addr; // @[Configs.scala:282:31]
wire _gemmini_io_ptw_0_req_bits_bits_need_gpa; // @[Configs.scala:282:31]
wire _dcache_io_cpu_req_ready; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_nack; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_nack_cause_raw; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_uncached; // @[HellaCache.scala:278:43]
wire [31:0] _dcache_io_cpu_s2_paddr; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_valid; // @[HellaCache.scala:278:43]
wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala:278:43]
wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala:278:43]
wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala:278:43]
wire [1:0] _dcache_io_cpu_resp_bits_size; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala:278:43]
wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_data; // @[HellaCache.scala:278:43]
wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala:278:43]
wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_replay_next; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala:278:43]
wire [39:0] _dcache_io_cpu_s2_gpa; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_ordered; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_store_pending; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_acquire; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_release; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_grant; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_tlbMiss; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_blocked; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[HellaCache.scala:278:43]
wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[HellaCache.scala:278:43]
wire _dcache_io_ptw_req_valid; // @[HellaCache.scala:278:43]
wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[HellaCache.scala:278:43]
wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[HellaCache.scala:278:43]
wire auto_buffer_out_1_a_ready_0 = auto_buffer_out_1_a_ready; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_b_valid_0 = auto_buffer_out_1_b_valid; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_1_b_bits_opcode_0 = auto_buffer_out_1_b_bits_opcode; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_1_b_bits_param_0 = auto_buffer_out_1_b_bits_param; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_1_b_bits_size_0 = auto_buffer_out_1_b_bits_size; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_1_b_bits_source_0 = auto_buffer_out_1_b_bits_source; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_1_b_bits_address_0 = auto_buffer_out_1_b_bits_address; // @[RocketTile.scala:141:7]
wire [15:0] auto_buffer_out_1_b_bits_mask_0 = auto_buffer_out_1_b_bits_mask; // @[RocketTile.scala:141:7]
wire [127:0] auto_buffer_out_1_b_bits_data_0 = auto_buffer_out_1_b_bits_data; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_b_bits_corrupt_0 = auto_buffer_out_1_b_bits_corrupt; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_c_ready_0 = auto_buffer_out_1_c_ready; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_d_valid_0 = auto_buffer_out_1_d_valid; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_1_d_bits_opcode_0 = auto_buffer_out_1_d_bits_opcode; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_1_d_bits_param_0 = auto_buffer_out_1_d_bits_param; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_1_d_bits_size_0 = auto_buffer_out_1_d_bits_size; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_1_d_bits_source_0 = auto_buffer_out_1_d_bits_source; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_1_d_bits_sink_0 = auto_buffer_out_1_d_bits_sink; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_d_bits_denied_0 = auto_buffer_out_1_d_bits_denied; // @[RocketTile.scala:141:7]
wire [127:0] auto_buffer_out_1_d_bits_data_0 = auto_buffer_out_1_d_bits_data; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_d_bits_corrupt_0 = auto_buffer_out_1_d_bits_corrupt; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_e_ready_0 = auto_buffer_out_1_e_ready; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_a_ready_0 = auto_buffer_out_0_a_ready; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_d_valid_0 = auto_buffer_out_0_d_valid; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_0_d_bits_opcode_0 = auto_buffer_out_0_d_bits_opcode; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_0_d_bits_param_0 = auto_buffer_out_0_d_bits_param; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_0_d_bits_size_0 = auto_buffer_out_0_d_bits_size; // @[RocketTile.scala:141:7]
wire [6:0] auto_buffer_out_0_d_bits_source_0 = auto_buffer_out_0_d_bits_source; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_0_d_bits_sink_0 = auto_buffer_out_0_d_bits_sink; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_d_bits_denied_0 = auto_buffer_out_0_d_bits_denied; // @[RocketTile.scala:141:7]
wire [127:0] auto_buffer_out_0_d_bits_data_0 = auto_buffer_out_0_d_bits_data; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_d_bits_corrupt_0 = auto_buffer_out_0_d_bits_corrupt; // @[RocketTile.scala:141:7]
wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[RocketTile.scala:141:7]
wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[RocketTile.scala:141:7]
wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[RocketTile.scala:141:7]
wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[RocketTile.scala:141:7]
wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[RocketTile.scala:141:7]
wire auto_hartid_in_0 = auto_hartid_in; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_a_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_c_bits_corrupt = 1'h0; // @[RocketTile.scala:141:7]
wire auto_cease_out_0 = 1'h0; // @[RocketTile.scala:141:7]
wire auto_halt_out_0 = 1'h0; // @[RocketTile.scala:141:7]
wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[RocketTile.scala:141:7]
wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[RocketTile.scala:141:7]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire broadcast_2_auto_in_0_rvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_auto_in_0_wvalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_auto_in_0_ivalid_0 = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_2_nodeIn_0_rvalid_0 = 1'h0; // @[MixedNode.scala:551:17]
wire broadcast_2_nodeIn_0_wvalid_0 = 1'h0; // @[MixedNode.scala:551:17]
wire broadcast_2_nodeIn_0_ivalid_0 = 1'h0; // @[MixedNode.scala:551:17]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_auto_in_1_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_1_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_x1_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire x1_tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17]
wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17]
wire bpwatchSourceNodeOut_0_rvalid_0 = 1'h0; // @[MixedNode.scala:542:17]
wire bpwatchSourceNodeOut_0_wvalid_0 = 1'h0; // @[MixedNode.scala:542:17]
wire bpwatchSourceNodeOut_0_ivalid_0 = 1'h0; // @[MixedNode.scala:542:17]
wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_in_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_out_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonOut_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonIn_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonIn_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_reset_vector_in = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_auto_in = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] reset_vectorOut = 32'h10000; // @[RocketTile.scala:141:7]
wire [31:0] reset_vectorIn = 32'h10000; // @[RocketTile.scala:141:7]
wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[RocketTile.scala:141:7]
wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[RocketTile.scala:141:7]
wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[RocketTile.scala:141:7]
wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[RocketTile.scala:141:7]
wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[RocketTile.scala:141:7]
wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire buffer_auto_out_1_a_ready = auto_buffer_out_1_a_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_1_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_1_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_1_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_1_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_1_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_1_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_1_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_b_valid = auto_buffer_out_1_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_1_b_bits_opcode = auto_buffer_out_1_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_1_b_bits_param = auto_buffer_out_1_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_1_b_bits_size = auto_buffer_out_1_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_1_b_bits_source = auto_buffer_out_1_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_1_b_bits_address = auto_buffer_out_1_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_1_b_bits_mask = auto_buffer_out_1_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_1_b_bits_data = auto_buffer_out_1_b_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_b_bits_corrupt = auto_buffer_out_1_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_c_ready = auto_buffer_out_1_c_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_1_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_1_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_1_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_1_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_1_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_1_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_d_valid = auto_buffer_out_1_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_1_d_bits_opcode = auto_buffer_out_1_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_1_d_bits_param = auto_buffer_out_1_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_1_d_bits_size = auto_buffer_out_1_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_1_d_bits_source = auto_buffer_out_1_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_1_d_bits_sink = auto_buffer_out_1_d_bits_sink_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_d_bits_denied = auto_buffer_out_1_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_1_d_bits_data = auto_buffer_out_1_d_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_d_bits_corrupt = auto_buffer_out_1_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_e_ready = auto_buffer_out_1_e_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_1_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_1_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_a_ready = auto_buffer_out_0_a_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_0_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_0_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_0_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] buffer_auto_out_0_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_0_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_0_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_0_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_a_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_d_valid = auto_buffer_out_0_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_0_d_bits_opcode = auto_buffer_out_0_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_0_d_bits_param = auto_buffer_out_0_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_0_d_bits_size = auto_buffer_out_0_d_bits_size_0; // @[Buffer.scala:40:9]
wire [6:0] buffer_auto_out_0_d_bits_source = auto_buffer_out_0_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_0_d_bits_sink = auto_buffer_out_0_d_bits_sink_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_d_bits_denied = auto_buffer_out_0_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_0_d_bits_data = auto_buffer_out_0_d_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_0_d_bits_corrupt = auto_buffer_out_0_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire wfiNodeOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[RocketTile.scala:141:7]
wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[RocketTile.scala:141:7]
wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[RocketTile.scala:141:7]
wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[RocketTile.scala:141:7]
wire int_localIn_0 = auto_int_local_in_0_0_0; // @[RocketTile.scala:141:7]
wire traceSourceNodeOut_insns_0_valid; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_iaddr; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_0_insn; // @[MixedNode.scala:542:17]
wire [2:0] traceSourceNodeOut_insns_0_priv; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_exception; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_interrupt; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_0_cause; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_tval; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
wire hartidIn = auto_hartid_in_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_1_a_bits_opcode_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_1_a_bits_param_0; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_1_a_bits_size_0; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_1_a_bits_source_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_1_a_bits_address_0; // @[RocketTile.scala:141:7]
wire [15:0] auto_buffer_out_1_a_bits_mask_0; // @[RocketTile.scala:141:7]
wire [127:0] auto_buffer_out_1_a_bits_data_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_a_valid_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_b_ready_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_1_c_bits_opcode_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_1_c_bits_param_0; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_1_c_bits_size_0; // @[RocketTile.scala:141:7]
wire [1:0] auto_buffer_out_1_c_bits_source_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_1_c_bits_address_0; // @[RocketTile.scala:141:7]
wire [127:0] auto_buffer_out_1_c_bits_data_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_c_valid_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_d_ready_0; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_1_e_bits_sink_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_1_e_valid_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_0_a_bits_opcode_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_buffer_out_0_a_bits_param_0; // @[RocketTile.scala:141:7]
wire [3:0] auto_buffer_out_0_a_bits_size_0; // @[RocketTile.scala:141:7]
wire [6:0] auto_buffer_out_0_a_bits_source_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_buffer_out_0_a_bits_address_0; // @[RocketTile.scala:141:7]
wire [15:0] auto_buffer_out_0_a_bits_mask_0; // @[RocketTile.scala:141:7]
wire [127:0] auto_buffer_out_0_a_bits_data_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_a_bits_corrupt_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_a_valid_0; // @[RocketTile.scala:141:7]
wire auto_buffer_out_0_d_ready_0; // @[RocketTile.scala:141:7]
wire auto_wfi_out_0_0; // @[RocketTile.scala:141:7]
wire auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7]
wire [39:0] auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7]
wire [31:0] auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7]
wire [2:0] auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7]
wire auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7]
wire auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7]
wire [63:0] auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7]
wire [39:0] auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7]
wire [63:0] auto_trace_source_out_time_0; // @[RocketTile.scala:141:7]
wire hartidOut; // @[MixedNode.scala:542:17]
wire broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17]
wire broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9]
wire hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17]
assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17]
wire broadcast_2_nodeIn_0_valid_0 = broadcast_2_auto_in_0_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17]
wire [2:0] broadcast_2_nodeIn_0_action = broadcast_2_auto_in_0_action; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire buffer_x1_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_a_ready = buffer_auto_in_1_a_ready; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeIn_a_valid = buffer_auto_in_1_a_valid; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_x1_nodeIn_a_bits_opcode = buffer_auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_x1_nodeIn_a_bits_param = buffer_auto_in_1_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] x1_tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_x1_nodeIn_a_bits_size = buffer_auto_in_1_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] x1_tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] buffer_x1_nodeIn_a_bits_source = buffer_auto_in_1_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] x1_tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_x1_nodeIn_a_bits_address = buffer_auto_in_1_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] x1_tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [15:0] buffer_x1_nodeIn_a_bits_mask = buffer_auto_in_1_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] x1_tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_x1_nodeIn_a_bits_data = buffer_auto_in_1_a_bits_data; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeIn_b_ready = buffer_auto_in_1_b_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_x1_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_b_valid = buffer_auto_in_1_b_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] x1_tlOtherMastersNodeOut_b_bits_opcode = buffer_auto_in_1_b_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] x1_tlOtherMastersNodeOut_b_bits_param = buffer_auto_in_1_b_bits_param; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] x1_tlOtherMastersNodeOut_b_bits_size = buffer_auto_in_1_b_bits_size; // @[Buffer.scala:40:9]
wire [31:0] buffer_x1_nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [1:0] x1_tlOtherMastersNodeOut_b_bits_source = buffer_auto_in_1_b_bits_source; // @[Buffer.scala:40:9]
wire [15:0] buffer_x1_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] x1_tlOtherMastersNodeOut_b_bits_address = buffer_auto_in_1_b_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_x1_nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] x1_tlOtherMastersNodeOut_b_bits_mask = buffer_auto_in_1_b_bits_mask; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] x1_tlOtherMastersNodeOut_b_bits_data = buffer_auto_in_1_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_b_bits_corrupt = buffer_auto_in_1_b_bits_corrupt; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_c_ready = buffer_auto_in_1_c_ready; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeIn_c_valid = buffer_auto_in_1_c_valid; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_x1_nodeIn_c_bits_opcode = buffer_auto_in_1_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_x1_nodeIn_c_bits_param = buffer_auto_in_1_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] x1_tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_x1_nodeIn_c_bits_size = buffer_auto_in_1_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] x1_tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] buffer_x1_nodeIn_c_bits_source = buffer_auto_in_1_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] x1_tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_x1_nodeIn_c_bits_address = buffer_auto_in_1_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] x1_tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_x1_nodeIn_c_bits_data = buffer_auto_in_1_c_bits_data; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeIn_d_ready = buffer_auto_in_1_d_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_x1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_d_valid = buffer_auto_in_1_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] x1_tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_1_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] x1_tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_1_d_bits_param; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] x1_tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_1_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] x1_tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_1_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] x1_tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_1_d_bits_sink; // @[Buffer.scala:40:9]
wire [127:0] buffer_x1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_1_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] x1_tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_1_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_x1_nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire x1_tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_1_d_bits_corrupt; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_e_ready = buffer_auto_in_1_e_ready; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire buffer_x1_nodeIn_e_valid = buffer_auto_in_1_e_valid; // @[Buffer.scala:40:9]
wire [3:0] x1_tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [3:0] buffer_x1_nodeIn_e_bits_sink = buffer_auto_in_1_e_bits_sink; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_a_ready = buffer_auto_in_0_a_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_0_a_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_0_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_0_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [6:0] buffer_nodeIn_a_bits_source = buffer_auto_in_0_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_0_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [15:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_0_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_a_bits_data = buffer_auto_in_0_a_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_0_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_d_valid = buffer_auto_in_0_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeOut_d_bits_opcode = buffer_auto_in_0_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeOut_d_bits_param = buffer_auto_in_0_d_bits_param; // @[Buffer.scala:40:9]
wire [6:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_size = buffer_auto_in_0_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [6:0] tlOtherMastersNodeOut_d_bits_source = buffer_auto_in_0_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_sink = buffer_auto_in_0_d_bits_sink; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_d_bits_denied = buffer_auto_in_0_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeOut_d_bits_data = buffer_auto_in_0_d_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeOut_d_bits_corrupt = buffer_auto_in_0_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_a_ready = buffer_auto_out_1_a_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_valid_0 = buffer_auto_out_1_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_opcode_0 = buffer_auto_out_1_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_param_0 = buffer_auto_out_1_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_size_0 = buffer_auto_out_1_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_source_0 = buffer_auto_out_1_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_address_0 = buffer_auto_out_1_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_mask_0 = buffer_auto_out_1_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_a_bits_data_0 = buffer_auto_out_1_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_b_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_b_ready_0 = buffer_auto_out_1_b_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_b_valid = buffer_auto_out_1_b_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_x1_nodeOut_b_bits_opcode = buffer_auto_out_1_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeOut_b_bits_param = buffer_auto_out_1_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeOut_b_bits_size = buffer_auto_out_1_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeOut_b_bits_source = buffer_auto_out_1_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_x1_nodeOut_b_bits_address = buffer_auto_out_1_b_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_x1_nodeOut_b_bits_mask = buffer_auto_out_1_b_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_x1_nodeOut_b_bits_data = buffer_auto_out_1_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_b_bits_corrupt = buffer_auto_out_1_b_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_c_ready = buffer_auto_out_1_c_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_c_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_valid_0 = buffer_auto_out_1_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_x1_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_bits_opcode_0 = buffer_auto_out_1_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_x1_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_bits_param_0 = buffer_auto_out_1_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_bits_size_0 = buffer_auto_out_1_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_bits_source_0 = buffer_auto_out_1_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_x1_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_bits_address_0 = buffer_auto_out_1_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_x1_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_c_bits_data_0 = buffer_auto_out_1_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_d_ready_0 = buffer_auto_out_1_d_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_d_valid = buffer_auto_out_1_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_x1_nodeOut_d_bits_opcode = buffer_auto_out_1_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeOut_d_bits_param = buffer_auto_out_1_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeOut_d_bits_size = buffer_auto_out_1_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_x1_nodeOut_d_bits_source = buffer_auto_out_1_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeOut_d_bits_sink = buffer_auto_out_1_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_d_bits_denied = buffer_auto_out_1_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] buffer_x1_nodeOut_d_bits_data = buffer_auto_out_1_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_d_bits_corrupt = buffer_auto_out_1_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_e_ready = buffer_auto_out_1_e_ready; // @[Buffer.scala:40:9]
wire buffer_x1_nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_e_valid_0 = buffer_auto_out_1_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_x1_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign auto_buffer_out_1_e_bits_sink_0 = buffer_auto_out_1_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_ready = buffer_auto_out_0_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_valid_0 = buffer_auto_out_0_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_opcode_0 = buffer_auto_out_0_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_param_0 = buffer_auto_out_0_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_size_0 = buffer_auto_out_0_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_source_0 = buffer_auto_out_0_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_address_0 = buffer_auto_out_0_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_mask_0 = buffer_auto_out_0_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_data_0 = buffer_auto_out_0_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_a_bits_corrupt_0 = buffer_auto_out_0_a_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_0_d_ready_0 = buffer_auto_out_0_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_valid = buffer_auto_out_0_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_0_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_0_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_0_d_bits_size; // @[Buffer.scala:40:9]
wire [6:0] buffer_nodeOut_d_bits_source = buffer_auto_out_0_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_0_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_denied = buffer_auto_out_0_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_d_bits_data = buffer_auto_out_0_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_0_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_0_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_out_0_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_a_ready = buffer_x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_1_a_valid = buffer_x1_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_opcode = buffer_x1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_param = buffer_x1_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_size = buffer_x1_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_source = buffer_x1_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_address = buffer_x1_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_mask = buffer_x1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_a_bits_data = buffer_x1_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_b_ready = buffer_x1_nodeOut_b_ready; // @[Buffer.scala:40:9]
assign buffer_x1_nodeIn_b_valid = buffer_x1_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_opcode = buffer_x1_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_param = buffer_x1_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_size = buffer_x1_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_source = buffer_x1_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_address = buffer_x1_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_mask = buffer_x1_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_data = buffer_x1_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_b_bits_corrupt = buffer_x1_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_c_ready = buffer_x1_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_1_c_valid = buffer_x1_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_c_bits_opcode = buffer_x1_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_c_bits_param = buffer_x1_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_c_bits_size = buffer_x1_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_c_bits_source = buffer_x1_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_c_bits_address = buffer_x1_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_c_bits_data = buffer_x1_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_d_ready = buffer_x1_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_x1_nodeIn_d_valid = buffer_x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_opcode = buffer_x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_param = buffer_x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_size = buffer_x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_source = buffer_x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_sink = buffer_x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_denied = buffer_x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_data = buffer_x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_d_bits_corrupt = buffer_x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeIn_e_ready = buffer_x1_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_1_e_valid = buffer_x1_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_1_e_bits_sink = buffer_x1_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_0_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_0_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_a_ready = buffer_x1_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_x1_nodeOut_a_valid = buffer_x1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_opcode = buffer_x1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_param = buffer_x1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_size = buffer_x1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_source = buffer_x1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_address = buffer_x1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_mask = buffer_x1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_a_bits_data = buffer_x1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_b_ready = buffer_x1_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_1_b_valid = buffer_x1_nodeIn_b_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_opcode = buffer_x1_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_param = buffer_x1_nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_size = buffer_x1_nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_source = buffer_x1_nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_address = buffer_x1_nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_mask = buffer_x1_nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_data = buffer_x1_nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_b_bits_corrupt = buffer_x1_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_c_ready = buffer_x1_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign buffer_x1_nodeOut_c_valid = buffer_x1_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_c_bits_opcode = buffer_x1_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_c_bits_param = buffer_x1_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_c_bits_size = buffer_x1_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_c_bits_source = buffer_x1_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_c_bits_address = buffer_x1_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_c_bits_data = buffer_x1_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_d_ready = buffer_x1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_1_d_valid = buffer_x1_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_opcode = buffer_x1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_param = buffer_x1_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_size = buffer_x1_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_source = buffer_x1_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_sink = buffer_x1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_denied = buffer_x1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_data = buffer_x1_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_d_bits_corrupt = buffer_x1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_1_e_ready = buffer_x1_nodeIn_e_ready; // @[Buffer.scala:40:9]
assign buffer_x1_nodeOut_e_valid = buffer_x1_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_x1_nodeOut_e_bits_sink = buffer_x1_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_valid = tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_a_bits_corrupt = tlOtherMastersNodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17]
assign buffer_auto_in_0_d_ready = tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9]
wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [6:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_a_ready = x1_tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_valid = x1_tlOtherMastersNodeOut_a_valid; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_opcode = x1_tlOtherMastersNodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_param = x1_tlOtherMastersNodeOut_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] x1_tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_size = x1_tlOtherMastersNodeOut_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] x1_tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_source = x1_tlOtherMastersNodeOut_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] x1_tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_address = x1_tlOtherMastersNodeOut_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] x1_tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_mask = x1_tlOtherMastersNodeOut_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] x1_tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_a_bits_data = x1_tlOtherMastersNodeOut_a_bits_data; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_b_ready = x1_tlOtherMastersNodeOut_b_ready; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeIn_b_valid = x1_tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlOtherMastersNodeIn_b_bits_opcode = x1_tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlOtherMastersNodeIn_b_bits_param = x1_tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlOtherMastersNodeIn_b_bits_size = x1_tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlOtherMastersNodeIn_b_bits_source = x1_tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] x1_tlOtherMastersNodeIn_b_bits_address = x1_tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] x1_tlOtherMastersNodeIn_b_bits_mask = x1_tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] x1_tlOtherMastersNodeIn_b_bits_data = x1_tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_b_bits_corrupt = x1_tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_c_ready = x1_tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_valid = x1_tlOtherMastersNodeOut_c_valid; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_bits_opcode = x1_tlOtherMastersNodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] x1_tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_bits_param = x1_tlOtherMastersNodeOut_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] x1_tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_bits_size = x1_tlOtherMastersNodeOut_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] x1_tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_bits_source = x1_tlOtherMastersNodeOut_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] x1_tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_bits_address = x1_tlOtherMastersNodeOut_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] x1_tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_c_bits_data = x1_tlOtherMastersNodeOut_c_bits_data; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_d_ready = x1_tlOtherMastersNodeOut_d_ready; // @[Buffer.scala:40:9]
wire x1_tlOtherMastersNodeIn_d_valid = x1_tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] x1_tlOtherMastersNodeIn_d_bits_opcode = x1_tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlOtherMastersNodeIn_d_bits_param = x1_tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlOtherMastersNodeIn_d_bits_size = x1_tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] x1_tlOtherMastersNodeIn_d_bits_source = x1_tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] x1_tlOtherMastersNodeIn_d_bits_sink = x1_tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_d_bits_denied = x1_tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] x1_tlOtherMastersNodeIn_d_bits_data = x1_tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_d_bits_corrupt = x1_tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_e_ready = x1_tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire x1_tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_e_valid = x1_tlOtherMastersNodeOut_e_valid; // @[Buffer.scala:40:9]
wire [3:0] x1_tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign buffer_auto_in_1_e_bits_sink = x1_tlOtherMastersNodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_corrupt = tlOtherMastersNodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_valid = x1_tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_opcode = x1_tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_param = x1_tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_size = x1_tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_source = x1_tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_address = x1_tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_mask = x1_tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_a_bits_data = x1_tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_b_ready = x1_tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_valid = x1_tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_bits_opcode = x1_tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_bits_param = x1_tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_bits_size = x1_tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_bits_source = x1_tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_bits_address = x1_tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_c_bits_data = x1_tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_d_ready = x1_tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_e_valid = x1_tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_tlOtherMastersNodeOut_e_bits_sink = x1_tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17]
assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17]
assign auto_trace_source_out_insns_0_valid_0 = traceSourceNodeOut_insns_0_valid; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_iaddr_0 = traceSourceNodeOut_insns_0_iaddr; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_insn_0 = traceSourceNodeOut_insns_0_insn; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_priv_0 = traceSourceNodeOut_insns_0_priv; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_exception_0 = traceSourceNodeOut_insns_0_exception; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_interrupt_0 = traceSourceNodeOut_insns_0_interrupt; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_cause_0 = traceSourceNodeOut_insns_0_cause; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_tval_0 = traceSourceNodeOut_insns_0_tval; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[RocketTile.scala:141:7]
assign broadcast_2_auto_in_0_valid_0 = bpwatchSourceNodeOut_0_valid_0; // @[MixedNode.scala:542:17]
assign broadcast_2_auto_in_0_action = bpwatchSourceNodeOut_0_action; // @[MixedNode.scala:542:17]
wire int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17]
assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17]
wire intSinkNodeIn_0; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_1; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_2; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_3; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_4; // @[MixedNode.scala:551:17]
assign auto_wfi_out_0_0 = wfiNodeOut_0; // @[RocketTile.scala:141:7]
reg wfiNodeOut_0_REG; // @[Interrupts.scala:131:36]
assign wfiNodeOut_0 = wfiNodeOut_0_REG; // @[Interrupts.scala:131:36]
wire _core_io_rocc_busy_T = _cmdRouter_io_busy | _gemmini_io_busy; // @[RocketTile.scala:213:49]
always @(posedge clock) begin // @[RocketTile.scala:141:7]
if (reset) // @[RocketTile.scala:141:7]
wfiNodeOut_0_REG <= 1'h0; // @[Interrupts.scala:131:36]
else // @[RocketTile.scala:141:7]
wfiNodeOut_0_REG <= _core_io_wfi; // @[RocketTile.scala:147:20]
always @(posedge)
TLXbar_MasterXbar_RocketTile_i2_o1_a32d128s2k4z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42]
.clock (clock),
.reset (reset),
.auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready),
.auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid),
.auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param),
.auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (widget_auto_anon_out_a_ready),
.auto_anon_in_0_a_valid (widget_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_opcode (widget_auto_anon_out_a_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_param (widget_auto_anon_out_a_bits_param), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_size (widget_auto_anon_out_a_bits_size), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_source (widget_auto_anon_out_a_bits_source), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_address (widget_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_mask (widget_auto_anon_out_a_bits_mask), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_a_bits_data (widget_auto_anon_out_a_bits_data), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_b_ready (widget_auto_anon_out_b_ready), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_b_valid (widget_auto_anon_out_b_valid),
.auto_anon_in_0_b_bits_opcode (widget_auto_anon_out_b_bits_opcode),
.auto_anon_in_0_b_bits_param (widget_auto_anon_out_b_bits_param),
.auto_anon_in_0_b_bits_size (widget_auto_anon_out_b_bits_size),
.auto_anon_in_0_b_bits_source (widget_auto_anon_out_b_bits_source),
.auto_anon_in_0_b_bits_address (widget_auto_anon_out_b_bits_address),
.auto_anon_in_0_b_bits_mask (widget_auto_anon_out_b_bits_mask),
.auto_anon_in_0_b_bits_data (widget_auto_anon_out_b_bits_data),
.auto_anon_in_0_b_bits_corrupt (widget_auto_anon_out_b_bits_corrupt),
.auto_anon_in_0_c_ready (widget_auto_anon_out_c_ready),
.auto_anon_in_0_c_valid (widget_auto_anon_out_c_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_opcode (widget_auto_anon_out_c_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_param (widget_auto_anon_out_c_bits_param), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_size (widget_auto_anon_out_c_bits_size), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_source (widget_auto_anon_out_c_bits_source), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_address (widget_auto_anon_out_c_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_c_bits_data (widget_auto_anon_out_c_bits_data), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_d_ready (widget_auto_anon_out_d_ready), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_d_valid (widget_auto_anon_out_d_valid),
.auto_anon_in_0_d_bits_opcode (widget_auto_anon_out_d_bits_opcode),
.auto_anon_in_0_d_bits_param (widget_auto_anon_out_d_bits_param),
.auto_anon_in_0_d_bits_size (widget_auto_anon_out_d_bits_size),
.auto_anon_in_0_d_bits_source (widget_auto_anon_out_d_bits_source),
.auto_anon_in_0_d_bits_sink (widget_auto_anon_out_d_bits_sink),
.auto_anon_in_0_d_bits_denied (widget_auto_anon_out_d_bits_denied),
.auto_anon_in_0_d_bits_data (widget_auto_anon_out_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (widget_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_e_ready (widget_auto_anon_out_e_ready),
.auto_anon_in_0_e_valid (widget_auto_anon_out_e_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_0_e_bits_sink (widget_auto_anon_out_e_bits_sink), // @[WidthWidget.scala:27:9]
.auto_anon_out_a_ready (x1_tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (x1_tlOtherMastersNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (x1_tlOtherMastersNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (x1_tlOtherMastersNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (x1_tlOtherMastersNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (x1_tlOtherMastersNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (x1_tlOtherMastersNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (x1_tlOtherMastersNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (x1_tlOtherMastersNodeIn_a_bits_data),
.auto_anon_out_b_ready (x1_tlOtherMastersNodeIn_b_ready),
.auto_anon_out_b_valid (x1_tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_opcode (x1_tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_param (x1_tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_size (x1_tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_source (x1_tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_address (x1_tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_mask (x1_tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_data (x1_tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_corrupt (x1_tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_c_ready (x1_tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_c_valid (x1_tlOtherMastersNodeIn_c_valid),
.auto_anon_out_c_bits_opcode (x1_tlOtherMastersNodeIn_c_bits_opcode),
.auto_anon_out_c_bits_param (x1_tlOtherMastersNodeIn_c_bits_param),
.auto_anon_out_c_bits_size (x1_tlOtherMastersNodeIn_c_bits_size),
.auto_anon_out_c_bits_source (x1_tlOtherMastersNodeIn_c_bits_source),
.auto_anon_out_c_bits_address (x1_tlOtherMastersNodeIn_c_bits_address),
.auto_anon_out_c_bits_data (x1_tlOtherMastersNodeIn_c_bits_data),
.auto_anon_out_d_ready (x1_tlOtherMastersNodeIn_d_ready),
.auto_anon_out_d_valid (x1_tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (x1_tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (x1_tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (x1_tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (x1_tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (x1_tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (x1_tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (x1_tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (x1_tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_e_ready (x1_tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_e_valid (x1_tlOtherMastersNodeIn_e_valid),
.auto_anon_out_e_bits_sink (x1_tlOtherMastersNodeIn_e_bits_sink)
); // @[HierarchicalElement.scala:55:42]
TLXbar_SlaveXbar_RocketTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41]
.clock (clock),
.reset (reset)
); // @[HierarchicalElement.scala:56:41]
IntXbar_i4_o1 intXbar ( // @[HierarchicalElement.scala:57:37]
.auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17]
.auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17]
.auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_out_0 (intSinkNodeIn_0),
.auto_anon_out_1 (intSinkNodeIn_1),
.auto_anon_out_2 (intSinkNodeIn_2),
.auto_anon_out_3 (intSinkNodeIn_3),
.auto_anon_out_4 (intSinkNodeIn_4)
); // @[HierarchicalElement.scala:57:37]
DCache dcache ( // @[HellaCache.scala:278:43]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (widget_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_auto_anon_in_a_bits_data),
.auto_out_b_ready (widget_auto_anon_in_b_ready),
.auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9]
.auto_out_c_valid (widget_auto_anon_in_c_valid),
.auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode),
.auto_out_c_bits_param (widget_auto_anon_in_c_bits_param),
.auto_out_c_bits_size (widget_auto_anon_in_c_bits_size),
.auto_out_c_bits_source (widget_auto_anon_in_c_bits_source),
.auto_out_c_bits_address (widget_auto_anon_in_c_bits_address),
.auto_out_c_bits_data (widget_auto_anon_in_c_bits_data),
.auto_out_d_ready (widget_auto_anon_in_d_ready),
.auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9]
.auto_out_e_valid (widget_auto_anon_in_e_valid),
.auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink),
.io_cpu_req_ready (_dcache_io_cpu_req_ready),
.io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_size (_dcacheArb_io_mem_req_bits_size), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_signed (_dcacheArb_io_mem_req_bits_signed), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[HellaCache.scala:292:25]
.io_cpu_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp), // @[HellaCache.scala:292:25]
.io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[HellaCache.scala:292:25]
.io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[HellaCache.scala:292:25]
.io_cpu_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), // @[HellaCache.scala:292:25]
.io_cpu_s2_nack (_dcache_io_cpu_s2_nack),
.io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw),
.io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached),
.io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr),
.io_cpu_resp_valid (_dcache_io_cpu_resp_valid),
.io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr),
.io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag),
.io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd),
.io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size),
.io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed),
.io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv),
.io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv),
.io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data),
.io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask),
.io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay),
.io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data),
.io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass),
.io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw),
.io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data),
.io_cpu_replay_next (_dcache_io_cpu_replay_next),
.io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld),
.io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st),
.io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld),
.io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st),
.io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld),
.io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st),
.io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa),
.io_cpu_ordered (_dcache_io_cpu_ordered),
.io_cpu_store_pending (_dcache_io_cpu_store_pending),
.io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire),
.io_cpu_perf_release (_dcache_io_cpu_perf_release),
.io_cpu_perf_grant (_dcache_io_cpu_perf_grant),
.io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss),
.io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked),
.io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad),
.io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW),
.io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad),
.io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad),
.io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore),
.io_cpu_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled), // @[HellaCache.scala:292:25]
.io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[PTW.scala:802:19]
.io_ptw_req_valid (_dcache_io_ptw_req_valid),
.io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[PTW.scala:802:19]
.io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[PTW.scala:802:19]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[PTW.scala:802:19]
.io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[PTW.scala:802:19]
.io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[PTW.scala:802:19]
.io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[PTW.scala:802:19]
.io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[PTW.scala:802:19]
.io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[PTW.scala:802:19]
.io_ptw_status_isa (_ptw_io_requestor_1_status_isa), // @[PTW.scala:802:19]
.io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[PTW.scala:802:19]
.io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[PTW.scala:802:19]
.io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[PTW.scala:802:19]
.io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[PTW.scala:802:19]
.io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[PTW.scala:802:19]
.io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[PTW.scala:802:19]
.io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[PTW.scala:802:19]
.io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[PTW.scala:802:19]
.io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[PTW.scala:802:19]
.io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[PTW.scala:802:19]
.io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[PTW.scala:802:19]
.io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[PTW.scala:802:19]
.io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[PTW.scala:802:19]
.io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[PTW.scala:802:19]
.io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[PTW.scala:802:19]
.io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[PTW.scala:802:19]
.io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[PTW.scala:802:19]
.io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[PTW.scala:802:19]
.io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[PTW.scala:802:19]
.io_ptw_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp), // @[PTW.scala:802:19]
.io_ptw_hstatus_spv (_ptw_io_requestor_1_hstatus_spv), // @[PTW.scala:802:19]
.io_ptw_hstatus_gva (_ptw_io_requestor_1_hstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_debug (_ptw_io_requestor_1_gstatus_debug), // @[PTW.scala:802:19]
.io_ptw_gstatus_cease (_ptw_io_requestor_1_gstatus_cease), // @[PTW.scala:802:19]
.io_ptw_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi), // @[PTW.scala:802:19]
.io_ptw_gstatus_isa (_ptw_io_requestor_1_gstatus_isa), // @[PTW.scala:802:19]
.io_ptw_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_dv (_ptw_io_requestor_1_gstatus_dv), // @[PTW.scala:802:19]
.io_ptw_gstatus_prv (_ptw_io_requestor_1_gstatus_prv), // @[PTW.scala:802:19]
.io_ptw_gstatus_v (_ptw_io_requestor_1_gstatus_v), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv), // @[PTW.scala:802:19]
.io_ptw_gstatus_gva (_ptw_io_requestor_1_gstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1), // @[PTW.scala:802:19]
.io_ptw_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr), // @[PTW.scala:802:19]
.io_ptw_gstatus_tw (_ptw_io_requestor_1_gstatus_tw), // @[PTW.scala:802:19]
.io_ptw_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm), // @[PTW.scala:802:19]
.io_ptw_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr), // @[PTW.scala:802:19]
.io_ptw_gstatus_sum (_ptw_io_requestor_1_gstatus_sum), // @[PTW.scala:802:19]
.io_ptw_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_fs (_ptw_io_requestor_1_gstatus_fs), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp), // @[PTW.scala:802:19]
.io_ptw_gstatus_vs (_ptw_io_requestor_1_gstatus_vs), // @[PTW.scala:802:19]
.io_ptw_gstatus_spp (_ptw_io_requestor_1_gstatus_spp), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie), // @[PTW.scala:802:19]
.io_ptw_gstatus_ube (_ptw_io_requestor_1_gstatus_ube), // @[PTW.scala:802:19]
.io_ptw_gstatus_spie (_ptw_io_requestor_1_gstatus_spie), // @[PTW.scala:802:19]
.io_ptw_gstatus_upie (_ptw_io_requestor_1_gstatus_upie), // @[PTW.scala:802:19]
.io_ptw_gstatus_mie (_ptw_io_requestor_1_gstatus_mie), // @[PTW.scala:802:19]
.io_ptw_gstatus_hie (_ptw_io_requestor_1_gstatus_hie), // @[PTW.scala:802:19]
.io_ptw_gstatus_sie (_ptw_io_requestor_1_gstatus_sie), // @[PTW.scala:802:19]
.io_ptw_gstatus_uie (_ptw_io_requestor_1_gstatus_uie), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value) // @[PTW.scala:802:19]
); // @[HellaCache.scala:278:43]
Gemmini gemmini ( // @[Configs.scala:282:31]
.clock (clock),
.reset (reset),
.auto_spad_id_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_spad_id_out_a_valid (tlOtherMastersNodeIn_a_valid),
.auto_spad_id_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode),
.auto_spad_id_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param),
.auto_spad_id_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size),
.auto_spad_id_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source),
.auto_spad_id_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address),
.auto_spad_id_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask),
.auto_spad_id_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data),
.auto_spad_id_out_a_bits_corrupt (tlOtherMastersNodeIn_a_bits_corrupt),
.auto_spad_id_out_d_ready (tlOtherMastersNodeIn_d_ready),
.auto_spad_id_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_spad_id_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_cmd_ready (_gemmini_io_cmd_ready),
.io_cmd_valid (_cmdRouter_io_out_0_valid), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_funct (_cmdRouter_io_out_0_bits_inst_funct), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_rs2 (_cmdRouter_io_out_0_bits_inst_rs2), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_rs1 (_cmdRouter_io_out_0_bits_inst_rs1), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_xd (_cmdRouter_io_out_0_bits_inst_xd), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_xs1 (_cmdRouter_io_out_0_bits_inst_xs1), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_xs2 (_cmdRouter_io_out_0_bits_inst_xs2), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_rd (_cmdRouter_io_out_0_bits_inst_rd), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_inst_opcode (_cmdRouter_io_out_0_bits_inst_opcode), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_rs1 (_cmdRouter_io_out_0_bits_rs1), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_rs2 (_cmdRouter_io_out_0_bits_rs2), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_debug (_cmdRouter_io_out_0_bits_status_debug), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_cease (_cmdRouter_io_out_0_bits_status_cease), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_wfi (_cmdRouter_io_out_0_bits_status_wfi), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_isa (_cmdRouter_io_out_0_bits_status_isa), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_dprv (_cmdRouter_io_out_0_bits_status_dprv), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_dv (_cmdRouter_io_out_0_bits_status_dv), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_prv (_cmdRouter_io_out_0_bits_status_prv), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_v (_cmdRouter_io_out_0_bits_status_v), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_sd (_cmdRouter_io_out_0_bits_status_sd), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_zero2 (_cmdRouter_io_out_0_bits_status_zero2), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mpv (_cmdRouter_io_out_0_bits_status_mpv), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_gva (_cmdRouter_io_out_0_bits_status_gva), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mbe (_cmdRouter_io_out_0_bits_status_mbe), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_sbe (_cmdRouter_io_out_0_bits_status_sbe), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_sxl (_cmdRouter_io_out_0_bits_status_sxl), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_uxl (_cmdRouter_io_out_0_bits_status_uxl), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_sd_rv32 (_cmdRouter_io_out_0_bits_status_sd_rv32), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_zero1 (_cmdRouter_io_out_0_bits_status_zero1), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_tsr (_cmdRouter_io_out_0_bits_status_tsr), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_tw (_cmdRouter_io_out_0_bits_status_tw), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_tvm (_cmdRouter_io_out_0_bits_status_tvm), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mxr (_cmdRouter_io_out_0_bits_status_mxr), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_sum (_cmdRouter_io_out_0_bits_status_sum), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mprv (_cmdRouter_io_out_0_bits_status_mprv), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_xs (_cmdRouter_io_out_0_bits_status_xs), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_fs (_cmdRouter_io_out_0_bits_status_fs), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mpp (_cmdRouter_io_out_0_bits_status_mpp), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_vs (_cmdRouter_io_out_0_bits_status_vs), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_spp (_cmdRouter_io_out_0_bits_status_spp), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mpie (_cmdRouter_io_out_0_bits_status_mpie), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_ube (_cmdRouter_io_out_0_bits_status_ube), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_spie (_cmdRouter_io_out_0_bits_status_spie), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_upie (_cmdRouter_io_out_0_bits_status_upie), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_mie (_cmdRouter_io_out_0_bits_status_mie), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_hie (_cmdRouter_io_out_0_bits_status_hie), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_sie (_cmdRouter_io_out_0_bits_status_sie), // @[LazyRoCC.scala:102:27]
.io_cmd_bits_status_uie (_cmdRouter_io_out_0_bits_status_uie), // @[LazyRoCC.scala:102:27]
.io_resp_ready (_respArb_io_in_0_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_resp_valid (_gemmini_io_resp_valid),
.io_resp_bits_rd (_gemmini_io_resp_bits_rd),
.io_resp_bits_data (_gemmini_io_resp_bits_data),
.io_mem_req_ready (_dcIF_io_requestor_req_ready), // @[LazyRoCC.scala:106:24]
.io_mem_resp_valid (_dcIF_io_requestor_resp_valid), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_addr (_dcIF_io_requestor_resp_bits_addr), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_tag (_dcIF_io_requestor_resp_bits_tag), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_cmd (_dcIF_io_requestor_resp_bits_cmd), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_size (_dcIF_io_requestor_resp_bits_size), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_signed (_dcIF_io_requestor_resp_bits_signed), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_dprv (_dcIF_io_requestor_resp_bits_dprv), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_dv (_dcIF_io_requestor_resp_bits_dv), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_data (_dcIF_io_requestor_resp_bits_data), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_mask (_dcIF_io_requestor_resp_bits_mask), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_replay (_dcIF_io_requestor_resp_bits_replay), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_has_data (_dcIF_io_requestor_resp_bits_has_data), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_data_word_bypass (_dcIF_io_requestor_resp_bits_data_word_bypass), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_data_raw (_dcIF_io_requestor_resp_bits_data_raw), // @[LazyRoCC.scala:106:24]
.io_mem_resp_bits_store_data (_dcIF_io_requestor_resp_bits_store_data), // @[LazyRoCC.scala:106:24]
.io_busy (_gemmini_io_busy),
.io_interrupt (_gemmini_io_interrupt),
.io_exception (_core_io_rocc_exception), // @[RocketTile.scala:147:20]
.io_ptw_0_req_ready (_ptw_io_requestor_0_req_ready), // @[PTW.scala:802:19]
.io_ptw_0_req_valid (_gemmini_io_ptw_0_req_valid),
.io_ptw_0_req_bits_bits_addr (_gemmini_io_ptw_0_req_bits_bits_addr),
.io_ptw_0_req_bits_bits_need_gpa (_gemmini_io_ptw_0_req_bits_bits_need_gpa),
.io_ptw_0_resp_valid (_ptw_io_requestor_0_resp_valid), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[PTW.scala:802:19]
.io_ptw_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[PTW.scala:802:19]
.io_ptw_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[PTW.scala:802:19]
.io_ptw_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[PTW.scala:802:19]
.io_ptw_0_status_debug (_ptw_io_requestor_0_status_debug), // @[PTW.scala:802:19]
.io_ptw_0_status_cease (_ptw_io_requestor_0_status_cease), // @[PTW.scala:802:19]
.io_ptw_0_status_wfi (_ptw_io_requestor_0_status_wfi), // @[PTW.scala:802:19]
.io_ptw_0_status_isa (_ptw_io_requestor_0_status_isa), // @[PTW.scala:802:19]
.io_ptw_0_status_dprv (_ptw_io_requestor_0_status_dprv), // @[PTW.scala:802:19]
.io_ptw_0_status_dv (_ptw_io_requestor_0_status_dv), // @[PTW.scala:802:19]
.io_ptw_0_status_prv (_ptw_io_requestor_0_status_prv), // @[PTW.scala:802:19]
.io_ptw_0_status_v (_ptw_io_requestor_0_status_v), // @[PTW.scala:802:19]
.io_ptw_0_status_mpv (_ptw_io_requestor_0_status_mpv), // @[PTW.scala:802:19]
.io_ptw_0_status_gva (_ptw_io_requestor_0_status_gva), // @[PTW.scala:802:19]
.io_ptw_0_status_tsr (_ptw_io_requestor_0_status_tsr), // @[PTW.scala:802:19]
.io_ptw_0_status_tw (_ptw_io_requestor_0_status_tw), // @[PTW.scala:802:19]
.io_ptw_0_status_tvm (_ptw_io_requestor_0_status_tvm), // @[PTW.scala:802:19]
.io_ptw_0_status_mxr (_ptw_io_requestor_0_status_mxr), // @[PTW.scala:802:19]
.io_ptw_0_status_sum (_ptw_io_requestor_0_status_sum), // @[PTW.scala:802:19]
.io_ptw_0_status_mprv (_ptw_io_requestor_0_status_mprv), // @[PTW.scala:802:19]
.io_ptw_0_status_fs (_ptw_io_requestor_0_status_fs), // @[PTW.scala:802:19]
.io_ptw_0_status_mpp (_ptw_io_requestor_0_status_mpp), // @[PTW.scala:802:19]
.io_ptw_0_status_spp (_ptw_io_requestor_0_status_spp), // @[PTW.scala:802:19]
.io_ptw_0_status_mpie (_ptw_io_requestor_0_status_mpie), // @[PTW.scala:802:19]
.io_ptw_0_status_spie (_ptw_io_requestor_0_status_spie), // @[PTW.scala:802:19]
.io_ptw_0_status_mie (_ptw_io_requestor_0_status_mie), // @[PTW.scala:802:19]
.io_ptw_0_status_sie (_ptw_io_requestor_0_status_sie), // @[PTW.scala:802:19]
.io_ptw_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp), // @[PTW.scala:802:19]
.io_ptw_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv), // @[PTW.scala:802:19]
.io_ptw_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_v (_ptw_io_requestor_0_gstatus_v), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie), // @[PTW.scala:802:19]
.io_ptw_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[PTW.scala:802:19]
.io_ptw_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19]
.io_ptw_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value) // @[PTW.scala:802:19]
); // @[Configs.scala:282:31]
Frontend frontend ( // @[Frontend.scala:393:28]
.clock (clock),
.reset (reset),
.auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid),
.auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address),
.auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_cpu_might_request (_core_io_imem_might_request), // @[RocketTile.scala:147:20]
.io_cpu_req_valid (_core_io_imem_req_valid), // @[RocketTile.scala:147:20]
.io_cpu_req_bits_pc (_core_io_imem_req_bits_pc), // @[RocketTile.scala:147:20]
.io_cpu_req_bits_speculative (_core_io_imem_req_bits_speculative), // @[RocketTile.scala:147:20]
.io_cpu_sfence_valid (_core_io_imem_sfence_valid), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_addr (_core_io_imem_sfence_bits_addr), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_asid (_core_io_imem_sfence_bits_asid), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_hv (_core_io_imem_sfence_bits_hv), // @[RocketTile.scala:147:20]
.io_cpu_sfence_bits_hg (_core_io_imem_sfence_bits_hg), // @[RocketTile.scala:147:20]
.io_cpu_resp_ready (_core_io_imem_resp_ready), // @[RocketTile.scala:147:20]
.io_cpu_resp_valid (_frontend_io_cpu_resp_valid),
.io_cpu_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType),
.io_cpu_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken),
.io_cpu_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask),
.io_cpu_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx),
.io_cpu_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target),
.io_cpu_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry),
.io_cpu_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history),
.io_cpu_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value),
.io_cpu_resp_bits_pc (_frontend_io_cpu_resp_bits_pc),
.io_cpu_resp_bits_data (_frontend_io_cpu_resp_bits_data),
.io_cpu_resp_bits_mask (_frontend_io_cpu_resp_bits_mask),
.io_cpu_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst),
.io_cpu_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst),
.io_cpu_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst),
.io_cpu_resp_bits_replay (_frontend_io_cpu_resp_bits_replay),
.io_cpu_gpa_valid (_frontend_io_cpu_gpa_valid),
.io_cpu_gpa_bits (_frontend_io_cpu_gpa_bits),
.io_cpu_gpa_is_pte (_frontend_io_cpu_gpa_is_pte),
.io_cpu_btb_update_valid (_core_io_imem_btb_update_valid), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_target (_core_io_imem_btb_update_bits_target), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc), // @[RocketTile.scala:147:20]
.io_cpu_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_valid (_core_io_imem_bht_update_valid), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken), // @[RocketTile.scala:147:20]
.io_cpu_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict), // @[RocketTile.scala:147:20]
.io_cpu_flush_icache (_core_io_imem_flush_icache), // @[RocketTile.scala:147:20]
.io_cpu_npc (_frontend_io_cpu_npc),
.io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire),
.io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss),
.io_cpu_progress (_core_io_imem_progress), // @[RocketTile.scala:147:20]
.io_ptw_req_ready (_ptw_io_requestor_2_req_ready), // @[PTW.scala:802:19]
.io_ptw_req_valid (_frontend_io_ptw_req_valid),
.io_ptw_req_bits_valid (_frontend_io_ptw_req_bits_valid),
.io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_2_resp_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[PTW.scala:802:19]
.io_ptw_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[PTW.scala:802:19]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[PTW.scala:802:19]
.io_ptw_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[PTW.scala:802:19]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[PTW.scala:802:19]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[PTW.scala:802:19]
.io_ptw_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[PTW.scala:802:19]
.io_ptw_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[PTW.scala:802:19]
.io_ptw_status_debug (_ptw_io_requestor_2_status_debug), // @[PTW.scala:802:19]
.io_ptw_status_cease (_ptw_io_requestor_2_status_cease), // @[PTW.scala:802:19]
.io_ptw_status_wfi (_ptw_io_requestor_2_status_wfi), // @[PTW.scala:802:19]
.io_ptw_status_isa (_ptw_io_requestor_2_status_isa), // @[PTW.scala:802:19]
.io_ptw_status_dprv (_ptw_io_requestor_2_status_dprv), // @[PTW.scala:802:19]
.io_ptw_status_dv (_ptw_io_requestor_2_status_dv), // @[PTW.scala:802:19]
.io_ptw_status_prv (_ptw_io_requestor_2_status_prv), // @[PTW.scala:802:19]
.io_ptw_status_v (_ptw_io_requestor_2_status_v), // @[PTW.scala:802:19]
.io_ptw_status_mpv (_ptw_io_requestor_2_status_mpv), // @[PTW.scala:802:19]
.io_ptw_status_gva (_ptw_io_requestor_2_status_gva), // @[PTW.scala:802:19]
.io_ptw_status_tsr (_ptw_io_requestor_2_status_tsr), // @[PTW.scala:802:19]
.io_ptw_status_tw (_ptw_io_requestor_2_status_tw), // @[PTW.scala:802:19]
.io_ptw_status_tvm (_ptw_io_requestor_2_status_tvm), // @[PTW.scala:802:19]
.io_ptw_status_mxr (_ptw_io_requestor_2_status_mxr), // @[PTW.scala:802:19]
.io_ptw_status_sum (_ptw_io_requestor_2_status_sum), // @[PTW.scala:802:19]
.io_ptw_status_mprv (_ptw_io_requestor_2_status_mprv), // @[PTW.scala:802:19]
.io_ptw_status_fs (_ptw_io_requestor_2_status_fs), // @[PTW.scala:802:19]
.io_ptw_status_mpp (_ptw_io_requestor_2_status_mpp), // @[PTW.scala:802:19]
.io_ptw_status_spp (_ptw_io_requestor_2_status_spp), // @[PTW.scala:802:19]
.io_ptw_status_mpie (_ptw_io_requestor_2_status_mpie), // @[PTW.scala:802:19]
.io_ptw_status_spie (_ptw_io_requestor_2_status_spie), // @[PTW.scala:802:19]
.io_ptw_status_mie (_ptw_io_requestor_2_status_mie), // @[PTW.scala:802:19]
.io_ptw_status_sie (_ptw_io_requestor_2_status_sie), // @[PTW.scala:802:19]
.io_ptw_hstatus_spvp (_ptw_io_requestor_2_hstatus_spvp), // @[PTW.scala:802:19]
.io_ptw_hstatus_spv (_ptw_io_requestor_2_hstatus_spv), // @[PTW.scala:802:19]
.io_ptw_hstatus_gva (_ptw_io_requestor_2_hstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_debug (_ptw_io_requestor_2_gstatus_debug), // @[PTW.scala:802:19]
.io_ptw_gstatus_cease (_ptw_io_requestor_2_gstatus_cease), // @[PTW.scala:802:19]
.io_ptw_gstatus_wfi (_ptw_io_requestor_2_gstatus_wfi), // @[PTW.scala:802:19]
.io_ptw_gstatus_isa (_ptw_io_requestor_2_gstatus_isa), // @[PTW.scala:802:19]
.io_ptw_gstatus_dprv (_ptw_io_requestor_2_gstatus_dprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_dv (_ptw_io_requestor_2_gstatus_dv), // @[PTW.scala:802:19]
.io_ptw_gstatus_prv (_ptw_io_requestor_2_gstatus_prv), // @[PTW.scala:802:19]
.io_ptw_gstatus_v (_ptw_io_requestor_2_gstatus_v), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero2 (_ptw_io_requestor_2_gstatus_zero2), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpv (_ptw_io_requestor_2_gstatus_mpv), // @[PTW.scala:802:19]
.io_ptw_gstatus_gva (_ptw_io_requestor_2_gstatus_gva), // @[PTW.scala:802:19]
.io_ptw_gstatus_mbe (_ptw_io_requestor_2_gstatus_mbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sbe (_ptw_io_requestor_2_gstatus_sbe), // @[PTW.scala:802:19]
.io_ptw_gstatus_sxl (_ptw_io_requestor_2_gstatus_sxl), // @[PTW.scala:802:19]
.io_ptw_gstatus_zero1 (_ptw_io_requestor_2_gstatus_zero1), // @[PTW.scala:802:19]
.io_ptw_gstatus_tsr (_ptw_io_requestor_2_gstatus_tsr), // @[PTW.scala:802:19]
.io_ptw_gstatus_tw (_ptw_io_requestor_2_gstatus_tw), // @[PTW.scala:802:19]
.io_ptw_gstatus_tvm (_ptw_io_requestor_2_gstatus_tvm), // @[PTW.scala:802:19]
.io_ptw_gstatus_mxr (_ptw_io_requestor_2_gstatus_mxr), // @[PTW.scala:802:19]
.io_ptw_gstatus_sum (_ptw_io_requestor_2_gstatus_sum), // @[PTW.scala:802:19]
.io_ptw_gstatus_mprv (_ptw_io_requestor_2_gstatus_mprv), // @[PTW.scala:802:19]
.io_ptw_gstatus_fs (_ptw_io_requestor_2_gstatus_fs), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpp (_ptw_io_requestor_2_gstatus_mpp), // @[PTW.scala:802:19]
.io_ptw_gstatus_vs (_ptw_io_requestor_2_gstatus_vs), // @[PTW.scala:802:19]
.io_ptw_gstatus_spp (_ptw_io_requestor_2_gstatus_spp), // @[PTW.scala:802:19]
.io_ptw_gstatus_mpie (_ptw_io_requestor_2_gstatus_mpie), // @[PTW.scala:802:19]
.io_ptw_gstatus_ube (_ptw_io_requestor_2_gstatus_ube), // @[PTW.scala:802:19]
.io_ptw_gstatus_spie (_ptw_io_requestor_2_gstatus_spie), // @[PTW.scala:802:19]
.io_ptw_gstatus_upie (_ptw_io_requestor_2_gstatus_upie), // @[PTW.scala:802:19]
.io_ptw_gstatus_mie (_ptw_io_requestor_2_gstatus_mie), // @[PTW.scala:802:19]
.io_ptw_gstatus_hie (_ptw_io_requestor_2_gstatus_hie), // @[PTW.scala:802:19]
.io_ptw_gstatus_sie (_ptw_io_requestor_2_gstatus_sie), // @[PTW.scala:802:19]
.io_ptw_gstatus_uie (_ptw_io_requestor_2_gstatus_uie), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[PTW.scala:802:19]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[PTW.scala:802:19]
.io_ptw_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[PTW.scala:802:19]
.io_ptw_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_ren (_ptw_io_requestor_2_customCSRs_csrs_0_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wen (_ptw_io_requestor_2_customCSRs_csrs_0_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_wdata (_ptw_io_requestor_2_customCSRs_csrs_0_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_value (_ptw_io_requestor_2_customCSRs_csrs_0_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_ren (_ptw_io_requestor_2_customCSRs_csrs_1_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wen (_ptw_io_requestor_2_customCSRs_csrs_1_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_wdata (_ptw_io_requestor_2_customCSRs_csrs_1_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_1_value (_ptw_io_requestor_2_customCSRs_csrs_1_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_ren (_ptw_io_requestor_2_customCSRs_csrs_2_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wen (_ptw_io_requestor_2_customCSRs_csrs_2_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_wdata (_ptw_io_requestor_2_customCSRs_csrs_2_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_2_value (_ptw_io_requestor_2_customCSRs_csrs_2_value), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_ren (_ptw_io_requestor_2_customCSRs_csrs_3_ren), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wen (_ptw_io_requestor_2_customCSRs_csrs_3_wen), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_wdata (_ptw_io_requestor_2_customCSRs_csrs_3_wdata), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_3_value (_ptw_io_requestor_2_customCSRs_csrs_3_value) // @[PTW.scala:802:19]
); // @[Frontend.scala:393:28]
TLFragmenter fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset)
); // @[Fragmenter.scala:345:34]
FPU fpuOpt ( // @[RocketTile.scala:242:62]
.clock (clock),
.reset (reset),
.io_hartid (_core_io_fpu_hartid), // @[RocketTile.scala:147:20]
.io_time (_core_io_fpu_time), // @[RocketTile.scala:147:20]
.io_inst (_core_io_fpu_inst), // @[RocketTile.scala:147:20]
.io_fromint_data (_core_io_fpu_fromint_data), // @[RocketTile.scala:147:20]
.io_fcsr_rm (_core_io_fpu_fcsr_rm), // @[RocketTile.scala:147:20]
.io_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid),
.io_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits),
.io_store_data (_fpuOpt_io_store_data),
.io_toint_data (_fpuOpt_io_toint_data),
.io_ll_resp_val (_core_io_fpu_ll_resp_val), // @[RocketTile.scala:147:20]
.io_ll_resp_type (_core_io_fpu_ll_resp_type), // @[RocketTile.scala:147:20]
.io_ll_resp_tag (_core_io_fpu_ll_resp_tag), // @[RocketTile.scala:147:20]
.io_ll_resp_data (_core_io_fpu_ll_resp_data), // @[RocketTile.scala:147:20]
.io_valid (_core_io_fpu_valid), // @[RocketTile.scala:147:20]
.io_fcsr_rdy (_fpuOpt_io_fcsr_rdy),
.io_nack_mem (_fpuOpt_io_nack_mem),
.io_illegal_rm (_fpuOpt_io_illegal_rm),
.io_killx (_core_io_fpu_killx), // @[RocketTile.scala:147:20]
.io_killm (_core_io_fpu_killm), // @[RocketTile.scala:147:20]
.io_dec_ldst (_fpuOpt_io_dec_ldst),
.io_dec_wen (_fpuOpt_io_dec_wen),
.io_dec_ren1 (_fpuOpt_io_dec_ren1),
.io_dec_ren2 (_fpuOpt_io_dec_ren2),
.io_dec_ren3 (_fpuOpt_io_dec_ren3),
.io_dec_swap12 (_fpuOpt_io_dec_swap12),
.io_dec_swap23 (_fpuOpt_io_dec_swap23),
.io_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn),
.io_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut),
.io_dec_fromint (_fpuOpt_io_dec_fromint),
.io_dec_toint (_fpuOpt_io_dec_toint),
.io_dec_fastpipe (_fpuOpt_io_dec_fastpipe),
.io_dec_fma (_fpuOpt_io_dec_fma),
.io_dec_div (_fpuOpt_io_dec_div),
.io_dec_sqrt (_fpuOpt_io_dec_sqrt),
.io_dec_wflags (_fpuOpt_io_dec_wflags),
.io_dec_vec (_fpuOpt_io_dec_vec),
.io_sboard_set (_fpuOpt_io_sboard_set),
.io_sboard_clr (_fpuOpt_io_sboard_clr),
.io_sboard_clra (_fpuOpt_io_sboard_clra),
.io_keep_clock_enabled (_core_io_fpu_keep_clock_enabled) // @[RocketTile.scala:147:20]
); // @[RocketTile.scala:242:62]
HellaCacheArbiter dcacheArb ( // @[HellaCache.scala:292:25]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[PTW.scala:802:19]
.io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[PTW.scala:802:19]
.io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[PTW.scala:802:19]
.io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[PTW.scala:802:19]
.io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack),
.io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw),
.io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached),
.io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr),
.io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr),
.io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag),
.io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd),
.io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size),
.io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed),
.io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv),
.io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv),
.io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data),
.io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask),
.io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay),
.io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data),
.io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass),
.io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw),
.io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data),
.io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next),
.io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld),
.io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st),
.io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld),
.io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st),
.io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld),
.io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st),
.io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa),
.io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered),
.io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending),
.io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire),
.io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release),
.io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant),
.io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss),
.io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked),
.io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad),
.io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW),
.io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad),
.io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad),
.io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore),
.io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_dcIF_io_cache_req_valid), // @[LazyRoCC.scala:106:24]
.io_requestor_1_s1_data_data (_dcIF_io_cache_s1_data_data), // @[LazyRoCC.scala:106:24]
.io_requestor_1_s1_data_mask (_dcIF_io_cache_s1_data_mask), // @[LazyRoCC.scala:106:24]
.io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack),
.io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw),
.io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached),
.io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr),
.io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr),
.io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag),
.io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd),
.io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size),
.io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed),
.io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv),
.io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv),
.io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data),
.io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask),
.io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay),
.io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data),
.io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass),
.io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw),
.io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data),
.io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next),
.io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld),
.io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st),
.io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld),
.io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st),
.io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld),
.io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st),
.io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa),
.io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered),
.io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending),
.io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire),
.io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release),
.io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant),
.io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss),
.io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked),
.io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad),
.io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW),
.io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad),
.io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad),
.io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore),
.io_requestor_2_req_ready (_dcacheArb_io_requestor_2_req_ready),
.io_requestor_2_req_valid (_core_io_dmem_req_valid), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_addr (_core_io_dmem_req_bits_addr), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_tag (_core_io_dmem_req_bits_tag), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_cmd (_core_io_dmem_req_bits_cmd), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_size (_core_io_dmem_req_bits_size), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_signed (_core_io_dmem_req_bits_signed), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_dprv (_core_io_dmem_req_bits_dprv), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_dv (_core_io_dmem_req_bits_dv), // @[RocketTile.scala:147:20]
.io_requestor_2_req_bits_no_resp (_core_io_dmem_req_bits_no_resp), // @[RocketTile.scala:147:20]
.io_requestor_2_s1_kill (_core_io_dmem_s1_kill), // @[RocketTile.scala:147:20]
.io_requestor_2_s1_data_data (_core_io_dmem_s1_data_data), // @[RocketTile.scala:147:20]
.io_requestor_2_s2_nack (_dcacheArb_io_requestor_2_s2_nack),
.io_requestor_2_s2_nack_cause_raw (_dcacheArb_io_requestor_2_s2_nack_cause_raw),
.io_requestor_2_s2_uncached (_dcacheArb_io_requestor_2_s2_uncached),
.io_requestor_2_s2_paddr (_dcacheArb_io_requestor_2_s2_paddr),
.io_requestor_2_resp_valid (_dcacheArb_io_requestor_2_resp_valid),
.io_requestor_2_resp_bits_addr (_dcacheArb_io_requestor_2_resp_bits_addr),
.io_requestor_2_resp_bits_tag (_dcacheArb_io_requestor_2_resp_bits_tag),
.io_requestor_2_resp_bits_cmd (_dcacheArb_io_requestor_2_resp_bits_cmd),
.io_requestor_2_resp_bits_size (_dcacheArb_io_requestor_2_resp_bits_size),
.io_requestor_2_resp_bits_signed (_dcacheArb_io_requestor_2_resp_bits_signed),
.io_requestor_2_resp_bits_dprv (_dcacheArb_io_requestor_2_resp_bits_dprv),
.io_requestor_2_resp_bits_dv (_dcacheArb_io_requestor_2_resp_bits_dv),
.io_requestor_2_resp_bits_data (_dcacheArb_io_requestor_2_resp_bits_data),
.io_requestor_2_resp_bits_mask (_dcacheArb_io_requestor_2_resp_bits_mask),
.io_requestor_2_resp_bits_replay (_dcacheArb_io_requestor_2_resp_bits_replay),
.io_requestor_2_resp_bits_has_data (_dcacheArb_io_requestor_2_resp_bits_has_data),
.io_requestor_2_resp_bits_data_word_bypass (_dcacheArb_io_requestor_2_resp_bits_data_word_bypass),
.io_requestor_2_resp_bits_data_raw (_dcacheArb_io_requestor_2_resp_bits_data_raw),
.io_requestor_2_resp_bits_store_data (_dcacheArb_io_requestor_2_resp_bits_store_data),
.io_requestor_2_replay_next (_dcacheArb_io_requestor_2_replay_next),
.io_requestor_2_s2_xcpt_ma_ld (_dcacheArb_io_requestor_2_s2_xcpt_ma_ld),
.io_requestor_2_s2_xcpt_ma_st (_dcacheArb_io_requestor_2_s2_xcpt_ma_st),
.io_requestor_2_s2_xcpt_pf_ld (_dcacheArb_io_requestor_2_s2_xcpt_pf_ld),
.io_requestor_2_s2_xcpt_pf_st (_dcacheArb_io_requestor_2_s2_xcpt_pf_st),
.io_requestor_2_s2_xcpt_ae_ld (_dcacheArb_io_requestor_2_s2_xcpt_ae_ld),
.io_requestor_2_s2_xcpt_ae_st (_dcacheArb_io_requestor_2_s2_xcpt_ae_st),
.io_requestor_2_s2_gpa (_dcacheArb_io_requestor_2_s2_gpa),
.io_requestor_2_ordered (_dcacheArb_io_requestor_2_ordered),
.io_requestor_2_store_pending (_dcacheArb_io_requestor_2_store_pending),
.io_requestor_2_perf_acquire (_dcacheArb_io_requestor_2_perf_acquire),
.io_requestor_2_perf_release (_dcacheArb_io_requestor_2_perf_release),
.io_requestor_2_perf_grant (_dcacheArb_io_requestor_2_perf_grant),
.io_requestor_2_perf_tlbMiss (_dcacheArb_io_requestor_2_perf_tlbMiss),
.io_requestor_2_perf_blocked (_dcacheArb_io_requestor_2_perf_blocked),
.io_requestor_2_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad),
.io_requestor_2_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW),
.io_requestor_2_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad),
.io_requestor_2_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad),
.io_requestor_2_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore),
.io_requestor_2_keep_clock_enabled (_core_io_dmem_keep_clock_enabled), // @[RocketTile.scala:147:20]
.io_mem_req_ready (_dcache_io_cpu_req_ready), // @[HellaCache.scala:278:43]
.io_mem_req_valid (_dcacheArb_io_mem_req_valid),
.io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr),
.io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag),
.io_mem_req_bits_cmd (_dcacheArb_io_mem_req_bits_cmd),
.io_mem_req_bits_size (_dcacheArb_io_mem_req_bits_size),
.io_mem_req_bits_signed (_dcacheArb_io_mem_req_bits_signed),
.io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv),
.io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv),
.io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys),
.io_mem_req_bits_no_resp (_dcacheArb_io_mem_req_bits_no_resp),
.io_mem_s1_kill (_dcacheArb_io_mem_s1_kill),
.io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data),
.io_mem_s1_data_mask (_dcacheArb_io_mem_s1_data_mask),
.io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[HellaCache.scala:278:43]
.io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[HellaCache.scala:278:43]
.io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[HellaCache.scala:278:43]
.io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[HellaCache.scala:278:43]
.io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[HellaCache.scala:278:43]
.io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[HellaCache.scala:278:43]
.io_mem_replay_next (_dcache_io_cpu_replay_next), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[HellaCache.scala:278:43]
.io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[HellaCache.scala:278:43]
.io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[HellaCache.scala:278:43]
.io_mem_ordered (_dcache_io_cpu_ordered), // @[HellaCache.scala:278:43]
.io_mem_store_pending (_dcache_io_cpu_store_pending), // @[HellaCache.scala:278:43]
.io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[HellaCache.scala:278:43]
.io_mem_perf_release (_dcache_io_cpu_perf_release), // @[HellaCache.scala:278:43]
.io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[HellaCache.scala:278:43]
.io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[HellaCache.scala:278:43]
.io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[HellaCache.scala:278:43]
.io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:278:43]
.io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:278:43]
.io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:278:43]
.io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:278:43]
.io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:278:43]
.io_mem_keep_clock_enabled (_dcacheArb_io_mem_keep_clock_enabled)
); // @[HellaCache.scala:292:25]
PTW ptw ( // @[PTW.scala:802:19]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_gemmini_io_ptw_0_req_valid), // @[Configs.scala:282:31]
.io_requestor_0_req_bits_bits_addr (_gemmini_io_ptw_0_req_bits_bits_addr), // @[Configs.scala:282:31]
.io_requestor_0_req_bits_bits_need_gpa (_gemmini_io_ptw_0_req_bits_bits_need_gpa), // @[Configs.scala:282:31]
.io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw),
.io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final),
.io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf),
.io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf),
.io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr),
.io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw),
.io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx),
.io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future),
.io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn),
.io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
.io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d),
.io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a),
.io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g),
.io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u),
.io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x),
.io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w),
.io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r),
.io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v),
.io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level),
.io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous),
.io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid),
.io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits),
.io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte),
.io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode),
.io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn),
.io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug),
.io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease),
.io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi),
.io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa),
.io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv),
.io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv),
.io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv),
.io_requestor_0_status_v (_ptw_io_requestor_0_status_v),
.io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv),
.io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva),
.io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr),
.io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw),
.io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm),
.io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr),
.io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum),
.io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv),
.io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs),
.io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp),
.io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp),
.io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie),
.io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie),
.io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie),
.io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie),
.io_requestor_0_hstatus_spvp (_ptw_io_requestor_0_hstatus_spvp),
.io_requestor_0_hstatus_spv (_ptw_io_requestor_0_hstatus_spv),
.io_requestor_0_hstatus_gva (_ptw_io_requestor_0_hstatus_gva),
.io_requestor_0_gstatus_debug (_ptw_io_requestor_0_gstatus_debug),
.io_requestor_0_gstatus_cease (_ptw_io_requestor_0_gstatus_cease),
.io_requestor_0_gstatus_wfi (_ptw_io_requestor_0_gstatus_wfi),
.io_requestor_0_gstatus_isa (_ptw_io_requestor_0_gstatus_isa),
.io_requestor_0_gstatus_dprv (_ptw_io_requestor_0_gstatus_dprv),
.io_requestor_0_gstatus_dv (_ptw_io_requestor_0_gstatus_dv),
.io_requestor_0_gstatus_prv (_ptw_io_requestor_0_gstatus_prv),
.io_requestor_0_gstatus_v (_ptw_io_requestor_0_gstatus_v),
.io_requestor_0_gstatus_zero2 (_ptw_io_requestor_0_gstatus_zero2),
.io_requestor_0_gstatus_mpv (_ptw_io_requestor_0_gstatus_mpv),
.io_requestor_0_gstatus_gva (_ptw_io_requestor_0_gstatus_gva),
.io_requestor_0_gstatus_mbe (_ptw_io_requestor_0_gstatus_mbe),
.io_requestor_0_gstatus_sbe (_ptw_io_requestor_0_gstatus_sbe),
.io_requestor_0_gstatus_sxl (_ptw_io_requestor_0_gstatus_sxl),
.io_requestor_0_gstatus_zero1 (_ptw_io_requestor_0_gstatus_zero1),
.io_requestor_0_gstatus_tsr (_ptw_io_requestor_0_gstatus_tsr),
.io_requestor_0_gstatus_tw (_ptw_io_requestor_0_gstatus_tw),
.io_requestor_0_gstatus_tvm (_ptw_io_requestor_0_gstatus_tvm),
.io_requestor_0_gstatus_mxr (_ptw_io_requestor_0_gstatus_mxr),
.io_requestor_0_gstatus_sum (_ptw_io_requestor_0_gstatus_sum),
.io_requestor_0_gstatus_mprv (_ptw_io_requestor_0_gstatus_mprv),
.io_requestor_0_gstatus_fs (_ptw_io_requestor_0_gstatus_fs),
.io_requestor_0_gstatus_mpp (_ptw_io_requestor_0_gstatus_mpp),
.io_requestor_0_gstatus_vs (_ptw_io_requestor_0_gstatus_vs),
.io_requestor_0_gstatus_spp (_ptw_io_requestor_0_gstatus_spp),
.io_requestor_0_gstatus_mpie (_ptw_io_requestor_0_gstatus_mpie),
.io_requestor_0_gstatus_ube (_ptw_io_requestor_0_gstatus_ube),
.io_requestor_0_gstatus_spie (_ptw_io_requestor_0_gstatus_spie),
.io_requestor_0_gstatus_upie (_ptw_io_requestor_0_gstatus_upie),
.io_requestor_0_gstatus_mie (_ptw_io_requestor_0_gstatus_mie),
.io_requestor_0_gstatus_hie (_ptw_io_requestor_0_gstatus_hie),
.io_requestor_0_gstatus_sie (_ptw_io_requestor_0_gstatus_sie),
.io_requestor_0_gstatus_uie (_ptw_io_requestor_0_gstatus_uie),
.io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l),
.io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a),
.io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x),
.io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w),
.io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r),
.io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr),
.io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask),
.io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l),
.io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a),
.io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x),
.io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w),
.io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r),
.io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr),
.io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask),
.io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l),
.io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a),
.io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x),
.io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w),
.io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r),
.io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr),
.io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask),
.io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l),
.io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a),
.io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x),
.io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w),
.io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r),
.io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr),
.io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask),
.io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l),
.io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a),
.io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x),
.io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w),
.io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r),
.io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr),
.io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask),
.io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l),
.io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a),
.io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x),
.io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w),
.io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r),
.io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr),
.io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask),
.io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l),
.io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a),
.io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x),
.io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w),
.io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r),
.io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr),
.io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask),
.io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l),
.io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a),
.io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x),
.io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w),
.io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r),
.io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr),
.io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask),
.io_requestor_0_customCSRs_csrs_0_ren (_ptw_io_requestor_0_customCSRs_csrs_0_ren),
.io_requestor_0_customCSRs_csrs_0_wen (_ptw_io_requestor_0_customCSRs_csrs_0_wen),
.io_requestor_0_customCSRs_csrs_0_wdata (_ptw_io_requestor_0_customCSRs_csrs_0_wdata),
.io_requestor_0_customCSRs_csrs_0_value (_ptw_io_requestor_0_customCSRs_csrs_0_value),
.io_requestor_0_customCSRs_csrs_1_ren (_ptw_io_requestor_0_customCSRs_csrs_1_ren),
.io_requestor_0_customCSRs_csrs_1_wen (_ptw_io_requestor_0_customCSRs_csrs_1_wen),
.io_requestor_0_customCSRs_csrs_1_wdata (_ptw_io_requestor_0_customCSRs_csrs_1_wdata),
.io_requestor_0_customCSRs_csrs_1_value (_ptw_io_requestor_0_customCSRs_csrs_1_value),
.io_requestor_0_customCSRs_csrs_2_ren (_ptw_io_requestor_0_customCSRs_csrs_2_ren),
.io_requestor_0_customCSRs_csrs_2_wen (_ptw_io_requestor_0_customCSRs_csrs_2_wen),
.io_requestor_0_customCSRs_csrs_2_wdata (_ptw_io_requestor_0_customCSRs_csrs_2_wdata),
.io_requestor_0_customCSRs_csrs_2_value (_ptw_io_requestor_0_customCSRs_csrs_2_value),
.io_requestor_0_customCSRs_csrs_3_ren (_ptw_io_requestor_0_customCSRs_csrs_3_ren),
.io_requestor_0_customCSRs_csrs_3_wen (_ptw_io_requestor_0_customCSRs_csrs_3_wen),
.io_requestor_0_customCSRs_csrs_3_wdata (_ptw_io_requestor_0_customCSRs_csrs_3_wdata),
.io_requestor_0_customCSRs_csrs_3_value (_ptw_io_requestor_0_customCSRs_csrs_3_value),
.io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_dcache_io_ptw_req_valid), // @[HellaCache.scala:278:43]
.io_requestor_1_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[HellaCache.scala:278:43]
.io_requestor_1_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[HellaCache.scala:278:43]
.io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw),
.io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final),
.io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf),
.io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf),
.io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr),
.io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw),
.io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx),
.io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future),
.io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn),
.io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software),
.io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d),
.io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a),
.io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g),
.io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u),
.io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x),
.io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w),
.io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r),
.io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v),
.io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level),
.io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous),
.io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid),
.io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits),
.io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte),
.io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode),
.io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn),
.io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug),
.io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease),
.io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi),
.io_requestor_1_status_isa (_ptw_io_requestor_1_status_isa),
.io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv),
.io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv),
.io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv),
.io_requestor_1_status_v (_ptw_io_requestor_1_status_v),
.io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv),
.io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva),
.io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr),
.io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw),
.io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm),
.io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr),
.io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum),
.io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv),
.io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs),
.io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp),
.io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp),
.io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie),
.io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie),
.io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie),
.io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie),
.io_requestor_1_hstatus_spvp (_ptw_io_requestor_1_hstatus_spvp),
.io_requestor_1_hstatus_spv (_ptw_io_requestor_1_hstatus_spv),
.io_requestor_1_hstatus_gva (_ptw_io_requestor_1_hstatus_gva),
.io_requestor_1_gstatus_debug (_ptw_io_requestor_1_gstatus_debug),
.io_requestor_1_gstatus_cease (_ptw_io_requestor_1_gstatus_cease),
.io_requestor_1_gstatus_wfi (_ptw_io_requestor_1_gstatus_wfi),
.io_requestor_1_gstatus_isa (_ptw_io_requestor_1_gstatus_isa),
.io_requestor_1_gstatus_dprv (_ptw_io_requestor_1_gstatus_dprv),
.io_requestor_1_gstatus_dv (_ptw_io_requestor_1_gstatus_dv),
.io_requestor_1_gstatus_prv (_ptw_io_requestor_1_gstatus_prv),
.io_requestor_1_gstatus_v (_ptw_io_requestor_1_gstatus_v),
.io_requestor_1_gstatus_zero2 (_ptw_io_requestor_1_gstatus_zero2),
.io_requestor_1_gstatus_mpv (_ptw_io_requestor_1_gstatus_mpv),
.io_requestor_1_gstatus_gva (_ptw_io_requestor_1_gstatus_gva),
.io_requestor_1_gstatus_mbe (_ptw_io_requestor_1_gstatus_mbe),
.io_requestor_1_gstatus_sbe (_ptw_io_requestor_1_gstatus_sbe),
.io_requestor_1_gstatus_sxl (_ptw_io_requestor_1_gstatus_sxl),
.io_requestor_1_gstatus_zero1 (_ptw_io_requestor_1_gstatus_zero1),
.io_requestor_1_gstatus_tsr (_ptw_io_requestor_1_gstatus_tsr),
.io_requestor_1_gstatus_tw (_ptw_io_requestor_1_gstatus_tw),
.io_requestor_1_gstatus_tvm (_ptw_io_requestor_1_gstatus_tvm),
.io_requestor_1_gstatus_mxr (_ptw_io_requestor_1_gstatus_mxr),
.io_requestor_1_gstatus_sum (_ptw_io_requestor_1_gstatus_sum),
.io_requestor_1_gstatus_mprv (_ptw_io_requestor_1_gstatus_mprv),
.io_requestor_1_gstatus_fs (_ptw_io_requestor_1_gstatus_fs),
.io_requestor_1_gstatus_mpp (_ptw_io_requestor_1_gstatus_mpp),
.io_requestor_1_gstatus_vs (_ptw_io_requestor_1_gstatus_vs),
.io_requestor_1_gstatus_spp (_ptw_io_requestor_1_gstatus_spp),
.io_requestor_1_gstatus_mpie (_ptw_io_requestor_1_gstatus_mpie),
.io_requestor_1_gstatus_ube (_ptw_io_requestor_1_gstatus_ube),
.io_requestor_1_gstatus_spie (_ptw_io_requestor_1_gstatus_spie),
.io_requestor_1_gstatus_upie (_ptw_io_requestor_1_gstatus_upie),
.io_requestor_1_gstatus_mie (_ptw_io_requestor_1_gstatus_mie),
.io_requestor_1_gstatus_hie (_ptw_io_requestor_1_gstatus_hie),
.io_requestor_1_gstatus_sie (_ptw_io_requestor_1_gstatus_sie),
.io_requestor_1_gstatus_uie (_ptw_io_requestor_1_gstatus_uie),
.io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l),
.io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a),
.io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x),
.io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w),
.io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r),
.io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr),
.io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask),
.io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l),
.io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a),
.io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x),
.io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w),
.io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r),
.io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr),
.io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask),
.io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l),
.io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a),
.io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x),
.io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w),
.io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r),
.io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr),
.io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask),
.io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l),
.io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a),
.io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x),
.io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w),
.io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r),
.io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr),
.io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask),
.io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l),
.io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a),
.io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x),
.io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w),
.io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r),
.io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr),
.io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask),
.io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l),
.io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a),
.io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x),
.io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w),
.io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r),
.io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr),
.io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask),
.io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l),
.io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a),
.io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x),
.io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w),
.io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r),
.io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr),
.io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask),
.io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l),
.io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a),
.io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x),
.io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w),
.io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r),
.io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr),
.io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask),
.io_requestor_1_customCSRs_csrs_0_ren (_ptw_io_requestor_1_customCSRs_csrs_0_ren),
.io_requestor_1_customCSRs_csrs_0_wen (_ptw_io_requestor_1_customCSRs_csrs_0_wen),
.io_requestor_1_customCSRs_csrs_0_wdata (_ptw_io_requestor_1_customCSRs_csrs_0_wdata),
.io_requestor_1_customCSRs_csrs_0_value (_ptw_io_requestor_1_customCSRs_csrs_0_value),
.io_requestor_1_customCSRs_csrs_1_ren (_ptw_io_requestor_1_customCSRs_csrs_1_ren),
.io_requestor_1_customCSRs_csrs_1_wen (_ptw_io_requestor_1_customCSRs_csrs_1_wen),
.io_requestor_1_customCSRs_csrs_1_wdata (_ptw_io_requestor_1_customCSRs_csrs_1_wdata),
.io_requestor_1_customCSRs_csrs_1_value (_ptw_io_requestor_1_customCSRs_csrs_1_value),
.io_requestor_1_customCSRs_csrs_2_ren (_ptw_io_requestor_1_customCSRs_csrs_2_ren),
.io_requestor_1_customCSRs_csrs_2_wen (_ptw_io_requestor_1_customCSRs_csrs_2_wen),
.io_requestor_1_customCSRs_csrs_2_wdata (_ptw_io_requestor_1_customCSRs_csrs_2_wdata),
.io_requestor_1_customCSRs_csrs_2_value (_ptw_io_requestor_1_customCSRs_csrs_2_value),
.io_requestor_1_customCSRs_csrs_3_ren (_ptw_io_requestor_1_customCSRs_csrs_3_ren),
.io_requestor_1_customCSRs_csrs_3_wen (_ptw_io_requestor_1_customCSRs_csrs_3_wen),
.io_requestor_1_customCSRs_csrs_3_wdata (_ptw_io_requestor_1_customCSRs_csrs_3_wdata),
.io_requestor_1_customCSRs_csrs_3_value (_ptw_io_requestor_1_customCSRs_csrs_3_value),
.io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready),
.io_requestor_2_req_valid (_frontend_io_ptw_req_valid), // @[Frontend.scala:393:28]
.io_requestor_2_req_bits_valid (_frontend_io_ptw_req_bits_valid), // @[Frontend.scala:393:28]
.io_requestor_2_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[Frontend.scala:393:28]
.io_requestor_2_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[Frontend.scala:393:28]
.io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid),
.io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw),
.io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final),
.io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf),
.io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf),
.io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr),
.io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw),
.io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx),
.io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future),
.io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn),
.io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software),
.io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d),
.io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a),
.io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g),
.io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u),
.io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x),
.io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w),
.io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r),
.io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v),
.io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level),
.io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous),
.io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid),
.io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits),
.io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte),
.io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode),
.io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn),
.io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug),
.io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease),
.io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi),
.io_requestor_2_status_isa (_ptw_io_requestor_2_status_isa),
.io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv),
.io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv),
.io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv),
.io_requestor_2_status_v (_ptw_io_requestor_2_status_v),
.io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv),
.io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva),
.io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr),
.io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw),
.io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm),
.io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr),
.io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum),
.io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv),
.io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs),
.io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp),
.io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp),
.io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie),
.io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie),
.io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie),
.io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie),
.io_requestor_2_hstatus_spvp (_ptw_io_requestor_2_hstatus_spvp),
.io_requestor_2_hstatus_spv (_ptw_io_requestor_2_hstatus_spv),
.io_requestor_2_hstatus_gva (_ptw_io_requestor_2_hstatus_gva),
.io_requestor_2_gstatus_debug (_ptw_io_requestor_2_gstatus_debug),
.io_requestor_2_gstatus_cease (_ptw_io_requestor_2_gstatus_cease),
.io_requestor_2_gstatus_wfi (_ptw_io_requestor_2_gstatus_wfi),
.io_requestor_2_gstatus_isa (_ptw_io_requestor_2_gstatus_isa),
.io_requestor_2_gstatus_dprv (_ptw_io_requestor_2_gstatus_dprv),
.io_requestor_2_gstatus_dv (_ptw_io_requestor_2_gstatus_dv),
.io_requestor_2_gstatus_prv (_ptw_io_requestor_2_gstatus_prv),
.io_requestor_2_gstatus_v (_ptw_io_requestor_2_gstatus_v),
.io_requestor_2_gstatus_zero2 (_ptw_io_requestor_2_gstatus_zero2),
.io_requestor_2_gstatus_mpv (_ptw_io_requestor_2_gstatus_mpv),
.io_requestor_2_gstatus_gva (_ptw_io_requestor_2_gstatus_gva),
.io_requestor_2_gstatus_mbe (_ptw_io_requestor_2_gstatus_mbe),
.io_requestor_2_gstatus_sbe (_ptw_io_requestor_2_gstatus_sbe),
.io_requestor_2_gstatus_sxl (_ptw_io_requestor_2_gstatus_sxl),
.io_requestor_2_gstatus_zero1 (_ptw_io_requestor_2_gstatus_zero1),
.io_requestor_2_gstatus_tsr (_ptw_io_requestor_2_gstatus_tsr),
.io_requestor_2_gstatus_tw (_ptw_io_requestor_2_gstatus_tw),
.io_requestor_2_gstatus_tvm (_ptw_io_requestor_2_gstatus_tvm),
.io_requestor_2_gstatus_mxr (_ptw_io_requestor_2_gstatus_mxr),
.io_requestor_2_gstatus_sum (_ptw_io_requestor_2_gstatus_sum),
.io_requestor_2_gstatus_mprv (_ptw_io_requestor_2_gstatus_mprv),
.io_requestor_2_gstatus_fs (_ptw_io_requestor_2_gstatus_fs),
.io_requestor_2_gstatus_mpp (_ptw_io_requestor_2_gstatus_mpp),
.io_requestor_2_gstatus_vs (_ptw_io_requestor_2_gstatus_vs),
.io_requestor_2_gstatus_spp (_ptw_io_requestor_2_gstatus_spp),
.io_requestor_2_gstatus_mpie (_ptw_io_requestor_2_gstatus_mpie),
.io_requestor_2_gstatus_ube (_ptw_io_requestor_2_gstatus_ube),
.io_requestor_2_gstatus_spie (_ptw_io_requestor_2_gstatus_spie),
.io_requestor_2_gstatus_upie (_ptw_io_requestor_2_gstatus_upie),
.io_requestor_2_gstatus_mie (_ptw_io_requestor_2_gstatus_mie),
.io_requestor_2_gstatus_hie (_ptw_io_requestor_2_gstatus_hie),
.io_requestor_2_gstatus_sie (_ptw_io_requestor_2_gstatus_sie),
.io_requestor_2_gstatus_uie (_ptw_io_requestor_2_gstatus_uie),
.io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l),
.io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a),
.io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x),
.io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w),
.io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r),
.io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr),
.io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask),
.io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l),
.io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a),
.io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x),
.io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w),
.io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r),
.io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr),
.io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask),
.io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l),
.io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a),
.io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x),
.io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w),
.io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r),
.io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr),
.io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask),
.io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l),
.io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a),
.io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x),
.io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w),
.io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r),
.io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr),
.io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask),
.io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l),
.io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a),
.io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x),
.io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w),
.io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r),
.io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr),
.io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask),
.io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l),
.io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a),
.io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x),
.io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w),
.io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r),
.io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr),
.io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask),
.io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l),
.io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a),
.io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x),
.io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w),
.io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r),
.io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr),
.io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask),
.io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l),
.io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a),
.io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x),
.io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w),
.io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r),
.io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr),
.io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask),
.io_requestor_2_customCSRs_csrs_0_ren (_ptw_io_requestor_2_customCSRs_csrs_0_ren),
.io_requestor_2_customCSRs_csrs_0_wen (_ptw_io_requestor_2_customCSRs_csrs_0_wen),
.io_requestor_2_customCSRs_csrs_0_wdata (_ptw_io_requestor_2_customCSRs_csrs_0_wdata),
.io_requestor_2_customCSRs_csrs_0_value (_ptw_io_requestor_2_customCSRs_csrs_0_value),
.io_requestor_2_customCSRs_csrs_1_ren (_ptw_io_requestor_2_customCSRs_csrs_1_ren),
.io_requestor_2_customCSRs_csrs_1_wen (_ptw_io_requestor_2_customCSRs_csrs_1_wen),
.io_requestor_2_customCSRs_csrs_1_wdata (_ptw_io_requestor_2_customCSRs_csrs_1_wdata),
.io_requestor_2_customCSRs_csrs_1_value (_ptw_io_requestor_2_customCSRs_csrs_1_value),
.io_requestor_2_customCSRs_csrs_2_ren (_ptw_io_requestor_2_customCSRs_csrs_2_ren),
.io_requestor_2_customCSRs_csrs_2_wen (_ptw_io_requestor_2_customCSRs_csrs_2_wen),
.io_requestor_2_customCSRs_csrs_2_wdata (_ptw_io_requestor_2_customCSRs_csrs_2_wdata),
.io_requestor_2_customCSRs_csrs_2_value (_ptw_io_requestor_2_customCSRs_csrs_2_value),
.io_requestor_2_customCSRs_csrs_3_ren (_ptw_io_requestor_2_customCSRs_csrs_3_ren),
.io_requestor_2_customCSRs_csrs_3_wen (_ptw_io_requestor_2_customCSRs_csrs_3_wen),
.io_requestor_2_customCSRs_csrs_3_wdata (_ptw_io_requestor_2_customCSRs_csrs_3_wdata),
.io_requestor_2_customCSRs_csrs_3_value (_ptw_io_requestor_2_customCSRs_csrs_3_value),
.io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[HellaCache.scala:292:25]
.io_mem_req_valid (_ptw_io_mem_req_valid),
.io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv),
.io_mem_s1_kill (_ptw_io_mem_s1_kill),
.io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[HellaCache.scala:292:25]
.io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[HellaCache.scala:292:25]
.io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[HellaCache.scala:292:25]
.io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[HellaCache.scala:292:25]
.io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[HellaCache.scala:292:25]
.io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[HellaCache.scala:292:25]
.io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25]
.io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[HellaCache.scala:292:25]
.io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[HellaCache.scala:292:25]
.io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[HellaCache.scala:292:25]
.io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[HellaCache.scala:292:25]
.io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[HellaCache.scala:292:25]
.io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[HellaCache.scala:292:25]
.io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[HellaCache.scala:292:25]
.io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[HellaCache.scala:292:25]
.io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[HellaCache.scala:292:25]
.io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25]
.io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25]
.io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25]
.io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25]
.io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25]
.io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[RocketTile.scala:147:20]
.io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[RocketTile.scala:147:20]
.io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_hv (_core_io_ptw_sfence_bits_hv), // @[RocketTile.scala:147:20]
.io_dpath_sfence_bits_hg (_core_io_ptw_sfence_bits_hg), // @[RocketTile.scala:147:20]
.io_dpath_status_debug (_core_io_ptw_status_debug), // @[RocketTile.scala:147:20]
.io_dpath_status_cease (_core_io_ptw_status_cease), // @[RocketTile.scala:147:20]
.io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[RocketTile.scala:147:20]
.io_dpath_status_isa (_core_io_ptw_status_isa), // @[RocketTile.scala:147:20]
.io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[RocketTile.scala:147:20]
.io_dpath_status_dv (_core_io_ptw_status_dv), // @[RocketTile.scala:147:20]
.io_dpath_status_prv (_core_io_ptw_status_prv), // @[RocketTile.scala:147:20]
.io_dpath_status_v (_core_io_ptw_status_v), // @[RocketTile.scala:147:20]
.io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[RocketTile.scala:147:20]
.io_dpath_status_gva (_core_io_ptw_status_gva), // @[RocketTile.scala:147:20]
.io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[RocketTile.scala:147:20]
.io_dpath_status_tw (_core_io_ptw_status_tw), // @[RocketTile.scala:147:20]
.io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[RocketTile.scala:147:20]
.io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[RocketTile.scala:147:20]
.io_dpath_status_sum (_core_io_ptw_status_sum), // @[RocketTile.scala:147:20]
.io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[RocketTile.scala:147:20]
.io_dpath_status_fs (_core_io_ptw_status_fs), // @[RocketTile.scala:147:20]
.io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[RocketTile.scala:147:20]
.io_dpath_status_spp (_core_io_ptw_status_spp), // @[RocketTile.scala:147:20]
.io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[RocketTile.scala:147:20]
.io_dpath_status_spie (_core_io_ptw_status_spie), // @[RocketTile.scala:147:20]
.io_dpath_status_mie (_core_io_ptw_status_mie), // @[RocketTile.scala:147:20]
.io_dpath_status_sie (_core_io_ptw_status_sie), // @[RocketTile.scala:147:20]
.io_dpath_hstatus_spvp (_core_io_ptw_hstatus_spvp), // @[RocketTile.scala:147:20]
.io_dpath_hstatus_spv (_core_io_ptw_hstatus_spv), // @[RocketTile.scala:147:20]
.io_dpath_hstatus_gva (_core_io_ptw_hstatus_gva), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_debug (_core_io_ptw_gstatus_debug), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_cease (_core_io_ptw_gstatus_cease), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_wfi (_core_io_ptw_gstatus_wfi), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_isa (_core_io_ptw_gstatus_isa), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_dprv (_core_io_ptw_gstatus_dprv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_dv (_core_io_ptw_gstatus_dv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_prv (_core_io_ptw_gstatus_prv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_v (_core_io_ptw_gstatus_v), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_zero2 (_core_io_ptw_gstatus_zero2), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mpv (_core_io_ptw_gstatus_mpv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_gva (_core_io_ptw_gstatus_gva), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mbe (_core_io_ptw_gstatus_mbe), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sbe (_core_io_ptw_gstatus_sbe), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sxl (_core_io_ptw_gstatus_sxl), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_zero1 (_core_io_ptw_gstatus_zero1), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_tsr (_core_io_ptw_gstatus_tsr), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_tw (_core_io_ptw_gstatus_tw), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_tvm (_core_io_ptw_gstatus_tvm), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mxr (_core_io_ptw_gstatus_mxr), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sum (_core_io_ptw_gstatus_sum), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mprv (_core_io_ptw_gstatus_mprv), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_fs (_core_io_ptw_gstatus_fs), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mpp (_core_io_ptw_gstatus_mpp), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_vs (_core_io_ptw_gstatus_vs), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_spp (_core_io_ptw_gstatus_spp), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mpie (_core_io_ptw_gstatus_mpie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_ube (_core_io_ptw_gstatus_ube), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_spie (_core_io_ptw_gstatus_spie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_upie (_core_io_ptw_gstatus_upie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_mie (_core_io_ptw_gstatus_mie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_hie (_core_io_ptw_gstatus_hie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_sie (_core_io_ptw_gstatus_sie), // @[RocketTile.scala:147:20]
.io_dpath_gstatus_uie (_core_io_ptw_gstatus_uie), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[RocketTile.scala:147:20]
.io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[RocketTile.scala:147:20]
.io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss),
.io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit),
.io_dpath_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata), // @[RocketTile.scala:147:20]
.io_dpath_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value), // @[RocketTile.scala:147:20]
.io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled)
); // @[PTW.scala:802:19]
RRArbiter_5 respArb ( // @[LazyRoCC.scala:101:25]
.clock (clock),
.reset (reset),
.io_in_0_ready (_respArb_io_in_0_ready),
.io_in_0_valid (_respArb_io_in_0_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_0_bits_rd (_respArb_io_in_0_q_io_deq_bits_rd), // @[Decoupled.scala:362:21]
.io_in_0_bits_data (_respArb_io_in_0_q_io_deq_bits_data), // @[Decoupled.scala:362:21]
.io_out_ready (_core_io_rocc_resp_ready), // @[RocketTile.scala:147:20]
.io_out_valid (_respArb_io_out_valid),
.io_out_bits_rd (_respArb_io_out_bits_rd),
.io_out_bits_data (_respArb_io_out_bits_data)
); // @[LazyRoCC.scala:101:25]
RoccCommandRouter cmdRouter ( // @[LazyRoCC.scala:102:27]
.clock (clock),
.reset (reset),
.io_in_ready (_cmdRouter_io_in_ready),
.io_in_valid (_core_io_rocc_cmd_valid), // @[RocketTile.scala:147:20]
.io_in_bits_inst_funct (_core_io_rocc_cmd_bits_inst_funct), // @[RocketTile.scala:147:20]
.io_in_bits_inst_rs2 (_core_io_rocc_cmd_bits_inst_rs2), // @[RocketTile.scala:147:20]
.io_in_bits_inst_rs1 (_core_io_rocc_cmd_bits_inst_rs1), // @[RocketTile.scala:147:20]
.io_in_bits_inst_xd (_core_io_rocc_cmd_bits_inst_xd), // @[RocketTile.scala:147:20]
.io_in_bits_inst_xs1 (_core_io_rocc_cmd_bits_inst_xs1), // @[RocketTile.scala:147:20]
.io_in_bits_inst_xs2 (_core_io_rocc_cmd_bits_inst_xs2), // @[RocketTile.scala:147:20]
.io_in_bits_inst_rd (_core_io_rocc_cmd_bits_inst_rd), // @[RocketTile.scala:147:20]
.io_in_bits_inst_opcode (_core_io_rocc_cmd_bits_inst_opcode), // @[RocketTile.scala:147:20]
.io_in_bits_rs1 (_core_io_rocc_cmd_bits_rs1), // @[RocketTile.scala:147:20]
.io_in_bits_rs2 (_core_io_rocc_cmd_bits_rs2), // @[RocketTile.scala:147:20]
.io_in_bits_status_debug (_core_io_rocc_cmd_bits_status_debug), // @[RocketTile.scala:147:20]
.io_in_bits_status_cease (_core_io_rocc_cmd_bits_status_cease), // @[RocketTile.scala:147:20]
.io_in_bits_status_wfi (_core_io_rocc_cmd_bits_status_wfi), // @[RocketTile.scala:147:20]
.io_in_bits_status_isa (_core_io_rocc_cmd_bits_status_isa), // @[RocketTile.scala:147:20]
.io_in_bits_status_dprv (_core_io_rocc_cmd_bits_status_dprv), // @[RocketTile.scala:147:20]
.io_in_bits_status_dv (_core_io_rocc_cmd_bits_status_dv), // @[RocketTile.scala:147:20]
.io_in_bits_status_prv (_core_io_rocc_cmd_bits_status_prv), // @[RocketTile.scala:147:20]
.io_in_bits_status_v (_core_io_rocc_cmd_bits_status_v), // @[RocketTile.scala:147:20]
.io_in_bits_status_mpv (_core_io_rocc_cmd_bits_status_mpv), // @[RocketTile.scala:147:20]
.io_in_bits_status_gva (_core_io_rocc_cmd_bits_status_gva), // @[RocketTile.scala:147:20]
.io_in_bits_status_tsr (_core_io_rocc_cmd_bits_status_tsr), // @[RocketTile.scala:147:20]
.io_in_bits_status_tw (_core_io_rocc_cmd_bits_status_tw), // @[RocketTile.scala:147:20]
.io_in_bits_status_tvm (_core_io_rocc_cmd_bits_status_tvm), // @[RocketTile.scala:147:20]
.io_in_bits_status_mxr (_core_io_rocc_cmd_bits_status_mxr), // @[RocketTile.scala:147:20]
.io_in_bits_status_sum (_core_io_rocc_cmd_bits_status_sum), // @[RocketTile.scala:147:20]
.io_in_bits_status_mprv (_core_io_rocc_cmd_bits_status_mprv), // @[RocketTile.scala:147:20]
.io_in_bits_status_fs (_core_io_rocc_cmd_bits_status_fs), // @[RocketTile.scala:147:20]
.io_in_bits_status_mpp (_core_io_rocc_cmd_bits_status_mpp), // @[RocketTile.scala:147:20]
.io_in_bits_status_spp (_core_io_rocc_cmd_bits_status_spp), // @[RocketTile.scala:147:20]
.io_in_bits_status_mpie (_core_io_rocc_cmd_bits_status_mpie), // @[RocketTile.scala:147:20]
.io_in_bits_status_spie (_core_io_rocc_cmd_bits_status_spie), // @[RocketTile.scala:147:20]
.io_in_bits_status_mie (_core_io_rocc_cmd_bits_status_mie), // @[RocketTile.scala:147:20]
.io_in_bits_status_sie (_core_io_rocc_cmd_bits_status_sie), // @[RocketTile.scala:147:20]
.io_out_0_ready (_gemmini_io_cmd_ready), // @[Configs.scala:282:31]
.io_out_0_valid (_cmdRouter_io_out_0_valid),
.io_out_0_bits_inst_funct (_cmdRouter_io_out_0_bits_inst_funct),
.io_out_0_bits_inst_rs2 (_cmdRouter_io_out_0_bits_inst_rs2),
.io_out_0_bits_inst_rs1 (_cmdRouter_io_out_0_bits_inst_rs1),
.io_out_0_bits_inst_xd (_cmdRouter_io_out_0_bits_inst_xd),
.io_out_0_bits_inst_xs1 (_cmdRouter_io_out_0_bits_inst_xs1),
.io_out_0_bits_inst_xs2 (_cmdRouter_io_out_0_bits_inst_xs2),
.io_out_0_bits_inst_rd (_cmdRouter_io_out_0_bits_inst_rd),
.io_out_0_bits_inst_opcode (_cmdRouter_io_out_0_bits_inst_opcode),
.io_out_0_bits_rs1 (_cmdRouter_io_out_0_bits_rs1),
.io_out_0_bits_rs2 (_cmdRouter_io_out_0_bits_rs2),
.io_out_0_bits_status_debug (_cmdRouter_io_out_0_bits_status_debug),
.io_out_0_bits_status_cease (_cmdRouter_io_out_0_bits_status_cease),
.io_out_0_bits_status_wfi (_cmdRouter_io_out_0_bits_status_wfi),
.io_out_0_bits_status_isa (_cmdRouter_io_out_0_bits_status_isa),
.io_out_0_bits_status_dprv (_cmdRouter_io_out_0_bits_status_dprv),
.io_out_0_bits_status_dv (_cmdRouter_io_out_0_bits_status_dv),
.io_out_0_bits_status_prv (_cmdRouter_io_out_0_bits_status_prv),
.io_out_0_bits_status_v (_cmdRouter_io_out_0_bits_status_v),
.io_out_0_bits_status_sd (_cmdRouter_io_out_0_bits_status_sd),
.io_out_0_bits_status_zero2 (_cmdRouter_io_out_0_bits_status_zero2),
.io_out_0_bits_status_mpv (_cmdRouter_io_out_0_bits_status_mpv),
.io_out_0_bits_status_gva (_cmdRouter_io_out_0_bits_status_gva),
.io_out_0_bits_status_mbe (_cmdRouter_io_out_0_bits_status_mbe),
.io_out_0_bits_status_sbe (_cmdRouter_io_out_0_bits_status_sbe),
.io_out_0_bits_status_sxl (_cmdRouter_io_out_0_bits_status_sxl),
.io_out_0_bits_status_uxl (_cmdRouter_io_out_0_bits_status_uxl),
.io_out_0_bits_status_sd_rv32 (_cmdRouter_io_out_0_bits_status_sd_rv32),
.io_out_0_bits_status_zero1 (_cmdRouter_io_out_0_bits_status_zero1),
.io_out_0_bits_status_tsr (_cmdRouter_io_out_0_bits_status_tsr),
.io_out_0_bits_status_tw (_cmdRouter_io_out_0_bits_status_tw),
.io_out_0_bits_status_tvm (_cmdRouter_io_out_0_bits_status_tvm),
.io_out_0_bits_status_mxr (_cmdRouter_io_out_0_bits_status_mxr),
.io_out_0_bits_status_sum (_cmdRouter_io_out_0_bits_status_sum),
.io_out_0_bits_status_mprv (_cmdRouter_io_out_0_bits_status_mprv),
.io_out_0_bits_status_xs (_cmdRouter_io_out_0_bits_status_xs),
.io_out_0_bits_status_fs (_cmdRouter_io_out_0_bits_status_fs),
.io_out_0_bits_status_mpp (_cmdRouter_io_out_0_bits_status_mpp),
.io_out_0_bits_status_vs (_cmdRouter_io_out_0_bits_status_vs),
.io_out_0_bits_status_spp (_cmdRouter_io_out_0_bits_status_spp),
.io_out_0_bits_status_mpie (_cmdRouter_io_out_0_bits_status_mpie),
.io_out_0_bits_status_ube (_cmdRouter_io_out_0_bits_status_ube),
.io_out_0_bits_status_spie (_cmdRouter_io_out_0_bits_status_spie),
.io_out_0_bits_status_upie (_cmdRouter_io_out_0_bits_status_upie),
.io_out_0_bits_status_mie (_cmdRouter_io_out_0_bits_status_mie),
.io_out_0_bits_status_hie (_cmdRouter_io_out_0_bits_status_hie),
.io_out_0_bits_status_sie (_cmdRouter_io_out_0_bits_status_sie),
.io_out_0_bits_status_uie (_cmdRouter_io_out_0_bits_status_uie),
.io_busy (_cmdRouter_io_busy)
); // @[LazyRoCC.scala:102:27]
SimpleHellaCacheIF dcIF ( // @[LazyRoCC.scala:106:24]
.clock (clock),
.reset (reset),
.io_requestor_req_ready (_dcIF_io_requestor_req_ready),
.io_requestor_resp_valid (_dcIF_io_requestor_resp_valid),
.io_requestor_resp_bits_addr (_dcIF_io_requestor_resp_bits_addr),
.io_requestor_resp_bits_tag (_dcIF_io_requestor_resp_bits_tag),
.io_requestor_resp_bits_cmd (_dcIF_io_requestor_resp_bits_cmd),
.io_requestor_resp_bits_size (_dcIF_io_requestor_resp_bits_size),
.io_requestor_resp_bits_signed (_dcIF_io_requestor_resp_bits_signed),
.io_requestor_resp_bits_dprv (_dcIF_io_requestor_resp_bits_dprv),
.io_requestor_resp_bits_dv (_dcIF_io_requestor_resp_bits_dv),
.io_requestor_resp_bits_data (_dcIF_io_requestor_resp_bits_data),
.io_requestor_resp_bits_mask (_dcIF_io_requestor_resp_bits_mask),
.io_requestor_resp_bits_replay (_dcIF_io_requestor_resp_bits_replay),
.io_requestor_resp_bits_has_data (_dcIF_io_requestor_resp_bits_has_data),
.io_requestor_resp_bits_data_word_bypass (_dcIF_io_requestor_resp_bits_data_word_bypass),
.io_requestor_resp_bits_data_raw (_dcIF_io_requestor_resp_bits_data_raw),
.io_requestor_resp_bits_store_data (_dcIF_io_requestor_resp_bits_store_data),
.io_cache_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[HellaCache.scala:292:25]
.io_cache_req_valid (_dcIF_io_cache_req_valid),
.io_cache_s1_data_data (_dcIF_io_cache_s1_data_data),
.io_cache_s1_data_mask (_dcIF_io_cache_s1_data_mask),
.io_cache_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[HellaCache.scala:292:25]
.io_cache_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[HellaCache.scala:292:25]
.io_cache_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[HellaCache.scala:292:25]
.io_cache_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[HellaCache.scala:292:25]
.io_cache_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[HellaCache.scala:292:25]
.io_cache_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[HellaCache.scala:292:25]
.io_cache_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[HellaCache.scala:292:25]
.io_cache_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25]
.io_cache_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[HellaCache.scala:292:25]
.io_cache_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25]
.io_cache_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[HellaCache.scala:292:25]
.io_cache_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25]
.io_cache_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[HellaCache.scala:292:25]
.io_cache_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[HellaCache.scala:292:25]
.io_cache_ordered (_dcacheArb_io_requestor_1_ordered), // @[HellaCache.scala:292:25]
.io_cache_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[HellaCache.scala:292:25]
.io_cache_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[HellaCache.scala:292:25]
.io_cache_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[HellaCache.scala:292:25]
.io_cache_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[HellaCache.scala:292:25]
.io_cache_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[HellaCache.scala:292:25]
.io_cache_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[HellaCache.scala:292:25]
.io_cache_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25]
.io_cache_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25]
.io_cache_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25]
.io_cache_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25]
.io_cache_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore) // @[HellaCache.scala:292:25]
); // @[LazyRoCC.scala:106:24]
Queue2_RoCCResponse respArb_io_in_0_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_respArb_io_in_0_q_io_enq_ready),
.io_enq_valid (_gemmini_io_resp_valid), // @[Configs.scala:282:31]
.io_enq_bits_rd (_gemmini_io_resp_bits_rd), // @[Configs.scala:282:31]
.io_enq_bits_data (_gemmini_io_resp_bits_data), // @[Configs.scala:282:31]
.io_deq_ready (_respArb_io_in_0_ready), // @[LazyRoCC.scala:101:25]
.io_deq_valid (_respArb_io_in_0_q_io_deq_valid),
.io_deq_bits_rd (_respArb_io_in_0_q_io_deq_bits_rd),
.io_deq_bits_data (_respArb_io_in_0_q_io_deq_bits_data)
); // @[Decoupled.scala:362:21]
Rocket core ( // @[RocketTile.scala:147:20]
.clock (clock),
.reset (reset),
.io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17]
.io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17]
.io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17]
.io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17]
.io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17]
.io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17]
.io_imem_might_request (_core_io_imem_might_request),
.io_imem_req_valid (_core_io_imem_req_valid),
.io_imem_req_bits_pc (_core_io_imem_req_bits_pc),
.io_imem_req_bits_speculative (_core_io_imem_req_bits_speculative),
.io_imem_sfence_valid (_core_io_imem_sfence_valid),
.io_imem_sfence_bits_rs1 (_core_io_imem_sfence_bits_rs1),
.io_imem_sfence_bits_rs2 (_core_io_imem_sfence_bits_rs2),
.io_imem_sfence_bits_addr (_core_io_imem_sfence_bits_addr),
.io_imem_sfence_bits_asid (_core_io_imem_sfence_bits_asid),
.io_imem_sfence_bits_hv (_core_io_imem_sfence_bits_hv),
.io_imem_sfence_bits_hg (_core_io_imem_sfence_bits_hg),
.io_imem_resp_ready (_core_io_imem_resp_ready),
.io_imem_resp_valid (_frontend_io_cpu_resp_valid), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_cfiType (_frontend_io_cpu_resp_bits_btb_cfiType), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_taken (_frontend_io_cpu_resp_bits_btb_taken), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_mask (_frontend_io_cpu_resp_bits_btb_mask), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_bridx (_frontend_io_cpu_resp_bits_btb_bridx), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_target (_frontend_io_cpu_resp_bits_btb_target), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_entry (_frontend_io_cpu_resp_bits_btb_entry), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_bht_history (_frontend_io_cpu_resp_bits_btb_bht_history), // @[Frontend.scala:393:28]
.io_imem_resp_bits_btb_bht_value (_frontend_io_cpu_resp_bits_btb_bht_value), // @[Frontend.scala:393:28]
.io_imem_resp_bits_pc (_frontend_io_cpu_resp_bits_pc), // @[Frontend.scala:393:28]
.io_imem_resp_bits_data (_frontend_io_cpu_resp_bits_data), // @[Frontend.scala:393:28]
.io_imem_resp_bits_mask (_frontend_io_cpu_resp_bits_mask), // @[Frontend.scala:393:28]
.io_imem_resp_bits_xcpt_pf_inst (_frontend_io_cpu_resp_bits_xcpt_pf_inst), // @[Frontend.scala:393:28]
.io_imem_resp_bits_xcpt_gf_inst (_frontend_io_cpu_resp_bits_xcpt_gf_inst), // @[Frontend.scala:393:28]
.io_imem_resp_bits_xcpt_ae_inst (_frontend_io_cpu_resp_bits_xcpt_ae_inst), // @[Frontend.scala:393:28]
.io_imem_resp_bits_replay (_frontend_io_cpu_resp_bits_replay), // @[Frontend.scala:393:28]
.io_imem_gpa_valid (_frontend_io_cpu_gpa_valid), // @[Frontend.scala:393:28]
.io_imem_gpa_bits (_frontend_io_cpu_gpa_bits), // @[Frontend.scala:393:28]
.io_imem_gpa_is_pte (_frontend_io_cpu_gpa_is_pte), // @[Frontend.scala:393:28]
.io_imem_btb_update_valid (_core_io_imem_btb_update_valid),
.io_imem_btb_update_bits_prediction_cfiType (_core_io_imem_btb_update_bits_prediction_cfiType),
.io_imem_btb_update_bits_prediction_taken (_core_io_imem_btb_update_bits_prediction_taken),
.io_imem_btb_update_bits_prediction_mask (_core_io_imem_btb_update_bits_prediction_mask),
.io_imem_btb_update_bits_prediction_bridx (_core_io_imem_btb_update_bits_prediction_bridx),
.io_imem_btb_update_bits_prediction_target (_core_io_imem_btb_update_bits_prediction_target),
.io_imem_btb_update_bits_prediction_entry (_core_io_imem_btb_update_bits_prediction_entry),
.io_imem_btb_update_bits_prediction_bht_history (_core_io_imem_btb_update_bits_prediction_bht_history),
.io_imem_btb_update_bits_prediction_bht_value (_core_io_imem_btb_update_bits_prediction_bht_value),
.io_imem_btb_update_bits_pc (_core_io_imem_btb_update_bits_pc),
.io_imem_btb_update_bits_target (_core_io_imem_btb_update_bits_target),
.io_imem_btb_update_bits_isValid (_core_io_imem_btb_update_bits_isValid),
.io_imem_btb_update_bits_br_pc (_core_io_imem_btb_update_bits_br_pc),
.io_imem_btb_update_bits_cfiType (_core_io_imem_btb_update_bits_cfiType),
.io_imem_bht_update_valid (_core_io_imem_bht_update_valid),
.io_imem_bht_update_bits_prediction_history (_core_io_imem_bht_update_bits_prediction_history),
.io_imem_bht_update_bits_prediction_value (_core_io_imem_bht_update_bits_prediction_value),
.io_imem_bht_update_bits_pc (_core_io_imem_bht_update_bits_pc),
.io_imem_bht_update_bits_branch (_core_io_imem_bht_update_bits_branch),
.io_imem_bht_update_bits_taken (_core_io_imem_bht_update_bits_taken),
.io_imem_bht_update_bits_mispredict (_core_io_imem_bht_update_bits_mispredict),
.io_imem_flush_icache (_core_io_imem_flush_icache),
.io_imem_npc (_frontend_io_cpu_npc), // @[Frontend.scala:393:28]
.io_imem_perf_acquire (_frontend_io_cpu_perf_acquire), // @[Frontend.scala:393:28]
.io_imem_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[Frontend.scala:393:28]
.io_imem_progress (_core_io_imem_progress),
.io_dmem_req_ready (_dcacheArb_io_requestor_2_req_ready), // @[HellaCache.scala:292:25]
.io_dmem_req_valid (_core_io_dmem_req_valid),
.io_dmem_req_bits_addr (_core_io_dmem_req_bits_addr),
.io_dmem_req_bits_tag (_core_io_dmem_req_bits_tag),
.io_dmem_req_bits_cmd (_core_io_dmem_req_bits_cmd),
.io_dmem_req_bits_size (_core_io_dmem_req_bits_size),
.io_dmem_req_bits_signed (_core_io_dmem_req_bits_signed),
.io_dmem_req_bits_dprv (_core_io_dmem_req_bits_dprv),
.io_dmem_req_bits_dv (_core_io_dmem_req_bits_dv),
.io_dmem_req_bits_no_resp (_core_io_dmem_req_bits_no_resp),
.io_dmem_s1_kill (_core_io_dmem_s1_kill),
.io_dmem_s1_data_data (_core_io_dmem_s1_data_data),
.io_dmem_s2_nack (_dcacheArb_io_requestor_2_s2_nack), // @[HellaCache.scala:292:25]
.io_dmem_s2_nack_cause_raw (_dcacheArb_io_requestor_2_s2_nack_cause_raw), // @[HellaCache.scala:292:25]
.io_dmem_s2_uncached (_dcacheArb_io_requestor_2_s2_uncached), // @[HellaCache.scala:292:25]
.io_dmem_s2_paddr (_dcacheArb_io_requestor_2_s2_paddr), // @[HellaCache.scala:292:25]
.io_dmem_resp_valid (_dcacheArb_io_requestor_2_resp_valid), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_addr (_dcacheArb_io_requestor_2_resp_bits_addr), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_tag (_dcacheArb_io_requestor_2_resp_bits_tag), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_cmd (_dcacheArb_io_requestor_2_resp_bits_cmd), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_size (_dcacheArb_io_requestor_2_resp_bits_size), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_signed (_dcacheArb_io_requestor_2_resp_bits_signed), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_dprv (_dcacheArb_io_requestor_2_resp_bits_dprv), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_dv (_dcacheArb_io_requestor_2_resp_bits_dv), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_data (_dcacheArb_io_requestor_2_resp_bits_data), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_mask (_dcacheArb_io_requestor_2_resp_bits_mask), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_replay (_dcacheArb_io_requestor_2_resp_bits_replay), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_has_data (_dcacheArb_io_requestor_2_resp_bits_has_data), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_2_resp_bits_data_word_bypass), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_data_raw (_dcacheArb_io_requestor_2_resp_bits_data_raw), // @[HellaCache.scala:292:25]
.io_dmem_resp_bits_store_data (_dcacheArb_io_requestor_2_resp_bits_store_data), // @[HellaCache.scala:292:25]
.io_dmem_replay_next (_dcacheArb_io_requestor_2_replay_next), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_2_s2_xcpt_ma_ld), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ma_st (_dcacheArb_io_requestor_2_s2_xcpt_ma_st), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_2_s2_xcpt_pf_ld), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_pf_st (_dcacheArb_io_requestor_2_s2_xcpt_pf_st), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_2_s2_xcpt_ae_ld), // @[HellaCache.scala:292:25]
.io_dmem_s2_xcpt_ae_st (_dcacheArb_io_requestor_2_s2_xcpt_ae_st), // @[HellaCache.scala:292:25]
.io_dmem_s2_gpa (_dcacheArb_io_requestor_2_s2_gpa), // @[HellaCache.scala:292:25]
.io_dmem_ordered (_dcacheArb_io_requestor_2_ordered), // @[HellaCache.scala:292:25]
.io_dmem_store_pending (_dcacheArb_io_requestor_2_store_pending), // @[HellaCache.scala:292:25]
.io_dmem_perf_acquire (_dcacheArb_io_requestor_2_perf_acquire), // @[HellaCache.scala:292:25]
.io_dmem_perf_release (_dcacheArb_io_requestor_2_perf_release), // @[HellaCache.scala:292:25]
.io_dmem_perf_grant (_dcacheArb_io_requestor_2_perf_grant), // @[HellaCache.scala:292:25]
.io_dmem_perf_tlbMiss (_dcacheArb_io_requestor_2_perf_tlbMiss), // @[HellaCache.scala:292:25]
.io_dmem_perf_blocked (_dcacheArb_io_requestor_2_perf_blocked), // @[HellaCache.scala:292:25]
.io_dmem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenLoad), // @[HellaCache.scala:292:25]
.io_dmem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_2_perf_canAcceptStoreThenRMW), // @[HellaCache.scala:292:25]
.io_dmem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_2_perf_canAcceptLoadThenLoad), // @[HellaCache.scala:292:25]
.io_dmem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterLoad), // @[HellaCache.scala:292:25]
.io_dmem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_2_perf_storeBufferEmptyAfterStore), // @[HellaCache.scala:292:25]
.io_dmem_keep_clock_enabled (_core_io_dmem_keep_clock_enabled),
.io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode),
.io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn),
.io_ptw_sfence_valid (_core_io_ptw_sfence_valid),
.io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1),
.io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2),
.io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr),
.io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid),
.io_ptw_sfence_bits_hv (_core_io_ptw_sfence_bits_hv),
.io_ptw_sfence_bits_hg (_core_io_ptw_sfence_bits_hg),
.io_ptw_status_debug (_core_io_ptw_status_debug),
.io_ptw_status_cease (_core_io_ptw_status_cease),
.io_ptw_status_wfi (_core_io_ptw_status_wfi),
.io_ptw_status_isa (_core_io_ptw_status_isa),
.io_ptw_status_dprv (_core_io_ptw_status_dprv),
.io_ptw_status_dv (_core_io_ptw_status_dv),
.io_ptw_status_prv (_core_io_ptw_status_prv),
.io_ptw_status_v (_core_io_ptw_status_v),
.io_ptw_status_mpv (_core_io_ptw_status_mpv),
.io_ptw_status_gva (_core_io_ptw_status_gva),
.io_ptw_status_tsr (_core_io_ptw_status_tsr),
.io_ptw_status_tw (_core_io_ptw_status_tw),
.io_ptw_status_tvm (_core_io_ptw_status_tvm),
.io_ptw_status_mxr (_core_io_ptw_status_mxr),
.io_ptw_status_sum (_core_io_ptw_status_sum),
.io_ptw_status_mprv (_core_io_ptw_status_mprv),
.io_ptw_status_fs (_core_io_ptw_status_fs),
.io_ptw_status_mpp (_core_io_ptw_status_mpp),
.io_ptw_status_spp (_core_io_ptw_status_spp),
.io_ptw_status_mpie (_core_io_ptw_status_mpie),
.io_ptw_status_spie (_core_io_ptw_status_spie),
.io_ptw_status_mie (_core_io_ptw_status_mie),
.io_ptw_status_sie (_core_io_ptw_status_sie),
.io_ptw_hstatus_spvp (_core_io_ptw_hstatus_spvp),
.io_ptw_hstatus_spv (_core_io_ptw_hstatus_spv),
.io_ptw_hstatus_gva (_core_io_ptw_hstatus_gva),
.io_ptw_gstatus_debug (_core_io_ptw_gstatus_debug),
.io_ptw_gstatus_cease (_core_io_ptw_gstatus_cease),
.io_ptw_gstatus_wfi (_core_io_ptw_gstatus_wfi),
.io_ptw_gstatus_isa (_core_io_ptw_gstatus_isa),
.io_ptw_gstatus_dprv (_core_io_ptw_gstatus_dprv),
.io_ptw_gstatus_dv (_core_io_ptw_gstatus_dv),
.io_ptw_gstatus_prv (_core_io_ptw_gstatus_prv),
.io_ptw_gstatus_v (_core_io_ptw_gstatus_v),
.io_ptw_gstatus_zero2 (_core_io_ptw_gstatus_zero2),
.io_ptw_gstatus_mpv (_core_io_ptw_gstatus_mpv),
.io_ptw_gstatus_gva (_core_io_ptw_gstatus_gva),
.io_ptw_gstatus_mbe (_core_io_ptw_gstatus_mbe),
.io_ptw_gstatus_sbe (_core_io_ptw_gstatus_sbe),
.io_ptw_gstatus_sxl (_core_io_ptw_gstatus_sxl),
.io_ptw_gstatus_zero1 (_core_io_ptw_gstatus_zero1),
.io_ptw_gstatus_tsr (_core_io_ptw_gstatus_tsr),
.io_ptw_gstatus_tw (_core_io_ptw_gstatus_tw),
.io_ptw_gstatus_tvm (_core_io_ptw_gstatus_tvm),
.io_ptw_gstatus_mxr (_core_io_ptw_gstatus_mxr),
.io_ptw_gstatus_sum (_core_io_ptw_gstatus_sum),
.io_ptw_gstatus_mprv (_core_io_ptw_gstatus_mprv),
.io_ptw_gstatus_fs (_core_io_ptw_gstatus_fs),
.io_ptw_gstatus_mpp (_core_io_ptw_gstatus_mpp),
.io_ptw_gstatus_vs (_core_io_ptw_gstatus_vs),
.io_ptw_gstatus_spp (_core_io_ptw_gstatus_spp),
.io_ptw_gstatus_mpie (_core_io_ptw_gstatus_mpie),
.io_ptw_gstatus_ube (_core_io_ptw_gstatus_ube),
.io_ptw_gstatus_spie (_core_io_ptw_gstatus_spie),
.io_ptw_gstatus_upie (_core_io_ptw_gstatus_upie),
.io_ptw_gstatus_mie (_core_io_ptw_gstatus_mie),
.io_ptw_gstatus_hie (_core_io_ptw_gstatus_hie),
.io_ptw_gstatus_sie (_core_io_ptw_gstatus_sie),
.io_ptw_gstatus_uie (_core_io_ptw_gstatus_uie),
.io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w),
.io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r),
.io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w),
.io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r),
.io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w),
.io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r),
.io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w),
.io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r),
.io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w),
.io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r),
.io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w),
.io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r),
.io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w),
.io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r),
.io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w),
.io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r),
.io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask),
.io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[PTW.scala:802:19]
.io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[PTW.scala:802:19]
.io_ptw_customCSRs_csrs_0_ren (_core_io_ptw_customCSRs_csrs_0_ren),
.io_ptw_customCSRs_csrs_0_wen (_core_io_ptw_customCSRs_csrs_0_wen),
.io_ptw_customCSRs_csrs_0_wdata (_core_io_ptw_customCSRs_csrs_0_wdata),
.io_ptw_customCSRs_csrs_0_value (_core_io_ptw_customCSRs_csrs_0_value),
.io_ptw_customCSRs_csrs_1_ren (_core_io_ptw_customCSRs_csrs_1_ren),
.io_ptw_customCSRs_csrs_1_wen (_core_io_ptw_customCSRs_csrs_1_wen),
.io_ptw_customCSRs_csrs_1_wdata (_core_io_ptw_customCSRs_csrs_1_wdata),
.io_ptw_customCSRs_csrs_1_value (_core_io_ptw_customCSRs_csrs_1_value),
.io_ptw_customCSRs_csrs_2_ren (_core_io_ptw_customCSRs_csrs_2_ren),
.io_ptw_customCSRs_csrs_2_wen (_core_io_ptw_customCSRs_csrs_2_wen),
.io_ptw_customCSRs_csrs_2_wdata (_core_io_ptw_customCSRs_csrs_2_wdata),
.io_ptw_customCSRs_csrs_2_value (_core_io_ptw_customCSRs_csrs_2_value),
.io_ptw_customCSRs_csrs_3_ren (_core_io_ptw_customCSRs_csrs_3_ren),
.io_ptw_customCSRs_csrs_3_wen (_core_io_ptw_customCSRs_csrs_3_wen),
.io_ptw_customCSRs_csrs_3_wdata (_core_io_ptw_customCSRs_csrs_3_wdata),
.io_ptw_customCSRs_csrs_3_value (_core_io_ptw_customCSRs_csrs_3_value),
.io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[PTW.scala:802:19]
.io_fpu_hartid (_core_io_fpu_hartid),
.io_fpu_time (_core_io_fpu_time),
.io_fpu_inst (_core_io_fpu_inst),
.io_fpu_fromint_data (_core_io_fpu_fromint_data),
.io_fpu_fcsr_rm (_core_io_fpu_fcsr_rm),
.io_fpu_fcsr_flags_valid (_fpuOpt_io_fcsr_flags_valid), // @[RocketTile.scala:242:62]
.io_fpu_fcsr_flags_bits (_fpuOpt_io_fcsr_flags_bits), // @[RocketTile.scala:242:62]
.io_fpu_store_data (_fpuOpt_io_store_data), // @[RocketTile.scala:242:62]
.io_fpu_toint_data (_fpuOpt_io_toint_data), // @[RocketTile.scala:242:62]
.io_fpu_ll_resp_val (_core_io_fpu_ll_resp_val),
.io_fpu_ll_resp_type (_core_io_fpu_ll_resp_type),
.io_fpu_ll_resp_tag (_core_io_fpu_ll_resp_tag),
.io_fpu_ll_resp_data (_core_io_fpu_ll_resp_data),
.io_fpu_valid (_core_io_fpu_valid),
.io_fpu_fcsr_rdy (_fpuOpt_io_fcsr_rdy), // @[RocketTile.scala:242:62]
.io_fpu_nack_mem (_fpuOpt_io_nack_mem), // @[RocketTile.scala:242:62]
.io_fpu_illegal_rm (_fpuOpt_io_illegal_rm), // @[RocketTile.scala:242:62]
.io_fpu_killx (_core_io_fpu_killx),
.io_fpu_killm (_core_io_fpu_killm),
.io_fpu_dec_ldst (_fpuOpt_io_dec_ldst), // @[RocketTile.scala:242:62]
.io_fpu_dec_wen (_fpuOpt_io_dec_wen), // @[RocketTile.scala:242:62]
.io_fpu_dec_ren1 (_fpuOpt_io_dec_ren1), // @[RocketTile.scala:242:62]
.io_fpu_dec_ren2 (_fpuOpt_io_dec_ren2), // @[RocketTile.scala:242:62]
.io_fpu_dec_ren3 (_fpuOpt_io_dec_ren3), // @[RocketTile.scala:242:62]
.io_fpu_dec_swap12 (_fpuOpt_io_dec_swap12), // @[RocketTile.scala:242:62]
.io_fpu_dec_swap23 (_fpuOpt_io_dec_swap23), // @[RocketTile.scala:242:62]
.io_fpu_dec_typeTagIn (_fpuOpt_io_dec_typeTagIn), // @[RocketTile.scala:242:62]
.io_fpu_dec_typeTagOut (_fpuOpt_io_dec_typeTagOut), // @[RocketTile.scala:242:62]
.io_fpu_dec_fromint (_fpuOpt_io_dec_fromint), // @[RocketTile.scala:242:62]
.io_fpu_dec_toint (_fpuOpt_io_dec_toint), // @[RocketTile.scala:242:62]
.io_fpu_dec_fastpipe (_fpuOpt_io_dec_fastpipe), // @[RocketTile.scala:242:62]
.io_fpu_dec_fma (_fpuOpt_io_dec_fma), // @[RocketTile.scala:242:62]
.io_fpu_dec_div (_fpuOpt_io_dec_div), // @[RocketTile.scala:242:62]
.io_fpu_dec_sqrt (_fpuOpt_io_dec_sqrt), // @[RocketTile.scala:242:62]
.io_fpu_dec_wflags (_fpuOpt_io_dec_wflags), // @[RocketTile.scala:242:62]
.io_fpu_dec_vec (_fpuOpt_io_dec_vec), // @[RocketTile.scala:242:62]
.io_fpu_sboard_set (_fpuOpt_io_sboard_set), // @[RocketTile.scala:242:62]
.io_fpu_sboard_clr (_fpuOpt_io_sboard_clr), // @[RocketTile.scala:242:62]
.io_fpu_sboard_clra (_fpuOpt_io_sboard_clra), // @[RocketTile.scala:242:62]
.io_fpu_keep_clock_enabled (_core_io_fpu_keep_clock_enabled),
.io_rocc_cmd_ready (_cmdRouter_io_in_ready), // @[LazyRoCC.scala:102:27]
.io_rocc_cmd_valid (_core_io_rocc_cmd_valid),
.io_rocc_cmd_bits_inst_funct (_core_io_rocc_cmd_bits_inst_funct),
.io_rocc_cmd_bits_inst_rs2 (_core_io_rocc_cmd_bits_inst_rs2),
.io_rocc_cmd_bits_inst_rs1 (_core_io_rocc_cmd_bits_inst_rs1),
.io_rocc_cmd_bits_inst_xd (_core_io_rocc_cmd_bits_inst_xd),
.io_rocc_cmd_bits_inst_xs1 (_core_io_rocc_cmd_bits_inst_xs1),
.io_rocc_cmd_bits_inst_xs2 (_core_io_rocc_cmd_bits_inst_xs2),
.io_rocc_cmd_bits_inst_rd (_core_io_rocc_cmd_bits_inst_rd),
.io_rocc_cmd_bits_inst_opcode (_core_io_rocc_cmd_bits_inst_opcode),
.io_rocc_cmd_bits_rs1 (_core_io_rocc_cmd_bits_rs1),
.io_rocc_cmd_bits_rs2 (_core_io_rocc_cmd_bits_rs2),
.io_rocc_cmd_bits_status_debug (_core_io_rocc_cmd_bits_status_debug),
.io_rocc_cmd_bits_status_cease (_core_io_rocc_cmd_bits_status_cease),
.io_rocc_cmd_bits_status_wfi (_core_io_rocc_cmd_bits_status_wfi),
.io_rocc_cmd_bits_status_isa (_core_io_rocc_cmd_bits_status_isa),
.io_rocc_cmd_bits_status_dprv (_core_io_rocc_cmd_bits_status_dprv),
.io_rocc_cmd_bits_status_dv (_core_io_rocc_cmd_bits_status_dv),
.io_rocc_cmd_bits_status_prv (_core_io_rocc_cmd_bits_status_prv),
.io_rocc_cmd_bits_status_v (_core_io_rocc_cmd_bits_status_v),
.io_rocc_cmd_bits_status_mpv (_core_io_rocc_cmd_bits_status_mpv),
.io_rocc_cmd_bits_status_gva (_core_io_rocc_cmd_bits_status_gva),
.io_rocc_cmd_bits_status_tsr (_core_io_rocc_cmd_bits_status_tsr),
.io_rocc_cmd_bits_status_tw (_core_io_rocc_cmd_bits_status_tw),
.io_rocc_cmd_bits_status_tvm (_core_io_rocc_cmd_bits_status_tvm),
.io_rocc_cmd_bits_status_mxr (_core_io_rocc_cmd_bits_status_mxr),
.io_rocc_cmd_bits_status_sum (_core_io_rocc_cmd_bits_status_sum),
.io_rocc_cmd_bits_status_mprv (_core_io_rocc_cmd_bits_status_mprv),
.io_rocc_cmd_bits_status_fs (_core_io_rocc_cmd_bits_status_fs),
.io_rocc_cmd_bits_status_mpp (_core_io_rocc_cmd_bits_status_mpp),
.io_rocc_cmd_bits_status_spp (_core_io_rocc_cmd_bits_status_spp),
.io_rocc_cmd_bits_status_mpie (_core_io_rocc_cmd_bits_status_mpie),
.io_rocc_cmd_bits_status_spie (_core_io_rocc_cmd_bits_status_spie),
.io_rocc_cmd_bits_status_mie (_core_io_rocc_cmd_bits_status_mie),
.io_rocc_cmd_bits_status_sie (_core_io_rocc_cmd_bits_status_sie),
.io_rocc_resp_ready (_core_io_rocc_resp_ready),
.io_rocc_resp_valid (_respArb_io_out_valid), // @[LazyRoCC.scala:101:25]
.io_rocc_resp_bits_rd (_respArb_io_out_bits_rd), // @[LazyRoCC.scala:101:25]
.io_rocc_resp_bits_data (_respArb_io_out_bits_data), // @[LazyRoCC.scala:101:25]
.io_rocc_busy (_core_io_rocc_busy_T), // @[RocketTile.scala:213:49]
.io_rocc_interrupt (_gemmini_io_interrupt), // @[Configs.scala:282:31]
.io_rocc_exception (_core_io_rocc_exception),
.io_trace_insns_0_valid (traceSourceNodeOut_insns_0_valid),
.io_trace_insns_0_iaddr (traceSourceNodeOut_insns_0_iaddr),
.io_trace_insns_0_insn (traceSourceNodeOut_insns_0_insn),
.io_trace_insns_0_priv (traceSourceNodeOut_insns_0_priv),
.io_trace_insns_0_exception (traceSourceNodeOut_insns_0_exception),
.io_trace_insns_0_interrupt (traceSourceNodeOut_insns_0_interrupt),
.io_trace_insns_0_cause (traceSourceNodeOut_insns_0_cause),
.io_trace_insns_0_tval (traceSourceNodeOut_insns_0_tval),
.io_trace_time (traceSourceNodeOut_time),
.io_bpwatch_0_valid_0 (bpwatchSourceNodeOut_0_valid_0),
.io_bpwatch_0_action (bpwatchSourceNodeOut_0_action),
.io_wfi (_core_io_wfi)
); // @[RocketTile.scala:147:20]
assign auto_buffer_out_1_a_valid = auto_buffer_out_1_a_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_opcode = auto_buffer_out_1_a_bits_opcode_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_param = auto_buffer_out_1_a_bits_param_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_size = auto_buffer_out_1_a_bits_size_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_source = auto_buffer_out_1_a_bits_source_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_address = auto_buffer_out_1_a_bits_address_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_mask = auto_buffer_out_1_a_bits_mask_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_a_bits_data = auto_buffer_out_1_a_bits_data_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_b_ready = auto_buffer_out_1_b_ready_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_valid = auto_buffer_out_1_c_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_bits_opcode = auto_buffer_out_1_c_bits_opcode_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_bits_param = auto_buffer_out_1_c_bits_param_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_bits_size = auto_buffer_out_1_c_bits_size_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_bits_source = auto_buffer_out_1_c_bits_source_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_bits_address = auto_buffer_out_1_c_bits_address_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_c_bits_data = auto_buffer_out_1_c_bits_data_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_d_ready = auto_buffer_out_1_d_ready_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_e_valid = auto_buffer_out_1_e_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_1_e_bits_sink = auto_buffer_out_1_e_bits_sink_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_valid = auto_buffer_out_0_a_valid_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_opcode = auto_buffer_out_0_a_bits_opcode_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_param = auto_buffer_out_0_a_bits_param_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_size = auto_buffer_out_0_a_bits_size_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_source = auto_buffer_out_0_a_bits_source_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_address = auto_buffer_out_0_a_bits_address_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_mask = auto_buffer_out_0_a_bits_mask_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_data = auto_buffer_out_0_a_bits_data_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_a_bits_corrupt = auto_buffer_out_0_a_bits_corrupt_0; // @[RocketTile.scala:141:7]
assign auto_buffer_out_0_d_ready = auto_buffer_out_0_d_ready_0; // @[RocketTile.scala:141:7]
assign auto_wfi_out_0 = auto_wfi_out_0_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_valid = auto_trace_source_out_insns_0_valid_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_iaddr = auto_trace_source_out_insns_0_iaddr_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_insn = auto_trace_source_out_insns_0_insn_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_priv = auto_trace_source_out_insns_0_priv_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_exception = auto_trace_source_out_insns_0_exception_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_interrupt = auto_trace_source_out_insns_0_interrupt_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_cause = auto_trace_source_out_insns_0_cause_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_insns_0_tval = auto_trace_source_out_insns_0_tval_0; // @[RocketTile.scala:141:7]
assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[RocketTile.scala:141:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_11 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_123
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_125
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_126
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_11( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_123 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_124 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_125 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_126 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_2 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
node _wentry_conf_T = sub(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T_2 = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_3 = tail(_wentry_conf_T_2, 1)
connect wentry.conf, _wentry_conf_T_3
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_2( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36]
wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36]
wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_5 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_6 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_6 | ~(_T_39 | ~(_T_44 | _GEN_5 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_7 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_8 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_8 | ~(_T_44 | _T_47 | ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_6 | _T_39 | ~(_T_44 | ~(_GEN_5 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<13>(0h1000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = or(_T_27, _T_32)
node _T_69 = or(_T_68, _T_37)
node _T_70 = or(_T_69, _T_42)
node _T_71 = or(_T_70, _T_47)
node _T_72 = or(_T_71, _T_52)
node _T_73 = or(_T_72, _T_57)
node _T_74 = or(_T_73, _T_62)
node _T_75 = or(_T_74, _T_67)
node _T_76 = and(_T_22, _T_75)
node _T_77 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_78 = or(UInt<1>(0h0), _T_77)
node _T_79 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<17>(0h10000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<29>(0h10000000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = and(_T_78, _T_89)
node _T_91 = or(UInt<1>(0h0), _T_76)
node _T_92 = or(_T_91, _T_90)
node _T_93 = and(_T_21, _T_92)
node _T_94 = asUInt(reset)
node _T_95 = eq(_T_94, UInt<1>(0h0))
when _T_95 :
node _T_96 = eq(_T_93, UInt<1>(0h0))
when _T_96 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_93, UInt<1>(0h1), "") : assert_2
node _T_97 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_98 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_99 = and(_T_97, _T_98)
node _T_100 = or(UInt<1>(0h0), _T_99)
node _T_101 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<14>(0h2000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<13>(0h1000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<18>(0h2f000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<17>(0h10000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<17>(0h10000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = or(_T_105, _T_110)
node _T_157 = or(_T_156, _T_115)
node _T_158 = or(_T_157, _T_120)
node _T_159 = or(_T_158, _T_125)
node _T_160 = or(_T_159, _T_130)
node _T_161 = or(_T_160, _T_135)
node _T_162 = or(_T_161, _T_140)
node _T_163 = or(_T_162, _T_145)
node _T_164 = or(_T_163, _T_150)
node _T_165 = or(_T_164, _T_155)
node _T_166 = and(_T_100, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(UInt<1>(0h0), _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_168, UInt<1>(0h1), "") : assert_3
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_175 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_175, UInt<1>(0h1), "") : assert_5
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(is_aligned, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_182 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_183 = asUInt(reset)
node _T_184 = eq(_T_183, UInt<1>(0h0))
when _T_184 :
node _T_185 = eq(_T_182, UInt<1>(0h0))
when _T_185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_182, UInt<1>(0h1), "") : assert_7
node _T_186 = not(io.in.a.bits.mask)
node _T_187 = eq(_T_186, UInt<1>(0h0))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_187, UInt<1>(0h1), "") : assert_8
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_191, UInt<1>(0h1), "") : assert_9
node _T_195 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_200 = and(_T_198, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_203 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<14>(0h2000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<18>(0h2f000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_224 = cvt(_T_223)
node _T_225 = and(_T_224, asSInt(UInt<17>(0h10000)))
node _T_226 = asSInt(_T_225)
node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0)))
node _T_228 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_234 = cvt(_T_233)
node _T_235 = and(_T_234, asSInt(UInt<27>(0h4000000)))
node _T_236 = asSInt(_T_235)
node _T_237 = eq(_T_236, asSInt(UInt<1>(0h0)))
node _T_238 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_239 = cvt(_T_238)
node _T_240 = and(_T_239, asSInt(UInt<13>(0h1000)))
node _T_241 = asSInt(_T_240)
node _T_242 = eq(_T_241, asSInt(UInt<1>(0h0)))
node _T_243 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_244 = cvt(_T_243)
node _T_245 = and(_T_244, asSInt(UInt<13>(0h1000)))
node _T_246 = asSInt(_T_245)
node _T_247 = eq(_T_246, asSInt(UInt<1>(0h0)))
node _T_248 = or(_T_207, _T_212)
node _T_249 = or(_T_248, _T_217)
node _T_250 = or(_T_249, _T_222)
node _T_251 = or(_T_250, _T_227)
node _T_252 = or(_T_251, _T_232)
node _T_253 = or(_T_252, _T_237)
node _T_254 = or(_T_253, _T_242)
node _T_255 = or(_T_254, _T_247)
node _T_256 = and(_T_202, _T_255)
node _T_257 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<29>(0h10000000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = or(_T_263, _T_268)
node _T_270 = and(_T_258, _T_269)
node _T_271 = or(UInt<1>(0h0), _T_256)
node _T_272 = or(_T_271, _T_270)
node _T_273 = and(_T_201, _T_272)
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(_T_273, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_273, UInt<1>(0h1), "") : assert_10
node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_279 = and(_T_277, _T_278)
node _T_280 = or(UInt<1>(0h0), _T_279)
node _T_281 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<14>(0h2000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<13>(0h1000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_292 = cvt(_T_291)
node _T_293 = and(_T_292, asSInt(UInt<17>(0h10000)))
node _T_294 = asSInt(_T_293)
node _T_295 = eq(_T_294, asSInt(UInt<1>(0h0)))
node _T_296 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<18>(0h2f000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<17>(0h10000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<13>(0h1000)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<17>(0h10000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_317 = cvt(_T_316)
node _T_318 = and(_T_317, asSInt(UInt<27>(0h4000000)))
node _T_319 = asSInt(_T_318)
node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0)))
node _T_321 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_322 = cvt(_T_321)
node _T_323 = and(_T_322, asSInt(UInt<13>(0h1000)))
node _T_324 = asSInt(_T_323)
node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0)))
node _T_326 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<13>(0h1000)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<29>(0h10000000)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = or(_T_285, _T_290)
node _T_337 = or(_T_336, _T_295)
node _T_338 = or(_T_337, _T_300)
node _T_339 = or(_T_338, _T_305)
node _T_340 = or(_T_339, _T_310)
node _T_341 = or(_T_340, _T_315)
node _T_342 = or(_T_341, _T_320)
node _T_343 = or(_T_342, _T_325)
node _T_344 = or(_T_343, _T_330)
node _T_345 = or(_T_344, _T_335)
node _T_346 = and(_T_280, _T_345)
node _T_347 = or(UInt<1>(0h0), _T_346)
node _T_348 = and(UInt<1>(0h0), _T_347)
node _T_349 = asUInt(reset)
node _T_350 = eq(_T_349, UInt<1>(0h0))
when _T_350 :
node _T_351 = eq(_T_348, UInt<1>(0h0))
when _T_351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_348, UInt<1>(0h1), "") : assert_11
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_355 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_355, UInt<1>(0h1), "") : assert_13
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(is_aligned, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_362 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_362, UInt<1>(0h1), "") : assert_15
node _T_366 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_366, UInt<1>(0h1), "") : assert_16
node _T_370 = not(io.in.a.bits.mask)
node _T_371 = eq(_T_370, UInt<1>(0h0))
node _T_372 = asUInt(reset)
node _T_373 = eq(_T_372, UInt<1>(0h0))
when _T_373 :
node _T_374 = eq(_T_371, UInt<1>(0h0))
when _T_374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_371, UInt<1>(0h1), "") : assert_17
node _T_375 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_375, UInt<1>(0h1), "") : assert_18
node _T_379 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_379 :
node _T_380 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_381 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
node _T_385 = or(UInt<1>(0h0), _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_385, UInt<1>(0h1), "") : assert_19
node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_391 = and(_T_389, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_394 = cvt(_T_393)
node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000)))
node _T_396 = asSInt(_T_395)
node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0)))
node _T_398 = and(_T_392, _T_397)
node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_400 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_401 = and(_T_399, _T_400)
node _T_402 = or(UInt<1>(0h0), _T_401)
node _T_403 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_404 = cvt(_T_403)
node _T_405 = and(_T_404, asSInt(UInt<14>(0h2000)))
node _T_406 = asSInt(_T_405)
node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0)))
node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_409 = cvt(_T_408)
node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000)))
node _T_411 = asSInt(_T_410)
node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0)))
node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_414 = cvt(_T_413)
node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000)))
node _T_416 = asSInt(_T_415)
node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0)))
node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<13>(0h1000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<29>(0h10000000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = or(_T_407, _T_412)
node _T_454 = or(_T_453, _T_417)
node _T_455 = or(_T_454, _T_422)
node _T_456 = or(_T_455, _T_427)
node _T_457 = or(_T_456, _T_432)
node _T_458 = or(_T_457, _T_437)
node _T_459 = or(_T_458, _T_442)
node _T_460 = or(_T_459, _T_447)
node _T_461 = or(_T_460, _T_452)
node _T_462 = and(_T_402, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_398)
node _T_464 = or(_T_463, _T_462)
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_464, UInt<1>(0h1), "") : assert_20
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_471 = asUInt(reset)
node _T_472 = eq(_T_471, UInt<1>(0h0))
when _T_472 :
node _T_473 = eq(is_aligned, UInt<1>(0h0))
when _T_473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_474 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_474, UInt<1>(0h1), "") : assert_23
node _T_478 = eq(io.in.a.bits.mask, mask)
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_478, UInt<1>(0h1), "") : assert_24
node _T_482 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_482, UInt<1>(0h1), "") : assert_25
node _T_486 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_486 :
node _T_487 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_488 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_489 = and(_T_487, _T_488)
node _T_490 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_491 = and(_T_489, _T_490)
node _T_492 = or(UInt<1>(0h0), _T_491)
node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_495 = and(_T_493, _T_494)
node _T_496 = or(UInt<1>(0h0), _T_495)
node _T_497 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<13>(0h1000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = and(_T_496, _T_501)
node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_504 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_505 = and(_T_503, _T_504)
node _T_506 = or(UInt<1>(0h0), _T_505)
node _T_507 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<14>(0h2000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<18>(0h2f000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<17>(0h10000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<13>(0h1000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<27>(0h4000000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<13>(0h1000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_543 = cvt(_T_542)
node _T_544 = and(_T_543, asSInt(UInt<13>(0h1000)))
node _T_545 = asSInt(_T_544)
node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0)))
node _T_547 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_548 = cvt(_T_547)
node _T_549 = and(_T_548, asSInt(UInt<29>(0h10000000)))
node _T_550 = asSInt(_T_549)
node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0)))
node _T_552 = or(_T_511, _T_516)
node _T_553 = or(_T_552, _T_521)
node _T_554 = or(_T_553, _T_526)
node _T_555 = or(_T_554, _T_531)
node _T_556 = or(_T_555, _T_536)
node _T_557 = or(_T_556, _T_541)
node _T_558 = or(_T_557, _T_546)
node _T_559 = or(_T_558, _T_551)
node _T_560 = and(_T_506, _T_559)
node _T_561 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_562 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<17>(0h10000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = and(_T_561, _T_566)
node _T_568 = or(UInt<1>(0h0), _T_502)
node _T_569 = or(_T_568, _T_560)
node _T_570 = or(_T_569, _T_567)
node _T_571 = and(_T_492, _T_570)
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(_T_571, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_571, UInt<1>(0h1), "") : assert_26
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(is_aligned, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_581 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_581, UInt<1>(0h1), "") : assert_29
node _T_585 = eq(io.in.a.bits.mask, mask)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_585, UInt<1>(0h1), "") : assert_30
node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_589 :
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_594 = and(_T_592, _T_593)
node _T_595 = or(UInt<1>(0h0), _T_594)
node _T_596 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_597 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_598 = and(_T_596, _T_597)
node _T_599 = or(UInt<1>(0h0), _T_598)
node _T_600 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_601 = cvt(_T_600)
node _T_602 = and(_T_601, asSInt(UInt<13>(0h1000)))
node _T_603 = asSInt(_T_602)
node _T_604 = eq(_T_603, asSInt(UInt<1>(0h0)))
node _T_605 = and(_T_599, _T_604)
node _T_606 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_607 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(UInt<1>(0h0), _T_608)
node _T_610 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<14>(0h2000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<18>(0h2f000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<17>(0h10000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_626 = cvt(_T_625)
node _T_627 = and(_T_626, asSInt(UInt<13>(0h1000)))
node _T_628 = asSInt(_T_627)
node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0)))
node _T_630 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<17>(0h10000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<27>(0h4000000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<13>(0h1000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_646 = cvt(_T_645)
node _T_647 = and(_T_646, asSInt(UInt<13>(0h1000)))
node _T_648 = asSInt(_T_647)
node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0)))
node _T_650 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<29>(0h10000000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = or(_T_614, _T_619)
node _T_656 = or(_T_655, _T_624)
node _T_657 = or(_T_656, _T_629)
node _T_658 = or(_T_657, _T_634)
node _T_659 = or(_T_658, _T_639)
node _T_660 = or(_T_659, _T_644)
node _T_661 = or(_T_660, _T_649)
node _T_662 = or(_T_661, _T_654)
node _T_663 = and(_T_609, _T_662)
node _T_664 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_665 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = and(_T_664, _T_669)
node _T_671 = or(UInt<1>(0h0), _T_605)
node _T_672 = or(_T_671, _T_663)
node _T_673 = or(_T_672, _T_670)
node _T_674 = and(_T_595, _T_673)
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_674, UInt<1>(0h1), "") : assert_31
node _T_678 = asUInt(reset)
node _T_679 = eq(_T_678, UInt<1>(0h0))
when _T_679 :
node _T_680 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(is_aligned, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_684 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_685 = asUInt(reset)
node _T_686 = eq(_T_685, UInt<1>(0h0))
when _T_686 :
node _T_687 = eq(_T_684, UInt<1>(0h0))
when _T_687 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_684, UInt<1>(0h1), "") : assert_34
node _T_688 = not(mask)
node _T_689 = and(io.in.a.bits.mask, _T_688)
node _T_690 = eq(_T_689, UInt<1>(0h0))
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_690, UInt<1>(0h1), "") : assert_35
node _T_694 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_694 :
node _T_695 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_696 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_699 = and(_T_697, _T_698)
node _T_700 = or(UInt<1>(0h0), _T_699)
node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_702 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_703 = and(_T_701, _T_702)
node _T_704 = or(UInt<1>(0h0), _T_703)
node _T_705 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<14>(0h2000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<18>(0h2f000)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_721 = cvt(_T_720)
node _T_722 = and(_T_721, asSInt(UInt<17>(0h10000)))
node _T_723 = asSInt(_T_722)
node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0)))
node _T_725 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_726 = cvt(_T_725)
node _T_727 = and(_T_726, asSInt(UInt<13>(0h1000)))
node _T_728 = asSInt(_T_727)
node _T_729 = eq(_T_728, asSInt(UInt<1>(0h0)))
node _T_730 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<27>(0h4000000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_736 = cvt(_T_735)
node _T_737 = and(_T_736, asSInt(UInt<13>(0h1000)))
node _T_738 = asSInt(_T_737)
node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0)))
node _T_740 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<13>(0h1000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = or(_T_709, _T_714)
node _T_746 = or(_T_745, _T_719)
node _T_747 = or(_T_746, _T_724)
node _T_748 = or(_T_747, _T_729)
node _T_749 = or(_T_748, _T_734)
node _T_750 = or(_T_749, _T_739)
node _T_751 = or(_T_750, _T_744)
node _T_752 = and(_T_704, _T_751)
node _T_753 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_754 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<17>(0h10000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = and(_T_753, _T_758)
node _T_760 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_761 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_762 = and(_T_760, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<17>(0h10000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_770 = cvt(_T_769)
node _T_771 = and(_T_770, asSInt(UInt<29>(0h10000000)))
node _T_772 = asSInt(_T_771)
node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0)))
node _T_774 = or(_T_768, _T_773)
node _T_775 = and(_T_763, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_752)
node _T_777 = or(_T_776, _T_759)
node _T_778 = or(_T_777, _T_775)
node _T_779 = and(_T_700, _T_778)
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(_T_779, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_779, UInt<1>(0h1), "") : assert_36
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(is_aligned, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_789 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_789, UInt<1>(0h1), "") : assert_39
node _T_793 = eq(io.in.a.bits.mask, mask)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_793, UInt<1>(0h1), "") : assert_40
node _T_797 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_797 :
node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_800 = and(_T_798, _T_799)
node _T_801 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_802 = and(_T_800, _T_801)
node _T_803 = or(UInt<1>(0h0), _T_802)
node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_805 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_806 = and(_T_804, _T_805)
node _T_807 = or(UInt<1>(0h0), _T_806)
node _T_808 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_809 = cvt(_T_808)
node _T_810 = and(_T_809, asSInt(UInt<14>(0h2000)))
node _T_811 = asSInt(_T_810)
node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0)))
node _T_813 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<18>(0h2f000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_834 = cvt(_T_833)
node _T_835 = and(_T_834, asSInt(UInt<27>(0h4000000)))
node _T_836 = asSInt(_T_835)
node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0)))
node _T_838 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<13>(0h1000)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<13>(0h1000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = or(_T_812, _T_817)
node _T_849 = or(_T_848, _T_822)
node _T_850 = or(_T_849, _T_827)
node _T_851 = or(_T_850, _T_832)
node _T_852 = or(_T_851, _T_837)
node _T_853 = or(_T_852, _T_842)
node _T_854 = or(_T_853, _T_847)
node _T_855 = and(_T_807, _T_854)
node _T_856 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_857 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<17>(0h10000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = and(_T_856, _T_861)
node _T_863 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_864 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_865 = and(_T_863, _T_864)
node _T_866 = or(UInt<1>(0h0), _T_865)
node _T_867 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_868 = cvt(_T_867)
node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000)))
node _T_870 = asSInt(_T_869)
node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0)))
node _T_872 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<29>(0h10000000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = or(_T_871, _T_876)
node _T_878 = and(_T_866, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_855)
node _T_880 = or(_T_879, _T_862)
node _T_881 = or(_T_880, _T_878)
node _T_882 = and(_T_803, _T_881)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_882, UInt<1>(0h1), "") : assert_41
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(is_aligned, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_892, UInt<1>(0h1), "") : assert_44
node _T_896 = eq(io.in.a.bits.mask, mask)
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_896, UInt<1>(0h1), "") : assert_45
node _T_900 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_900 :
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_903 = and(_T_901, _T_902)
node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_905 = and(_T_903, _T_904)
node _T_906 = or(UInt<1>(0h0), _T_905)
node _T_907 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_908 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_909 = and(_T_907, _T_908)
node _T_910 = or(UInt<1>(0h0), _T_909)
node _T_911 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_912 = cvt(_T_911)
node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000)))
node _T_914 = asSInt(_T_913)
node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = and(_T_910, _T_915)
node _T_917 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_918 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_919 = cvt(_T_918)
node _T_920 = and(_T_919, asSInt(UInt<14>(0h2000)))
node _T_921 = asSInt(_T_920)
node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0)))
node _T_923 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_924 = cvt(_T_923)
node _T_925 = and(_T_924, asSInt(UInt<17>(0h10000)))
node _T_926 = asSInt(_T_925)
node _T_927 = eq(_T_926, asSInt(UInt<1>(0h0)))
node _T_928 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_929 = cvt(_T_928)
node _T_930 = and(_T_929, asSInt(UInt<18>(0h2f000)))
node _T_931 = asSInt(_T_930)
node _T_932 = eq(_T_931, asSInt(UInt<1>(0h0)))
node _T_933 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_934 = cvt(_T_933)
node _T_935 = and(_T_934, asSInt(UInt<17>(0h10000)))
node _T_936 = asSInt(_T_935)
node _T_937 = eq(_T_936, asSInt(UInt<1>(0h0)))
node _T_938 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_939 = cvt(_T_938)
node _T_940 = and(_T_939, asSInt(UInt<13>(0h1000)))
node _T_941 = asSInt(_T_940)
node _T_942 = eq(_T_941, asSInt(UInt<1>(0h0)))
node _T_943 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_944 = cvt(_T_943)
node _T_945 = and(_T_944, asSInt(UInt<27>(0h4000000)))
node _T_946 = asSInt(_T_945)
node _T_947 = eq(_T_946, asSInt(UInt<1>(0h0)))
node _T_948 = xor(io.in.a.bits.address, UInt<29>(0h10016000))
node _T_949 = cvt(_T_948)
node _T_950 = and(_T_949, asSInt(UInt<13>(0h1000)))
node _T_951 = asSInt(_T_950)
node _T_952 = eq(_T_951, asSInt(UInt<1>(0h0)))
node _T_953 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_954 = cvt(_T_953)
node _T_955 = and(_T_954, asSInt(UInt<13>(0h1000)))
node _T_956 = asSInt(_T_955)
node _T_957 = eq(_T_956, asSInt(UInt<1>(0h0)))
node _T_958 = or(_T_922, _T_927)
node _T_959 = or(_T_958, _T_932)
node _T_960 = or(_T_959, _T_937)
node _T_961 = or(_T_960, _T_942)
node _T_962 = or(_T_961, _T_947)
node _T_963 = or(_T_962, _T_952)
node _T_964 = or(_T_963, _T_957)
node _T_965 = and(_T_917, _T_964)
node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_967 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_968 = and(_T_966, _T_967)
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<17>(0h10000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_976 = cvt(_T_975)
node _T_977 = and(_T_976, asSInt(UInt<29>(0h10000000)))
node _T_978 = asSInt(_T_977)
node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0)))
node _T_980 = or(_T_974, _T_979)
node _T_981 = and(_T_969, _T_980)
node _T_982 = or(UInt<1>(0h0), _T_916)
node _T_983 = or(_T_982, _T_965)
node _T_984 = or(_T_983, _T_981)
node _T_985 = and(_T_906, _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_985, UInt<1>(0h1), "") : assert_46
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(is_aligned, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_995 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_995, UInt<1>(0h1), "") : assert_49
node _T_999 = eq(io.in.a.bits.mask, mask)
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_999, UInt<1>(0h1), "") : assert_50
node _T_1003 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1007 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_1011 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1011 :
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_1015 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_54
node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_55
node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_56
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_57
node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1031 :
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(sink_ok, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1038 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_60
node _T_1042 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(_T_1042, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1042, UInt<1>(0h1), "") : assert_61
node _T_1046 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_62
node _T_1050 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_63
node _T_1054 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1055 = or(UInt<1>(0h1), _T_1054)
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_64
node _T_1059 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1059 :
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(sink_ok, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1066 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_67
node _T_1070 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_68
node _T_1074 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_69
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = or(_T_1078, io.in.d.bits.corrupt)
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(_T_1079, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1079, UInt<1>(0h1), "") : assert_70
node _T_1083 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1084 = or(UInt<1>(0h1), _T_1083)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_71
node _T_1088 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1092 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_73
node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_74
node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1101 = or(UInt<1>(0h1), _T_1100)
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_75
node _T_1105 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1105 :
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1109 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_77
node _T_1113 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1114 = or(_T_1113, io.in.d.bits.corrupt)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_78
node _T_1118 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1119 = or(UInt<1>(0h1), _T_1118)
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_79
node _T_1123 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1123 :
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1127 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_81
node _T_1131 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_82
node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1136 = or(UInt<1>(0h1), _T_1135)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1140 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(_T_1140, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1140, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1144 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1148 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1152 = eq(a_first, UInt<1>(0h0))
node _T_1153 = and(io.in.a.valid, _T_1152)
when _T_1153 :
node _T_1154 = eq(io.in.a.bits.opcode, opcode)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_87
node _T_1158 = eq(io.in.a.bits.param, param)
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(_T_1158, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1158, UInt<1>(0h1), "") : assert_88
node _T_1162 = eq(io.in.a.bits.size, size)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_89
node _T_1166 = eq(io.in.a.bits.source, source)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_90
node _T_1170 = eq(io.in.a.bits.address, address)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_91
node _T_1174 = and(io.in.a.ready, io.in.a.valid)
node _T_1175 = and(_T_1174, a_first)
when _T_1175 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1176 = eq(d_first, UInt<1>(0h0))
node _T_1177 = and(io.in.d.valid, _T_1176)
when _T_1177 :
node _T_1178 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_92
node _T_1182 = eq(io.in.d.bits.param, param_1)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_93
node _T_1186 = eq(io.in.d.bits.size, size_1)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_94
node _T_1190 = eq(io.in.d.bits.source, source_1)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_95
node _T_1194 = eq(io.in.d.bits.sink, sink)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_96
node _T_1198 = eq(io.in.d.bits.denied, denied)
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_97
node _T_1202 = and(io.in.d.ready, io.in.d.valid)
node _T_1203 = and(_T_1202, d_first)
when _T_1203 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1204 = and(io.in.a.valid, a_first_1)
node _T_1205 = and(_T_1204, UInt<1>(0h1))
when _T_1205 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1206 = and(io.in.a.ready, io.in.a.valid)
node _T_1207 = and(_T_1206, a_first_1)
node _T_1208 = and(_T_1207, UInt<1>(0h1))
when _T_1208 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1209 = dshr(inflight, io.in.a.bits.source)
node _T_1210 = bits(_T_1209, 0, 0)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1219 = and(io.in.d.ready, io.in.d.valid)
node _T_1220 = and(_T_1219, d_first_1)
node _T_1221 = and(_T_1220, UInt<1>(0h1))
node _T_1222 = eq(d_release_ack, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1224 = and(io.in.d.valid, d_first_1)
node _T_1225 = and(_T_1224, UInt<1>(0h1))
node _T_1226 = eq(d_release_ack, UInt<1>(0h0))
node _T_1227 = and(_T_1225, _T_1226)
when _T_1227 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1228 = dshr(inflight, io.in.d.bits.source)
node _T_1229 = bits(_T_1228, 0, 0)
node _T_1230 = or(_T_1229, same_cycle_resp)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1234 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1235 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1236 = or(_T_1234, _T_1235)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_100
node _T_1240 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_101
else :
node _T_1244 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1245 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1246 = or(_T_1244, _T_1245)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_102
node _T_1250 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(_T_1250, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1250, UInt<1>(0h1), "") : assert_103
node _T_1254 = and(io.in.d.valid, d_first_1)
node _T_1255 = and(_T_1254, a_first_1)
node _T_1256 = and(_T_1255, io.in.a.valid)
node _T_1257 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1258 = and(_T_1256, _T_1257)
node _T_1259 = eq(d_release_ack, UInt<1>(0h0))
node _T_1260 = and(_T_1258, _T_1259)
when _T_1260 :
node _T_1261 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1262 = or(_T_1261, io.in.a.ready)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_104
node _T_1266 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1267 = orr(a_set_wo_ready)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
node _T_1269 = or(_T_1266, _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_24
node _T_1273 = orr(inflight)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
node _T_1275 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1276 = or(_T_1274, _T_1275)
node _T_1277 = lt(watchdog, plusarg_reader.out)
node _T_1278 = or(_T_1276, _T_1277)
node _T_1279 = asUInt(reset)
node _T_1280 = eq(_T_1279, UInt<1>(0h0))
when _T_1280 :
node _T_1281 = eq(_T_1278, UInt<1>(0h0))
when _T_1281 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1278, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1282 = and(io.in.a.ready, io.in.a.valid)
node _T_1283 = and(io.in.d.ready, io.in.d.valid)
node _T_1284 = or(_T_1282, _T_1283)
when _T_1284 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1285 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1286 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1287 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1288 = and(_T_1286, _T_1287)
node _T_1289 = and(_T_1285, _T_1288)
when _T_1289 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1290 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1291 = and(_T_1290, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1292 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1293 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1294 = and(_T_1292, _T_1293)
node _T_1295 = and(_T_1291, _T_1294)
when _T_1295 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1296 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1297 = bits(_T_1296, 0, 0)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1302 = and(io.in.d.valid, d_first_2)
node _T_1303 = and(_T_1302, UInt<1>(0h1))
node _T_1304 = and(_T_1303, d_release_ack_1)
when _T_1304 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1305 = and(io.in.d.ready, io.in.d.valid)
node _T_1306 = and(_T_1305, d_first_2)
node _T_1307 = and(_T_1306, UInt<1>(0h1))
node _T_1308 = and(_T_1307, d_release_ack_1)
when _T_1308 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1309 = and(io.in.d.valid, d_first_2)
node _T_1310 = and(_T_1309, UInt<1>(0h1))
node _T_1311 = and(_T_1310, d_release_ack_1)
when _T_1311 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1312 = dshr(inflight_1, io.in.d.bits.source)
node _T_1313 = bits(_T_1312, 0, 0)
node _T_1314 = or(_T_1313, same_cycle_resp_1)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1318 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(_T_1318, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1318, UInt<1>(0h1), "") : assert_109
else :
node _T_1322 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_110
node _T_1326 = and(io.in.d.valid, d_first_2)
node _T_1327 = and(_T_1326, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1328 = and(_T_1327, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1329 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1330 = and(_T_1328, _T_1329)
node _T_1331 = and(_T_1330, d_release_ack_1)
node _T_1332 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1333 = and(_T_1331, _T_1332)
when _T_1333 :
node _T_1334 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1335 = or(_T_1334, _WIRE_23.ready)
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_111
node _T_1339 = orr(c_set_wo_ready)
when _T_1339 :
node _T_1340 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_25
node _T_1344 = orr(inflight_1)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
node _T_1346 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1347 = or(_T_1345, _T_1346)
node _T_1348 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1349 = or(_T_1347, _T_1348)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1353 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1354 = and(io.in.d.ready, io.in.d.valid)
node _T_1355 = or(_T_1353, _T_1354)
when _T_1355 :
connect watchdog_1, UInt<1>(0h0)
extmodule plusarg_reader_26 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_27 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_12( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _T_1282 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1282; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1282; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1355 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1355; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1355; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1205 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1205; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1205; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1282 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46]
wire _T_1254 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_1254 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_1355 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1326 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1326 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_1355 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_60( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
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